A New Switching Algorithm in Back to

Back CHB Multilevel Converters with the

Advantage of Eliminating Isolation Stage

Mohsen Asoodar
School of Electrical and Computer
Engineering
University of Tehran
Tehran, Iran
asoodar@kth.se

Hossein Iman-Eini
School of Electrical and Computer
Engineering
University of Tehran
Tehran, Iran
imaneini@ut.ac.ir
AbstractBack to Back CHB Multilevel converters have
been widely considered in high power applications; however,
there are certain drawbacks which restrict the use of these
structures. In this paper, a new switching algorithm is
introduced for a back to back cascaded H-bridge (CHB)
converter with the ability to regulate the DC bus voltages to a
reference value and produce a low frequency output voltage. The
main purpose of this novel switching algorithm is to eliminate
the need for an isolation stage between the H-bridge cells. The
proposed back to back converter can connect directly to MV
levels and correct the input power factor, even if the output load
is non-linear. In order to limit the switching loss, a maximum
switching frequency of 3kHz has been chosen for the line side
converter; furthermore, to eliminate a specific harmonic
component, the load side converter is modulated through the
selective harmonic elimination method. Using the predictive
current control method for the rectifier, the input current is
programmed to be sinusoidal and in phase with the input
voltage; in addition, the current distortion is kept below 5% at
maximum power consumption. The validity and effectiveness of
the proposed method is verified through simulations on a 5-level
back to back converter in the MATLAB/SIMULINK
environment.

I. INTRODUCTION

In recent years there has been an immense interest of
research on multilevel power converters. This is due to their
extensive usage in high-voltage/high-power applications.
Moreover, multilevel inverters have shown some advantages
in comparison to conventional inverters. The most prominent
benefits in using multilevel inverters are their low voltage
distortion, less dv/dt, less input current distortion, and their
ability to operate under low switching frequencies [1].
The main aim in multilevel inverters is to create a
sinusoidal voltage from several voltage levels. As the number
of levels increases, the THD and dv/dt of the output voltage
will decrease; however, increasing the voltage levels will lead
to a more complex control algorithm, especially for the back
to back multilevel structure where the DC links have to be
equally balanced. Three major topologies have been presented
for multilevel structures: cascaded H-bride [2], [3], [4], diode
clamped [5], and capacitor clamped [2], [6], [7] converters.
The cascaded structure is chosen in this paper since it has
some advantages amongst other multilevel structures:

This structure requires the least number of
components among other structures to create the
same voltage level [8].
The CHB converter is extremely modular and can be
easily extended to different voltage and power levels
[8].
Moreover, soft switching can be used in this
structure in order to eliminate the need for lossy
snubbers [9].

Many rectifying control methods have been proposed for
multilevel rectifiers such as the Proportion Resonance (PR)
controller [10], the hysteresis current controller[11], and the
predictive current controller[12]. The PR controller and the
fixed hysteresis band current controller have the drawback of
random switching frequency. On the other hand, the
predictive current controller has the advantage to operate
under a fixed and lower switching frequency and therefore,
this controlling method is used in this paper.
Back to back cascaded H-bridge structures have mostly
been used for high-voltage drives [13] and power electronic
transformer [14]. These structures can also be used in
applications such as high voltage electronic tap changers [15]
and high voltage cycloconverters [16]. The back to back
cascaded H-bridge structure has been mainly introduced with
a coupled isolating device for each H-bridge. The main
challenge in this paper is to eliminate the isolating devices
without destabilizing the DC voltage links to create smaller,
cheaper and more applicable back to back multilevel
structures.

II. CIRCUIT CONFIGURATION

A. Conventional structures and difficulties
There are three typical isolating methods for back to back
multilevel structures. The first design consists of isolating
transformers at the input of each H-bridge. Due to the low
frequency voltage (50Hz) of these transformers, the magnetic
cores are usually very bulky to prevent the core saturation;
furthermore, these bulky cores are usually heavy which
increases the overall weight of the back to back structure. The
second method is to install the isolation stage at the output
links of the back to back structure. This design has the same
978-1-4577-1829-8/12/$26.00 2012 IEEE
disadvantages of the first isolating method.
is to use a DC/DC converter between ea
units. In this structure, by chopping the DC l
a high frequency modulation, the produced A
transferred with a much smaller transformer
requires smaller and cheaper component
preferred to the former designs; however in
the switching loss is almost high and there
considered as an efficient solution.

B. Non-isolated back to back CHB conver
The case study in this paper is a 5-level
to back CHB inverter which is shown in F
unit consists of four IGBT switches with anti

Figure 1. 5-level back to back CHB inverter
device

In the demonstrated structure, the line s
H-bridge units are directly connected to ea
the installation of an isolation stage. It is al
the switches on the rectifier side and i
switched independently. In this case, there ar
states at which one or both of the DC link c
short-circuited. For example, if the load s
inverter) is creating a zero voltage by s
voltage on the upper H-bridge and a Vd
lower H-bridge, and both of the upper and
line side converter (or rectifier) are at the
capacitor connected to the lower CHBs will b
The dashed line in Fig. 1 shows the path in
circuit current flows. Since this fault
switching states, the conventional back to ba
cannot be used without any isolating device.

III. PREDICTIVE CURRENT CONTRO
VOLTAGE MODULATIO

A. Predictive current control basics
The predictive current control metho
active rectifiers has been proposed in [17].
been chosen for voltage rectification in
equivalent circuit of the rectifying side is sh
this paper, the switching frequency is chosen
The final method
ach two H-bridge
link voltages with
AC voltage can be
r. As this method
ts, it is usually
n the latter design
efore it cannot be
rter
non-isolated back
Fig. 1. Each CHB
i-parallel diodes.

r without any isolating
side and load side
ach other without
lso presumed that
inverter side are
re some switching
capacitors will be
side converter (or
umming a +Vdc
dc voltage on the
lower cells of the
e +Vdc state, the
be short circuited.
n which the short
occurs in many
ack CHB inverters

OL AND SHE
ON
od for multilevel
This method has
this paper. An
hown in Fig. 2. In
n to be 3kHz.
Figure 2. Equivalent c

According to [17], at each tim
be calculated by means of the f

:
ubk
= -
L
1
s
(i
k
B. Voltage level selection
Although the calculated :
value, due to the cascaded H
discrete voltage levels are p
proposed that calculates the
to :
ubk
[17]. Equations
mathematically; That is, during
of the discrete voltage levels co

] :
ubk
tk+1s
tk
Jt = I
Iob
k
. Is = I
k
Ion
Ion
k
=
(
Ion
k+1
=

Since there are switching redun
in CHB structures, for a specif
switching configurations can
been proposed to select the op
of a voltage level among vario
This algorithm suggests the
optimally equalizes the DC vo

C. SHE voltage modulation
In this paper the selectiv
voltage modulation method ha
converter. The most promin
modulation method is its lo
advantage will effectively inc
the converter due to its low
Moreover, the rectified voltag
ripple residing on the const
quarter-symmetry structure o
100Hz and every other even
filtered and prevented from be

circuit of the rectifier side [17]
me, the AC terminal voltage can
following equation:
+1
-i
k
) +
1
1
s
. ] cJt
.
1
s
(4)

:
ubk
could have any continuous
H-bridge structure, only a few
permitted. A method has been
e two voltage levels adjacent
(5-8) illustrate this idea
g each period, the average value
orresponds to v
abk
.
I
k
Ion
k
+ I
k+1
Ion
k+1
(5)

n
k
+ I
k+1
Ion
k+1
(6)

(v
k+1
-vub
k
)
(v
k+1
-v
k)
.Ts (7)

= Is - Ion
k
(8)
ndancies for most voltage levels
fic voltage level, more than one
be assumed. An algorithm has
ptimum switching configuration
ous switching redundancies [18].
e switching configuration that
ltage links.
ve harmonic elimination (SHE)
as been utilized for the load side
nent motive in choosing this
ow switching frequency. This
crease the overall efficiency of
switching power dissipations.
ge usually has a 100Hz voltage
tant DC voltage. Due to the
f the SHE output signals, the
harmony will be automatically
ing transferred to the output.
IV. NOVEL SWITCHING SC

In this paper, a novel switching method
the aim of eliminating any isolating device.
to avoid the switching states at which a shor
occur. In order to find the faulty switching c
circuit shown in Fig. 3 has been designed and

Figure 3. Designed circuit for finding the inc
configurations

Since the short circuited current always
lines that connect the H-bridge circuits, an a
distinguish the incorrect switching states
ones. In Fig. 3 the DC link capacitors have b
DC voltage supplies. Also, since the sho
doesnt flow through the input grid line or
they have been removed and replaced with a
any floating endings in the circuit. A
programmed to check every possible switch
and examine the possibility of applying that
the current magnitude turned out to be
predefined value, that specific configuration
to be acceptable in the practical implementat
In this paper a 5-level back to back structure
Since there are 16 possible switching states
rectifiers and 5-level CHB inverters, a total
configurations can be considered for the 5-l
CHB inverter. In order to organize t
possibility results, a 16 16 matrix has bee
matrix, each row refers to a switching state a
and each column refers to a switching sta
side. Therefore, each element denotes one s
configuration. After simulation, the elemen
will be 0 or 1. Number 1 indicates t
configuration is applicable, whereas, numb
unusable switching configuration. Fig. 4
matrix results for a 5-level back to back CH
simulation. For this matrix, the switching sta
to every row and column were labeled. The
Fig. 4 indicate the number of correspondin
H-bridge cells shown in Fig. 1. Also, in
column, the first two switch numbers corresp
CHEME
d is proposed with
The main idea is
rt circuit fault will
configurations, the
d simulated.

correct switching
flows through the
ampere-meter can
from the correct
been replaced with
ort-circuit current
r the output load,
a resistor to avoid
A controller was
hing configuration
t configuration. If
e smaller than a
n was considered
tion of the circuit.
has been studied.
s for 5-level CHB
of 256 switching
evel back to back
he configuration
en created. In this
at the inverter side
te at the rectifier
specific switching
nts of the matrix
that the switching
ber 0 shows an
shows the final
HB structure after
ates corresponding
numbers 1 to 4 in
ng switches in the
n every row and
pond to the upper
cell while the second two swi
lower cell. This matrix is used
following simulations.

Figure 4. Final matrix for a
V. NOVEL SW
The novel switching algo
based on a mutual switching d
side and the inverter side s
charging the DC link capac
switches are in their off sta
the proper switches are chosen
[18]. After the capacitors are
method is changed to the n
inverter side to produce an ou
the rectifying process. For th
charging process, the first ha
terminal voltage i.e. :
ub1
is ex
modulation index and the des
proper firing angles,
1
and
2
,
As shown in Fig. 5, by
angles, a staircase voltage si
same phase and frequency as :

Figure 5. Produced stairc
The staircase voltage sign
the output voltage; therefore
itch numbers correspond to the
d as a switching reference in the

5-level back to back CHB structure

WITCHING ALGORITHM

rithm presented in this paper is
dependency between the rectifier
switching states. At first, for
citors, all of the inverter side
ate. During the initial charging,
n by the algorithm explained in
e fully charged, the switching
novel algorithm, allowing the
utput voltage simultaneous with
his purpose, during the initial
armonic component of the AC
xtracted. Next, according to the
sired harmonic elimination, the
are calculated.
y comparing :
ub1
to the firing
ignal is created which has the
:
ub1
.


case voltage using :
ub
and :
ub1


nal is a low voltage model for
e, each level in the staircase
indicates the actual output voltage level. Finally, the staircase
signal and the :
ub
voltage are mutually considered to find the
proper switching states at both rectifier and inverter sides.
This proper switching selection is performed by means of the
switching reference matrix shown in Fig. 4. At each time, the
output voltage level is specified by the calculated staircase
voltage signal; also, the voltage level at the rectifier side is
calculated through (4) to (8).
Having in hand the voltage levels at both rectifier and
inverter sides, a row and column of the reference matrix
corresponding to these voltage levels is chosen. For each
voltage level there are one or more switching redundancies.
Among all these redundancies, the switching configuration
which denotes number 1 in the reference matrix is chosen.
As mentioned before, this choice allows the creation of the
desired input and output voltage levels without causing a
short circuit in the DC link capacitors. In cases where more
than one possible switching configuration is available, for a
specific rectifier and inverter voltage level, the configuration
which has a greater performance in equalizing the DC-link
capacitors is chosen. As shown in Fig. 4, there are many
theoretical voltage formations which have no acceptable
switching configurations. For example, if the inverter voltage
is set to +2Vdc, there are no possible switching configurations
for Vdc and -2Vdc voltage levels at the rectifier side. This
disadvantage restricts the output voltage only to have the
same frequency as the grid voltage. As shown in Fig. 5 and
according to the reference matrix in Fig. 4 having equalized
the input and output voltage frequencies and forcing the
output voltage to be almost in phase with the AC terminal
voltage prevents the occurrence of such voltage formations.
Further explained, with this idea the AC side and load side
voltages would have the same periodic waveform shown in
Fig. 5 at all times, that is, in steady state, their frequency,
magnitude and phase will stay constant. Therefore by
comparing the voltage levels of :
ub
(where each voltage
level indicates one or more columns in the reference matrix)
and the produced staircase voltage shown in Fig. 5(in which
each voltage level indicates one or more rows in the reference
matrix) with the reference matrix in Fig. 4, it is observed that
for each voltage level that appears at the AC terminal, the
output staircase voltage would be in a state that approves a
possible switching configuration, i.e. by checking the
elements corresponding to these rows and columns in the
reference matrix, there would definitely be a 1 for the
created voltage levels.
As an example to this situation, it is observed in Fig. 5
that when the maximum control signal occurs, the AC
terminal voltage has a value of 0, +Vdc or +2Vdc. Referring
to the reference matrix, it is observed that for the first row
(+2Vdc at the inverter side) it is possible to have 0, +Vdc or
+2Vdc at the AC terminal voltage. The same explanation can
be given for other control voltage levels and the applicable
AC terminal voltages at each level. As explained before in
addition to the frequency correspondence, the output voltage
phase can neither be of any desired value. That is, it can only
have a slight difference from the :
ub
voltage phase otherwise
it is possible to have an unwanted switching configuration
which leads to a short circuit in the DC link capacitors. This is
also a procedure to avoid voltage formations which have no
applicable switching configurations. Although the
disadvantage of having the same frequency restricts the usage
of this structure in many applications, such as constant v/f
motor drives, having a close phase value cannot be considered
as a practical drawback. This is due to the fact that any
possible load which was limited to the nominal power of this
multilevel structure could be driven regardless of the output
voltage phase; therefore, equalizing the input and output
voltage phases did not interfere with the practical applications
of this structure.

VI. SIMULATION RESULTS

A 5-level back to back CHB Multilevel structure has
been simulated with the novel strategy presented in this paper.
The case study parameters for this simulation are shown in
Table I.
The simulation has been carried out for a linear load with
an active power of 80 kW and a reactive power of 35kVAR.
The objectives were to have a modulation coefficient of 1
and to eliminate the 5
th
harmonic component. Since this
structure is meant to be used in three phase systems, the 3
rd

harmonic will automatically be eliminated in the three phase
system. Fig. 6 shows the input voltage and current i.e.
:
s
anu i
s
. Correctly anticipated, the input current was in
phase with the input voltage resulting in a power factor of
1. The spectra of the input current is depicted in Fig. 7
showing a THD smaller than 5%. The two DC link voltages
are depicted in Fig. 8. Simulation results confirmed a nearly
constant value of 600V in these links. Also, the voltages in
both DC link capacitors were kept close to each other which
approved proper functioning of the predictive controller. At
the time t = u.21 Scc, an undershoot can be observed in the
DC bus voltages. This is due to the change in the switching
algorithm. At this time, before the controller is fully adjusted
to the new algorithm, a small amount of energy is taken from
the DC link capacitors. Another undershoot occurs at
t = u.4S Scc which is due to the load connection. After the
load is connected, again some energy is consumed from the
DC link capacitors resulting in a slight voltage drop. Finally
this voltage drop is compensated by the control circuit.
Although a 100Hz ripple can be easily detected in these plots,
due to the quarter-symmetry voltage outputs of the SHE
modulation, the even harmonies were automatically filtered
while the DC voltages were transferred to the output links.
The output voltage and its bar-view spectra are shown in Fig.
9 and Fig. 10 respectively. In Fig. 9, although the five level
structure of the output voltage is evident, due to some
harmonics on the DC links, small deviations from the nominal
voltage level rate can be observed. Fig. 10 implies that the
even harmonic components of the output v
reasonably filtered which was one of the a
the SHE modulation. Also, the 5
th
harmonic
was the selected harmonic component to b
been considerably damped.

TABLE I. Case study parameters

Figure 6. :
s
and i
s
signals. The i
s
signal has been
gain.


Figure 7. Spectra of the input current i
s
with the
100%

1 1.01 1.02 1.03 1.04 1.05 1.06
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
Time [Sec]
V
o
l
t
a
g
e

[
V
]
,

C
u
r
r
e
n
t
*
5

[
A
]

0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
3
Harmonic order
Fundamental (50Hz) = 161.9 , THD=
M
a
g

(
%

o
f

F
u
n
d
a
m
e
n
t
a
l
)
voltage have been
aims for choosing
component which
be eliminated has


enlarged with a 5

first harmony being
Figure 8. DC bus voltages. New switc
Figure 9. Outp
Figure 10. Spectra
The spectra illustrated in F
distortion in the output voltage
of voltage levels chosen in thi
number of CHBs and therefor
the THD of the output voltage

CONCL
In this study a new switching
back to back CHB multilevel
of removing the isolation stag
multilevel structures, this circ
structure. This new algorithm
frequency at both inverter and
lower switching loss. In ad
algorithm also uses the most
the DC bus voltages. Moreove
less than 5% at maximum pow
1.07 1.08 1.09 1.1
V
s
i
s
5 6 7 8
4.42%
0 0.2 0.4 0.6 0.8
-200
0
200
400
600
800
T
V
o
l
t
a
g
e

[
V
]

1.64 1.65 1.66 1.67 1.68
-1500
-1000
-500
0
500
1000
1500
V
o
l
t
a
g
e

[
V
]

0 0.2 0.4
0 2 4 6 8
0
2
4
6
8
10
Ha
Fundamental (50
M
a
g

(
%

o
f

F
u
n
d
a
m
e
n
t
a
l
)

ching algorithm applied at t = u.21 Scc.

put voltage signal

of the output voltage

Fig. 10 shows a large amount of
e. This is due to the few number
is simulation. By increasing the
re the number of voltage levels,
will significantly decrease.
LUSION

g algorithm was designed for a
structure. Having the advantage
ge, compared with conventional
cuit had a cheaper and simpler
also offers a reduced switching
rectifier sides which results in a
ddition to these benefits, this
optimum method for balancing
er, the input current has a THD
wer consumption. In this paper,
1 1.2 1.4 1.6 1.8 2
Time [Sec]

Upper half bridge voltage
Lower half bridge voltage
8 1.69 1.7 1.71 1.72 1.73 1.74
Time [Sec]

Output Voltage
0.6 0.8 1 1.2
Time (s)
8 10 12 14 16 18 20
armonic order
0Hz) = 1206 , THD= 19.26%
the new algorithm was only applied to a 5-level back to back
inverter. However, the same method can be applied to back to
back CHB multilevel inverters with higher voltage levels to
create output voltage signals with lower THD values.
Simulation results confirm that using this new switching
algorithm, while having acceptable and reasonable
voltage/current qualities, all isolating devices can be removed
from the conventional back to back cascaded H-bridge
inverter structures. It has also been proven that the novel
algorithm is very promising for back to back CHB multilevel
inverters utilized in power system applications; especially for
power electronic transformers and high power voltage
regulators.

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