Modeling Gigabit Pre-Emphasis Using IBIS [Driver Schedule]: Application Note

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 19912007 Cadence Design Systems, Inc. All rights reserved. Portions Apache Software Foundation, Sun Microsystems, Free Software Foundation, Inc., Regents of the University of California, Massachusetts Institute of Technology, University of Florida. Used by permission. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Allegro PCB SI contains technology licensed from, and copyrighted by: Apache Software Foundation, 1901 Munsey Drive Forest Hill, MD 21050, USA 2000-2005, Apache Software Foundation. Sun Microsystems, 4150 Network Circle, Santa Clara, CA 95054 USA 1994-2007, Sun Microsystems, Inc. Free Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 1989, 1991, Free Software Foundation, Inc. Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, 2001, Regents of the University of California. Daniel Stenberg, 1996 - 2006, Daniel Stenberg. UMFPACK 2005, Timothy A. Davis, University of Florida, (davis@cise.ulf.edu). Ken Martin, Will Schroeder, Bill Lorensen 1993-2002, Ken Martin, Will Schroeder, Bill Lorensen. Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts, USA 2003, the Board of Trustees of Massachusetts Institute of Technology. All rights reserved. Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadences trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specied in this permission statement, this publication may not be copied, reproduced, modied, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used only in accordance with a written agreement between Cadence and its customer. 2. The publication may not be modied in any way. 3. Any authorized copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement. 4. The information contained in this document cannot be used in the development of like products or software, whether for internal or external use, and shall not be used for the benet of any other party, whether or not for consideration. Patents: Allegro PCB SI, described in this document, is protected by U.S. Patents 5,481,695; 5,510,998; 5,550,748; 5,590,049; 5,625,565; 5,715,408; 6,516,447; 6,594,799; 6,851,094; 7,017,137; 7,143,341; 7,168,041. Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Modeling Gigabit Pre-Emphasis Using IBIS [Driver Schedule] Application Note

Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Modeling Gigabit Pre-emphasis using IBIS [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . 4 Task 1: Understand IBIS [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Task 2: Schedule Main and Boost Drivers Using Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 [Driver Schedule]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Modeling Gigabit Pre-emphasis using IBIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Task 3: Test it in Allegro PCB SI/SigXplorer [Driver.Schedule] . . . . . . . . . . . . . . . . . . . . . . . 4 Task 1: Understand IBIS [Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 a. IBIS Model ds-2tap.ibs . Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Task 2: Schedule Main and.Boost. Drivers. Using . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 b. Translate to DML . . . . . . . . . . . . . . . . [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. Simulate in SigXp (DS_2tap.top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Task 3: Test it in Allegro PCB SI/SigXplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 a. IBIS Model ds-2tap.ibs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 b. Translate to DML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. Simulate in SigXp (DS_2tap.top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Modeling Gigabit Pre-Emphasis Using IBIS [Driver Schedule]: Application Note

The purpose of this application note is to describe how you use the IBIS [Driver Schedule] feature for pre-emphasis differential models, then simulate them in Allegro PCB SI. You will benet from this application note if you are a user of Allegro platform high-speed products, specically Allegro PCB SI and SigXplorer, and are familiar with the I/O Buffer Information Specication (IBIS), Cadence Device Modeling Language (DML), and Allegro PCB SI ESPICE syntax. ___________________________________________________. For additional information on the technology used in this application note, see: Modeling Pre-/de-emphasis Buffers with [Driver Schedule] by Arpad Muranyi: www.eda.org/ibis/summits/jan05/muranyi.pdf IBIS can help model gigabit pre-emphasis by Arpad Muranyi and Michael Mirmak: www.eet.com/news/latest/showArticle.jhtml?articleID=60300186 IBIS Specication www.eda.org/ibis How to build fast and accurate multi-gigabit transceiver models www.cadence.com/webinars/webinars.aspx?xml=pcbmacromodeling ___________________________________________________

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Overview
Serial differential buffers are increasingly used in todays high-speed system designs. To combat interconnect losses and ISI effects, serial differential interface technologies such as Serial ATA and PCI Express typically use pre-emphasis to selectively boost their buffer output and to increase margins. System designers need fast, accurate pre-emphasis modeling is needed to analyze performance and prevent signal integrity problems before production. IBISthe I/O Buffer Information Specication is commonly used in PCB system EDA tools. However, many view IBIS models as either too difcult to use or not up to the task of accurate pre-emphasis modeling. This application note outlines how to use the IBIS [Driver Schedule] keyword to create simple, modular and accurate models of serial-differential buffer designs featuring the most common form of pre-emphasis. Within the Cadence Allegro PCB SI environment, it will be simply translated into a DML MacroModel section and seamlessly used in the simulation. Important The les referred to in this application note are available for your use. You can access them at the following location in your installation hierarchy:
<install_dir>/doc/IBIS_DS_AN/examples

Modeling Gigabit Pre-emphasis using IBIS [Driver Schedule]

The [Driver Schedule] is designed for scheduling multi-driver efforts in IBIS. It is often used in multi-stage drivers with such limitations as xed delay schedules, pre-dened initial states, etc. Pre-emphasis is a multi-stage driver effort. It often uses one main driver and one or more boost drivers with delays. So, before starting work on [driver schedule], you must properly prepare the main driver and boost drivers in IBIS, as depicted in Figure 1.

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Figure -1 Prepare the Main Driver and Boost Drivers

The three major tasks associated with are: 1. Understand IBIS [Driver Schedule] 2. Schedule main and boost drivers using IBIS [Driver Schedule] 3. Test it in Allegro PCB SI/Signal Explorer The balance of this application note covers each of these tasks in detail.

Task 1: Understand IBIS [Driver Schedule]

The [Driver Schedule] keyword description in the IBIS 4.1 Specication is: Keyword: Required: [Driver Schedule] No

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Description:

Describes the relative model switching sequence for referenced models to produce a multi-staged driver. The [Driver schedule] keyword establishes a hierarchical order between models and should be placed under the [Model] which acts as the toplevel model. The scheduled models are then referenced from the top-level model by the [Driver Schedule] keyword. When a multi-staged buffer is modeled using the [Driver Schedule] keyword, all of its stages (including the first stage, or normal driver) have to be modeled as scheduled models. If there is support for this feature in a EDA tool, the [Driver Schedule] keyword will cause it to use the [Pulldown], [Pulldown Reference], [Pullup], [Pullup Reference], [Voltage Range], [Ramp], [Rising Waveform] and [Falling Waveform] keywords from the scheduled models instead of the top-level model, according to the timing relationships described in the [Driver Schedule] keyword. Consequently, the keywords in the above list will be ignored in the top-level model. Also, all other keywords not shown in the above list will be ignored in the scheduled model(s). However, both the top-level and the scheduled model(s) have to be complete models, i.e., all of the required keywords must be present and follow the syntactical rules. For backwards compatibility reasons and for EDA tools which do not support multi-staged switching, the keywords in the above list can be used in the top-level [Model] to describe the overall characteristics of the buffer as if it was a composite model. It is not guaranteed, however, that such a top-level model will yield the same simulation results as a full multistage model. It is recommended that a golden

Usage Rules:

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waveform for the device consisting of a [Rising Waveform] table and a [Falling Waveform] table be supplied in the top-level model to serve as a reference for validation. Even though some of the keywords are ignored in the scheduled model, it may still make sense in some cases to supply correct data with them. One such situation would arise when a [Model] is used both as a regular top-level model as well as a scheduled model. The [Driver Schedule] table consists of five columns. The first column contains the model names of other models that exists in the.is file. The remaining four columns describe delays: Resoundingly, Rise_off_dly, Fall_on_dly, and Fall_off_dly. The t=0 time of each delay is the event when the EDA tools internal pulse initiates a rising or falling transition. All specified delay values must be equal to or greater than 0. There are only five valid combinations in which these delay values can be defined: 1) 2) 3) 4) Rise_on_dly Rise_off_dly Rise_on_dly Fall_on_dly with with with with Fall_on_dly Fall_off_dly Rise_off_dly Fall_off_dly

5) All four delays defined (be careful about correct sequencing) The four delay parameters have the meaning as described below. (Note that this description applies to buffer types which have both pullup and pulldown structures. For those buffer types which have only a pullup or pulldown structure, the description for the missing structure can be omitted.)

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Rise_on_dly is the amount of time that elapses from the internal simulator pulse initiating a RISING edge to the t = 0 time of the waveform or ramp that turns the I-V table of the PULLUP device ON, and the t = 0 time of the waveform or ramp that turns the I-V table of the PULLDOWN device OFF (if they were not already turned ON and OFF, respectively, by another event). Rise_off_dly is the amount of time that elapses from the internal simulator pulse initiating a RISING edge to the t = 0 time of the waveform or ramp that turns the I-V table of the PULLUP device OFF, and the t = 0 time of the waveform or ramp that turns the I-V table of the PULLDOWN device ON (if they were not already turned ON and OFF, respectively, by another event). Fall_on_dly is the amount of time that elapses from the internal simulator pulse initiating a FALLING edge to the t = 0 time of the waveform or ramp that turns the I-V table of the PULLDOWN device ON, and the t = 0 time of the waveform or ramp that turns the I-V table of the PULLUP device OFF (if they were not already turned ON and OFF, respectively, by another event). Fall_off_dly is the amount of time that elapses from the internal simulator pulse initiating a FALLING edge to the t = 0 time of the waveform or ramp that turns the I-V table of the PULLDOWN device OFF, and the t = 0 time of the waveform or ramp that turns the I-V table of the PULLUP device ON (if they were not already turned ON and OFF, respectively, by another event). Note that some timing combinations may only be possible if the two halves of a complementary buffer are modeled separately as two open_* models. Use NA when no delay value is applicable. For each scheduled model the transition sequence

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must be complete, i.e., the scheduled model must return to its initial state. No [Driver Schedule] table may reference a model which itself has within it a [Driver Schedule] keyword. To use the [Driver Schedule] keyword correctly, you must understand that [Driver Schedule]:
s

Works for a single instance of a cycle (Rising and Falling) Example of a Full Cycle for a [Driver schedule]: Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dly X1 or NA X2 or NA X3 or NA X4 or NA Full cycle: down-up, up-down down-up-down-up, up-down-up-down sequencing for slow clock. (There is no over-clocking.)

Follows top-level [Model] Polarity Non-Inverting and Inverting modes (phasing in a transparent manner) Relates to Rise or Fall edges of a Master Clock Knows the initial state (High or Low) of the signal Allows a single switch and one cycle simulation

s s s

The [Driver schedule] is based on knowing the initial state, as shown in Table 1. Table -1 Initial State Driver Schedule Rise_on_dly Xr NA X1 X2 NA NA Xr1 Rise_off_dly NA Xr X2 X1 NA NA Xr2 Fall_on_dly Xf NA NA NA X1 X2 Xf2 States Fall_off_dly NA Xf NA NA X2 X1 Xf1 Non-Invert Low High Low High High Low Low Inverting High Low Low High High Low Low

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Driver Schedule Xr2 Xr1 Xf1

States Xf2 High High

Some examples of bad sequences in [Driver Schedule] are shown in Table 2: Table -2 Bad Sequences in [Driver Schedule] Rise_on_dly NA Xr NA Xr1 Rise_off_dly NA NA Xr Xr2 Fall_on_dly NA NA Xf Xf1 Fall_off_dly NA Xf NA Xf2 Reason Unknown initial state rising-rising sequencing falling-falling sequencing rising-fallingfalling-rising sequencing falling-risingrising-falling sequencing

Xr2

Xr1

Xf2

Xf1

Note: You must use a complete cycle to create a correct model.

Task 2: Schedule Main and Boost Drivers Using [Driver Schedule]

a. Use the IBIS [Driver Schedule] keyword to tie together the elements of your preemphasis driver. [Driver Schedule] can activate or de activate IBIS models using xed values of delays from rising and/or falling edges in the buffer input stimulus pattern. Without [Driver Schedule], model users can only connect buffer models in a cumbersome wired-or fashion. Do not use the same delay values for all buffer speeds or designs. For example, a Serial ATA Generation I buffer has a nominal eye width of 666.66 ps. The delay to use for the boost in a two-tap design is therefore 666.66 ps. Serial ATA Generation II has a nominal eye width of 333.33 ps. To simulate a buffer running at Generation
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II data rates requires you to edit the IBIS model [Driver Schedule] delay values. Also, make sure your main and boost IBIS [Model] V-T tables are shorter than the minimum target eye width to ensure that your buffer settles completely after each transition in simulation. b. Model your buffer as multiple [Model] sections. In most of todays two-tap buffer designs, a boost driver adds current to the output of a main driver after each transition of the input stimulus (the boost output is often some fraction of the main output). Collect separate I-V and V-T table data for the main and boost sections of your design and generate an IBIS model for each one. Create a third top-level model and add a [Driver Schedule] keyword section to it, referencing the main and boost buffers. Do not neglect buffer capacitance effects. Models using [Driver Schedule], per the IBIS specication, are only required to have valid C_comp (buffer capacitance) data in the top-level model. Properly separate your main and boost stages when making their IBIS equivalents. It may be necessary to manually disable portions of the silicon buffers netlist if control bits do not allow this to be done externally. c. Use [Driver Schedule] to provide logical control over your driver output. The [Driver Schedule] delay parameters control how buffer pullups and pulldowns turn on and off. You can therefore use [Driver Schedule] to invert your output relative to the input stimulus pattern by lling in only the turn off delays after input edges. For example, this syntax describes a simple inverter with no actual delay added to the input stimulus. [Driver Schedule] Model_name Rise_on_dly inverter NA

Rise_off_dly Fall_on_dly 0.0ns NA

Fall_off_dly 0.0ns

d. Fill in the [Driver Schedule] delays based upon the bit duration of your interface. To implement two-tap pre-emphasis, we assume the boost buffer turns on in response to the input stimulus pattern inverted and delayed by one bits duration. By combining the logical control capability of [Driver Schedule] with bit duration information, you can achieve complex pre-emphasis switching effects. For example, here is the syntax for a two-tap buffer with an eye width of 400 ps. [Driver Schedule] Model_name Rise_on_dly main 0.0ns boost NA

Rise_off_dly Fall_on_dly NA 0.0ns 0.400ns NA

Fall_off_dly NA 0.400ns

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This buffers main section switches immediately after an input rising edge. Tools will interpret the boost section delay format as inversion, while the 400 ps value provides the one bit delay component. The same technique could be used to model additional taps, as needed. e. Follow the specication rules in adding [Driver Schedule] to your IBIS les. [Driver Schedule] is used in a top-level buffer model containing C_comp (buffer capacitance) and clamp information for use by the tool. Other parts of the top-level model are ignored in favor of the tables in the scheduled buffer. f. Use the [Diff Pin] keyword to link the inverting and non-inverting parts of your buffer. Many EDA tools that support IBIS will permit you to use a single input pattern to stimulate serial-differential buffer designs if [Diff Pin] is present.

Task 3: Test it in Allegro PCB SI/SigXplorer

It is very important to test the results of tasks 1 and 2 in SI and/or SigXplorer and correlate with the real device before you distribute or use it. The following steps use an IBIS 2-tap pre-emphasis model (ds_2tap) as an example to show how to test it in SigXplorer.

a. IBIS Model ds-2tap.ibs

Component Pin List: [Component] Test [Manufacturer] Cadence [Package] | typ min max R_pkg 0.10Ohm 0.10Ohm 0.10Ohm L_pkg 1.00nH 1.00nH 1.00nH C_pkg 1.00pF 1.00pF 1.00pF |************************************************************************** [PIN] signal_name model_name R_pin L_pin C_pin | 1 Vcc Power 2 GND GND 3 TX_P 2tap 4 TX_N 2tap Differential Pairs: [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max

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3 4 NA 0 0 0 Model 2tap and Driver Schedule: [Model] 2tap Model_type Open_drain | Vmeas = 1.2 Vref = 1.5 Rref = 50 Cref = 0.0 | | typ min max | C_comp 1pF 1pF 1pF [Voltage Range] 1.500V 1.50V 1.5V [Temperature Range] 60.0 110.0 -10.0 | [Driver Schedule] | | Model_name Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dly main 0.0ns NA 0.0ns NA boost NA 0.400ns NA 0.400ns | Main Driver: |*************************************************************************** [Model] main Model_type Open_drain | Vmeas = 0.9 Vref = 1.5 Rref = 50 Cref = 0.0 | | typ min max | C_comp 0pF 0pF 0pF [Voltage Range] 1.500V 1.50V 1.5V [Temperature Range] 60.0 110.0 -10.0 | Boost Driver: |*************************************************************************** |
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[Model] boost Model_type Open_drain | Vmeas = 1.4 Vref = 1.5 Rref = 50 Cref = 0.0 | | | C_comp [Voltage Range] [Temperature Range]

typ 0pF 1.500V 60.0

min 0pF 1.50V 110.0

max 0pF 1.5V -10.0

b. Translate to DML
Use ibis2signoise to translate ds_2tap.ibs to DML. (ds_2tap.dml) The following is the DML MacroModel section following translation:
(IbisIOCell (DS_2TAP_2tap (DelayMeasurementFixture (C 0) (R 50) (Threshold (maximum 1.200000e+000) (minimum 1.200000e+000) (typical 1.200000e+000)) (V 1.5)) (MacroModel (NumberOfTerminals 7) (Parameters (Buffers (DS_2TAP_2tap_BUFF DS_2TAP_2tap) (T001_BUFF DS_2TAP_main) (T002_BUFF DS_2TAP_boost)) (MinTypMaxParams (MTMSUBCKT (ftstype PullDownVIC)
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(maximum maximum) (minimum minimum) (typical typical)))) (SubCircuits .subckt DS_2TAP_2tap 1 2 3 4 5 6 7 ibis_file=TBD +DS_2TAP_2tap_BUFF=TBD +T001_BUFF=TBD +T002_BUFF=TBD +MTMSUBCKT=typical * Sources for enabling/disabling the individual bdrvr IV/VT curves von ON 0 1 voff OFF 0 0 * The main bdrvr, with PullUp and PullDown disabled. * Output drive is supplied by the Driver Schedule bdrvrs below. bdrvr_DS_2TAP_2tap 1 2 3 4 5 6 7 OFF OFF ON OFF file=ibis_file model=DS_2TAP_2tap_BUFF * This will call the correct typical, minimum, or maximum subckt. X_mintypmax 1 2 3 4 5 6 7 MTMSUBCKT +DS_2TAP_2tap_BUFF=DS_2TAP_2tap_BUFF +T001_BUFF=T001_BUFF +T002_BUFF=T002_BUFF +MTMSUBCKT=MTMSUBCKT * Definition of the typical mode subckt. .subckt typical 1 2 3 4 5 6 7 file=ibis_file +DS_2TAP_2tap_BUFF=TBD +T001_BUFF=TBD +T002_BUFF=TBD +MTMSUBCKT=typical * Sources for enabling/disabling the individual bdrvr IV/VT curves von ON 0 1 voff OFF 0 0

* [Driver Schedule] DS_2TAP_main 0.0ns NA 0.0ns NA * No pullup required

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* pulldown driver bdrvr_T001_PD 1 2 3 T001_PD_in 5 6 7 OFF ON OFF OFF file=ibis_file model=T001_BUFF c_compX=0 .node_param T001_PD_in NAME=(name(2) T001_PD_in) PRINT e_T001_PD_in T001_PD_in 3 pwl 4 3 delay=0.0000n datapoints vv 1 1 0 0 end vv * [Driver Schedule] DS_2TAP_boost NA 0.400ns NA 0.400ns * No pullup required * pulldown driver bdrvr_T002_PD 1 2 3 T002_PD_in 5 6 7 OFF ON OFF OFF file=ibis_file model=T002_BUFF c_compX=0 .node_param T002_PD_in NAME=(name(2) T002_PD_in) PRINT e_T002_PD_in T002_PD_in 3 pwl 4 3 delay=0.4000n datapoints vv 1 0 0 1 end vv .ends typical

3. Simulate in SigXp (DS_2tap.top)

Figures 2 through 4 illustrate the results of this process in SigXplorer and SigWave.

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Figure -2

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Figure -3

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Figure -4

Summary
Gigabit pre-emphasis can be modeled using IBIS. Given an understanding of IBIS [Driver Schedule], a main driver and boost drivers can be scheduled correctly for pre-emphasis efforts. Allegro PCB SI supports these IBIS models. It can perform analysis for pre-emphasis through topologies, nets, and boards.

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Contributors
Donald Telian Arpad Muranyi Michael Mirmak Lance Wang Technologist, Cadence Design System, IBIS Founder Sr. SI Engineer, Intel, IBIS Founder Sr. SI Engineer, Intel, IBIS Chair 2003-2005 Sr. Member Technical Staff, Cadence Design Systems

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