APPLICATION

NOTE
AP-415
Febiuaiy 1994
83C51FAFB
PCA Cookbook
BETSY JONES
FCO APPLICATIONS FNOINFFR
Order Number 270609-002
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COPYRIGHT INTEL CORPORATION 1996
83C51FAFB PCA
COOKBOOK
CONTENTS PAGE
PCA OVERVIEW 1
PCA TIMERCOUNTER 1
COMPARECAPTURE MODULES 3
CAPTURE MODE 5
Measuring Pulse Widths 5
Measuring Periods 7
Measuring Frequencies 7
Measuring Duty Cycles 9
Measuring Phase Differences 10
Reading the PCA Timer 13
COMPARE MODE 13
SOFTWARE TIMER 13
HIGH SPEED OUTPUT 15
WATCHDOG TIMER 18
PULSE WIDTH MODULATOR 19
CONCLUSION 21
APPENDICES
A Test Routines A-1
B Duty Cycle Calculation B-1
C Special Function Registers C-1
FIGURES PAGE
1 PCA TimerCounter and Compare
Capture Modules 1
2 PCA Interrupt 4
3 PCA Capture Mode 5
4 Measuring Pulse Width 5
5 Measuring Period 7
6 Measuring Frequency 7
7 Measuring Duty Cycle 9
8 Measuring Phase Differences 10
9 Software Timer Mode 13
10 High Speed Output Mode 15
11 Watchdog Timer Mode 18
12 PWM Mode 19
13 CCAPnH Varies Duty Cycle 20
LISTINGS PAGE
1 Measuring Pulse Widths 6
2 Measuring Frequencies 8
3 Measuring Duty Cycle 9
4 Measuring Phase Differences 11
5 Software Timer 14
6 High Speed Output (Without
Interrupt) 15
7 High Speed Output (With Interrupt) 16
8 High Speed Output (Single Pulse) 17
9 Watchdog Timer 19
10 PWM 21
TABLES PAGE
1 PCA TimerCounter Inputs 2
2 CMOD Values 2
3 CompareCapture Mode Values 3
4 PWM Frequencies 20
AP-415
This appIication note iIIustiates the diffeient functions
of the PiogiammabIe Countei Aiiay (PCA) which aie
avaiIabIe on the 83C51FA and 83C51FB. IncIuded aie
cookbook sampIes of code in typicaI appIications to
simpIify the use of the PCA. Since aII the exampIes aie
wiitten in assembIy Ianguage, it is assumed the ieadei is
famiIiai with ASM51. Foi fuithei infoimation on these
pioducts oi ASM51 iefei to the Fmbedded ContioIIei
Handbook (VoI. I).
PCA OVERVIEW
The majoi new featuie on the 83C51FA and 83C51FB
is the PiogiammabIe Countei Aiiay. The PCA pio-
vides moie timing capabiIities with Iess CPU inteiven-
tion than the standaid timei/counteis. Its advantages
incIude ieduced softwaie oveihead and impioved accu-
iacy.
The PCA consists of a dedicated timei/countei which
seives as the time base foi an aiiay of five compaie/
captuie moduIes. Figuie 1 shows a bIock diagiam of
the PCA. Notice that the PCA timei and moduIes aie
aII 16-bits. If an exteinaI event is associated with a
moduIe, that function is shaied with the coiiesponding
Poit 1 pin. If the moduIe is not using the poit pin, the
pin can stiII be used foi standaid I/O.
Fach of the five moduIes can be piogiammed in any
one of the foIIowing modes:
- Rising and/oi FaIIing Fdge Captuie
- Softwaie Timei
- High Speed Output
- Watchdog Timei (ModuIe 4 onIy)
- PuIse Width ModuIatoi.
AII of these modes wiII be discussed Iatei in detaiI.
Howevei, Iets fiist Iook at how to set up the PCA
timei and moduIes.
PCA TIMERCOUNTER
The timei/countei foi the PCA is a fiee-iunning 16-bit
timei consisting of iegisteis CH and CL (the high and
Iow bytes of the count vaIues). It is the onIy timei
which can seivice the PCA. The cIock input can be
seIected fiom the foIIowing foui modes:
- osciIIatoi fiequency
d
12 (Mode 0)
- osciIIatoi fiequency
d
4 (Mode 1)
- Timei 0 oveifIows (Mode 2)
- exteinaI input on P1.2 (Mode 3)
2706091
Figure 1 PCA TimerCounter and CompareCapture Modules
1
AP-415
The tabIe beIow summaiizes the vaiious cIock inputs foi each mode at two common fiequencies. In Mode 0, the
cIock input is simpIy a machine cycIe count, wheieas in Mode 1 the input is cIocked thiee times fastei. In Mode 2,
Timei 0 oveifIows aie counted aIIowing foi a iange of sIowei inputs to the timei. And finaIIy, if the input is exteinaI
the PCA timei counts 1-to-0 tiansitions with the maximum cIock fiequency equaI to x osciIIatoi fiequency.
Table 1 PCA TimerCounter Inputs
PCA TimerCounter Mode
Clock Increments
12 MHz 16 MHz
Mode 0 fosc 12 1 msec 075 msec
Mode 1 fosc 4 330 nsec 250 nsec
Mode 2 Timer 0 Overflows
Timer 0 programmed in
8-bit mode 256 msec 192 msec
16-bit mdoe 65 msec 49 msec
8-bit auto-reload 1 to 255 msec 075 to 191 msec
Mode 3 External Input MAX 066 msec 050 msec
In Mode 2 the overflow interrupt for Timer 0 does not need to be enabled
SpeciaI Function Registei CMOD contains the Count PuIse SeIect bits (CPS1 and CPS0) to specify the PCA timei
input. This iegistei aIso contains the FCF bit which enabIes an inteiiupt when the countei oveifIows. In addition,
the usei has the option of tuining off the PCA timei duiing IdIe Mode by setting the Countei IdIe bit (CIDL). This
can fuithei ieduce powei consumption by an additionaI 30%.
CMOD Counter Mode Register
CIDL WDTE CPS1 CPS0 ECF
Address
e
0D9H Reset Value
e
00XX X000B
Not Bit Addressable
NOTE
The user should write 0s to unimplemented bits These bits may be used in future MCS-51 products to invoke new features
and in that case the inactive value of the new bit will be 0 When read these bits must be treated as dont-cares
TabIe 2 Iists the vaIues foi CMOD in the foui possibIe timei modes with and without the oveifIow inteiiupt enabIed.
This Iist assumes that the PCA wiII be Ieft iunning duiing IdIe Mode.
Table 2 CMOD Values
PCA Count Pulse Selected
CMOD value
without interrupt enabled with interrupt enabled
Internal clock Fosc12 00 H 01 H
Internal clock Fosc 4 02 H 03 H
Timer 0 overflow 04H 05 H
External clock at P12 06 H 07 H
2
AP-415
The CCON iegistei shown beIow contains the Countei Run bit (CR) which tuins the timei on oi off. When the PCA
timei oveifIows, the Countei OveifIow bit (CF) gets set. CCON aIso contains the five event fIags foi the PCA
moduIes. The puipose of these fIags wiII be discussed in the next section.
CCON Counter Control Register
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
Address
e
0D8H Reset Value
e
00X0 0000B
Bit Addressable
The PCA timei iegisteis (CH and CL) can be iead and wiitten to at any time. Howevei, to iead the fuII 16-bit timei
vaIue simuItaneousIy iequiies using one of the PCA moduIes in the captuie mode and toggIing a poit pin in softwaie.
Moie infoimation on ieading the PCA timei is piovided in the section on the Captuie Mode.
COMPARECAPTURE MODULES
Fach of the five compaie/captuie moduIes has a mode iegistei caIIed CCAPMn (n
e
0,1,2,3,oi 4) to seIect which
function it wiII peifoim. Note the FCCFn bit which enabIes an inteiiupt to occui when a moduIes event fIag is set.
CCAPMn CompareCapture Mode Register
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Address
e
0DAH (n
e
0) Reset Value
e
X000 0000B
0DBH (n
e
1)
0DCH (n
e
2)
0DDH (n
e
3)
0DEH (n
e
4)
TabIe 3 Iists the CCAPMn vaIues foi each diffeient mode with and without the PCA inteiiupt enabIed, that is, the
inteiiupt is optionaI foi aII modes. Howevei, some of the PCA modes iequiie softwaie seivicing. Foi exampIe, the
Captuie modes need an inteiiupt so that back-to-back events can be iecognized. AIso, in most appIications the
puipose of the Softwaie Timei mode is to geneiate inteiiupts in softwaie so it wouId be useIess not to have the
inteiiupt enabIed. The PWM mode, on the othei hand, does not iequiie CPU inteivention so the inteiiupt is
noimaIIy not enabIed.
Table 3 CompareCapture Mode Values
Module Function
CCAPMn Value
without interrupt enabled with interrupt enabled
Capture Positive only 20H 21 H
Capture Negative only 10H 11 H
Capture Pos or Neg 30H 31 H
Software Timer 48H 49 H
High Speed Output 4C H 4D H
Watchdog Timer 48 or 4C H
Pulse Width Modulator 42 H 43H
3
AP-415
It shouId be mentioned that a paiticuIai moduIe can change modes within the piogiam. Foi exampIe, a moduIe
might be used to sampIe incoming data. InitiaIIy it couId be set up to captuie a faIIing edge tiansition. Then the same
moduIe can be ieconfiguied as a softwaie timei to inteiiupt the CPU at ieguIai inteivaIs and sampIe the pin.
Fach moduIe aIso has a paii of 8-bit compaie/captuie iegisteis (CCAPnH, CCAPnL) associated with it. These
iegisteis aie used to stoie the time when a captuie event occuiied oi when a compaie event shouId occui. Remem-
bei, event times aie based on the fiee-iunning PCA timei (CH and CL). Foi the PWM mode, the high byte iegistei
CCAPnH contioIs the duty cycIe of the wavefoim.
When an event occuis, a fIag in CCON is set foi the appiopiiate moduIe. This iegistei is bit addiessabIe so that event
fIags can be checked individuaIIy.
CCON Counter Control Register
CF CR CCF4 CCF3 CCF2 CCF1 CCF0
Address
e
0D8H Reset Value
e
00X0 0000B
Bit Addressable
These five event fIags pIus the PCA timei oveifIow fIag shaie an inteiiupt vectoi as shown beIow. These fIags aie not
cIeaied when the haidwaie vectois to the PCA inteiiupt addiess (0033H) so that the usei can deteimine which event
caused the inteiiupt. This aIso aIIows the usei to define the piioiity of seivicing each moduIe.
2706092
Figure 2 PCA Interrupt
An additionaI bit was added to the Inteiiupt FnabIe (IF) iegistei foi the PCA inteiiupt. SimiIaiIy, a high piioiity bit
was added to the Inteiiupt Piioiity (IP) iegistei.
IE Interrupt Enable Register
EA EC ET2 ES ET1 EX1 ET0 EX0
Address
e
0A8H Reset Value
e
0000 0000B
Bit Addressable
IP Interrupt Priority Register
PPC PT2 PS PT1 PX1 PT0 PX0
Address
e
0B8H Reset Value
e
X000 0000B
Bit Addressable
Remembei, each of the six possibIe souices foi the PCA inteiiupt must be individuaIIy enabIed as weII-in the
CCAPMn iegistei foi the moduIes and in the CCON iegistei foi the timei.
4
AP-415
CAPTURE MODE
Both positive and negative tiansitions can tiiggei a cap-
tuie with the PCA. This aIIows the PCA fIexibiIity to
measuie peiiods, puIse widths, duty cycIes, and phase
diffeiences on up to five sepaiate inputs. This section
gives exampIes of aII these diffeient appIications.
Figuie 3 shows how the PCA handIes a captuie event.
Using ModuIe 0 foi this exampIe, the signaI is input to
P1.3. When a tiansition is detected on that pin, the 16-
bit vaIue of the PCA timei (CH,CL) is Ioaded into the
captuie iegisteis (CCAP0H,CCAP0L). ModuIe 0s
event fIag is set and an inteiiupt is fIagged. The intei-
iupt wiII then be geneiated if it has been piopeiIy en-
abIed.
In the inteiiupt seivice ioutine, the 16-bit captuie vaIue
must be saved in RAM befoie the next event captuie
occuis, a subsequent captuie wiII wiite ovei the fiist
captuie vaIue. AIso, since the haidwaie does not cIeai
the event fIag, it must be cIeaied in softwaie.
The time it takes to seivice this inteiiupt ioutine detei-
mines the iesoIution of back-to-back events with the
same PCA moduIe. To stoie two 8-bit iegisteis and
cIeai the event fIag takes at Ieast 9 machine cycIes. That
incIudes the caII to the inteiiupt ioutine. At 12 MHz,
this ioutine wouId take Iess than 10 micioseconds.
Howevei, depending on the fiequency and inteiiupt Ia-
tency, the iesoIution wiII vaiy with each appIication.
Measuring Pulse Widths
To measuie the puIse width of a signaI, the PCA mod-
uIe must captuie both iising and faIIing edges (see Fig-
uie 4). The moduIe can be piogiammed to captuie ei-
thei edge if it is known which edge wiII occui fiist.
Howevei, if this is not known, the usei can seIect which
edge wiII tiiggei the fiist captuie by choosing the piop-
ei mode foi the moduIe.
Listing 1 shows an exampIe of measuiing puIse widths.
(Its assumed the incoming signaI matches the one in
Figuie 4.) In the inteiiupt ioutine the fiist set of cap-
tuie vaIues aie stoied in RAM. Aftei the second cap-
tuie, a subtiaction ioutine caIcuIates the puIse width in
units of PCA timei ticks. Note that the subtiaction
does not have to be compIeted in the inteiiupt seivice
ioutine. AIso, this exampIe assumes that the two cap-
tuie events wiII occui within 2
16
counts of the PCA
timei, i.e. ioIIoveis of the PCA timei aie not counted.
2706094
Time (Capture 2) b Time (Capture 1) e Pulse Width
Figure 4 Measuring Pulse Width
2706093
Figure 3 PCA Capture Mode (Module 0)
5
AP-415
Listing 1 Measuring Pulse Widths
_ RAN locations to store capture values
0AF1URE IA1A 0H
FUL$E lI1H IA1A 2H
FLA0 Bl1 20H.0
_
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1: _ lnitialize F0A timer
N07 0N0I, 00H _ lnput to timer 4 l/l2 X Fosc
N07 0H, 00H
N07 0L, 00H
_
_ lnitialize Nouule 0 in capture moue
N07 00AFN0, 2lH _ 0apture positive eue first
_ for measurin pulse wiuth
_
$E1B E0 _ EnaIle F0A interrupt
$E1B EA
$E1B 0R _ 1urn F0A timer on
0LR FLA0 _ clear test fla
_
_
_ Nain proram oes here
_
_
_ 1his example assumes Nouule 0 is the only F0A mouule
_ Iein useu. lf other mouules are useu, software must
_ check which mouules event causeu the interrupt.
_
F0A lR1ERRUF1:
0LR 00F0 _ 0lear Nouule 0s event fla
5B FLA0, $E00RI 0AF1URE _ 0heck if this is the first
_ capture or seconu
FlR$1 0AF1URE:
N07 0AF1URE, 00AF0L _ $ave l8-Iit capture value
N07 0AF1URE0l, 00AF0H _ in RAN
N07 00AFN0, llH _ 0hane mouule to now capture
_ fallin eues
$E1B FLA0 _ $inify lst capture complete
RE1l
_
$E00RI 0AF1URE:
FU$H A00
FU$H F$
0LR 0
N07 A, 00AF0L _ l8-Iit suItract
$UBB A, 0AF1URE
N07 FUL$E lI1H, A _ l8-Iit result storeu in
N07 A, 00AF0H _ two 3-Iit RAN locations
$UBB A, 0AF1URE0l
N07 FUL$E lI1H0l, A
_
N07 00AFN0, 2lH _ 0ptional~neeueu if user wants to
0LR FLA0 _ measure next pulse wiuth
F0F F$
F0F A00
RE1l
6
AP-415
Measuring Periods
Measuiing the peiiod of a signaI with the PCA is simi-
Iai to measuiing the puIse width. The onIy diffeience
wiII be the tiiggei souice foi the captuie mode. In Fig-
uie 5, iising edges aie captuied to caIcuIate the peiiod.
The code is identicaI to Listing 1 except that the cap-
tuie mode shouId not be changed in the inteiiupt iou-
tine. The iesuIt of the subtiaction wiII be the peiiod.
Measuring Frequencies
Measuiing a fiequency with the PCA captuie mode
invoIves caIcuIating a sampIe time foi a known numbei
of sampIes. In Figuie 6, the time between the fiist cap-
tuie and the Nth captuie equaIs the sampIe time T.
Listing 2 shows the code foi N
e
10 sampIes. Its as-
sumed that the sampIe time is Iess than 2
16
counts of
the PCA timei.
2706095
Time (Capture 2) b Time (Capture 1) e Period
Figure 5 Measuring Period
2706096
Time (Capture N) b Time (Capture 1) e T
Frequency e
N
T
e
of Samples
Sample Time
Figure 6 Measuring Frequency
7
AP-415
Listing 2 Measuring Frequencies
_ RAN locations to store capture values
0AF1URE IA1A 0H
FERl0I IA1A 2H
$ANFLE 00UR1 IA1A 4H
FLA0 Bl1 20H.0
_
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1:
_ lnitialization of F0A timer, Nouule 0, anu interrupt is the
_ same as in Listin l. Also neeu to initialize the sample
_ count.
_
N07 $ANFLE 00UR1, l0I _ R 4 l0 for this example
_
_
_ Nain proram oes here
_
_
_ 1his coue assumes only Nouule 0 is Iein useu.
F0A lR1ERRUF1:
0LR 00F0 _ 0lear mouule 0s event fla
5B FLA0, REX1 0AF1URE
_
FlR$1 0AF1URE:
N07 0AF1URE, 00AF0L
N07 0AF1URE0l, 00AF0H
$E1B FLA0 _ $inify first capture complete
RE1l
_
REX1 0AF1URE:
I5R7 $ANFLE 00UR1, EXl1
FU$H A00
FU$H F$
0LR 0
N07 A, 00AF0L _ l8-Iit suItraction
$UBB A, 0AF1URE
N07 FERl0I, A
N07 A, 00AF0H
$UBB A, 0AF1URE0l
N07 FERl0I0l, A
_
N07 $ANFLE 00UR1, l0I _ Reloau for next periou
0LR FLA0
F0F F$
F0F A00
EXl1:
RE1l
8
AP-415
The usei may instead want to measuie fiequency by
counting puIses foi a known sampIe time. In this case,
one moduIe is piogiammed in the captuie mode to
count edges (eithei iising oi faIIing), and a second mod-
uIe is piogiammed as a softwaie timei to maik the
sampIe time. An exampIe of a softwaie timei is given
Iatei. Foi infoimation on iesoIution in measuiing fie-
quencies, iefei to AiticIe Repiint AR-517, Using the
8051 MiciocontioIIei with Resonant Tiansduceis, in
the Fmbedded ContioIIei Handbook.
Measuring Duty Cycles
To measuie the duty cycIe of an incoming signaI, both
iising and faIIing edges need to be captuied. Then the
duty cycIe must be caIcuIated based on thiee captuie
vaIues as seen in Figuie 7. The same initiaIization iou-
tine is used fiom the pievious exampIe. OnIy the PCA
inteiiupt seivice ioutine is given in Listing 3.
2706097
Time (Capture 2) bTime (Capture 1)
Time (Capture 3) bTime (Capture 1)
e
pulse width
period
e duty cycle
Figure 7 Measuring Duty Cycle
Listing 3 Measuring Duty Cycle
_ RAN locations to store capture values
0AF1URE IA1A 0H
FUL$E lI1H IA1A 2H
FERl0I IA1A 4H
FLA0 l Bl1 20H.0
FLA0 2 Bl1 20H.l
_
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1:
_ lnitialization for F0A timer, mouule, anu interrupt the same
_ as in Listin l. 0apture positive eue first, then either
_ eue.
_
_
_ Nain proram oes here
_
_
_ 1his coue assumes only Nouule 0 is Iein useu.
F0A lR1ERRUF1:
0LR 00F0 _ 0lear Nouule 0s event fla
5B FLA0 l, $E00RI 0AF1URE
_
FlR$1 0AF1URE:
N07 0AF1URE, 00AF0L
N07 0AF1URE0l, 00AF0H
$E1B FLA0 l _ $inify first capture complete
N07 00AFN0, lH _ 0apture either eue now
RE1l
9
AP-415
Listing 3 Measuring Duty Cycle (Continued)
_
$E00RI 0AF1URE:
FU$H A00
FU$H F$
5B FLA0 2, 1HlRI 0AF1URE
0LR 0 _ 0alculate pulse wiuth
N07 A, 00AF0L _ l8-Iit suItract
$UBB A, 0AF1URE
N07 FUL$E lI1H, A
N07 A, 00AF0H
$UBB A, 0AF1URE0l
N07 FUL$E lI1H0l, A
$E1B FLA0 2 _ $inify seconu capture complete
F0F F$
F0F A00
RE1l
_
1HlRI 0AF1URE:
0LR 0 _ 0alculate periou
N07 A, 00AF0L _ l8-Iit suItract
$UBB A, 0AF1URE
N07 FERl0I, A
N07 A, 00AF0H
$UBB A, 0AF1URE0l
N07 FERl0I0l, A
N07 00AFN0, 2lH _ 0ptional reconfiure mouule to
0LR FLA0 l _ capture positive eues for next
0LR FLA0 2 _ cycle
F0F F$
F0F A00
RE1l
Aftei the thiid captuie, a 16-bit by 16-bit divide ioutine
needs to be executed. This ioutine is Iocated in Appen-
dix B. Due to its Iength, its up to the usei whethei the
divide ioutine shouId be compIeted in the inteiiupt iou-
tine oi be caIIed as a subioutine fiom the main pio-
giam.
Measuring Phase Differences
Because the PCA moduIes shaie the same time base,
the PCA is usefuI foi measuiing the phase diffeience
between two oi moie signaIs. Foi this exampIe, two
signaIs aie input to ModuIes 0 and 1 as seen in Figuie
8. Both moduIes aie piogiammed to captuie iising edg-
es onIy. Listing 4 shows the code needed to measuie the
diffeience between these two signaIs. This code does
not assume one signaI is Ieading oi Iagging the othei.
2706098
ABS Time (Capture 2) b Time (Capture 1) e Phase Difference
Figure 8 Measuring Phase Differences
10
AP-415
Listing 4 Measuring Phase Differences
_ RAN locations to store capture values
0AF1URE 0 IA1A 0H
0AF1URE l IA1A 2H
FHA$E IA1A 4H
FLA0 0 Bl1 20H.0
FLA0 l Bl1 20H.l
_
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1:
_ $ame initialization for F0A timer, anu interrupt as
_ in Listin l. lnitialize two F0A mouules as follows:
_
N07 00AFN0, 2lH _ Nouule 0 capture risin eues
N07 00AFNl, 2lH _ Nouule l same
_
_
_ Nain proram oes here
_
_ 1his coue assumes only Nouules 0 anu l are Iein useu.
F0A lR1ERRUF1:
5B 00F0, N0IULE 0 _ Ietermine which mouules
5B 00Fl, N0IULE l _ event causeu the interrupt
_
N0IULE 0:
0LR 00F0 _ 0lear Nouule 0s event fla
N07 0AF1URE 0, 00AF0L _ $ave l8-Iit capture value
N07 0AF1URE 00l, 00AF0H
5B FLA0 l, 0AL0ULA1E FHA$E _ lf capture complete on
_ Nouule l, o to calculation
$E1B FLA0 0 _ $inify capture on Nouule 0
RE1l
11
AP-415
Listing 4 Measuring Phase Differences (Continued)
N0IULE l:
0LR 00F l _ 0lear Nouule ls event fla
N07 0AF1URE l, 00AFlL
N07 0AF1URE l0l, 00AFlH
5B FLA0 0, 0AL0ULA1E FHA$E _ lf capture complete on
_ Nouule 0, o to calculation
$E1B FLA0 l _ $inify capture on Nouule l
RE1l
_
0AL0ULA1E FHA$E:
FU$H A00 _ 1his calculation uoes not
FU$H F$ _ have to Ie completeu in the
0LR 0 _ interrupt service routine
_
5B FLA0 0, N0I0 LEAIlR0
5B FLA0 l, N0Il LEAIlR0
_
N0I0 LEAIlR0:
N07 A, 0AF1URE l
$UBB A, 0AF1URE 0
N07 FHA$E, A
N07 A, 0AF1URE l0l
$UBB A, 0AF1URE 00l
N07 FHA$E0l, A
0LR FLA0 0
5NF EXl1
_
N0Il LEAIlR0:
N07 A, 0AF1URE 0
$UBB A, 0AF1URE l
N07 FHA$E, A
N07 A, 0AF1URE 00l
$UBB A, 0AF1URE l0l
N07 FHA$E0l, A
0LR FLA0 l
EXl1:
F0F F$
F0F A00
RE1l
12
AP-415
Reading the PCA Timer
Some appIications may iequiie that the PCA timei be
iead instantaneousIy as a ieaI-time event. Since the tim-
ei consists of two 8-bit iegisteis (CH,CL), it wouId noi-
maIIy take two MOV instiuctions to iead the whoIe
timei. An invaIid iead couId occui if the iegisteis ioIIed
ovei in the middIe of the two MOVs.
Howevei, with the captuie mode a 16-bit timei vaIue
can be Ioaded into the captuie iegisteis by toggIing a
poit pin. Foi exampIe, configuie ModuIe 0 to captuie
faIIing edges and initiaIize P1.3 to be high. Then when
the usei wants to iead the PCA timei, cIeai P1.3 and
the fuII 16-bit timei vaIue wiII be saved in the captuie
iegisteis. Its stiII optionaI whethei the usei wants to
geneiate an inteiiupt with the captuie.
COMPARE MODE
In this mode, the 16-bit vaIue of the PCA timei is com-
paied with a 16-bit vaIue pie-Ioaded in the moduIes
compaie iegisteis. The compaiison occuis thiee times
pei machine cycIe in oidei to iecognize the fastest pos-
sibIe cIock input, i.e. x osciIIatoi fiequency. When
theie is a match, one of thiee events can happen:
(1) an inteiiupt - Softwaie Timei mode
(2) toggIe of a poit pin - High Speed Output mode
(3) a ieset - Watchdog Timei mode.
FxampIes of each compaie mode wiII foIIow.
SOFTWARE TIMER
In most appIications a softwaie timei is used to tiiggei
inteiiupt ioutines which must occui at peiiodic intei-
vaIs. Figuie 9 shows the sequence of events foi the Soft-
waie Timei mode. The usei pieIoads a 16-bit vaIue in a
moduIes compaie iegisteis. When a match occuis be-
tween this compaie vaIue and the PCA timei, an event
fIag is set and an inteiiupt is fIagged. An inteiiupt is
then geneiated if it has been enabIed.
If necessaiy, a new 16-bit compaie vaIue can be Ioaded
into (CCAP0H, CCAP0L) duiing the inteiiupt iou-
tine. The user should be aware that the hardware tempo-
rarily disables the comparator function while these regis-
ters are being updated so that an invalid match will not
occur That is, a wiite to the Iow byte (CCAPn0) dis-
abIes the compaiatoi whiIe a wiite to the high byte
(CCAP0H) ie-enabIes the compaiatoi. Foi this ieason,
usei softwaie must wiite to CCAP0L fiist, then
CCAP0H. The usei may aIso want to hoId off any in-
teiiupts fiom occuiiing whiIe these iegisteis aie being
updated. This can easiIy be done by cIeaiing the FA bit.
See the code exampIe in Listing 5.
2706099
Figure 9 Software Timer Mode (Module 0)
13
AP-415
Listing 5 Software Timer
_ 0enerate an interrupt in software every 20 msec
_
_
_ Frequency 4 l2 NHz
_ F0A clock input 4 l/l2 x Fosc x l msec
_
_ 0alculate reloau value for compare reisters:
_ 20 msec
_ ------------- 4 20,000 counts
_ l msec/count
_
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1:
_ lnitialize F0A timer same as in Listin l
_ N07 00AFN0, 49H _ Nouule 0 in $oftware 1imer moue
N07 00AF0L, L0|20000, _ rite to low Iyte first
N07 00AF0H, Hl0H|20000,
_
$E1B E0 _ EnaIle F0A interrupt
$E1B EA
$E1B 0R _ 1urn on F0A timer
_
_
_ Nain proram oes here
_
_
F0A lR1ERRUF1:
0LR 00F0 _ 0lear Nouule 0s event fla
FU$H A00
FU$H F$
0LR EA _ Holu off interrupts
N07 A, L0|20000, _ l8-Bit Auu
AII A, 00AF0L _ Rext match will occur
N07 00AF0L, A _ 20,000 counts later
N07 A, Hl0H|20000,
AII0 A, 00AF0H
N07 00AF0H, A
$E1B EA
_ .
_ .
_ 0ontinue with routine
_ .
_ .
F0F F$
F0F A00
RE1l
14
AP-415
HIGH SPEED OUTPUT
The High Speed Output (HSO) mode toggIes a poit pin when a match occuis between the PCA timei and the pie-
Ioaded vaIue in the compaie iegisteis (see Figuie 10). The HSO mode is moie accuiate than toggIing pins in softwaie
because the toggIe occuis before bianching to an inteiiupt, i.e. inteiiupt Iatency wiII not effect the accuiacy of the
output. In fact, the inteiiupt is optionaI. OnIy if the usei wants to change the time foi the next toggIe is it necessaiy
to update the compaie iegisteis. Otheiwise, the next toggIe wiII occui when the PCA timei ioIIs ovei and matches
the Iast compaie vaIue. FxampIes of both aie shown.
27060910
Figure 10 High Speed Output Mode (Module 0)
Without any CPU inteivention, the fastest wavefoim the PCA can geneiate with the HSO mode is a 30.5 Hz signaI
at 16 MHz. Refei to Listing 6. By changing the PCA cIock input, sIowei wavefoims can aIso be geneiated.
Listing 6 High Speed Output (Without Interrupt)
_ Naximum output with H$0 moue without interrupts 4 0.5 Hz sinal
_ Frequency 4 l8 NHz
_ F0A clock input 4 l/4 x Fosc x 250 nsec
_
N07 0N0I, 02H
N07 0L, 00H
N07 0H, 00H
N07 00AFN0, 40H _ H$0 moue without interrupt enaIleu
N07 00AF0L, 0FFH _ rite to low Iyte first
N07 00AF0H, 0FFH _ Fl. will tole every 2
l8
counts
_ or l8.4 msec
_ Feriou 4 0.5 Hz
$E1B 0R _ 1urn on F0A timer
15
AP-415
In this next exampIe, the PCA inteiiupt is used to change the compaie vaIue foi each toggIe. This way a vaiiabIe
fiequency output can be geneiated. Listing 7 shows an output of 1 KHz at 16 Mhz.
Listing 7 High Speed Output (With Interrupt)
27060911
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1:
N07 0N0I, 02H _ 0lock input 4 250 nsec
N07 0L, 00H _ at l8 NHz
N07 0H, 00H
N07 00AFN0, 4IH _ Nouule 0 in H$0 moue with
N07 00AF0L, L0|l000, _ F0A interrupt enaIleu
N07 00AF0H, Hl0H|l000, _ t 4 l000 |arIitrary,
0LR Fl.
_
$E1B E0 _ EnaIle F0A interrupt
$E1B EA
$E1B 0R _ 1urn on F0A timer
_
_
_ Nain proram oes here
_
_
_ 1his coue assumes only Nouule 0 is Iein useu.
F0A lR1ERRUF1:
0LR 00F0 _ 0lear Nouule 0s event fla
FU$H A00
FU$H F$
0LR EA _ Holu off interrupts
N07 A, L0|2000, _ l8-Iit auu
AII A, 00AF0L _ 2000 counts later, Fl.
N07 00AF0L, A _ will tole
N07 A, Hl0H|2000,
AII0 A, 00AF0H
N07 00AF0H, A
$E1B EA
F0F F$
F0F A00
RE1l
16
AP-415
Anothei option with the HSO mode is to geneiate a singIe puIse. Listing 8 shows the code foi an output with a puIse
width of 20 msec. As in the pievious exampIe, the PCA inteiiupt wiII be used to change the time foi the toggIe. The
fiist toggIe wiII occui at time t. Aftei 80 counts of the PCA timei, 20 msec wiII have expiied, and the next toggIe
wiII occui. Then the HSO mode wiII be disabIed.
Listing 8 High Speed Output (Single Pulse)
27060912
0R0 0000H
5NF F0A lRl1
0R0 00H
5NF F0A lR1ERRUF1
_
F0A lRl1:
N07 0N0I, 02H _ 0lock input 4 250 nsec
N07 0L, 00H _ at l8 NHz
N07 0H, 00H
N07 00AFN0, 4IH _ Nouule 0 in H$0 moue with
N07 00AF0L, L0|l000, _ F0A interrupt enaIleu
N07 00AF0H, Hl0H|l000, _ t 4 l000 |arIitrary,
0LR Fl.
_
$E1B E0 _ EnaIle F0A interrupt
$E1B EA
$E1B 0R _ 1urn on F0A timer
_
_
_ Nain proram oes here
_
_
_ 1his coue assumes only Nouule 0 is Iein useu.
F0A lR1ERRUF1:
0LR 00F0 _ 0lear Nouule 0s event fla
5RB Fl., I0RE
_
FU$H A00
FU$H F$
0LR EA _ Holu off interrupts
N07 A, L0|30, _ l8-Iit auu
AII A, 00AF0L _ 30 counts later, Fl.
N07 00AF0L, A _ will tole
N07 A, Hl0H|30,
AII0 A, 00AF0H
N07 00AF0H, A
$E1B EA
F0F F$
F0F A00
RE1l
_
I0RE:
N07 00AFN0, 00H _ IisaIle H$0 moue
RE1l
17
AP-415
WATCHDOG TIMER
An on-boaid watchdog timei is avaiIabIe with the PCA
to impiove the ieIiabiIity of the system without incieas-
ing chip count. Watchdog timeis aie usefuI foi systems
which aie susceptibIe to noise, powei gIitches, oi eIec-
tiostatic dischaige. ModuIe 4 is the onIy PCA moduIe
which can be piogiammed as a watchdog. Howevei,
this moduIe can stiII be used foi othei modes if the
watchdog is not needed.
Figuie 11 shows a diagiam of how the watchdog woiks.
The usei pie-Ioads a 16-bit vaIue in the compaie iegis-
teis. Just Iike the othei compaie modes, this 16-bit vaI-
ue is compaied to the PCA timei vaIue. If a match is
aIIowed to occui, an inteinaI ieset wiII be geneiated.
This wiII not cause the RST pin to be diiven high.
In oidei to hoId off the ieset, the usei has thiee options:
(1) peiiodicaIIy change the compaie vaIue so it wiII
nevei match the PCA timei,
(2) peiiodicaIIy change the PCA timei vaIue so it wiII
nevei match the compaie vaIue, oi
(3) disabIe the watchdog by cIeaiing the WDTF bit be-
foie a match occuis and then ie-enabIe it.
The fiist two options aie moie ieIiabIe because the
watchdog timei is nevei disabIed as in option 3. If the
piogiam countei evei goes astiay, a match wiII eventu-
aIIy occui and cause an inteinaI ieset. The second op-
tion is aIso not iecommended if othei PCA moduIes aie
being used. Remembei, the PCA timei is the time base
foi all moduIes, changing the time base foi othei mod-
uIes wouId not be a good idea. Thus, in most appIica-
tions the fiist soIution is the best option.
Listing 9 shows the code foi initiaIizing the watchdog
timei. ModuIe 4 can be configuied in eithei compaie
mode, and the WDTF bit in CMOD must aIso be set.
The useis softwaie then must peiiodicaIIy change
(CCAP4H,CCAP4L) to keep a match fiom occuiiing
with the PCA timei (CH,CL). This code is given in the
WATCHDOO ioutine.
This ioutine shouId not be pait of an inteiiupt seivice
ioutine. Why! Because if the piogiam countei goes as-
tiay and gets stuck in an infinite Ioop, inteiiupts wiII
stiII be seiviced and the watchdog wiII keep getting ie-
set. Thus, the puipose of the watchdog wouId be defeat-
ed. Instead caII this subioutine fiom the main piogiam
within 2
16
count of the PCA timei.
27060913
Figure 11 Watchdog Timer Mode (Module 4)
18
AP-415
Listing 9 Watchdog Timer
lRl1 A10HI00:
N07 00AFN4, 40H _ Nouule 4 in compare moue
N07 00AF4L, 0FFH _ rite to low Iyte first
N07 00AF4H, 0FFH _ Before F0A timer counts up to
_ FFFF Hex, these compare values
_ must Ie chaneu
0RL 0N0I, 40H _ $et the I1E Iit to enaIle the
_ watchuo timer without chanin
_ the other Iits in 0N0I
_
_
_
_ Nain proram oes here, Iut 0ALL A10HI00 periouically.
_
_
_
A10HI00:
0LR EA _ Holu off interrupts
N07 00AF4L, 00 _ Rext compare value is within
N07 00AF4H, 0H _ 255 counts of the current F0A
$E1B EA _ timer value
RE1
PULSE WIDTH MODULATOR
The PCA can geneiate 8-bit PWMs by compaiing the
Iow byte of the PCA timei (CL) with the Iow byte of
the compaie iegisteis (CCAPnL). When
CL
k
CCAPnL the output is Iow. When
CL
t
CCAPnL the output is high.
To contioI the duty cycIe of the output, the usei actuaI-
Iy Ioads a vaIue into the high byte CCAPnH (see Figuie
12). Since a wiite to this iegistei is asynchionous, a new
vaIue is not shifted into CCAPnL foi compaiison untiI
the next peiiod of the output: that is, when CL ioIIs
ovei fiom 255 to 00. This mechanism piovides gIitch-
fiee wiites to CCAPnH when the duty cycIe of the
output is changed.
CCAPnH can contain any integei fiom 0 to 255, but
Figuie 13 shows a few common duty cycIes and the
coiiesponding vaIues foi CCAPnH. Note that a 0%
duty cycIe can be obtained by wiiting to the poit pin
diiectIy with the CLR bit instiuction. To caIcuIate the
CCAPnH vaIue foi a given duty cycIe, use the foIIow-
ing equation:
CCAPnH e 256 (1 - Duty Cycle)
wheie CCAPnH is an 8-bit integei and Duty CycIe is
expiessed as a fiaction.
27060914
Figure 12 PWM Mode (Module 0)
19
AP-415
27060915
Figure 13 CCAPnH Varies Duty Cycle
Table 4 PWM Frequencies
PCA Timer Mode
PWM Frequency
12 MHz 16 MHz
112 Osc Frequency 39 KHz 52 KHz
Osc Frequency 118 KHz 156 KHz
Timer 0 Overflow
8-bit 155 Hz 203 Hz
16-bit 006 Hz 008 Hz
8-bit Auto-Reload 39 KHz to 153 Hz 52 KHz to 203 Hz
External Input (Max) 59 KHz 78 KHz
20
AP-415
Listing 10 PWM
lRl1-FN:
$E1B Fl. _ For alternate function
N07 0N0I, 02H _ 0lock input 4 250 nsec at l8 NHz
N07 0L, 00H _ Frequency of output 4 l5.8 KHz
N07 0H, 00H
N07 00AFN0, 42H _ Nouule 0 in FN moue
N07 00AF0L, 00H
N07 00AF0H, l23I _ 50 percent uuty cycle
_
$E1B 0R _ 1urn on F0A timer
The fiequency of the PWM output wiII depend on
which of the foui inputs is chosen foi the PCA timei.
The maximum fiequency is 15.6 KHz at 16 MHz. Re-
fei to TabIe 4 foi a summaiy of the diffeient PWM
fiequencies possibIe with the PCA.
Listing 10 shows how to initiaIize ModuIe 0 foi a PWM
signaI at 50% duty cycIe. Notice that no PCA inteiiupt
is needed to geneiate the PWM (i.e no softwaie ovei-
head!). To cieate a PWM output on the 8051 iequiies a
haidwaie timei pIus softwaie oveihead to toggIe the
poit pin. The advantage of the PCA is obvious, not to
mention it can suppoit up to 5 PWM outputs with just
one chip.
CONCLUSION
This Iist of exampIes with the PCA is by no means
exhaustive. Howevei, the advantages of the PCA can
easiIy be seen fiom the given appIications. Foi exampIe,
the PCA can piovide bettei iesoIution than Timeis 0, 1
and 2 because the PCA cIock iate can be thiee times
fastei. The PCA can aIso peifoim many tasks that
these haidwaie timeis can not, i.e. measuie phase dif-
feiences between signaIs oi geneiate PWMs. In a sense,
the PCA piovides the usei with five moie timei/coun-
teis in addition to Timeis 0, 1 and 2 on the
8XC51FA/FB.
Appendix A incIudes test ioutines foi aII the softwaie
exampIes in this appIication note. The divide ioutine
foi caIcuIating duty cycIes is in Appendix B. And finaI-
Iy, Appendix C is a tabIe of the SpeciaI Function Regis-
teis foi the 8XC51FA/FB with the new oi modified
iegisteis boldfaced.
21
AP-415
APPENDIX A
TEST ROUTINES
27060916
A-1
AP-415
27060917
A-2
AP-415
27060918
A-3
AP-415
27060919
A-4
AP-415
27060920
A-5
AP-415
27060921
A-6
AP-415
27060922
A-7
AP-415
27060923
A-8
AP-415
27060924
A-9
AP-415
27060925
A-10
AP-415
27060926
A-11
AP-415
27060927
A-12
AP-415
27060928
A-13
AP-415
27060929
27060930
A-14
AP-415
27060931
27060932
A-15
AP-415
27060933
A-16
AP-415
27060934
A-17
AP-415
APPENDIX B
Duty Cycle Calculation
27060935
B-1
AP-415
27060936
B-2
AP-415
27060937
B-3
AP-415
APPENDIX C
A map of the SpeciaI Function Registei (SFR) space is
shown in TabIe A1. Those iegisteis which aie new oi
have new bits added foi the 83C51FA and 83C51FB
have been boldfaced.
Note that not aII of the addiesses aie occupied. Unoc-
cupied addiesses aie not impIemented on the chip.
Read accesses to these addiesses wiII in geneiaI ietuin
iandom data, and wiite accesses wiII have no effect.
Usei softwaie shouId not wiite 1s to these unimpIe-
mented Iocations, since they may be used in futuie 8051
famiIy pioducts to invoke new featuies. In that case the
ieset oi inactive vaIues of the new bits wiII aIways be 0,
and theii active vaIues wiII be 1.
Table A1 Special Function Register Memory Map and Values After Reset
F8 CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H FF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
F0 B F7
00000000
E8 CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L EF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
E0 ACC E7
00000000
D8 CCON CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF
00X00000 00XXX000 X0000000 X0000000 X0000000 X0000000 X0000000
D0 PSW D7
00000000
C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF
00000000 XXXXXXX0 00000000 00000000 00000000 00000000
C0 C7
B8 IP SADEN BF
X0000000 00000000
B0 P3 B7
11111111
A8 IE SADDR AF
00000000 00000000
A0 P2 A7
11111111
98 SCON SBUF 9F
00000000 XXXXXXXX
90 P1 97
11111111
88 TCON TMOD TL0 TL1 TH0 TH1 8F
00000000 00000000 00000000 00000000 00000000 00000000
80 P0 SP DPL DPH PCON 87
11111111 00000111 00000000 00000000 00XX0000
e Found in the 8051 core (See 8051 Hardware Description in the Embedded Controller Handbook for explanations of
these SFRs)
e See description of PCON SFR Bit PCON4 is not affected by reset
X e Undefined
C-1