CMOS IC Design Flow

The Study of Background Theory Schematic Level Design Schematic Level Simulation (Pre-Layout Simulation) Circuit Layout Layout Level Simulation (Post-Layout Simulation) IC Fabrication & Testing

CMOS Layout
Schematic Capture Real IC Structure What will we do during the Layout Procedure?
Drawing the layout of your circuit Design Rule Check Circuit and Parasitic Extraction Post-Layout Simulation

How to start with layout..

The Study of CMOS Structure A Copy of Layout Design Rules from IC foundry Familiar with the Design Tools

Poly-Silicon CMOS
Self-Alignment of Source, Drain and Gate

Poly-Silicon CMOS
p-substrate CMOS Structure (Cross Section)

Usually we study CMOS structure with its cross section, How about the plan view?

Poly-Silicon CMOS
p-substrate CMOS Structure (Plan View)

Why we need to study the plan view of a CMOS Process?

The Layout Process is done in plan view

CMOS Layout
Using Cadence Virtuoso Layout Editor The Drawing Sequence of Layers is arbitrary The Layout of PMOS and NMOS is nearly the same, with a little difference The mask definition for different technology is different We use AMS Tech CUP 0.6um CMOS Technology in this course

CMOS Layout (PMOS 6/0.6)

1. Choose the POLY1(dg) layer, with the help of ruler tool, draw a rectangle with size 6 * 0.6 um.

Defining the poly-gate of the PMOS

CMOS Layout (PMOS 6/0.6)

2. Choose the layer CONT(dg), check the minimum distance between POLY1 and CONT and the minimum DIFF enclosure of CONT from the Design Rule, Draw some CONT on the layout editor

CONT create some holes on the oxide layer for metals contact with the active area

CMOS Layout (PMOS 6/0.6)

3. Choose the layer DIFF(dg), draw the active area on the layout editor.

This step defines the active area of the PMOS

CMOS Layout (PMOS 6/0.6)

4. Check the minimum POLY1 extension of DIFF, use the stretch tool, modify the size of the poly-gate to fit the requirement.

The minimum extension mainly overcomes the misalignment of masks to avoid failure of device.

CMOS Layout (PMOS 6/0.6)

5. Choose the MET1(dg) Layer. Check MET1 minimum enclosure of CONT from the design rule, draw two metal strip on the layout editor.

This step tries to use the metal 1 layer to connect with the active area of the PMOS.

CMOS Layout (PMOS 6/0.6)

6. Choose the PPLUS(dg) Layer. Check the minimum PPLUS extension of DIFF, draw the PPLUS implantation mask.

The area with PPLUS layer will be implanted to p+ region to ensure ohmic contact between the metal and the substrate.

CMOS Layout (PMOS 6/0.6)

7. Choose the layer NTUB(dg), check the minimum NTUB enclosure of PDIFF from the design rule, draw a rectangle in NTUB layer.

PDIFF = the overlapping area of PPLUS and DIFF

CMOS Layout (PMOS 6/0.6)

8. Choose the Layer FIMP(dg), draw a rectangle exactly overlapped with NTUB. FIMP

The two layers NTUB and FIMP together forms the NWELL for the PMOS. These two layers must be exactly overlapped.

CMOS Layout (PMOS 6/0.6)

(Note: Step 9 Step 10 trying to draw the bulk pin of the PMOS, with the assumption that the bulk is connect to the source of the PMOS. If the bulk is not connected to source, you need to separate the DIFF of the contact to the PMOS) 9. Check from the design rule for the minimum PDIFFCON spacing to NDIFF, use the ruler to mark this position. PDIFFCON = CONT over PDIFF region

CMOS Layout (PMOS 6/0.6)

10. At the position located by step 9, draw a substrate contact formed by the four layers MET1, CONT, DIFF and NPLUS. You need to check the distance requirements from the design rule.

CMOS Layout (PMOS 6/0.6)

The last thing we need to connect the POLY gate with MET1

CMOS Layout (NMOS 6/0.6)

The Layout Procedure of a NMOS is similar to a PMOS, with the following difference:
No N-Well is needed for NMOS (i.e., no need to draw the mask NTUB and FIMP) The PPLUS and NPLUS implant is exchanged
i.e. PPLUS region NPLUS region NPLUS region PPLUS region

CMOS Layout (NMOS 6/0.6)

CMOS Layout
The size of the transistor is defined by the overlapping area between POLY1 and DIFF. Difference between NMOS and PMOS in a psubstrate n-well process:
1. PMOS requires a n-well, while NMOS not. 2. The bulk pin of all NMOS in the same die is the same potential, while PMOS is not.

Design Example: 2 to 1 MUX

Step 1: Schematic Level Design

F = A*S + B*NS NS = S

All PMOS and NMOS size are 6/0.6

Example: 2 to 1 MUX
Step 2: Layout Design We have PMOS and NMOS ready in previous slides. How to connect them?

Example: 2 to 1 MUX
Simply connect your nets use either POLY1 or MET1. If the connection cannot be done, then you may need MET2, MET3 or even more layers.

Example: 2 to 1 MUX
Complete Layout

Run DRC
DRC (Design Rule Check) Choose Assura Run DRC a DRC window will pop up. Use default setting and press OK. It will pop up Progress Form, press OK. The region which cannot passed DRC will be displayed with shining crosses.

Run LVS
LVS (Layout vs. Schematic) Before run RCX, you must run LVS to enable extract the RC Parasitic Choose Assura Run LVS, use the default setting in the pop window and press OK Press OK or Yes in the following pop windows You can get the LVS debug window. Or you can browse the choose Assura LVS debug ENV or LVS Error report

Run RCX (Parasitic extraction)

RCX (Resistor Capacitor eXtract) means Parasitic extraction You can choose Assura Run RCX, use the default setting in the pop window and press OK (you can choose the Rule Set as Typical or Worst Case by your requirement) It will generate the new view named av_extracted You can open the av_extracted view and press F to show data in this view.

Post layout Simulation

You will apply the symbol to simulate your design. Choose the Setup Environment in Analog Design Environment. And in Switch View List add the av_extracted that created by the Run RCX at the preview step. Other sets are same as the pre-layout simulation Then you can get the simulation result of the design.

Example2: inverter (schematic)

Inverter schematic

Example2: inverter (layout)

Inverter layout
You must add the pins of OUT, IN, VDD, GND by the layer of PIN M1

Example2: inverter (Run DRC)

Example2: inverter (Run DRC)

In Error layer Window, you can see the error list, and choose to the error place.

Example2: inverter (Run LVS)

Example2: inverter (Run LVS)

It will pop the some windows The LVS ENV can see the LVS errors

Example2: inverter (Run RCX)

Example2: inverter (Extracted view)

Example2: inverter (Post layout Simulation)

Test design example

Example2: inverter (Post layout Simulation)

Note: add av_extracted in Switch View List

Example2: inverter (Post layout Simulation)