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Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop Dynamic logic Multiple phase clock Clock distribution
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Clocked Systems
Most VLSI systems are a combination of
pipelines and finite state machines(FSM) Pipelined systems
Input D Q Logic D Q ... Logic D Q output
CLK
CLK
Comb. Logic
QD CLK or CLKS
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D Q
data
Ts: setup time -- the time before the clock edge during which the data input (D) has to be stable Th: hold time -- the time after the clock edge during which the data input (D) has to remain stable Tq: clock-to-Q delay -- The delay from the clock edge to the Q output
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clk D Q
clk
0 Q D 1 s CLK
D Q
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D QM Q
slave
clk=0
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System timing
(A) Positive-edge triggered
Tc
clock
Register A
Tq
Combinational Logic Td
Ts
Register B
Tq Td Ts
Tc >Tq + Td + Ts
(B) Alternatively, one may use latches as storage elements to save area.
clock
Latch A
Tq
Combinational Logic Td
Ts
Latch B
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clock
Tc1
Tco
Tc1>Tqa+Tda+Tsb Tsb=Tsc
Tqa
Tda Tsb Tqb Tdb Tsc
Tco>Tqb+Tdb+Tsc
If Tc=Tc1+Tco and Tc1=Tco, Tqa=Tqb, => The limit is Tc = Tda + Tdb + 2(Tq+Ts)
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M2
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1) C2=C1
C2
C1
C1 = C2
C2 C1
or
C2 = C1
C1 C2
L1
L2
Comb
Wrong only if Comb.
CLK
Logic
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clk
clk
clk
clk-in
clk
3.Very careful simulation(HSPICE) 4.Very small rise and fall time on the clock-- large buffer for large load 5.Multiple clocking strategies
clk
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or
D c lk c lk c lk
Transmission-gate latch
Q D
c lk
buffered input
VLSI System Design
(b)
DD
V
(c)
DD
V
DD
Q D
clk
-clk
SS
clk
-clk
clk
-clk
SS
SS
-clk
D clk clk clk Q clk
-clk
clk D -clk
clk Q
clk D -clk
clk Q
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-Q clk
D
-Q clk
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(a)
clk
-clk
clk
-clk
(b)
clk
-clk
clk
clk
-set -clk
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(a)
(b)
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clk D
D
clk
-clk Q
clk D -clk
-clk Q clk
-clk
-clk clk
(c)Tristate inverter
(d)master-slave F/F
(e)
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PLL techniques
(2)
bus high speed tristate bus
(3)
chip PLL /4
clock clock pad clock route dclk output pad dclk+dpad clock d clk
clock
system clock
Charge pump: charge or Discharge a capacitor according to D and U. Filter: filter the capacitor output (smoother). VCO: Change the oscillation frequency depending on the control voltage. (Voltage Control Oscillator)
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Phase Detector
F1
F1 16/8 16/8 16/8 16/8 16/8 UP 16/8
F2
16/8 16/8
F2 16/8
16/8 16/8
16/8 16/8 DN
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Charge Pump
40/2 P1 P-REF CHGUP N2 40/2 CHGDN N4 N-REF P-REF P1 40/2
SW0
2/5 2/5
N1
N3 10/2
IN
Bias circuit
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Filter
VCO
in 2/6 4/6
32/1
13stages
out
32/1
32/1
2400/6
2400/6
16/1 16/1
VCO
16/1 16/1
in
out
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Metastability Problem
D clk clk Q Q
clock 4ns delay 2ns Q -Q No Problem data
delay=2.2ns
If the setup or hold time is not satisfied, I.e., D changes at the activation edge of the clock, then the output Q will have a state depending on the timing relation between D and CLK
delay=2.3ns
Output error
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VB
Inv2
0V
VLSI System Design
2.5V
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clk
(b)
p-logic block
C2MOS latch
p-logic C2MOS latch block From n or buffered p-logic n-p CMOS clk logic stage
-clk logic
clk logic
clk -clk 0 1 1 0
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R1: During precharge, logicblocks must be switched off. R2: During evaluation, internal inputs can make only one transition. When a static logic is used in a N-P CMOS dynamic logic, it should be placed after dynamic logic (I.e., one should keep the static logic up to the C2MOS latch. Reason: static logic after creates a glitch at its output.
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R3: There exists in each logic block Reason: at least one dynamic gate that is separated from 1 1 or the previous C2MOS 2 output stage by an even number C MOS of inventions. clk or clk C2MOS R4: The total number of inversions or Domino between two consecutive C2MOS stage is even.
-clk clk clk -clk
clk
clk
OR
phi1 phi2
-phi2 phi2 DFF1 Q
skewed clokcs
C1
C2
C2
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-phi 2
D
DD
-V
tn Q DEF1A
Q
(a) phi1 phi 2
phi1
-phi1 D phi1
phi2
-phi 1
p leakers
-phi
2 n
D phi
n 1 phi2
phi2
DEF2 Both of these dynamic registers have to drive a local storage gate.
VLSI System Design
DEF3
clk (c)
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2. Dynamic logic
-phi1 from phi2 stage -phi1 phi1 n-logic -phi2 -phi2 phi1 n-logic to phi 1 phi2 stage phi2
phi1 phi1
phi1
evaluate phi1 logic precharge phi1 logic latch phi data 2 evaluate phi2 logic precharge phi2 logic latch phi1 data latch phi2 data
phi2
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Four-Phase clock
11 12 nonoverlapping 23 24
clk 1 clk 2 D clk 1 clk 3 n 1 clk 4 clk 3 in v2 clk 3 clk 34 clk 3 clk 1 Q clk 2 clk 3 clk 4
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Slave Latch
Logic
Master Latch
Logic
clk1
clk2
clk3
clk4
Clock distribution
n-bit datapath
n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath clock n-bit datapath delays have to match between stages n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath
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