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Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.


1. Explain the NMOS transistor fabrication process sequence based on wafer cross-section diagram shown in Figure 1.
Source Gate Drain Polysilicon SiO2

n+ p

n+ bulk Si

Figure 1 (12 marks, CLO2, JSP3.1, M) 2. Draw the physical structure of a Twin-tub CMOS transistor. (3 marks, CLO2, JSP3.2, L)

3. Explain the characteristic of a Twin-tub CMOS transistor. (3 marks, CLO2, JSP3.2, M)

4. What is the purpose of Well Tap and Substrate Tap in the physical structure of a CMOS inverter? (2 marks, CLO2, JSP3.3, L)

5. Explain the parasitic capacitance problem that exists in CMOS transistor operation. (5 marks, CLO2, JSP3.3, M)

6. Draw the physical structure of Silicon On Insulator (SOI). (3 marks, CLO2, JSP3.2, L) 7. Explain the characteristic of Silicon on insulator (SOI) CMOS transistor. (3 marks, CLO2, JSP3.2, M)

8. Explain the latch-up problem that exists in CMOS transistor operation. (5 marks, CLO2, JSP3.3, M) 9. Define Application-Specific Integrated Circuit (ASICs). (2 marks, CLO3, JSP4.1, L)

10. Discuss the advantages and disadvantages of Specific-Custom IC over Standard IC. (6 marks, CLO3, JSP4.1, H)

11. Compare the differences between Semi-Custom methodology and Full-Custom methodology. (6 marks, CLO3, JSP4.2, JSP4.3, H)

Department of Electrical Engineering Politeknik Port Dickson


PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.


12. Describe Standard Cell Library. (5 marks, CLO3, JSP4.5, L)

13. Discuss the advantages and disadvantages of Standard cells methodology. (6 marks, CLO3, JSP4.5, H)

14. Discuss at least 2 methods to increase the percentage of gate usage in gate array design. (4 marks, CLO3, JSP4.4, M)

15. Explain the advantages and disadvantages of full-custom methodology. (6 marks, CLO3, JSP4.2, M)

16. Explain the gate-array design floor plan with aid of a diagram. (7 marks, CLO3, JSP4.4, M)

17. Describe the design methodology selection criteria. (5 marks, CLO3, JSP4.6, H)

PREPARED BY: Course Lecturer

APPROVED BY: Head of Programme

Date:

Date:

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