Advanced Computer Architecture Fall 2012

Submitted By :

Iqbal Uddin Khan

Subject : Advanced Computer Architecture

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Advanced Computer Architecture Fall 2012

Introduction
The technological advancements and need of multi-dimensional computation lead us to the limits of Single processors processes and Single processor computing systems. From the birth of digital computing the processing techniques evolves rapidly from first generation to fifth or Artificial Intelligence generation. The computation its self was and is helpful to accelerates the innovation and advancement of computing power. After commercial and laboratory usage of computer adopted, the dependency on computer increases with the hunger of increase in computing power and reliability. The organizations, universities and research departments started using computer for deep and wide mathematical calculation instead of consuming brains power of researchers and staff. The increase of efficiency and power of digital computation helps the scientists and researchers to squeeze out the maximum from the digital architecture of a processor and leads towards the saturation of amendments of any processors architecture. Till the late 90s, processors architecture was modified from four bits to thirty two bits, memory increased form few words memory to few hundred megabytes of memory and system clock speed from few hundred kilo hertz to few hundred megahertz and so on. In the late 80s the researchers realized that with device characteristics approaching physical limits, parallel or distributed processing will be widely adopted as a promising approach for building high performance computing systems. The continued impetus in research in these areas arises from two factors: (a) the technological development in the area of VLSI designing and (b) the observation that significant exploitable software parallelism is inherent in many scientific and engineering applications [1]. The concept of parallel computing lead towards a new research ground and also enlighten the adoption of distributed computing, having either heterogeneous or homogenous environment. To have maximum from distributed or parallel computing environment, the communication or message passing should be efficient and with less communication overhead among systems or processors. The emergence of inter processor connection and communication is discussed in the next section.

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Advanced Computer Architecture Fall 2012

Inter Connection / Inter Connecting Networks

As we can hear or read the term Inter-Connection or Inter-connecting networks, when talking about the parallel processing or distributed computing environments. It is not that simple as connecting two or multiple entities. It is the ground which was active for researchers of Computer Science and Engineering fields in the era of 80s. There are books and thousands of research paper delivering their thoughts about how to connect multiple processors to build a single computing entity. In our further discussion we will refer Inter-Connecting Networks instead of Inter-Connection Networks. The Inter-connecting phenomenon is one of major difference between single and multiple processor architectures. It is differentiated over few attributes depending on connecting theory and connecting points available or its complexity. The Inter-connecting Networks can also be expressed in the term named Switching Fabric. To make understand lets have few lines on switching fabric, will generate the picture if Inter-Connecting network. Switching Fabric is an embedded system that receives data from its input and transmits it from a specific port build within it. Figure below illustrates the working of switching fabric as it receives data from input 0 to 4 and deliver it to a R G B C output port.

The switching fabric is independent of the bus technology used and infrastructure of system used to move data between nodes and also separate from the router. The term is sometimes used to mean collectively all switching hardware and software in a network [2].

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Advanced Computer Architecture Fall 2012 After having light on Switching Fabric, now we can visualize what could be an Inter-Connecting network and how it made possible the communication and message passing among multiple processors. Inter-Connecting can be categorized according to a number of attributes such as topology, routing strategy and switching technique. Inter-Connecting networks are generally buildup of switching elements. Topology is the pattern in which the individual switches are connected to other elements, like processors, memories and other switches [3]. Switching techniques / Topologies can be judge under the following classes: Direct topologies connect each switch directly to a node, while in indirect topologies at least some of the switches connect to other switches. Circuit switching, in which the entire path through the network is reserved before a message is transferred. Packet switching, with virtual cut through, in which a packet is forwarded immediately after it determines an appropriate switch output. Wormhole routing, which relaxes requirements of completely buffering of blocked packets in a single switch, typical for packet switching.

Now moving forward we take flow and reference from [4], to make and deliver the concept of Inter- Connecting Networks. In the next Section we will discuss in detail that what is Inter Connecting network and where and how it is used.

Description
The generic architecture of a Multi-processor system having Inter Connect is illustrated in figure next page. Here we assume that each processor module also consist of a Control unit, a small cache and an assigned Process. Processors are sharing the common Memory Modules (MM), Hard Disk and Common used IOs. Every module communicates with other via its respective Inter Connecting Module. Below are three acronyms used in figure on next page. PMIN - Processor to Memory Interconnection Network PIOIN - Processor to I/O Interconnection Network PPIN = Processor to Processor Interconnection Network

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Advanced Computer Architecture Fall 2012

Now after working out on the conceptual picture building of topic, we now discuss on the properties of Inter connecting Networks. We also mentioned few attributes regarding network properties but here we will discuss more explicitly. Below is the list of properties.

Topology
It indicated that how nodes are connected to each other, will be discussed later.

Network Diameter
The maximum hops between an t two farthest nodes in network.

Node Degree
Number of edges of other nodes connected with a node is called node degree. If the edge carries data from the node, it is called out degree and if this carries data into the node it is called in degree.

Bisection Bandwidth
Number of edges required to be cut to divide a network into two halves is called bisection bandwidth.

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Advanced Computer Architecture Fall 2012

Latency
Time elapsed to transfer a message from source node to destination node.

Network Throughput
The amount of traffic can flow through a network without congestion.

Routing Functions
The functions executed to generate path for data to deliver from source node to destination.

Hardware Cost
The cost involved in the implementation of an interconnection network. It includes the cost of switches, arbiter unit, connectors, arbitration unit, and interface logic.

Blocking and Non Blocking Network

In non-blocking networks the route from any free input node to any free output node can always be provided, no dedicated path for any specific traffic. In a blocking network simultaneous route establishment between a pair of nodes may not be possible.

Static and Dynamic Interconnecting Network

If the Inter Connecting pattern can be reconfigured upon need is said to be Dynamic or else vice versa.

In this part we will focus on different types of Inter Connecting schemes commonly known as topologies.

Fully connected
This is the most powerful interconnection topology. In this each node is directly connected to all other nodes. The shortcoming of this network is that it requires too many connections. In figure below PE is acronym of Processing Elements.

Cross Bar
The crossbar network is the simplest interconnection network. It has a two dimensional grid of switches. It is a non-blocking network and provides connectivity between inputs and outputs and it is possible to join any of the inputs to any output. First figure is the distinctive figure for cross bar switch and other is the internal connections concept of cross bar switch.
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Advanced Computer Architecture Fall 2012

Linear Array
This is a most fundamental interconnection pattern. In this processors are connected in a linear one-dimensional array. This concept is illustrated in the figure below.

Mesh
It is a two dimensional network. In this all processing elements are arranged in a two dimensional grid. The processor in rows i and column j are denoted by PEi. Illustration is below.

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Advanced Computer Architecture Fall 2012

Ring
This is a simple linear array where the end nodes are connected. It is equivalent to a mesh with wrap around connections. The data transfer in a ring is normally one direction.

Torus
The mesh network with wrap around connections is called Tours Network.

Tree interconnection network

In the tree interconnection network, processors are arranged in a complete binary tree pattern.

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Advanced Computer Architecture Fall 2012

Fat tree
It is a modified version of the tree network. In this network the bandwidth of edge or the connecting wire between nodes increases towards the root of network.

Following are the seven issues, must be considered when designing any Inter Connecting Network. 1) Dimension and size of network: It should be decided how many PEs are there in the network and what the dimensionality of the network is i.e. with how many processor are connected to each other. 2) Symmetry of the network: It is important to consider whether all processors are connected with same number of processing elements, or the processing elements of corners or edges have different number of adjacent elements. 3) What is data communication strategy: Whether all processors are communicating with each other in one time unit synchronously or asynchronously on demand basis. 4) Message Size: What is message size and How much data a processor can send in a unit time. 5) Start up time: What is the time required to initiate the communication process. 6) Data transfer time: How long does it take for a message to reach to another processor. Whether this time is a function of link distance between two processors or it depends upon the number of nodes coming in between. 7) The interconnection network is static or dynamic: That means whether the configuration of interconnection network is governed by algorithm or the algorithm allows flexibility in choosing the path.
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Advanced Computer Architecture Fall 2012

There is still lot to discuss about inter - connecting Networks, few topologies are not discussed, and regarding the domain of Multi-processor computing different examples are also missing. But all the above discussed is in the light of references mentioned specially reference 4, which helps us to clearly understand the Inter connecting phenomenon. In the present, the Inter Connecting is truly dynamic and reconfigurable in FPGAs by the user or programmers. Where, from each wire to routing block is configurable according to the desire of programmer.

1. Performance of Multiprocessor Interconnection Networks. Laxmi N. Bhuyan, Qing Yang and Dharma P. Agrawal. 2. http://searchstorage.techtarget.com/definition/switching-fabric 3. http://www.icsr.agh.edu.pl/publications/html/ppam97prof/node7.html 4. http://vedyadhara.ignou.ac.in/wiki/images/6/63/B1U3mcse-011.pdf

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