Advanced Digital-Radio Baseband Processor

A Software-Defined Radio Baseband Processor IC

INNOVATIONS INV/TwoWay/981/1 March 2004

Combination Full-Duplex Voice-Codec and Digital Signal Processor IC A-to-D and D-to-A Interfaces

n Software-Defined Radio (SDR) Processor IC n Multi-Mode Digital/Analogue PMR and Trunked Radio n High Integration Saves Cost, Space, Power

and Design Time

n Programmable Flexibility Enables Use in Many Radio Systems n Transmit and Receive Analogue and Digital Processing

- Tx and Rx programmable multi-tap FIR filters

n Exceptional Rx SINAD Performance n Full-Duplex Voice Codec with Input and Output Gain Setting

and Speaker/Earpiece Power Amplifiers

n Flexible Serial Interfaces for Multi-Processor

Operation
n Auxiliary ADCs and DACs for Ancillary Radio

Functions
n Autonomously Performs Many Critical DSP

Intensive Functions
n Low-Power 2.5V Operation n EV9810 EvKit Available
CML Microcircuits
COMMUNICATION SEMICONDUCTORS

SUITABLE APPLICATIONS TETRA - APCO25 - Tetrapol - RCR STD-39 - ARIB STD-T61 - ARIB STD-T85 . . . . and many other digital radio systems Two-Way Radio

Digital Radio*

- Communicate with CML RF Modulator

Voice Coder Channel Coding, TDMA Frame Formatting
p /4 DQPSK
RRC DAC

Narrowband digital radio systems provide many advantages over traditional analogue FM approaches. By implementing error correction, a digital system can consistently maintain a respectable operating range even in the presence of significant interference. The majority of current PMR and trunked digital radio systems deal not only in voice transactions, but also in data, video and still graphics; all within a fixed bandwidth. In the case of voice transactions over a digital system, the digital radio system can provide high-quality voice output, even in high noise environments.
Processing

'I'
90

Cartesian Loop Linear PA

ADC

Voice Filter

RRC

DAC

'Q'

Carrier Oscillator

Local Oscillator RF Amp

Oscillator
DAC ADC

IF Amp Bandpass Filter

90

'I'

DAC

ADC

Tx Radio Interface

Mod. and RF Tx Battery

'Q'

Tx Audio Interface C and/or DSP Rx Audio Interface Rx Radio Interface Ancillary Tx Radio Analogue Interface Interfaces

PA Temp. PA Power AGC RSSI RF Rx, IF and Demod.

DAC

A theoretical narrowband digital radio implementation

Voice Filter

Voice Decoder p pi/4 DQPSK Demodulator, Channel Decoder, TDMA Framing

RRC

ADC

'I'

RRC

ADC

'Q' CMX981 element

CMX981 within a typical (TETRA) digital radio - the CMX981 performs the majority of baseband processes

Narrowband Digital Radio Standards

High Performance Digital Radio voice designs rely on a DSP to perform many of the signal control, encoding, interfacing, routing, level and shaping tasks. The CMX981 is a truly universal in-phase and quadrature (I and Q) compatible digital radio baseband processor and voice-codec that can be used with many types of analogue and digital modulation schemes. With its flexibility, via software definition, the CMX981 can be used in many types of system, including those operating in: AM and FM modes, and using QAM, BPSK, QPSK, pi/4 DQPSK and FSK modulation schemes. The CMX981 goes many steps further in the provision, on chip, of the majority of baseband and system interfacing: voiceband digital-to-analogue and analogue-to-digital conversion, Rx and Tx signal shaping via multi-tap digital FIR filters and pi/4 DQPSK modulation. Included on chip is a voice-codec section with gain control and loudspeaker and earphone amplifiers. In addition to baseband signal path processing, the CMX981 offers auxiliary D-to-A and A-to-D functions for the interfacing of other radio operations. The integration of signal processing functions digitally within the CMX981 reduces the load requirements on the host DSP and C, thus allowing the selection of a lower cost, lower speed and lower powered DSP/C, and releasing the host controllers time and power for other tasks. The CMX981s default filter co-efficients are aimed at the TETRA standard, but this versatile baseband IC can be programmed to operate in many other radio voice and high-speed data systems. Direct access is available for writing to the I and Q Tx filters; additionally, the pi/4 DQPSK modulator can be bypassed to allow formatted data to be written directly to the signal path. Flexible clock dividers allow different voice codec and signal codec rates to be accommodated. TETRA: TErrestrial Trunked RAdio is an open digital trunked radio standard defined by the European Telecommunications Standardisation Institute (ETSI) to meet the needs of digital, cellular, trunked radio networks. TETRA systems have been, to-date, designed and developed notably as a mobile system for handling emergency and safety tasks and is widely established in over 55 countries. APCO 25 (P25) is an open digital radio standard suite specified for high-performance public safety radio applications in North America. Supporting both voice and data services the suite includes several American National Standards Institute (ANSI) approved technical standards developed by the TIA TR-8 Committee and its subcommittees. P25 Phase 1 radios support both digital and analog FM modulation so they interoperate with legacy analog FM equipment. Spectral efficiency is 1 voice per 12.5kHz RF bandwidth. P25 Phase 2 radios provide 1 voice per 6.25kHz RF bandwidth. In certain public safety bands, FCC rules now require that radios support P25 interoperability mode. Tetrapol is a digital trunked radio system based on FDMA access and GMSK modulation. Like its competitor, TETRA, Tetrapol is widely used in a large number of countries, predominately in Europe. RCR STD-39 is the standard for 400MHz professional digital mobile communication systems including TDMA public radio in Japan. ARIB STD-T61 is the standard for 800MHz digital MCA systems in Japan using p/4 shift QPSK for land vehicles such as taxis. ARIB STD-T85 is the standard for 400MHz and 150MHz Japanese professional digital mobile communication systems, including SCPC public radio.

*For the purposes of this Innovations document, discussions centre around narrowband public and
private mobile and trunked radio systems. Other radio systems can employ the CMX981.

Contents

- Digital Radio 2 - Operational Functions 3 - Voice Codec 4 Transmit 5 - Receive 6 - Control; Power; Interface 7 - Package and Evaluation outside back cover -

2 2

Operational Functions
Microphone 1 Microphone 2

VSSPA

Loudspeaker VDDPA

Earpiece

VSSPA

AUXDAC4

AUXDAC3

AUXDAC2

AUXDAC1

Master (MCLK) Clock In (up to 10MHz)

CLOCK GEN
Serial Interface Clock (Out) (MCLK MCLK/2 MCLK/4)

CLOCKS

Select 0/20dB
0 to 22.5dB 1.5dB Step

10-bit DAC
0 or 6 dB 0 or 6 dB

10-bit DAC

10-bit DAC

10-bit DAC

Decimation Filter

Bandpass Filter S-D

ADC

Symbol Clock (18kHz) N_IRQ1 N_IRQ2 N_RESET CBUSEN

Tx (encode)
Control

PAs
-12.5 to -27.5dB 1dB Step

Sidetone

10-bit ADC
AUXADC1 0 to -30dB 2dB Step

SRAM

AUXADC2 AUXADC3
MUX

Interpolation Filter

Bandpass Filter

S
S-D Tone Generator

DAC

Rx (decode)
Fast Serial Port 1 / C-BUS
CMDFS/CCLK

Ancillary Functions
(analogue interfaces) (Rx and Tx audio interface)

Sample and Hold

AUXADC4 AUXADC5 AUXADC6

Linear Voice Codec

To and From Host C or DSP

CMDDATI/CDATA CMDRDFSI/CSN

CMDRDDATI/RDATA

Interface, Test, Coefficient and Control Data

Control and Routing

18kSymbol/sec

ITXP

CMDFS2

Fast Serial Port 2

36kb/sec Data

16 x 4 FIFO

p pi/4 DQPSK Modulator

18kSymbol/sec for each channel

I Q

I Q
RRC Filter (63-tap FIR)

RRC Filter (79-tap FIR)

I Q Gain, Phase,
Ramping, and Offset Adjustment

Q
SD

I
DAC Logic

I Q

SD

Reconstruction Filter

I Q

ITXN

QTXP

CMDDAT2 CMDRDFS2 CMDRDDAT2

Direct Write Access Point

1
Tx Data Access Point

14-bit DAC

QTXN

Ctrl Rx/Tx loopback (test and monitor)

4
Tx/Rx loopback (test and monitor)

TXFS

I
Fast Serial Port 3

IRXP

TXDAT

Rx DATA
144kSample/sec for each channel

RXFS RXDAT

RRC Filter (63-tap FIR)

I Q Low Pass

Q
144kSample/sec for each channel

Filter (63-tap FIR)

Gain and Offset Adjustment

I
SD

Q I Q

0 1 2

Decimation Filter and Vernier Control

I Q

IRXN

Anti-alias Filter

QRXP

16-bit ADC

QRXN

Serial Interfaces
VDDRX VDDTX

Receive Channel
(Rx radio interface)

Ctrl

Supply Inputs
VDDIO VDDAUX VDDVC VDDD VDDD BIAS1 BIAS2 VSSD VSSD VSSD VSSVC VSSAUX VSSTX VSSRX

- Give us the signal - Let us do the rest -

I and Q Inputs from Demodulator

2.304Mb/sec for each channel

I and Q Outputs to Modulator

Transmit Channel
(Tx radio interface)

144kSample/sec for each channel

144kSample/sec for each channel

Voice Codec
n Encode (Tx) analogue-to-digital conversion with coarse and fine level
control

n Decode (Rx) digital-to-analogue conversion with level control plus earpiece

and loudspeaker PAs

n Sidetone facility with level adjust n Call/user tones available to Rx path n Selectable clock/sample rates

Encode (Tx) Path

n n n n n
Earpiece VDDPA VSSPA

Microphone 1

Microphone 2

Loudspeaker VSSPA
0/20dB
0 to 22.5dB 1.5dB Step

Select

Dual selectable differential microphone sources Input amp with selectable gain: 0db, 20dB and mute Fine gain control with 22.5dB range 14-bit Sigma-Delta analogue-to-digital conversion Digital encode bandpass filter conforms to CCITT G.712 standard; with selectable highpass section n Decimation filter provides (8kHz) data suitable for radio system signal formatting process

Decimation Filter

Bandpass Filter S-D

ADC

0 or 6 dB

0 or 6 dB

Control and Routing

Tx
Sidetone

PAs
-12.5 to -27.5dB 1dB Step

Separate Rx and Tx Paths

n Controlled by host via internal registers n Configurable to full-duplex operation

0 to -30dB 2dB Step

Interpolation Filter

Bandpass Filter

S
S-D Tone Generator

DAC

Decode (Rx) Path

n Data written via serial interface interpolated to 32kHz n Digital decode bandpass filter conforms to CCITT G.712 standard; with selectable highpass section n Level and period adjustable ring-tone generator (0 to 4 kHz) and programmable sidetone path available n 14-bit Sigma-Delta digital-to-analogue conversion n Fine gain control with 0 to -30 dB range n Two selectable output driver (0 or 6 dB) amps: - Differential speaker (130mW into 8W ) - Single-ended earpiece (16.5mW into 32W )

Rx

Linear Voice Codec

The digitizing voice codec of the CMX981 converts voice signals to and from digital form and can be configured to apply a digital voice filter to meet the G.712 standard. The encode path (Tx) accepts a differential analogue audio input signal, converts it into digital form and then applies digital filtering to produce a processed data stream. The decode path (Rx) accepts a digital stream written to the serial interface, applies digital filtering, converts the result to an analogue signal, and presents the audio at either differential speaker or single-ended earphone driver outputs. Additionally a sidetone path and audio tones can be programmed. The inclusion of this audio/digital interface facility on-chip minimizes the need for additional areas of PCB and the attendant external components; on chip processing in this section reduces the host C/DSP hardware, software, capacity and power requirements.

Transmit Section
n n n n n n n
pi/4 DQPSK modulation Accurate controllable filtering Channel gain, phase and offset manipulation Analogue reconstruction Transmit data access Programmable clock/sample rates Programmable output signal ramping
The transmit section of the CMX981 accepts the data stream from the host processor, via the serial interface, and passes it through the pi/4 DQPSK modulator. I and Q data streams from the modulator are applied to the relevant channel multi-tap digital filter to provide shaping in accordance with the RF channel requirements. The availability of gain, phase and offset adjustments allow the dynamic compensation of RF hardware and transmission channel anomalies. To minimise the generation of spurii at Tx on and off, the signal level of each channel can be ramped up (and down) at a programmed rate. Both channel signals are reconstructed via digitalto-analogue converters and lowpass filters before being made available as differential analogue outputs to the RF modulator. Provision is made, to each digital channel, to allow the input of data streams after the pi/4 DQPSK modulator for use with systems using alternative modulation schemes. As a system check, Tx and Rx loopback test and monitor paths are available. Note that the 18ksymbols/sec rate is suitable for TETRA use. Other rates may be programmed for use in other systems.

Channel Gain, Phase and Offset Adjust

n Independent (I and Q) channel attenuation is programmable - channel phase inversion is facilitated n Phase pre-distortion provides compensation for non-orthogonal carrier-phase in the RF modulator n Independent I and Q digital offset correction for analogue Tx path offsets - I or Q advance or retard

pi/4 DQPSK Modulation

n Symbol data from external processes via serial port n 4-word deep FIFO n Bypassable pi/4 DQPSK modulator provides encoded I and Q values for each input phase

Interface, Test, Coefficient and Control Data

Control and Routing

Transmit Channel
18kSymbol/sec DATA

Serial Interfaces

ITXP

Tx DATA
36kb/sec

16 x 4 FIFO

pi/4 DQPSK p Modulator

Q
18kSymbol/sec for each channel

I Q

I Q
RRC Filter (63-tap FIR)

RRC Filter (79-tap FIR)

Q Gain, Phase,
Ramping, and Offset Adjustment

Q
DS
144kSample/sec for each channel

I
DAC Logic

I Q

DS

Reconstruction Filter

I Q

ITXN

4 4

QTXP QTXN

14-bit DAC

144kSample/sec for each channel

Rx/Tx loopback (test and monitor)

Ctrl

Tx/Rx loopback (test and monitor)

Transmit Data Access

n Read and write functions - Read the I or Q signal value at that point - Write data directly into the Sigma-Delta DAC for other modulation schemes n Direct write access to the I or Q inputs of the FIR filters for the insertion of data

Accurate, Controllable Filtering

n Programmable multi-tap FIR filters for both (I and Q) channels provide stopband rejection and Root Raised Cosine (RRC) shaping n Alternative FIR coefficients can be programmed via serial interface

Analogue Reconstruction Programmable Output Ramping

n Two modes of Tx output signal-ramping are available: Linear or Sigmoidal n Both amplitude ramp-up and ramp-down actions are programmable n Low distortion 14-bit Sigma-Delta digital-to-analogue conversion n Switched capacitor lowpass filters shape I and Q outputs to RF modulator n Tx/Rx and Rx/Tx loopback facilities for test and monitoring

I and Q Outputs to Modulator

Direct Write - for alternative modulation inputs Access Points

Tx Data Access Points

Receive Section
n n n n n
Analogue-to-digital conversion Exceptional SINAD performance Dynamic signal manipulation Digital processing Programmable clock dividers
The receive section of the CMX981 accepts the demodulated I and Q output signal from the radio section via differential channel inputs. In-band pick-up is minimized using this input method. Sampling frequency rejection is carried out by the bypassable anti-alias filter. The following Sigma-Delta analogue-to-digital converter displays extremely low distortion and a dynamic range in excess of 90dB. Gain and offset adjustment is available, to each channel, to set the dynamic range of data within the channel and to remove system generated offsets; phase inversion is available. The two channels are independently programmable thus allowing differential gain corrections within the digital domain. Digital filtering is applied to the data by two cascaded multi-tap FIR filters which enhance stopband rejection and provide a programmed shape (the default is an RRC response) and reduce the reliance on analogue components. The CMX981 processed Rx data is then available to the system processor/s; demodulation, would typically be performed by an external DSP.

Analogue-to-Digital
n Differential analogue I and Q inputs n Selectable anti-alias filters exhibit high sampling frequency rejection n Wide range, low-distortion Sigma-Delta analogue-to-digital conversion provides I and Q single bits for processing

Dynamic Signal Manipulation

n Dynamic gain adjustment with signal phase inversion if required n System offsets can be stabilised
Interface, Test, Coefficient and Control Data
Tx/Rx loopback (test and monitor) Rx/Tx loopback (test and monitor)

Control and Routing

Serial Interfaces

I
Rx DATA
144kSample/sec for each channel

IRXP

I Q Low Pass
Filter (63-tap FIR)
144kSample/sec for each channel

RRC Filter (63-tap FIR)

Gain and Offset Adjustment

I
SD

Q I Q

0 1 2

Decimation Filter and Vernier Control

I Q

IRXN

Anti-alias Filter

QRXP QRXN

16-bit ADC

Receive Channel

Ctrl

Digital Processing
n Programmable multi-tap low-pass and RRC FIR decimation filters provide pre-process shaping n I and Q channels are independently programmable n Rx/Tx and Tx/Rx loopback facilities for test and monitoring

I and Q Inputs from Demodulator

2.304Mb/sec for each channel

Control; Power; Interface

Master Clock (MCLK) In (up to 10MHz)

MCLK SClk

CLOCK GEN
Serial Interface Clock Out MCLK MCLK/2 MCLK/4

CLOCKS

n n n n

Versatile Processor Interfaces Control and Programming Individual Power Rails Ancillary Functions
10-bit DAC 10-bit DAC 10-bit DAC 10-bit DAC
AUXDAC4

AUXDAC3

AUXDAC2

AUXDAC1

Serial Interfaces
Symbol Clock (18kHz)

N_IRQ2 N_RESET CBUSEN

Control

N_IRQ1

Versatile Processor Interfaces

n C-BUS and Fast serial interfaces provide adaptable control and data paths to cater for multi-processor (C or DSP) systems n Selectable interface serial-clock rate: MCLK, MCLK/2, MCLK/4 n Bi-directional operation n Hardware interlock modes n Automatic powersave mode
10-bit ADC
AUXADC1

SRAM

AUXADC2 AUXADC3

MUX

Ancillary Functions
CMDFS/CCLK

Fast Serial Port 1 / C-BUS

Control and Programming

n Tx, Rx and codec sample rates are independently programmable n Versatile clock division permits a wide range of sample rates to suit different data rates and system requirements

Sample and Hold

AUXADC4 AUXADC5 AUXADC6

To and From Host C or DSP

CMDDATI/CDATA CMDRDFSI/CSN

Interface, Test, Coefficient and Control Data

Control and Routing

CMDRDDATI/RDATA

Ancillary Functions
n Programming and control is via internal registers from the serial interface/s n Four 10-bit monotonic digital-to-analogue converters to assist in external control functions n Additionally, one DAC output is available to enable sequenced power ramping of the RF output - the ramp profile is programmable n A multi-input multiplexed analogue-to-digital converter, with sample and hold facility for external monitoring

CMDDAT2 CMDRDFS2 CMDRDDAT2

TXDAT RXFS RXDAT

Fast Serial Port 3

TXFS

Fast Serial Port 2

CMDFS2

Individual Power Supply Rails

n n n n 2.25 to 2.75 volt range with 3.3 volt tolerant interface circuits Separate interface power rail Analogue and digital supply separation Separate isolated power-pins help maintain low noise design - Analogue and digital - Voice codec - Interface - Ancillary functions n Separate analogue and DAC reference levels (VBIAS)

Supply Inputs

VDDRX

VDDTX

VDDIO

VDDAUX

VDDVC

VDDD

VDDD

BIAS1

BIAS2

VSSD

VSSD

VSSD

VSSVC

VSSAUX

VSSTX

VSSRX

Recent Two-Way Radio IC Products From CML CMX649 CMX838 CMX823 CMX881 CMX882 CMX883 Adaptive Delta Modulation (ADM) Codec FRS/PMR446/GMRS Family Radio Processor Multi-Standard Analogue Paging-Tone Decoder Baseband Processor for PMR and Trunked Radios Baseband Processor with Data for Leisure Radios Baseband Processor for Leisure Radios

EV9810 Evaluation Kit for the CMX981

The EV9810 evaluation kit is intended to allow investigation, demonstration and evaluation of the CMX981 IC. This PCB-based EvKit provides a hardware and interface platform for both hardware and software designers to develop, test and interface prototype equipments.

CMLs full range of products for Two-Way Radio, Wireline Telecom and Wireless Data environments can be viewed on www.cmlmicro.com

n n n n n n n n n n n n n n

Analogue PCB with Low Noise-Floor Design Buffered Serial Interface Ports with Signal Shifting Differential or Single-ended Baseband Signal I/O Dual (+ and -) 8 Volt Supply Requirement On-board Regulators for All Power Rails Separate 5-Volt Power Rail for Analogue Interfaces Auxiliary ADC and DAC Connections Available Microphone Inputs and Speaker/Earpiece Outputs via 3.5mm Mono Jack Sockets Signal and Power Test Access Access to All CMX981 Functions CMX981 Q1 Device Supplied In-Situ Separate Digital and Analogue Ground Planes User Manual and Circuit and EvKit Layout Diagrams Provided CML Help Desk: techsupport@cmlmicro.com

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