LESSON PLAN

Sub Name : SWITCHING Branch: EEE Year : II Semester: II

THEORY AND LOGIC DESIGN Class: B.Tech

LP Rev. No: 00 Date: 24-11-12

UNIT I: Review of Number systems: Representation of numbers of different radix, conversion of numbers from one radix to another radix, r-1s complement and rs complement of unsigned numbers subtraction, problem solving. Signed binary numbers, different forms, problem solving for subtraction. 4-bit codes: BCD, EXCESS 3, alphanumeric codes,9s complement, 2421, etc.. (Text Books: 2,, Reference Books: 1,2,4)
Objective: S. No 1 2 3 4 5 6 7 8 9 Topics to be covered Session No. 1 2,3 4 5 6 7 8 9 10 Ref 2 2 2 2 2 2 2 2 Teaching Method BB BB BB BB BB BB BB

Subject Introduction Representation of numbers of different radix conversion of numbers from one radix to another radix r-1s complement and rs complement of unsigned numbers subtraction Problems Signed Binary Numbers, different forms 4-bit codes: BCD, EXCESS 3 alphanumeric codes,9s complement, 2421 Unit test

UNIT II Logic operation, error detection and correction codes: Basic logic operations NOT, OR,AND,Boolean theorems, Complement and dual of logical expressions, NAND and NOR Gates, EX-OR, EX-NOR Gates, standard SOP and POS, Minimisation of logic functions using theorems, Generation of self dual functions. Gray code, error detection and error correction codes, parity checking even parity, odd parity, Hamming code, multi leveled AND-NOR Realisations. Two level NAND-NAND and NOR-NOR realizations. Degenerative forms and multi level realizations. (Text Books: 1,2, Reference Books: 12,4)
.

Objective: S. No 10 11 12 13 14 15 16 17 18 19 20 Topics to be covered Session No. 11 12 13 14 15 16,17 18 19 20 21 22 Ref No. 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 5 1 Teaching Method BB BB BB BB BB BB BB BB BB

Basic logic operations NOT, OR,AND Boolean Theorems Complement and dual of logical expressions Universal Gates, Ex-OR and Ex-NOR Gates standard SOP and POS Minimizations Of Logic Functions using Boolean Theorems Gray code, error detection and error correction codes, parity checking even parity, odd parity Hamming code multi leveled AND-NOR Realisations. Two level NAND-NAND and NOR-NOR realizations. Degenerative forms and multi level realizations Unit test

LESSON PLAN
Sub Name : SWITCHING Branch: EEE Year : II Semester: II

THEORY AND LOGIC DESIGN Class: B.Tech

LP Rev. No: 00 Date: 24-11-12

UNIT III Minimisation of switching functions: Minimisation of switching functions using K-Map up to 6-variables, Tabular minimization, minimal SOP and POS Realisation. Problem solving using K-map such as code converters binary multiplier etc.,(Text Books: 1,2 , Reference Books: 2,4)
Objective: S. No 21 22 23 24 25 26 27 28 29 Topics to be covered Session No 23 24 25 26 27 28 29 30 31 Ref No. 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB BB BB

Introduction to Level minmization Karnaugh Map Method (K-Map) Minimization Of Boolean Functions Using 4 Variable Minimization Of Boolean Functions Using 5 Variable Minimization Of Boolean Functions Using 6 Variable POS and SOP Simplifications with Dont Care Conditions using K-Map Tabular minimization, minimal SOP and POS Realisation Problem solving using K-map such as code converters binary multiplier Unit test

UNIT IV Combinational logic circuits-I: Design of Half adder, full adder, half subtractor, full subtractor, applications of full adders, 4-bit binary adder, 4-bit binary subtractor, addersubtractor circuit, BCD adder circuit Excess3 adder circuit, look-a-head adder circuit. (Text Books: 2, , Reference Books: 1,2,3)
Objective: S. No 30 31 32 33 34 35 36 37 38 Topics to be covered Session No. 32 33 34 35.36 37 38 39 40 41 Ref No. 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB BB BB

Introduction to Combinational Arithmatic Logic Circuits Design Of Half Adder, Full Adder Design of Half Subtractor, Full Subtractor applications of full adders, 4-bit binary adder, 4-bit binary subtractor adder-subtractor circuit BCD adder circuit Excess3 adder circuit look-a-head adder circuit Problems Unit test

UNIT V Combinational logic circuits-II: Design of decoder, Demultiplexer, higher order demultiplexing, encoder, multiplexer, higher order multiplexer, realization of Boolean functions using decoders and multiplexers, priority encoder, different code converter using full adders. (Text Books: 1,2, Reference Books: 1,2,3)
S. No 39 40 41 42 Topics to be covered Session No 42 43 44 45 Ref No. 3 3 3 3 Teaching Method BB BB BB BB

Introduction to Combinational logic circuits Design of Decoders, Encoders Design of Multiplexers, Demultiplexers Design of Higher Order Demultiplexers

and

LESSON PLAN
Sub Name : SWITCHING Branch: EEE Year : II Semester: II

THEORY AND LOGIC DESIGN Class: B.Tech

LP Rev. No: 00 Date: 24-11-12

43 44 45 46

Multiplexers Realization Of Boolean Functions Using Decoders and Multiplexers Priority Encoders, Code Converters Problems Unit test

46 47 49 50

3 3 3

BB BB BB -

UNIT VI Combinational logic circuits-III: PROM,PLA,PAL, realization of switching functions using PROM,PLA and PAL; comparison of PROM,PLA,and PAL, Programming tables of PROM,PLA and PAL. (Text Books: 1,2, Reference Books: 1,2,4)
Objective: S. No 47 48 49 50 51 52 53 54 Topics to be covered Session No. 51 52 53 54 55 56 57 58 Ref No. 3 3 3 3 3 3 3 Teaching Method BB BB BB BB BB BB BB

Introduction to Programmable Logic Devices PLA PAL, PROM Realization of Switching Functions Using PROM, PAL and PLA. Comparison of PLA, PAL and PROM Programming Tables of PLA, PAL and PROM. Problems Unit test

UNIT VII Sequential circuits I: Classification of sequential circuits (synchronous and asynchronous): basic flip-flops, truth tables and excitation tables (nand RS latch, nor RS latch, RS flip-flop. JK flip-flop, T flip-flop, D flip-flop with reset and clear terminals).Conversion of flip-flop to flip-flop. Design of ripple counters, design of synchronous counters, Johnson counters, ring counters. Design of registers, Buffer register, control buffer register, shift register, bidirectional shift register, universal shift register. (Text Books: 1,2, Reference Books: 1,2,3)
Objective: S. No 55 56 57 58 59 60 61 62 63 64 65 66 Topics to be covered Session No. 59 60 61 62,63 64,65 66,67 68 69 70 71 72,73 74 Ref 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB BB BB BB BB BB BB

Introduction to Sequential Logic Circuits Classification, Basic Sequential Logic Circuits Latch and Flip-Flop Latch using NAND and NOR Gates and their Truth Tables. RS, JK, T and D Flip Flops, Truth Tables, Excitation Tables Conversion of Flip Flops Flip Flops With Asynchronous Inputs (Preset and Clear). Design of ripple ,synchronous counters Design of Johnson counters, ring counters Design of registers, Buffer register, control buffer register, shift register bi-directional shift register, universal shift register Unit test

UNIT VIII

LESSON PLAN
Sub Name : SWITCHING Branch: EEE Year : II Semester: II

THEORY AND LOGIC DESIGN Class: B.Tech

LP Rev. No: 00 Date: 24-11-12

Sequential circuits II: Finite state machine, capabilities and limitations, analysis of clocked sequential circuits, design procedures, reduction of state tables and state assignment. Realization of circuits using various flip-flops. Meelay to Moore conversion and vice-versa. (Text Books: 1 Reference Books: 1,2,4) Objective:
S. No 67 68 69 70 71 72 Topics to be covered Session No. 75 76,77 78,79 80 81 82 Ref 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 1,2,4 Teaching Method BB BB BB BB BB

Introduction Finite state machine capabilities and limitations, analysis of clocked sequential circuits design procedures, reduction of state tables and state assignment Realization of circuits using various flip-flops Meelay to Moore conversion and vice-versa Unit test

Text Book:
S. No 1 2 Text Book Name Editon Author Publisher

Switching theory and logic design. Modern Digital Electronics

MH

Hill and Peterson RP Jain

Mc-Graw Hill TMH

References:
S. No 1 2 3 4 Reference Book Name Editon Author Publisher

Switching Theory and Logic Design Digital design Micro electronics Fundamentals of Logic Design 2nd MH

A.AnandKumar Mano Millman Charles H.Roth Jaico Publishers PHI

Prepared by Signature Name Department Designation Date

V.PRASANNANJANEYAREDDY ECE Asst. Professor 24-11-12

Approved by

Dr.CH.BALA SWAMY ECE Professor & HOD 24-11-12