2009 Second International Conference on Computer and Electrical Engineering

FPGA Implementation of Space Vector PWM Technique for Voltage Source Inverter Fed Induction Motor Drive
R.RAJENDRAN
Dept. of IT Karpagam College of Engineering Coimbatore, India raja_mein@yahoo.co.in Abstract This paper presents implementation of Space Vector Pulse Width Modulation (SVPWM) technique for three phase Voltage Source Inverter (VSI) using Field Programmable Gate Array (FPGA). Variable voltage and frequency supply to ac drives is invariably obtained from a three phase voltage source inverter. A number of Pulse Width Modulation scheme is used to obtain variable voltage and frequency supply. The most widely used PWM schemes for three phase VSI are carrier-based sinusoidal PWM and space vector PWM.There is an increasing trend of using space vector PWM because of their easier digital realization and better dc bus utilization. Both simulation and experimental results are presented.
Keywords-VSI; SVPWM; FPGA; Induction Motor

Dr.N.DEVARAJAN
Dept. of EEE Government College of Technology Coimbtore, India profdevarajan@yahoo.com simultaneous instead of sequential execution. Also it is very convenient for laboratory implementation of a project due to its unique hardware reconfigurable feature. Therefore the implementation and circuit realization using FPGA for SVM IC design has been reported in many papers [12-14]. The rest of the paper is organized as follows. Section II briefly introduces principle of space vector PWM method. Section III proposes FPGA Implementation of SVPWM method. Secion IV explains simulation and experimental results and section V is the conclusion. II. SPACE VECTOR PWM Space Vector PWM (SVPWM) refers to a special technique of determining the switching sequence of the upper three power transistors of a three phase voltage source inverter. It has been shown to generate less harmonic distortion in the output voltages or current in the windings of the motor load. SVPWM provides more efficient use of the dc bus voltage, in comparison with the direct sinusoidal modulation technique. The structure of a typical three-phase voltage source inverter is shown in Fig.1. The voltages V a, Vb, Vc are the output voltages applied to the windings of a motor.Q1 through Q6 are the six power transistors which are controlled by a, a, b, b, c and c gating signals and shape the output voltages. When an upper transistor is switched on, i.e., when a, b, and c are 1, the corresponding lower transistor is switched off, i.e., the corresponding a, b or c is 0. The on and off states of upper transistor Q1, Q3 and Q5, or the states to evaluate the output voltage.

I.

INTRODUCTION

Advance in power electronics has led to an increased interest in voltage source inverters with pulse width modulation control of ac drives [1]. Space vector pulse width modulation technique has been widely investigated for decades. It gives a higher output voltage for the same DC bus voltage, lower switching losses, and better harmonic performance [2-6], in comparison to carrier based Sine PWM. Three-phase inverter voltage control by space vector modulation includes switching between the two active and zero voltage vectors so that the time interval times the voltage in the chosen sectors equals the command voltage times the time period within each switching cycle. [78].Most of the ac drives in use today was adapting either fully DSP based digital control strategy or partially FPGA and DSP as reported in [9-10]. This arrangement has the advantages of simpler circuitry, software control and flexibility in adaptation to various applications, but it suffers the disadvantages of sluggishness and limited computation resources due to the sequential computation feature, complicated design process and long development time cycle [11]. Of course, multiple DSPs can alleviate this problem at the expense of high cost. On the other hand, the recent advancement of ASIC based devices such as field programmable gate array (FPGA) has provided an economic solution and fast circuit response due to its
978-0-7695-3925-6/09 $26.00 2009 IEEE DOI 10.1109/ICCEE.2009.119 422 424

Figure 1 Three Phase VSI Supplying an Induction Motor

A. Switching Patterns and Basic Space Vectors There are eight possible combinations of on and off states for the three upper power transistors. The on and off states of the lower power transistors are opposite to the upper ones, so they are determined once the states of the upper transistors are known. The eight combinations are derived output line-line and phase voltages in terms of DC supply voltage Vdc, according to (1.1) and (1.2), which are shown in Table1.1. The relationship between the switching variable vector [a, b, c]T and the line to line voltage vector [Vab, Vbc, Vca]T is given by the following:

(1.3) The groups of the 8 vectors are referred to as the basic space vectors and are denoted by V0, through V7. The d-q transformation can be applied to the reference a, b, and c voltages to obtain the reference Vout in the d-q plane as shown in Fig.2.

(1.1) In addition, phase (line-to-line) output voltage vector [Va, Vb, Vc]T is given by (1.2)

Figure 2 Possible space vectors (1.2) Table 1.1 Switching Pattern and Output Voltage of VS C.Approximation of output with Basic Space Vectors The objective of the space vector PWM techniques is to approximate the reference voltage vector Vout by a combination of the eight switching patterns. One simple means of approximation is to require the average output voltage of the inverter (in small period T) to be the same as the average of Vout in the same period. This is shown in (1.4) for the output voltage in the sector 0, where T4 and T6 are the respective durations in time for which switching patterns are V4 and V6.

1 T
B. Expresions of the Space Voltages in (d-q) frame Assuming q and d are the horizontal and vertical axes of the stator coordinate frame, the d-q transmission given in (1.3) can transform three phase voltage vector into a vector in the d-q coordinate frame. This vector represents the spatial vector sum of the three phase voltage. The phase voltages corresponding to the eight combinations of switching patterns can be mapped into the d-q plane by the same d- q transformation. This mapping results in 6 nonzero vectors and 2 zero vectors. The non-zero vectors form the axes of a hexagonal as shown in Fig.2. The angle between any two adjacent non-zero vectors is 600. The 2 zero vectors are positioned at the origin and apply zero voltage to a motor.

( n +1)T

nT

Vout dt

1 (T4V4 + T6V6) n=0,1,2 T

where T4+T6 T (1.4) Assuming the PWM period, Tows, is small and the change of Vout is relatively slow, from (1.4), we obtain
( n +1)Tpwm

Tpwm

Vout dt = T

pwmVout

= (T4V4+ T6V6) (1.5)

n=0, 1, 2, where T4+T6 Tpwm

Pwm1 Pwm2 Pwm3

T Figure 3 Timing Diagrams

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Equation (1.5) shows that for every PWM period, the desired reference voltage Vout can be approximated by having the power inverter in a switching pattern of V4and V6 for T4 and T6 periods of time, respectively as shown ib Fig.3. Since the sum of T4 and T6 is less than or equal to Tpwm, the inverter needs to have a 0((000)V0 or (111)V7 pattern for the rest of the period. Therefore, (1.5) will then become TpwmVout = T4V4 + T6V6 + T0(V0 or V7) (1.6) where T1 + T2 + T0 = Tpwm III. FIELD ROGRAMABLE GATE ARRAY(FPGA) A Field Programmable Gate Array is a reconfigurable digital integrated circuit that can be programmed to do any digital function. There are two main advantages of an FPGA over a microcontroller chip [17]. FPGA has the ability to operate faster. FPGA supports hardware that is upwards of one million gates.. FPGAs are programmed using support software and a download cable connected to a host computer. Once they are programmed, they can be disconnected from the computer and will retain their functionality until the power is removed from the chip. The FPGAs can be programmed while they run, because they can be reprogrammable in the order of milliseconds. The FPGA consists of three major configurable elements Configurable Logic Blocks (CLBs) arranged in an array that provides the functional elements and implements most of the logic in a FPGA. Input-Output Blocks (IOBs) that provide the interface between the package pins internal signal lines. Programmable interconnects that provide routing path to connect inputs and outputs of CLBs and IOBs to the appropriate network. The most recent FPGAs are produced using a 65-nm copper process. Their density can reach more than 10 million equivalent gates per chip with clock system frequencies of more than 500 MHz. The two main FPGA manufacturers are Altera and Xilinx. A. Implementation of SVPWM using FPGA The SVPWM scheme discussed previously is implemented on a low cost SPARTAN 3 FPGA, that contains 400,000 logical gates and works at 50MHz(clock period equal to 20 ns). The Spartan 3 generic hardware architecture is composed of a matrix of 5,376 slices, which are configurable logic blocks linked to each other by a programmable interconnection network. The SPARTAN 3 FPGA Includes also 16 embedded [18x18] hardware multipliers, 18Kb internal RAM memories and enhanced configurable input/output blocks. The structural diagram of SVPWM IC is shown in Fig.4. B. Hardware Description Laguage(HDL) The hardware architecture of each control algorithm is designed to an efficient design methodology [18] that offers considerable design advantages such as reusability,
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reduction of the development time and optimization of the consumed resources.

Figure 4 Structural Diagram of SVPWM IC The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). HDL describes hardware behavior. There are main differences between traditional programming languages and HDL. Traditional languages are a sequential process whereas HDL is a parallel process. HDL runs forever whereas traditional programming languages will only run if directed. IV. SIMULATION AN DEXPERIMENTAL RESULTS VHDL code was developed to examine the three switching patterns of SVPWM method. This code is synthesized using Xilinx ISE. The switching delays and the forward drop of the power switches and the dead time of the inverter are all neglected in the models. It is assumed that the model load has a fixed RL = 100, L=1mH and the voltage source of the inverter is 150 Vdc, inverter switching frequency fs=20000Hz. Fig.5 shows the experimental setup of this work.Fig.6 and Fig.7 shows the simulation and experimental results of this work. FPGA BOARD DRIVER CIRCUIT

POWER MODULE INDUCTION MOTOR Figure5. Experimental Setup

(a)

(b)

(c) Figure 6 Simulation Results of Switching Pattern

(d)

(a) N=200 RPM Figure 7 Oscillograms of output voltage VAB

(b) N=1500 RPM

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V.

CONCLUSION

This paper presents a FPGA implementation method of PWM pattern generator with space vector modulation. This FPGA chips develops triggering signal to drive MOSFET based inverter. The PWM generator is also extendable to multi-level cascaded VSI inverter applications. The conventional microprocessors are serial machines which perform one instruction at a time, while the structure of FPGA is adapted in parallel, which means the performance is several degrees better. Another advantage is that only one FPGA chip is capable of performing multiple functions including control, signal processing and system input and output. REFERENCES [1] B.K.Bose, Power Electronics and Variable Frequency Drives, IEEE PRESS, New York 1997 [2] H.Stemmeler, State of the art future trends in High power electronics, in Conf.Rec.International Power Electronics Conference IPEC-Tokyo 00, pp.4-14, 2000. [3] Y.Tzou & H.Hsu,FPGA Realization of Space Vector PWM Control IC for three-phase PWM Inverters, IEEE Transation on Power Electronics, vol.12, no6, Nov.1997, pp 953-963. [4] M. A.Jabbar, A.M. Khambadkone, and Y.Zhang, Space-vector modulation in a two- phase induction motor drive for constant-power operation, IEEE Transaction on. Electronics, Vol. 51, no. 5, pp. 10811088, Oct. 2004. [5] V. S. Kumar and P. S. Kannan, Harmonic studies space vector PWM inverter drive system, in Proceeding of. International Conference on. Power System Technology, 2004, vol. 1, pp. 123127. [6] A. M. Trzynadlowski, K. Borisov, L. Yuan, and Q. Ling, A novel random PWM technique with low computational overhead and constant sampling frequency for high-volume, low-cost applications, IEEE Transaction on. Power Electronics, vol.20, no. 1, pp. 116122, Jan. 2005. [7] B. P. McGrath, D. G. Holmes, and T. Maynard, Reduced pwm harmonic distortion for multilevel inverters operating over a wide modulation range, IEEE Transaction on Power Electronics, vol. 21, no. 4, pp. 941949, Jul. 2006. [8] Z. Kalimantan W. Danwei, Relationship between space-vector Modulation and three-phase carrier-based PWM: A comprehensive analysis, IEEE Transacton on Industrial Electronics, vol. 49, no. 1, pp.186196, Feb. 2002. [9] H. Bain, Z. Zhao, S. Meng, J. Liu, and X. Sun, Comparison of three PWM strategies-SPWM, SVPWM & one-cycle control, in Proc. 5th International Conference on Power Electronics Drive system, vol. 2, pp. 13131316. 2003.

[10] S.Meshkat and I.Ahmed, Using DSPs in AC Induction Motor Drive Drives, IEEE Transaction on Control Engineering, vol.35, no.2, pp.54-56, Feb. 1998. [11] S.Vadivel, G.Bhuvaneshwari, and G.S.Rao, A Unified Approach to the real time implementation of DSP based PWM waveforms, IEEE Transactions on Power Electronics, vol.6, no.4, pp.565-575, 1991. [12] Y.Y.Tzau, MIEE, and H.J.Hsu, FPGA Realization of Space Vector PWM control IC for Three Phase PWM Inverter, IEEE Transactions on Power Electronics, vol.12, no.6, pp953-963, Nov.1997. [13] M.Tonelli, et al., FPGA Implementation of an Universal Space Vector Modulator, IECON. 01 The 27th Annual Conference of the IEEE Industrial Electronics Society, 2001. [14] W.P.Hew, et al, Realization of space vector modulation technique in a single FPGA chip for induction motor drive PWM, IEEE International Conference on Electron Devices and Solid State Circuits, Hong Kong, pp.817-820, Dec.2005. [15] Z.Zhou, et al, Realization of an FPGA- based space vector PWM controller, IEEE International Power Electronics and Motion Control (IPEMC2006), 2006. [16] Bob Zeidman and Robert Zeidman, Design with FPGA and CPLD, CMP Books, Bekerly 2002. [17] Xilinx Application Notes. [18] Ying-Yu Tzou, Tien Sung Kuo, Design and Implementation of FPGA-based Motor control IC for Permanent magnet AC servo motors IEEE Transaction on Industrial Electronics, Vol.38, No.2, 1996.

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