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    Mitchell Lee
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    Mixed-Signal and Power IC LAB NCTU, LAB 912 Layout styles of MOS Transistor Schematic view VDD Layout view CMOS cross section view.

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    Mixed-Signal and Power IC LAB NCTU, LAB 912 Layout styles of MOS Transistor Schematic view VDD Layout view CMOS cross section view.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    388 views57 pages

    Analog Layout 20111028

    Uploaded by

    Mitchell Lee
    Mixed-Signal and Power IC LAB NCTU, LAB 912 Layout styles of MOS Transistor Schematic view VDD Layout view CMOS cross section view.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 57

    Analog Layout

    Advisor: Ke-Horng Chen Student: Yu-Huei Lee 2011.10.28

    MixedSignalandPowerICLab NCTU,LAB912

    Outline

    Layout of MOS Transistor Layout of Resistor Layout of Capacitor OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Schematic view
    VDD

    Layout view

    CMOS cross section view

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Contact Resistance

    Metal1 Rc N+ Poly (b) Equivalent circuit


    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Gate Etching Effect

    1 W 2 I d oCOX Vgs Vt 2 L

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Gate Etching Effect

    Compensation of Boundary dependent etching with dummy elements


    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Gate Etching Effect
    Iref Iout

    Dummy

    M1

    M2

    Dummy

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor



    D G S
    S G D

    D 16/1 G S 4/1 4/1 4/1 4/1

    MOSMOSLW N
    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    MOSSourceDrain SourceDrain

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Gradient Effect
    M1 M2

    Gradient
    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Gradient Effect

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    One Dimensional Common-Centroid Arrays

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Two Dimensional Common-Centroid Arrays

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Common Centroid MOS
    M1a M2a M2b M1b

    1Cox M1a M2a

    2Cox M1b

    3Cox M2b

    4Cox

    1Cox

    2Cox

    3Cox

    4Cox

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Common Centroid

    1/2M1

    1/2M2

    1/2M2

    1/2M1

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Common Centroid

    b
    M1
    M1 M2

    M2

    M1

    M2

    M2

    M1

    M2

    M1

    c
    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    Differential pair

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor

    Out_P Out_N

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout styles of MOS Transistor


    A Wide Digital Transistor Layout

    S
    MixedSignalandPowerICLab NCTU,LAB912

    Outline

    Layout styles of MOS Transistor Layout of Resistor Layout of Capacitor OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor
    Resistance Estimation:

    L R Rs ( )ohms W

    t : thickness L: conductor length W: conductor width Rs: sheet resistance

    R Rs (

    4L )ohms 4W L Rs ( )ohms W

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor
    Process Parameters:
    *File: lvs35 . *************** Define Resistor ****************************************** ELEMENT RES[M1] MT1RES MT1 ;define metal resistor PARAMETER RES[M1] 0.083 . . ELEMENT RES[M4] MT4RES MT4 ;define metal resistor PARAMETER RES[M4] 0.051 ELEMENT RES[WR] RWELL NXWELL ;define n_well resistor PARAMETER RES[WR] 1050 ELEMENT RES[P1] RESPN CPOLY ;define ploy1 resistor PARAMETER RES[P1] 8.0 ELEMENT RES[PR] RESPP CPOLY ;define p+ploy1 resistor PARAMETER RES[PR] 8.0 ELEMENT RES[P2] RESP2 C2POLY ;define ploy2 resistor PARAMETER RES[P2] 50.0 ELEMENT RES[PD] RESDP PDIFF ;define pimp-DIFF resistor PARAMETER RES[PD] 150 ELEMENT RES[ND] RESDN NDIFF ;define nimp-DIFF resistor PARAMETER RES[ND] 80.0

    R = Rs (L/W) ohms
    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    NWELLSubstrate

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor
    Resistor Dummy & Shielding
    Dummy
    Dummy
    Dummy

    Metal 2

    Res

    Res

    Res

    Res

    Res

    Res

    Dummy
    MixedSignalandPowerICLab NCTU,LAB912

    Dummy

    Metal 3

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Resistor

    MixedSignalandPowerICLab NCTU,LAB912

    Outline

    Layout styles of MOS Transistor Layout of Resistor Layout of Capacitor OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor
    Process Parameters:
    *File: lvs35 ********** Define Capacitor ******************************************** ELEMENT CAP[PC] CAPPL CPOLY C2POLY ;define poly cap. PARAMETER CAP[PC] 8.9E-16 7.3E-18 AND CDUMMY METAL1 MCAP1 AND MCAP1 METAL2 MCAP2 AND MCAP2 POLY1 MCAP3 ;define cap. region ELEMENT CAP[MC] MCAP3 MT1 MT2 ;define metal cap. PARAMETER CAP[MC] 9.0E-17 5.34E-17

    Capacitance Estimation:

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor
    Why Using Unit Capacitor?

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor
    45

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor
    32 32 32 32 32 32 32 32 16 32 32 16 16 32 32 16 8 8 8 16 32 32 16 4 4 8 16 32 32 16 2 1 2 16 32 32 16 4 4 8 16 32 32 16 8 8 8 16 32 32 16 32 32 16 16 32 32 32 32 32 32 32 32

    MixedSignalandPowerICLab NCTU,LAB912

    Layout of Capacitor

    MixedSignalandPowerICLab NCTU,LAB912

    Outline

    Layout styles of MOS Transistor Layout of Resistor Layout of Capacitor OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    OPA Layout
    VDD VDD

    M1 M2

    M3 M4

    R2 OUT M5

    IP

    Q1

    Q2

    IN Q3

    Q4

    R1

    MixedSignalandPowerICLab NCTU,LAB912

    The CMOS Differential Amplifiers with Active Load

    MixedSignalandPowerICLab NCTU,LAB912

    OPA Layout
    VDD

    VBG M1 BP M4 M5 M6 COLLECT

    R1

    IN

    M2

    M3 C1

    Q3

    R2 Q1 Q2

    M7

    R3

    R4

    MixedSignalandPowerICLab NCTU,LAB912

    OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    OPA Layout

    MixedSignalandPowerICLab NCTU,LAB912

    Thank you for your attention

    MixedSignalandPowerICLab NCTU,LAB912

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