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5. CMOS Gates: DC and Transient Behavior 40

J. A. Abraham
60 Department
of Electrical and Computer Engineering The University of Texas at Austin EE 382M.7 VLSI I Fall 2011
September 12, 2011
80
ECE Department, University of Texas at Austin
Lecture 5. CMOS Gates: DC and Transient Behavior
J. A. Abraham, September 12, 2011
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Topics
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DC Response Logic Levels and Noise Margins Transient Response Delay Estimation
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Transistor Behavior
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Behavior in dierent situations (increase, decrease, or not change).

1 2 3
If the width of a transistor increases, the current will

40 If the length of a transistor increases, the current will
If the supply voltage of a chip increases, the maximum transistor current will If the width of a transistor increases, its gate capacitance will If the length of a transistor increases, its gate capacitance will If the supply voltage of a chip increases, the gate capacitance of each transistor will
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Transistor Behavior
Behavior in dierent situations (increase, decrease, or not mm 40 60 80 100 change).
1 2
120
If the width of a transistor increases, the current will increase If the length of a transistor increases, the current will decrease 40 If the supply voltage of a chip increases, the maximum transistor current will increase If the width of a transistor increases, its gate capacitance will 60 increase If the length of a transistor increases, its gate capacitance will increase If the supply voltage of a chip increases, the gate capacitance 80 of each transistor will not change
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DC Response: Vout vs. Vin for a Gate

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Study the response of Inverters
When Vin = 0 = Vout = VDD When Vin = VDD = Vout = 0

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In between, Vout depends on transistor size and current By KCL, current must be such that Idsn = |Idsp | 60 We could solve equations, but graphical solution gives more insight
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Transistor Operation
Current through transistor depends on the region of operation mm to identify for what60in and Vout are nMOS100 pMOS 120 40 80 Need V and in Cuto, Linear or Saturation nMOS Operation
40 Cuto Vgsn < Vtn Vin < Vtn 60
Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn Vtn Vout < Vin Vtn
Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn Vtn Vout > Vin Vtn
Vgsn = Vin Vdsn = Vout

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pMOS Operation
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Cuto Vgsp > Vtp Vin > VDD + Vtp

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Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp Vtp Vout > Vin Vtp
Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp Vtp Vout < Vin Vtp
Vgsp = Vin VDD

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Vdsp = Vout VDD Vtp < 0
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I-V Characteristics
Make pMOS wider than nMOS such that n = p = mmox W C L
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Current vs. Vout , Vin

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Load Line Analysis

mm 40 60 80 To nd the Vout for a given Vin For a given Vin , plot Idsn , Idsp vs. Vout 100 120
Vout must be where |currents| are equal in the graph below

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DC Transfer Curve
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Transcribe points on to Vin vs. Vout plot
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Operating Regions
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Revisit transistor operating regions
Region A B C D E
nMOS 40 Cuto Saturation Saturation Linear 60 Linear
pMOS Linear Linear Saturation Saturation Cuto
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Beta Ratio
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If p /n = 1, 40 switching point will move from VDD /2 Called skewed gate

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Analysis of more complex gates 80 Collapse into equivalent inverter

ECE Department, University of Texas at Austin Lecture 5. CMOS Gates: DC and Transient Behavior J. A. Abraham, September 12, 2011 12 / 35
Noise Margins
How much noise can a gate input see before it does not recognize mm 40 60 80 100 120 the input?
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Logic Levels
To maximize noise margins Select logic levels at unity gain point 80 DC transfer of mm 40 60 100 characteristic
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Transient Response
mm 60 80 DC analysis40 gives the Vout if Vin is constant 100 120
Transient analysis tells us Vout as Vin changes Input is usually considered to be a step or ramp (from 0 to VDD or vice-versa)
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Inverter Step Response

Find the step response of an inverter driving a load capacitance
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Vin (t) = u(t t0 )VDD Vout (t < t0 ) = VDD

dVout (t) dt
dsn (t) = ICload
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Idsn80 = (t)
0
2 (VDD
V )2
Vout (t) 2
t t0 Vout > VDD Vt Vout (t) Vout < VDD Vt

J. A. Abraham, September 12, 2011 16 / 35
VDD Vt
Delay Denitions
tpdr : rising propagation delay
V mm From input to rising output crossing80 DD /2 40 60 100 120
tpdf : falling propagation delay

From input to falling output crossing VDD /2
tpd : average propagation delay

40 tpd = (tpdr + tpdf )/2 From output crossing 0.2 VDD to 0.8 VDD
tr : rise time tf : fall time

60 From output crossing 0.8 VDD to 0.2 VDD From input to rising output crossing VDD /2
tcdr : rising contamination delay tcdf : falling contamination delay tcd : average contamination delay
tpd = (tcdr + tcdf )/2
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From input to falling output crossing VDD /2
Simulated Inverter Delay

Solving dierential equations by hand too hard
mm SPICE simulator solves equations numerically 40 60 80 Uses more accurate I-V models too! 100 120
But simulations take time to write

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Delay Estimation
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We would like to be able to easily estimate delay

Not as accurate as simulation But easier to ask what if ...?
The step response usually looks like a rst order RC response 40 with a decaying exponential Use RC delay models to estimate delay
60 C = total capacitance on output node Use eective resistance R So that tpd = RC Depends on average current as gate switches 80
Characterize transistors by nding their eective R
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Example: Sizing 3-Input NAND Gate for Equal Rise and Fall Times
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Determine the transistor widths to achieve eective rise and fall resistances (times) equal to that of a unit inverter R 80 Annotate the 3-input NAND gate with gate and diusion capacitances
Example 3-Input NAND Gate

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Determine the transistor widths to achieve eective rise and fall resistances (times) equal to that of a unit inverter R
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Annotate the 3-input NAND gate with gate and diusion capacitances
Example: Sizing Complex Gate

Size the transistors in the circuit mm so that it has the below 40 60 same drive strength, in the worst case, as an inverter that has PW = 5 and NW = 3. Use the smallest widths possi40 ble to achieve this ratio. Note: if there are multiple paths 60 through a transistor, use the size for the worst-case input combination.
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Example: Sizing Complex Gate

Size the transistors in the circuit below so that it has mm 40 60 the same drive strength, in the worst case, as an inverter that has PW = 5 and NW = 3. Use the smallest widths possible to40 achieve this ratio. This solution does NOT use the smallest widths Note:60 if there are multiple paths through a transistor, use the size for the worst-case input combination.
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Example: Sizing of Complex Gate Better Solution

Size the transistors in the circuit below so 40 that it has mm 60 the same drive strength, in the worst case, as an inverter that has PW = 5 and NW = 3. Use the smallest widths possi40 ble to achieve this ratio. Note: if there are multiple paths 60 through a transistor, use the size for the worst-case input combination.
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Elmore Delay
Finding the delay of ladder networks ON transistors look like resistors
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Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder tpd 40 =

nodes i
Ritosource Ci
= R1 C1 + (R1 + R2 )C2 + . . . + (R1 + R2 + . . . + RN )CN

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NOTE: Ci includes all the o-path capacitance on nodes that are connected to node i
Example: Delay of 2-Input NAND Using Elmore Formulation

mm 40 60 80 100 Estimate rising and falling propagation delays of a 2-input NAND 120 driving h identical gates
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tpdr = (6 + 4h)RC
Lecture 5. CMOS Gates: DC and Transient Behavior J. A. Abraham, September 12, 2011 26 / 35
Example: Delay of 2-Input NAND Using Elmore Formulation

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates
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tpdf = (2C)
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R + (6 + 4h)C 2 = (7 + 4h)RC
R R + 2 2
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Example of Elmore Delay Calculation

Calculate the Elmore delay from C to F in the circuit. The widths mm 40 60 100 120 of the pass transistors are shown, and the 80 inverters have minimum-sized transistors
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Example of Elmore Delay Calculation

Calculate the Elmore delay from C to F in the circuit. The widths of the pass transistors are shown, and the inverters have mm 40 60 80 100 120 minimum-sized transistors
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R R R R 9C + 5C + + 7C + 3RC = 12.33RC 3 3 3 3 o-path Gates: DC and Transient Behavior J. A. Abraham, September 12, 2011 ECE Department, University of Texas at Austin Lecture 5. CMOS Delay =
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Another Example: Elmore Delay Calculation

Use the Elmore delay approximation to nd the worst-case rise and fall delays at output F for the following circuit. The gate sizes of the mm 40 60 80 100 120 transistors are shown in the gure. Assume NO sharing of diusion regions, and the worst-case conditions for the initial charge on a node. Input for worst-case rise delay = 40 Worst-case rise delay = Input for worst-case fall delay = 60 Worst-case fall delay =
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Delay with Dierent Input Sequences

Find the delays for the given input transitions (gate sizes shown in gure) mm 40 60 Assumptions: diusion capacitance is equal to the gate capacitance, the resistance of an nMOS transistor with unit width is R and the resistance of a 40 pMOS transistor with width 2 is also R, and NO sharing of diusion regions O-path capacitances can contribute to delay, and 60a node does not need to be if charged (or discharged), its capacitance can be ignored ABCD = 0101 ABCD = 1101 80 ABCD = 1111 ABCD = 0111 ABCD = 1010 ABCD = 1101
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Delay with Dierent Input Sequence, Contd

Look at the charges on the nodes at the end of the rst input of the sequence; only the capacitances mm 40 60 of the nodes which would change with the second vector need to be considered 40 ABCD = 0101 ABCD = 1101; Delay = 36RC ABCD = 1111 60 ABCD = 0111; Delay = 16RC ABCD = 1010 80 ABCD = 1101; Delay = 43RC
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Delay Components
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Delay has two parts Parasitic Delay 6 or 7 RC 40 Independent of Load Eort Delay 60 4h RC Proportional to load capacitance
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Contamination Delay
Minimum (Contamination) Delay
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Best-case (contamination) delay can be substantially less than propagation delay Example, If both inputs fall simultaneously Important for hold time (will see later in the course) 40
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tcdr = (3 + 2h)RC
Lecture 5. CMOS Gates: DC and Transient Behavior J. A. Abraham, September 12, 2011 34 / 35
Diusion Capacitance
We assumed contacted diusion on every source/drain Good minimizes diusion area mm layout 40 60 80 100 Example, NAND3 layout shares one diusion contact
Reduces output capacitance by 2C Merged uncontacted diusion might help too 40 120
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80 These general observations can be used for initial estimates of area and performance using tools to extract parasitics will provide more accurate results for a particular technology

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5. CMOS Gates: DC and Transient Behavior 40

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Behavior in dierent situations (increase, decrease, or not change).

If the width of a transistor increases, the current will

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

DC Response: Vout vs. Vin for a Gate

Study the response of Inverters

When Vin = 0 = Vout = VDD When Vin = VDD = Vout = 0

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Vgsn = Vin Vdsn = Vout

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Cuto Vgsp > Vtp Vin > VDD + Vtp

Vgsp = Vin VDD

Vdsp = Vout VDD Vtp < 0

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Current vs. Vout , Vin

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Load Line Analysis

Vout must be where |currents| are equal in the graph below

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Transcribe points on to Vin vs. Vout plot

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

Revisit transistor operating regions

nMOS 40 Cuto Saturation Saturation Linear 60 Linear

pMOS Linear Linear Saturation Saturation Cuto

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

If p /n = 1, 40 switching point will move from VDD /2 Called skewed gate

Analysis of more complex gates 80 Collapse into equivalent inverter

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

ECE Department, University of Texas at Austin

Lecture 5. CMOS Gates: DC and Transient Behavior

J. A. Abraham, September 12, 2011

ECE Department, University of Texas at Austin