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Ernest H. Wittenbreder Technical Witts, Inc. 3260 S. Gillenwater Drive, Flagstaff, AZ 86001 (928) 773-8673 etecwitt@npgcable.com
VLINE
DBOOT CBOOT
This circuit is in high volume commercial production and has been ~4 years.
VCC
PWM
COUT2
Simple and cheap, but does not work for active reset circuits. 3 Confidential - Property of Technical Witts, Inc.
CBOOT
I CIN I
Driver input is driven low to start transition Driver output goes high enabling MOSFET gate MOSFET source voltage rises Current from source forward biases low side clamp diode and charges input capacitor
4 Confidential - Property of Technical Witts, Inc.
I CBOOT
I CIN
Driver input is driven high to start transition Driver output goes low disabling MOSFET gate MOSFET source voltage falls with CBOOT High side clamp diode becomes forward biased discharging input capacitor
5 Confidential - Property of Technical Witts, Inc.
EMI Filter
MAUX LZVS
PWM
DCLAMP MMAIN
RSENSE
VHK
DHK CHK
LDO Regulator
+5 v
Patents: 5,402,329; 6,580,255; and 6,650,550 Appn. Ser. No.: 10/944,588 Confidential - Property of Technical Witts, Inc.
The Problem with the Prior Art Gate Driver for Active Reset
New High Side Gate Driver Turns Off Here
VCRESET Prior Art High Side Gate Driver Turns Off Here
Main Switch On
Main Switch On
Source of Aux FET tracks CRESET during off time of main switch In prior art driver, input to driver goes high forcing the output low when VCRESET and source voltage of Aux FET falls In prior art driver, Aux FET turns off too soon due to falling voltage of CRESET
7 Confidential - Property of Technical Witts, Inc.
VHK
DBOOT
CHK
PWM
MAUX
MMAIN
CHK
External Passives
CDUTY
Logic Supply
VBOOT
5v
Com
Logic Gate
+5 v
Logic In
Logic Out
Com
External Passives
Logic In
PWM CIN or
RFB
Logic Out
RFB provides positive current feedback that rejects voltage variations at the source of the Aux FET. 12 Confidential - Property of Technical Witts, Inc.
MOS Driver
+5 v
VBOOT
MOS Drive In
Com
VBOOT
DDRAIN
Out
Patent: 6,580,255
Com
Channel 1: Drain Source voltage of Main FET (100 volts/division) Channel 2: Gate Source voltage of Aux FET (4 volts/division) Channel 3: PWM output signal (5 volts/division) Channel 4: Gate Source voltage Main FET (5 volts/division)
Channel 1: Drain Source voltage of Main FET (100 volts/division) Channel 2: Logic Gate output voltage to Aux FET source (4 volts/division)
Channel 1: Drain Source voltage of Main FET (100 volts/division) Channel 2: MOS Driver output voltage to Aux FET source (4 volts/division)
Channel 1: Drain Source voltage of Main FET (100 volts/division) Channel 2: Gate Source voltage of Aux FET (4 volts/division)
CRESET
MAUX
PWM
MMAIN
CBOOT
DBOOT
Logic Gate
MOS Driver
RCFB
CHILO VHK CHK PWM MOS Driver
CDUTY
MMAIN CCOUPLELO
MOS Driver
RSTART
MMAIN
21
Yet Another Possibility - PWM Controller with Half Bridge Driver for Active Reset Circuits