Project 1

Part 1a
Design a 4-to-1 multiplexor that uses 8-bit buses on the inputs (instead of single bits). The output will be a single 8-bit bus. Design: To design my 8 bit 4-to-1 mux I used - 2to4 decoder - 4x2 AND-OR - 4to1 mux The schematics to these are below. 2-to-4 DECODER I used 2 inversters, and 4 2ANDgates. Inputs - a0,a1 Outpiuts D0,D1,D2,D3

4 x 2 AND-OR I used 4 2AND and 1 4OR gate. Inputs are a0, a1, a2, a3, b0, b1, b2, b3. And the only output is c.

Using these parts I can construct a 4-to-1 multiplexor that uses 8-bit buses. 8 bit 4x2 AND-OR

The above circuit consists of 8 4-to-2 AND-ORs. The input is 4 8bit values and a, b, c, d selectors. The output is an 8 bit value. I used 8bit expanders to take the input and traverse through the circuit. While on the other end I used a merger of 8 bit to output the 8 bit value.

Using a decoder I can have 2 select bits which is needed for my 4-to-1 multiplexer. 2^n = 4, n = 2. So we need 2 selectors. Implementing the decoder and my 8 4x2 AND-OR I get my mux. Part 1a (8 bit 4-to-1 multiplexer) Gates: Previous 8bit 4 x 2 AND-OR also the 2-4 decoder from the previous page. You input s0, s1 and 4 8bit values in i0-i3. Output is an 8bit value. This confirms the gates in the circuit are indeed working and the 8 bit inputs are passing through correctly.

To verify I use the waveform and vary the inputs to ensure that all of the signals of the 8 bit inputs have passed all the way through the 4 x2 AND-OR gates, this is successful making my multiplexer valid.

Part 1b
Build an 8 bit adder. Design: To create this adder I first created a full adder using 2 half adders. Full adders do bit/binary addition, so the output is the sum well as a carry bit. Details schematics are on the next page.

HALF ADDER; simply put this uses a 2XOR gate and a 2AND gate with the inputs x,y and outputs the sum s and carry bit c.

FULL ADDER; just 2 half adders, all to a 2OR. Inputs are x,y,z outputs are just the same sum and carry bit.

This circuit will be used multiple times for my 8 bit adder. To verify this circuit works when x = 1, y=0, z=0; s should be 1 and c shoul Part 1d (8-bit adder) d be 0 on the ouput. As you can see in the diagram above this is successful. WAVEFORMS BELOW> To test the funcationality of this full adder we can simply let bit x be 1. And to test the carry bit one of the half adders have to produce a carry. Or 2 of the inputs have to be 1. When x = 1. (n0) n2 which is sum bit is 1.

2 inputs 1. In this n3 and n0 are my inputs and n7 is my carry.

Part 1b (8-bit adder)

Finally, my 8 bit adder, using 8 full adders, 2 vertical expanders 1 merger. Therefore the inputs are 2 8 bit buses essentially and output is just one 8 bit bus and the carry.

To verify that this adder is indded functional I use three simple test cases. When both bytes are 0, and when both bytes add up to a number less then 255, and finally when they exceed the 255 limit and give a carry output. This is shown below using a waveform. N27 IS CARRY BIT N35 IS SUM BIT N1 and N4 are 8 bit inputs. When both are 0 n35(sum) is 0

When both are 126 and 129 the sum bit is 255.

When both add up to 255 or greater. You see when I change n4 to 127 the sum becomes 255 which makes n27 1 which is the carry bit and the sum bit is 0.

Reference Mano, M. M., & Kime, C. R. (2004). Logic Computer Design Fundamentals. New Jersey: Pearson Prentice Hall. Project 1 Part 1 Part 1A: To create an 8 bit 4-to-1 multiplexer A 8 bit 4-to-1 multiplexer is useful passing values through using 2 select bits. To make a 8 bit 4-to-1 multiplexer I used a 2-4 decoder and an 8 4x2 AND-OR. The decoder takes in the 2 select bits and gives out 4. Those 4 bits are used to AND each 8 bit buffer. 1AI: 2-4 decoder Gates used: 2 INV, 4 2AND Inputs: i1, i0 Outputs: a, b, c, d

Tested on all inputs(4) i1 (n0) i0(n1) a(n4) 0 0 1 1 0 1 0 1 1 0 0 0

b(n5) 0 1 0 0

c(n6) 0 0 1 0

d(n7) 0 0 0 1

The values obtained in the waveform match the truth table, so this means that the circuit is working correctly. 1AII: 4x2 AND-OR Gates used: 4 2AND, 1 4OR Inputs: a0, a1, a2, a3, b0, b1, b2, b3 Outputs: Z

1AIII: 8 4x2 AND-OR Gates used: 8 4x2 AND-ORs Inputs: A, B, C, D, 8 bit buffers I0, I1, I2, I3 Outputs: 8 bit buffer Z

1AIV: 8 bit 4-to-1 multiplexer Gates used: 2-4 decoder, 8 4x2 AND-OR Inputs: s0, s1 8 bit buffers i0, i1, i2, i3 Outputs: 8 bit buffer Z

Part 1B: To create an 8 bit adder An 8 bit adder adds two 8 bits buffers. It adds the two corresponding bits of each buffer. Such as 00000001+00000010. Which is 00000011. As you can see it adds by separating the buffer into every bit, and then does the same for the other buffer and adds the two bits which are of the same 2n place. If the sum is greater than 255, then the carry bit is flipped. An 8 bit adder can be created using 8 full adders. 1BI: Full adder Gates used: 2 2XOR, 4 2AND, 1 2OR Inputs: X,Y,Z Outputs: S, C

1BII: 8 bit Adder Gates used: 8 full adders Inputs: 8 bit Buffers A and B, VCC Outputs: 8 bit buffer S, C

CS 266 Part 2 Part 2: An 8 bit ALU is used to perform a set of basic arithmetic and logic micro operations. It does this by using a 3 bit bus as selection bits to choose the appropriate operation. It decodes the selection bits making it possible to do 8 different tasks. The ALU is composed of two primary parts. The Arithmetic circuit and the Logic circuit. Each take inputs A, B, alu_sel. The Arithmetic circuit also takes in c_in. The Following table shows the actions of the ALU.

Part 1: The Logic Circuit

The Logic circuit will be used to perform the tasks based on the alu_sel. Because alu_sel1 is always 0 when the Logic Circuit is needed, we can disregard the bit and only use alu_sel0 and alu_sel2 to choose

the desired operation.The Logic Circuit will be able to perform 4 different logic operations. NOT, OR, XOR, and AND. Part a: 8bit-OR inputs: Two 8 bit buses A and B output: 8 bit bus Y composed of 8 OR's, two expanders, and a merger

To test the 8bit-OR we see the wave form.

Part b: 8bit-inv inputs: One 8bit bus A outputs: Y composed of 8 inv, one expanders, and a merger

The wave form shows that it works properly

This is because when A is 255 Y is 0, meaning that every bit was negates. The same is true for when A is 0 since Y now becomes 255. Part c: 8bit XOR inputs: Two 8 bit buses A and B output: 8 bit bus Y composed of 8 XORs, two expanders, and a merger

The wave forms show that this circuit works because when both A and B are the same the out put is zero, the same way a XOR works.

part d: 8bit-AND inputs: Two 8 bit buses A and B output: 8 bit bus Y composed of 8 ANDS, two expanders, and a merger

The following waves show that the AND works.

part e: 8bit-4-1mux This is the same mux from part 1

To make the Logic circuit we simply pass the values of the logic gates to the mux. The select bits for

the mux are just alu_sel0 and alu_sel2. This is because the Logic circuit performs four tasks, and only 2 bits are needed to select the tasks from the mux, also aul_sel0 is always 0 when the Logic circuit is outputted.

Since we know that the 8bit logic gates that we made work as desired, to check if the Logic circuit works, we just have to check to see if the aul_sel bits are selecting the correct operation to pass to the out put of the Logic circuit.

A 3 3 3 3 3 3 3

B 5 5 5 5 5 5 5

aul_sel 000 001 010 011 100 101 110

ORy 7 7 7 7 7 7 7

INVy 252 252 252 252 252 252 252

XORy 6 6 6 6 6 6 6

ANDy 1 1 1 1 1 1 1

Y 7 252 7 252 6 1 6

3 5 111 7 252 6 1 7 The table shows how when alu_sel is set for the Logic circuit, the Y is the output corresponding to the operations in the ALU action table, there fore it works correctly.

Part 2: The Arithmetic Circuit

The Arithmetic Circuit is used to do various arithmetic operations to A and B. Depending on the selection bits alu_sel, the Arithmetic Circuit will do a different task. Because alu_sel1 is always 1 when the circuit is needed, we can disregard the bit and only use alu_sel0 and alu_sel2 to choose the desired operation. Using 2 bits will only give us 4 possible operations, but the use of c_in as a carry bit input allows us to be able to do 8 different operations for the circuit. The Arithmetic Circuit takes in A, B, aul_sel, and c_in. To design my circuit I used 8bit 4to1 MUX, design is above, (part 1a, Amar Patel) 8bit INV 4, 8-bit adders with carry, overflow, sum outputs (description above, Patel) 2 1-bit 4to1 muxs

To account for the new parameter that checks overflow I edited my (Patel) 8bit full adder to output v, the overflow bit. You can view previous adder from submission 1. Here is my new full adder; I used an XOR on the carry bit outputs of the last 2 full-adders.

The ALU:
Now that both components of the ALU are made we can combine both to form a working ALU. To do this we used the Logic Circuit, the Arithmetic Circuit and used other gates to output the sign bit if the operation uses a signed number. We also used other gates to choose whether the output should be that of the Logic Circuit or of the Arithmetic Circuit. Parts: Logic Circuit, Arithmetic Circuit, 8bit 4-1 mux, one 3AND gates, one 2OR gate, three 2AND gate, 1 3 bit expander, 1 8 bit expander , and one 8 bit merger

This table shows the inputs of the ALU

As you can see from the design, we AND the enable with all the single bit out puts. Although this means that the ALU still does computations, putting the enable at the end causes no problems with any of the parts. To determine which output(either the out put of the Logic Circuit or the Arithmetic Circuit) will pass to M we used an 8bit 4-1 mux. We use alu_sel1 to select between the two by using it as the s1 select bit of the mux. When it is 1, the output of the Arithmetic Circuit passes through. When it is 0, the value of the Logic Circuit passes through. The last two inputs of the mux(i2 and i3) are connected to ground, this with the enable bit connected to the s0 select bit of the mux makes it possible to pass zero

when enable is not selected. The m7 or the sign bit if the operation calls for sign numbers is produced by using the alu_sel, according to the different selects when alu_sel is 2 or 6, we have a signed number as our output, so m7 will just be the most significant bit, when alu_sel is 2 OR 6. Which is exactly what I implemented to account for this. I OR both when alu_sel is 2,6 then use that to AND both the most significant bit. The carry bit is produced using the adders, explained above and in the part1 of project, this AND the enable would simply produce the carry bit.

Using the waveform, we constructed the table to show that our ALU does in fact work according to the specified operations requested.

A 151 151 151 151 151 151 151 151 151 151 151 151 151

B 162 162 162 162 162 162 162 162 162 162 162 162 162

alu_sel 0 1 2 2 3 3 4 5 6 6 7 7 7

enable 0 0 0 0 0 0 0 0 0 0 0 0 1

c_in 0 0 0 1 0 1 0 0 0 1 1 0 0

M 183 104 244 245 58 57 53 130 150 151 152 151 0

v 0 0 1 0 0 1 1 0 0 0 0 0 0

m7 0 0 1 1 0 0 0 0 1 1 0 0 0

c_out 0 1 0 0 1 1 1 0 1 1 0 0 0

Part 3: Registers and Memory

3a) RegisterWithEn: A one bit register with enable. Used in the 8bitReg Parts: INV, 2 AND2,1 OR2, DFF Inputs: D , Load, clock Output: Q

Explanation: The waveform confirms the register works. Only when Load is high does the circuit work. When D is high Q is high on the first clock cycle. But when clock is high again and D is low Q is also low. When load is high Q is changed. So every clock cycle the value of D is what Q becomes only if load is high.

8bitReg: An 8-bit Register with enable. Used in IR, RegisterFile, and Memory. Parts: 8 Register with Enable, 8-bit Expander, 8-bit Merger Inputs: D (8 bit bus), Load, clock Outputs: Q (8 bit bus)

Explanation: This just takes the value of D into each bit in the registers which is merged and output to Q. The waveform explains that when enable or Load is high it takes the value of D and set Q to it. You can see that first clock cycle D goes into 0 when enable is high. But nothing happens until load is set to high. Same thing occurs when D is set to 5. The value of Q becomes 5 in this case right when another clock and load high.

Instruction Register Parts: 2 8bitReg, 8 bit merger, 16bit merger, 2 8bit_4-1Mux Inputs: in(8 bit bus), ir_ld0, ir_ld1(selects where in gets placed), oe(enables the output), clock Outputs: out(16 bit bus)

Explanation: The waveform for this circuit shows that the circuit only has output when oe is high which is like an enable. Furthermore, this shows how ir_ld1 and ir_dl0 choose the 8 bit register, referring to 3.0 and 5.0 on the waveform. The first change is after the first clock cycle at 3.0 when out becomes 257. At 5.0 again the clock is changed and the new value relative to the inputs ir_ld1 and ir_ld0 becomes 1. This shows this circuit is working the way that it should.

3b) 8bit 8-1mux: Used in the RegisterFile. Parts: 3 8bit_4-1Mux, 3 bit expander, 8 bit merger Inputs: i0,i1,i2,i3,i4,i5,i6,i7, (all 8 bit) sel (3 bit). Outputs: out (8 bit)

Explanation: This 8 bit mux like previous circuits of this nature we have created in this project works similarly. We set the input busses to the name of the corresponding input bus to help show using the waveform that the 8 to 1 mux works like it is supposed to. If you look at the out, it is set to the value of the input when the corresponding select is chosen, this suggests that the circuit is in fact functional.

RegisterFile: Used in Memory.

Parts: 8 8bitReg, 2 8bit_8-1Mux Inputs: RES (8 bit bus), r0_u, r1_u, r2_u, r3_u, r4_u, r5_u, r6_u, r7_u, clock, a_sel, and b_sel (both sel 3bit) Outputs: A, B (Both 8bit bus)

Explanation: As you can see, from 0 to 6 ns we are just loading the values into the individual registers. The values that are loaded correspond to the address of the register, so the first register is has the value 0 stored. From 6.0ns to 8.0ns we are simply choosing the outputs of the register file. This means that A_sel and B_sel chooses what value of RES will be the output to A and B. Above you can see that this is what happens when the inputs are changed from 0 to 7 for testing purposes, the results of the A and B outputs are correctly reflect what is needed for this register.

3c) DecForMem Parts: 4 2-4 Decoders, 16 AND4, 8 bit expander Inputs: in (8bit bus) Outputs: 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16

Explanation: This waveform shows that we only need a 16 word memory, which the problem specified. To retrieve the addresses from the 8 bit bus, we created something similar to an 8 bit decoder. But instead of using all the values that an 8bit decoder would produce, we only used the first 16. This works because we will never have an address that is bigger than 15. As you can see from the waveform, as the IN bus increases from 0 to 15, the corresponding output bits are flipped. So when IN is 9, only output 9 is flipped.

Memory: Parts: DecForMem, 2 8bitReg, 16 AND2, 2 RegisterFile, INV, Mergers, Expanders Inputs: write, clock, 8 bit ALU, mdr_sel (2 bit bus), mar_sel,

Outputs: out (8bit bus)

Explanation: The memory circuit is valid, we can confirm this by showing the values of the input and outputs using the waveform. The first of the three images above show test when mdr_sel is 1, which outputs the value of the ALU circuit. as you will observe from the waves, write is alternating meaning that during this time we are also writing to the register files. To clarify the process, the values stored in memory correspond to the individual address. This allows someone to fully understand how to circuit works using the waveform. Meaning that the memory at address 4, has a value of 4. Moreover, for the second of the three waveforms we are still writing, until 25ns. Which is when mdr_sel is 0, meaning that the mdr is now obtaining data from the 2 register files. The address of the data that mdr retrieves is set by mar, which gets the address from the ALU. We can understand this process by reviewing the waveform after 25ns. We observe that the value in the ALU is the address. For example when the value of the ALU is 4, the output becomes 4. This means that mdr has acquired the data from the 4th register, since 4 is the value that was stored in said register.

Part 4: Complete Processor

A) 3bit 4-1 mux: A 3 bit 4-to-1 mux used in the construction of the controlUnit, IR-Loader, and the final processor. Parts: 4 3-bit Expanders, 3 4-to-1 mux, 3 bit Merger Inputs: i0, i1, i2, i3, i4, s0, s1 Outputs: out

The waveform for the muc confirms that the circuit works. We know this because as you can see when s1 and s0 are 0, the value that is outputted is 0, which corresponds to the first input. As s1 and s2 increment, the values that are outputted are those of the corresponding inputs. For example 1 corresponds to the i1 input, and 2 for the i2 input. controlUnit: The control unit get the instruction from IR and sends the corresponding signals to the ALU, the memory, IR, and the Register file. Parts: Inputs: Outputs:

The controlUnit had to separate the instruction word and send the correct values to their designated areas. It also had to output the correct instruction for the ALU based on the opcode.
Opcode Operation 10000 XOR 10010 Subtraction 10001 XOR with Immediate 10011 Subtraction with Immediate 00100 Store 01000 Load

This waveform is for testing the first format of the instruction word. The first format being:
bits bits bits bits bits 15 10 07 05 02 11 08 06 03 00 Opcode register to store result unused first operand second operand

As you can see the decimal instruction 34059, which is 1000-101-00-001-011, outputs the values that correspond to the correct instruction. The instruction being R1 XOR R3 -->R5

This waveform shows the test for the second format of the instruction word, when we are using and immediate value or sending a memory address. The second format is so:
bits 15 - 11 Opcode bits 10 - 08 Register bits 07 - 00 memory address or immediate value

As you can see for the tested decimal instruction 39951, which is 10011-100-00001111 the outputs reflect the format. The immediate signal is on because the instruction is to subtract 16 from R4 and store that in R4. When the immediate signal is on, we dont care about B because this signal passes the value 16 into the ALU.

B) counter: The counter is includedin the IR-Loader to generate signals. This part simply cycles through the 4 possible outputs. It counts from 0 to 3 and outputs the results in two ways, decoded in 4 bits, or encoded with 2 bits. The reason for this being that in some instances it is better to use the encoded result, while other times it makes more sense to use the decoded values. Parts: 4 AND2, AND3, 6 INV, OR3, OR2, 2 DFF, 2-4 Decoder Inputs: Start, Clock, reset Outputs: 0, 1, 2, 3, encodedout, encodedout1

IR-Loader: The IR-Loader generates signals that are used to load the individual parts of IR. It does this by using the counter to select between the predetermined values to output.These values correspond to the values that are used with the ALU, memory, the IR, and register file. Parts: 5 3bit Merger, Counter, 2 3bit 4-to-1 Mux, OR2 Inputs: InstructDone, start, clock, reset, Outputs: done, ir1_sel, ir0_sel, cin, a_sel, alu_sel, mdr_sel

C) 2-1mux: This mux is used to select between c_in values in the final processor circuit. Parts: INV, 2AND, 2OR Inputs: A, B, sel

Outputs: out

Processor: To create the processor, we combined all the previous parts from the whole project. At the current stated of this part, the Processor is not functional. However All the major component have wired and what is missing is timing parameter. Parts: All the parts from the previous projects. Inputs: At this point, none. Outputs: None