EE559 MOS VLSI Design

EE559: MOS VLSI Design

Instructors: K. Roy I t t K R
Email: kaushik@ecn.purdue.edu URL1: www.ece.purdue.edu/~kaushik Office: MSEE 232 Telephone: 494-2361 Office Hours: Tuesday/Thursday 11am-12noon or b appointments by i t t

Grading Policy
Mid-terms + quizzes + hw will account for 75% of the grade
3 mid-terms Mandatory and has to be taken on the scheduled day of the exam.

Project will account for 25% of the grade. Late projects will not be accepted. You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above. Any form of cheating will be heavily penalized and reported to the Dean of students and may result in a failing g y g grade. Instructor reserves right to change project requirements.

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EE559 MOS VLSI Design

Text and References

Text:
Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall, Second edition

References:
Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley Circuits, Interconnects, and Packaging for VLSI, H. Bakoglu, Addison Wesley

Class Notes:
http://www.ece.purdue.edu/~vlsi/ee559/20001

Conferences & Journals

IEEE Transactions on VLSI Systems IEEE Transactions on CAD of ICs IC s IEEE Journal of Solid State Circuits IEEE VLSI Circuits Symposium Journal of Electronic Testing ACM Design Automation Conference IEEE International Conference on CAD IEEE Solid State Circuits Conference International symposium on Low-Power Electronics & Design IEEE Conference on Computer Design IEEE International Test Conference

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EE559 MOS VLSI Design

Course Outline
Introduction: Historical perspective and Future Trend Semiconductor Devices CMOS Logic Layout techniques Logic, MOS devices, SPICE models Inverters: transfer characteristics, static and dynamic behavior, power and energy consumption of static MOS inverters Designing combinational logic gates in CMOS
Static CMOS design: Complementary CMOS, ratioed logic, pass-transistor logic Dynamic CMOS logic

Course Outline (Contd)

Designing combinational logic gates (Contd)
Power consumption in CMOS g p gates Low-power design

Designing sequential circuits Interconnect and timing issues Designing memory and array structures Designing arithmetic building blocks VLSI testing and verification S f

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EE559 MOS VLSI Design

VLSI CAD Lab and TA

VLSI CAD Lab located in 360 Potter Engineering Center
SUN workstations running Mentor Graphics tools Courtesy key for after-hour access can be obtained from front desk in Potter Engineering Library Additional workstations in MSEE 186

Lab TA: Kuntal Roy (royk@purdue.edu)

Facilitates the use of lab design tools. Office hours: TBA Lab Orientation will be held in the second week

Lab URL
http://min.ecn.purdue.edu/~mgcdevel/ee559_lab.html

Course Project
Complete design of a functional logic block or system
Complexity of 1000+ transistors or novelty Design using the CADENCE tools and HSPICE
Design your own library from scratch

Functionality to be verified Critical path timing should be verified using HSPICE Project report due the last day of class Project presentation by each group in the last week of class Work in a group of 2 will be allowed in special cases Start early! Emphasis on new ideas, power dissipation, performance, reconfigurability, low voltage design

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EE559 MOS VLSI Design

Introduction: A Historical Perspective and Future Trends

References:
Adapted from: Digital Integrated Circuits: A Design Perspective, p g g g p J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

Digital Computation: Particle Location is an Indicator of State

1 1 0 0 1 0

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EE559 MOS VLSI Design

Physical Medium for Computation: Barrier Model

GATE

V=0

SOURCE

DRAIN

Leff

Tox

V=Vmin=Ebmin Eb

Vg

Vd

1. Can we operate with Vmin ~ KBTln2 ? 2. Can we operate with Qmin = q ?

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EE559 MOS VLSI Design

The First Computer

The Babbage Differential g Engine (1834) 25,000 mechanical parts Cost 17,470

Digital Electronic Computing

Started with the introduction of vacuum tube ENIAC for computing artillery firing tables in 1946 Integration density
80 feet long, 8.5 feet high, and several feet wide 18,000 vacuum tubes

Reliability issues and excessive power consumption Did not go far until the invention of the transistor at Bell Lab in 1947

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EE559 MOS VLSI Design

HISTORY
MOS field-effect transistor: Lilienfeld (1925), Heil (1935) Bipolar transistors: Bardeen (1947), Schockley (1949) First Bipolar digital logic: Harris (1956)
IC Logic family:
Transistor-Transistor Logic (TTL) (1962) Emitter-Coupled Logic (ECL) (1971) Integrated Injection Logic (I2L) (1972)

PMOS and NMOS transistors on the same substrate: Weimer ( (1962), Wanlass (1965) ), ( ) PMOS-only logic until 1971 when NMOS technology emerged NMOS-only logic until late 1970s, when CMOS technology took over Later developments: BiCMOS, GaAs, low-temperator CMOS, super-conducting technologies, Nano-electronic

Exponential Increase in Leakage

1970 1980 2000 2010 2020

5 m

1 m

100 nm

10 nm Non Silicon Non-Silicon Technology

Silicon Micro- electronics

I ON = 106 I OFF
Subthreshold Gate Leakage Leakage Gate
Source S

Silicon Nano- electronics

I ON = 103 I OFF
Leakage Power (% of Total) % 50% 40% 30% 20% 10% 0%

I ON ~ 102~6 I OFF

Must stop at 50%

Drain

n+

n+
Junction leakage
Bulk

A. Grove, IEDM 2002

1.5

0.7

0.35 0.18 0.09 0.05

Technology ()

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EE559 MOS VLSI Design

Technology Trend

Fully-depleted body
VG

Nano devices
VD

Bulk-CMOS
VG VS Gate VD Source Floating Body Drain

VS Source

Gate

Drain

DGMOS

Buried Oxide (BOX)

Substrate Vback

Buried Oxide (BOX) Substrate

FD/SOI

Carbon nanotube III-V devices nano-wires Spintronics

FinFET

Trigate

PD/SOI

Single gate device

Multi-gate devices

Design methods to exploit the advantages of technology innovations

The Scale of Things Nanometers and More

Things Natural
10-2 m 1 cm 10 mm

Things Manmade
Head of a pin 1-2 mm

The Challenge

Ant ~ 5 mm

10-3 m

1,000,000 nanometers = 1 millimeter (mm)

Microwave

Dust mite 200 m

4 10-4 m

MicroElectroMechanical (MEMS) devices 10 -100 m wide

0.1 0 1 mm 100 m

Human hair ~ 60-120 m wide

Microworld

Fly ash ~ 10-20 m

10-5 m

0.01 mm 10 m
Infrared

O O

Red blood cells with white cell ~ 2-5 m

Pollen grain Red blood cells Zone plate x-ray lens Outer ring spacing ~35 nm

10-6 m

1,000 nanometers = 1 micrometer (m)

Visible

Smaller is different!
10-7 m

Nanoworld

Ultraviolet

0.1 m 100 nm Self-assembled, Nature-inspired structure Many 10s of nm Nanotube electrode

Fabricate and combine nanoscale building blocks to make useful devices, e.g., a photosynthetic reaction center with integral semiconductor storage.

10-8 m

~10 nm diameter ATP synthase

0.01 m 10 nm

10-9 m
Soft x-ray

1 nanometer (nm)

More is different!
DNA ~2-1/2 nm diameter Atoms of silicon spacing ~tenths of nm 10-10 m 0.1 nm Quantum corral of 48 iron atoms on copper surface positioned one at a time with an STM tip Corral diameter 14 nm

Carbon nanotube ~1.3 nm diameter

Carbon buckyball ~1 nm diameter

Office of Basic Energy Sciences Office of Science, U.S. DOE Version 10-07-03, pmd

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EE559 MOS VLSI Design

Variation in Process Parameters

1 .4 Nor rmalized Frequency

Device 1

Device 2

1 .3 1 .2

30%
130nm

1 .1 1 .0 0 .9

Source: Intel
5X
1 2 3 4 N o rm a liz e d L e a k a g e ( Is b ) 5

Channel length
# dopant atoms

Delay and Leakage Spread

10000

Source: Intel
1000 100 10
1000 500 250 130 65 32

Inter and Intra-die Variations

Technology Node (nm)

Random dopant fluctuation

Device parameters are no longer deterministic

Reliability
Temporal degradation of performance -- NBTI
Failure probability y

Tech. generation

Time Defects Interface trap generation over time Life time Lif ti degradation

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EE559 MOS VLSI Design

Scaling & Ion/Ioff

1 um 100 nm 10 nm

Silicon micro electronics

Silicon nano electronics

Non-Silicon technology I V Carbon Nanotubes Molecular transistors Molecular RTDs

Increasing leakage Increasing p process variations Short Channel Effects

I ON = 106 I OFF
I ON = 103 I OFF

I ON = 10 4 I OFF

2. Power & Power Density

100 P6 10 8086 8085 1 8080 8008 4004 286 386 486

0.1 1971 1974 1978 1985 1992 2000

Year Increased Average Power Battery Life Cooling Cost

Source: Intel

Power Density (W/cm2)

Pentium proc

Power (Wa atts)

Year Increased Power Density Reliability

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EE559 MOS VLSI Design

Nano-Scaled Si Devices
Si Fin

DGMOS
Planar double-gate structure

FinFET or Tri-Gate
Quasi-planar DG structure

Ground PlaneSOI MOS

Shared back gate DG devices

Independent gate FinFET

Bulk Si MOSFETs

Variation in Process Parameters

Freque ency (norm) q y
1 .4 1 .3 1 .2

30%
130nm

1 .1 1 .0 0 .9 1 2 3

Source: Intel S I t l
5X
4 5

Leakage (normalized)
10000

# dopant ato oms

Source: Intel
1000 100 10

Inter and Intra-die Variations

1000 500

250 130

65

32

Technology Node (nm)

Random dopant fluctuation

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EE559 MOS VLSI Design

Evolution in Complexity

Processor Trends
800 700 600 500 400 300 i386 200 100 0 i386C-33 HP PA8000 UltraSparc-167 PPro 150 PPro-150 MIPS R10000 SuperSparc2-90 A21164-300 HP PA7200 PPro200 Die Size (mil2) PPC 604-120 A21064A MIPS R4400 PP-100 PPC 601-80 486-66 i486C-33 DX4 100 PP-133

PP-66 PP 66

'91

'93

'94

'95

'96

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EE559 MOS VLSI Design

Processor Trends (contd)

300 A21064A 250 A21164-300

200 Freq(MHz)

M R4400 IPS

HP PA8000 UltraSparc-167

M R5000 IPS PPro200 M R10000 IPS

150

HP PA7200 PP-133 DX4 100

PP166 PPro-150

PPC 604-120 100 PP-100 SuperSparc2-90 PPC603e-100

50

486-66 PPC 601-80 PP-66 i386C-33 i486C-33 i386

'91 '93 '94 '95 '96

Higher Performance: Higher Frequencies (2x/Generation) Higher Device counts (2x /Generation)

Power Trends
40 35 30 25 Power(W) 20 15 10 5 0 PP-66 PPC 601-80 i486C-33
'91

A21164-300

HP PA8000

A21064A UltraSparc-167 PPro-150 HP PA7200

PPro200 MIPS R10000

SuperSparc2-90 PPC 604-120 MIPS R4400 PP-100 PP-133 MIPS R5000 PP166

486-66 DX4 100

'93 '94 '94

PPC603e-100
'95 '96 [Source: Microprocessor Report]

i386 i386C-33

2x Performance Increase ==> 2x power increase

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EE559 MOS VLSI Design

Heat Dissipation
Chips fail when they get hot Need compact and cost-effective cooling solns p g
CPU 486/33mhz 486DX2 66mhz Pentium 66mhz Thermal Soln Cost HeatSink $0.50 Heatsink $1.00 Larger Heatsink $2.00 System Fan $4.00

Cooling Solns will become more exotic/expensive

Extruded Heatsinks, Heatpipes, Blowers, Noise....

Every Watt impacts System Cost, esp. for HVM

Where is the Power Going? (Mobile PC)

30 25 20 15 10 5 0 89 CPU 91 92 93 Graphics 94 95 I/O Subsystem 96 Total 97

CPU Power: predicted from average device count/area growth p g g

CPU Power increasing (Predicted in 1994 Low power workshop) Graphics & Chipset Power increasing faster than predicted
Power reduction is not only a CPU problem

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EE559 MOS VLSI Design

Intel 4004 Microprocessor

Intel Pentium (II) Microprocessor

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EE559 MOS VLSI Design

Dunnington is the first IA (Intel Architecture) processor with 6-cores, is based on the 45nm high-k process technology, and has large shared caches.

Tukwila, 4-cores, world's first 2 billion transistor microprocessor

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EE559 MOS VLSI Design

National Technology Roadmap for Semiconductor (NTRS)

Technology (um) T h l ( ) Year # transistors On-Chip Clock (MHz) Area (mm2) Wiring Levels

0.25 0 25 1998 28M 450 300 5

0.18 0 18 2001 64M 600 360 5-6

0.13 0 13 2004 150M 800 430 6

0.10 0 10 2007 350M 1000 520 6-7

0.07 0 07 2010 800M 1100 620 7-8

Interconnect Performance Trend

Technology (um) 2cm line delay (ns) 1mm line delay (ns)

0.25 0.18 0.15 2.589 2.480 2.650 0.059 0.049 0.051

0.13 2.620 0.044 0.045

0.10 3.730 0.052 0.039

0.07 4.670 0.042 0.022

Intrinsic gate delay (ns) 0.071 0.051 0.049

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EE559 MOS VLSI Design

Interconnect Complexity
Technology (um) Length (m) Wiring Levels Opt. # buffers per net Opt. # wiresizes per net Opt. # buffers per chip 0.25 0.18 820 1,480 6 6-7 6 few few 5K 25K 0.13 2,840 7 0.10 5,140 7-8 8 0.07 10,000 8-9 89 many many 230K 797K

54K

Performance Signal reliability Electromigration

Distributions of Wire lengths

1E+07

Nu umber of Interconnect ts

1E+06 1E+05 1E+04 1E+03 1E+02 1E+01

0.25 um tech.

Rent's exponent = 0.6 Rent s Rent's coefficient = 4.0 Avg. fanout = 3

0.07 um tech.

1E+00

10

20

30

Length (mm)

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EE559 MOS VLSI Design

Technology Scaling
Technology scaling improves: Transistor & interconnect performance Transistor density Energy consumed per switching transition 0.7X scaling factor (30% scaling) results in: 30% gate d l reduction (43% f t delay d ti freq. ) 2X transistor density increase (49% area ) Energy per transition reduction

Technology Scaling
Speed & Performance
High drive current and low parasitics Low gate delay and high frequency

Density & Area

Small feature size

Power & Reliability

Low power supply voltage L Low off-state leakage ff t t l k

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EE559 MOS VLSI Design

Technology Generation Scaling

Dimensions scale 0.7, Vdd scales , Vt scales I= kW 0.7 (Vdd Vt ) scales = Tox 0.7 CVdd I
2

D=

scales

0.7

= 0.7

(30% delay reduction)

E = CVdd

scales 0.7

IC Frequency & Power Trends

Clock frequency improves 50% Gate delay improves ~30% Power increases 50% Power = CL V2 f

1000 1000 100 100 10 10 11

Power

Chip Power (W) Chip Power (W W)

Pentium R Processor

800 800 600 600

486DX CPU 386

400 Frequency 200

7

0.1 0.1
1 2 3 4

0.01 0.01

00

1.0 0.8

0.6 .35 .25 .18

Technology Generation (m)

Active switched capacitance CL is increasing.
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Fr requency (M Hz) ) Frequency (MH Hz)

Pentium R II Processor

1000 1000

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EE559 MOS VLSI Design

Constant Voltage vs Field Scaling

Recently: constant efield scaling, aka voltage scaling VCC 1V VCC & modest VT scaling Loss in gate overdrive (VCC-VT)

5 VCC or VT (V)
V CC or V T (V)

5 4 3

VCC

4 3

22 11 00
0

(VCC- VT ) Gate over drive

VCC=1.8V

VT
1 2 3 4

VT =.45V

1.4 1.0 0.8 0.6 .35 .25 .18 Technology Generation (m)
Voltage scaling is good for controlling ICs active power, but it requires aggressive VT scaling for high performance
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Barriers to Voltage Scaling

Voltage Scaling = Constant Electric Field Scaling Voltage scaling is good for ICs active power, but degrades gate over drive. Requires VT scaling.

Leakage power Short-channel effects Special circuit functionality, noise Soft error Parameter variation
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EE559 MOS VLSI Design

Barriers to Voltage Scaling

Subthreshold Leak kage
1000 constrained Ioff maintain Vcc/Vt

100

10

1 0.25um 0.18um 0.13um 0.09um

Leakage power Short-channel effects Soft error Special circuit functionality

Technology Generation

61

Delay
CV d = L DD ID
d =
CL V W ( ) C oxV DD (1 T ) 2 2L V DD

Long Channel MOSFET

d =

CL WC ox SAT (1 VT ) VDD

Short Channel MOSFET

. CL0.5T 05 1 2.2 ox ( ) = + V W W 13 n . 0.3(0.9 T p V V ) DD DD

[1]

[1] C. Hu, Low Power Design Methodologies, Kluwer Academic Publishers, p. 25.

Performance significantly degrades when VDD approaches 3VT.

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EE559 MOS VLSI Design

VT Scaling: VT and IOFF Trade-off

Performance vs Leakage: VT IOFF ID(SAT) ID(SAT)

Low VT
IDS
K1e
(VGS VT )

I OFF I subth
I D ( SAT )

Weff Leff

High VT
VD = VDD fixed Tox

Weff Leff

IOFFL IOFFH VTL VTH

K 2 (VGS VT ) 2

I D ( SAT ) K 3Weff Cox SAT (VGS VT )

VG

As VT decreases, sub-threshold leakage increases Leakage is a barrier to voltage scaling

63

IOFF vs VT
1E-04

IOFF (A)
1E-05

1E-06

Log IOFF

1E-07

1E-08

I OFF e (VGS VT )

1E-09

1E-10 -0.5

-0.45

-0.4

-0.35

-0.3

-0.25

-0.2

VT (V) - Normalized

VTP (V)

IOFF is an exponential function of VT.

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EE559 MOS VLSI Design

Future: Projected Leakage Trends

10,000 0.10 um 0.13 um 1,000 IOFF (nA/ m) 0.18 um 0.25 0 25 um

100

10

30

40

50

60

70

80

90

100 110

Temperature (C)

IOFF (0.25um) = 1 nA/um (scales 5X) VT (0.25um) = 450 mV (scales by 15%)

St (30C) = 80 mV/dec St (100C) = 100 d VT/dT = 0.7 mV/C

Why Excessive leakage an Issue?

Leakage component to active power becomes significant % of total power Approaching ~10% in 0.18 m technology Acceptable limit less than ~10%, implies serious challenge in VT scaling!
1 10100 1 1010
1.E+02

1.E+01

Active Power

Power (W) )

0 101

1.E+00

10

-1 10-1
-2 -3

1.E-01

386

Pentium P ti 486DX Processor CPU

Pentium R Pro Processor

-2 1010 -3 1010

1.E-02

1.E-03

10-4 10-5 10

10-4 10-5 10-6 -6 6

1.E-04

Standby power (component Transistor Leakage T=110C)

1.E-05

1.E-06 0 1 2 3 4 5 6 7

1.0 0.8 0.6 .35 .25 .18 Technology Generation (m)

Barrier

high static leakage (standby) power

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EE559 MOS VLSI Design

Power Trends
Enable development of ultra low voltage circuits Vt Variation for optimum energy At lower Vt, 2.5
Normalized Energy

leakage becomes a p g problem 2 Signal integrity and Noise margin

1.5

Vdd =1.7V Decreasing Switching Power Decreasing Leakage Power

Vdd = 0..5V

f=20MHz

Vdd = 0..9V 0.5 Multiple on-chip Vt Vt, 0 0.2 dynamic Vt Other challenges for low voltages ? 0.4 0.6 Threshold Voltage (Vt) 0.8 1

[Source: A.Chandrakasan et.al. Proc of IEEE April95]

Trends in Microelectronics
Improvement in device technology
Smaller circuits Faster circuits More circuits on a chip

Higher Integration
More complex systems Lower cost of computation Higher reliability

Limitations
Intrinsic device scaling limits Cost of fabrication Interconnect limitation Large scale design management

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EE559 MOS VLSI Design

Problems of Microelectronics
Design Cost:
design time fabrication time impossibility t repair i ibilit to i reduce design cost to be competitive in price

Marketing Issues:
use most recent technologies to stay competitive in performance volume production is inexpensive time-to-market is critical evolving market

Solution:
Hierarchical and abstraction Different design styles Computer-Aided-Design

Circuit and System Representations

Complex digital system Component gates + Memory systems

3 design domains
Behavioral
specifies what a particular system does

Structural
how entities are connected together to effect the prescribed manner

Physical
how to actually build a structure that has the required connectivity to implement the prescribed behavior

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EE559 MOS VLSI Design

Design Abstraction Levels

SYSTEM

MODULE + GATE

CIRCUIT

DEVICE G S n+ D n+

For a Digital Design

Architecture Algorithm Module or Functional Block logical Switch Circuit Layout

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EE559 MOS VLSI Design

Behavioral Representation Domain

Hardware description language
VHDL Verilog VHDL, V il

Boolean equation Within this domain, there are various level of abstraction
Algorithm Register transfer level (communication between registers)

Acc

Acc + R1 CO = A.B + A.C + B.C carry

Boolean equations

Behavioral Representation Domain - cont.

Algorithm level (Verilog)

can include speed info

MODULE carry (co, a,b,c) output co input a, b, c assign co = (a&b)|(a&c)|(b&c); ENDMODULE

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EE559 MOS VLSI Design

Structural Domain
The levels of abstraction include
module gate switch circuit

MODULE carry (co, a, b, c) input a, b, c; output co; wire x, y, z , AND g1 (x, a, b) AND g2 (y, a, c) AND g3 (z, b, c) OR g4 (co, x, y, z); ENDMODULE

Structural Domain- cont.

a b g1

b c g3

a c g2

x y z g4

co

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EE559 MOS VLSI Design

Transistor Level
MODULE carry (co, a, b, c) input a, b, c; output co; wire i1, i2, i3, i4, cn; NMOS n1(i1, vss, a) NMOS n2(i1, vss, b)

. . . . . .

p ( , , ); PMOS p1(i3, vdd, b); PMOS p2(cn, i3, a);

ENDMODULE

Physical Representation
MODULE carry ; Input a, b, c; p , , ; output co; boundary [0, 0, 100, 400] port a aluminum width = 1 origin = [0,2] port b aluminum width = 1 origin = [0,7] port

. . .

Port ci polysilicon .
ENDMODULE

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EE559 MOS VLSI Design

CMOS Logic
a s b s b a

NMOS transistor
a s=0 b a s=1 s=1 b a b s=1 a

PMOS transistor
a

Consider them as switches

s=0 b s=0 b a a b b a b

Inverter (A)
VDD

- Low power dissipation

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EE559 MOS VLSI Design

NAND (AB)

A+ B
A B 0 Out A 1 B B

A.B

NOR (A+B)

A. B
B 0 B A B 1

A+B

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EE559 MOS VLSI Design

Complex Gates
F = (( A + B + C ).D ) = D + ABC
F = ( A + B + C ).D
A B C D

VLSI Design is Inter-Disciplinary

Breadth of field
Semiconductor physics and technology Integrated electronics Systems design Testing Computer-Aided Design

Depth of field p
Complexity of fabrication technology Difficulty of design problems

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