1. what are the various timing models?

Different timing models are EXTRACTED TIMING MODEL:-ETMs offer significant performance improvements over the original netlist, but because circuit timing is abstracted there is some loss of accuracy -Original netlist replaced by model containing timing arcs for block interfaces. -NLDM lookup tables are extracted for each of the timing arcs. -These arcs whose delay are a function of input transition and output load. This makes ETM usable with different input transition times and different output loads. -Used for implementation (not sign-off) of IP models. Here the content are protected because the model contains abstracted timing information, without any netlist information Advantages of ETM -Much smaller than the original netlist. -Significantly reduce the time needed to analyze a large design. -Using a model in place of a netlist prevents a user from seeing the contents of the block. INTERFACE LOGIC MODEL: It is a gate level model of a physical block normally used in hierarchical design flows. In this model, only the connections from the inputs to the first stage of flip-flops, and the connections from the last stage of flip-flops to the outputs are in the model (including the flip-flops and the clock tree driving these flip-flops). All other internal flip-flop to flip-flop paths are stripped out of ILM model. When the chip becomes very large, sometimes it takes too long to run static timing analysis on the full chip. The way to get around this problem is to run STA on the block level for intrablock paths, and then run a chip level STA for intra-block paths. Once timing closure has been achieved on all hierarchical blocks, these blocks are integrated to create the final chip implementation. QUICK TIME MODEL Provide means to quickly and easily create a timing model of an unfinished block for performing timing analysis. A temporary model used early in the design cycle for a block that has no netlist available. QTM creation is faster than writing ad-hoc model . The model contains both min and max time arc for setup and hold checks.
2. What are the different tree types.

best_case_tree estimates only the wire capacitance because the load pin is modeled adjacent to the driver. The capacitance is modeled before any resistance of the net at the output pin of the driving cell.

worst_case_tree estimates both the wire capacitance and wire resistance because the load pin is modeled at the end of the wire. This puts the capacitance for each load modeled at the end of the wire,

and each leg of the wire is assumed to have the entire R value.

balanced_tree estimates both the wire capacitance and wire resistance equally because all the load pins are modeled on equal branches of the interconnect wire.

3. How to identify from the library that it is of 20nm technology library and what are the standard cells that you found in that library

The technology used is always present in library HEADER -Buffer/3-state Buffer w/ & w/o enable/Inverter -Half/Full Adder -Mux with/without inverted output -Clock Buffer/Inverted Clock Buffer/Gated Clock Latch -DFF: pos-edge, neg-edge, async/sync R/S, -Enable DFF; async/sync R, w/o R - Scan version of all DFFs -Latch: active high/low enable, async R/S - INV/NAND/AND/MUX/XOR
-Antenna cell/Decoupling cells 4. What is miller effect.

When there is an opposite voltage swing in two wires the coupling capacitance between them is doubled and this phonomenon leading to more capacitance is called miller effect which produces devastating effects in integrated circuits.

5. How are access time and data hold time for a memory defined in memory.lib?

6. What are pre-control and post-control in clock gating and its advantages

Post control:

-In post control the combinational logic (AND of EN & SI) comes after the latch. Post control limits your ability to check proper operation of the CG latch . It has got timing advantage .

Pre control:

-In pre control the combo logic appears before the latch.

-It is DFT compatible.

7. what are Mill grades and Commercial grades?

Commercial temperature range: 0 to 70 degree Celsius Miltary temperature range:-55 to +125 degree Celsius Industrial temperature range :-40 to +85 degree Celsius

8. What are the different types of paracitic extractions?

Parasitic data contains extracted R and C values from actual routing Different file formats are, SBPF-Synopsys Binary Parasitic Format SPF-Standard Parasitic Format SPEF-Standard Parasitic Extraction Format DSPF-Detailed Standard Parasitic Format RSPF-Reduced Standard Parasitic Format --SBPF SBPF is a Synopsys binary format supported by PrimeTime. Parasitic data converted to this format occupies less disk space and can be read much faster than the same data stored in SPEF format. --RSPF RSPF represents each net as an RC "pi" model, which consists of an equivalent near" capacitance at the driver of the net, an equivalent "far" capacitance for the net, and an equivalent resistance connecting these two capacitances. Each net has a single "pi" network for the network, regardless of how many pins are on the net. --DSPF DSPF models a detailed network of RC parasitics for every net. DSPF is therefore more accurate than RSPF, but DPSF files can be an order of magnitude larger than RSPF files for the same design. In addition, there is no specification for coupling caps in DSPF. DSPF is more similar to a SPICE netlist than the other formats. --SPEF It is an IEEE standard for representing parasitic data of wires in a chip. SPEF is most popular specification for parasitic exchange between different tools of EDA domain during any phase of design. --SPF SPF is a Cadence Design Systems standard for defining netlist parasitics

9. What is OPP?

Operating Point of Power ,Performance ,Area Scheduler With respect to standard cell library -Track height -Availability of multi Vt and multi channel length cells -Operating range