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Why these special cells are used in design?

Decap cells: Decap cells are basically capacitors used for decoupling. The gates in a circuit consume most power (dynamic) only at the clock edges. No voltage source is perfect hence glitches are produced on the power line due to huge current draw at the clock edges. Decap filler cells are small capacitors which are placed between vdd and ground all over the layout. all these small capacitors add up to a big capacitor between vdd and ground. This helps to smoothen out the glitches. End cap cells: End caps are placed at the end of cell rows and handle end-of-row well tie-off requirements. The library does not have well or substrate ties inside the cells. You are required to tie the NWELLS to Vdd and the substrate to Vss before place-and-route using the FILLTIE cell. End caps are used to connect power and ground rails across an area and are also used to ensure gaps do not occur between well or implant layers which could cause design rule violations. End cap is placed at right or left most boundary filler cell for isolation of routing. Route is not beyond end cap area. it does not allowed to routing come out side beyond end cap. An end cap normally terminates or ends the follow pins at the ends. It also means, that it is end of the row, if not dangling nets will not be reported. Well tap cells: The CMOS FETs are actually 4 terminal devices, source, gate, drain and body. TAP cells provide a low resistance connection path to the body. In digital circuits, body of MOSFETs is usually connected to the power or ground. That is why if you look closely at the digital P&R layout, you'll see the TAP cells are usually on the power rails of standard cells. Tap cells gives reverse bias to the nwell and p well. This is to avoid latch up. Latch up in simple words is, phenomenon where the thyristor formed by adjacent junctions in the substrate turns on and goes to a high current mode. Well tap cells are used to limit resistance between power or ground connections to wells of the substrate. Taps are traditionally used so that your VDD and GND are connected to substrate and n-wells respectively. This is to help tie them to your VDD and GND levels so that they don't drift too much (especially towards the middle of the chip) and cause latchup. How the tool will place decap cells for the list of decap you mention? The following command adds 1000 fF of capacitance to the design using DECAP1 and DECAP8 cells, in that order addDeCap -totCap 1000 -cells DECAP1 DECAP8 Explore the various options in setPlaceMode and setOptMode command? setPlaceMode [-congEffort {low | medium | high | auto}] [-powerDriven {true | false}]

[-timingDriven {true | false}] [-wireLenOptEffort {none | medium | high}] setOptMode [-addInst {true | false}] [-congOpt {true | false}] [-effort {low | high}] [-holdFixingCells {list_of_buffers}] What are the methods to optimize placement efficiently? setOptMode [-addInst {true | false}] [-congOpt {true | false}] [-effort {low | high}] [-fixDRC {true | false}] [-holdFixingEffort {low | high}] [-holdFixingCells {list_of_buffers}] placeDesign [-clkGateRecloning] [-inPlaceOpt] [-incremental] [-noPrePlaceOpt] Write a script to add spare cells and report the no. of spare cells in the block?

The following command adds instances of the cells specified in spare_file and ties them to logical net 0. It ties the clock pins to clk addSpareInstance -file spare_file -tie 0 -clock clk displaySpareCell Write a script in spare cell placements by mentioning fence with {100, 50}, {200,150} on block -clock clk placeSpareModule -moduleName Spare_mod -area 100 50 200 150 How the tool will place decap cells for the list of decap you mention? the

createSpareModule -moduleName Spare_mod -cell {DFFNSRX2 5 INVX4 10 NOR2X2 12}

Adds the specified total decoupling capacitance to the design. The software chooses from the available decoupling capacitance cell candidates, and adds enough cells until their combined total capacitance value equals the user-specified value. The following command adds 1000 fF of capacitance to the design using DECAP1 and DECAP8 cells, in that order addDeCap -totCap 1000 -cells DECAP1 DECAP8 Write a script to place the spare cells evenly in the core, without binding them to thetop_design hierarchy. specifySpareGate -hinst proc0/iu0/i_703 setPlaceMode -ignoreSpare true setPlaceMode -fp setPlaceMode -maxRouteLayer 4 placeDesign (declaring proc0/iu0/i_703 instance as spare module) (without bounding them so they can placed anywhere in the design) (placemen according to floorplan mode) ( setting maximum routing layer 4) (place standard cell)

Write a script to place the spare cells within the bounds of top_design hierarchy. specifySpareGate -hinst proc0/c0/icache0 setPlaceMode -moduleAwareSpare true ( Design contains hierarchical modules, specify

the following setPlaceMode parameter to ensure that the spare cells within the modules are kept within bounds of the hierarchy) setPlaceMode -modulPlan false setPlaceMode -maxRouteLayer 4 placeDesign

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