Interconnect-Centric SoC Design for Networkon-Chip

Personal Project Manager: Ph.D. Li-Rong Zheng, KTH, Electrum 229, Kista Project Supervisor: Prof. Hannu Tenhunen, KTH, Electrum 229, Kista Ph.D. Students: Dinesh Pamunuwa, Jian Liu, Meigen Shen, Wim Michielsen

1: Introduction
The system-on-chip (SoC) design paradigm and deep submicron (DSM) technology bring two main challenges to the ASIC design community. The first one is productivity to use millions of gates within ever shorter time-to-market, which is currently tackled with the design methodology based on Intellectual Property Right (IPR) blocks. The second challenge is coping with rapidly changed technology parameters, where interconnect invites many signal and power integrity related problems. It is now clear that in ultra-deep submicron SoC design, interconnect will be a main design constraint and dominating effects in terms of system architecture, performance, robustness, power consumption, and cost. As an example, our study revealed that in a 0.07m CMOS chip, unless the system cock rate is greatly reduced otherwise, the maximum region that can be synchronized is about 6mm due to excessive interconnect delay and crosstalk [1]. Thus, new models and templates for design architectures are needed. One of such strongly emerging approaches is network-onchip (NoC) based architectures and platforms. In a multiple-processor SoC or network-on-chip, global interconnects are reserved for global communications. Consequently, the maximum synchronous region would be just 3 mm due to the interconnect limitation. Therefore, in future SoC design, issues of interconnect constraints must be accurately addressed in early system decisions and performance analysis in all abstraction levels and in different phases of the design refinement process. Interconnects are no longer separate post-layout and back-annotated issues, but are up-front system and architecture design issues. We need to describe the necessary physical properties and constraints in as attributes to interconnect library or interconnect IPRs. Only when these virtual wires are integrated in analyses, decisions made at high levels will be accurate; rework and iterations between system design and physical design will be reduced. In this project, we take interconnect as the main design object. We try to demonstrate the basic methods and techniques of how a system

architecture can be optimally defined by early addressing the interconnect constraints. The problems we will study include: 1. Issues of interconnect constraints and how they constrain the system architectures and global communications (For example, the maximum synchronous region, maximum bandwidth of memory and global communications); 2. How to incorporate the effects of lower level decisions in higherlevel system architecture decisions? (For example, the new design flow and method) 3. How to evaluate and select the best global communication architecture under interconnect performance and wireability constraints? 4. How to estimate the performance of the select system architecture particularly the NoC? (For example, interconnect library and performance estimator) 5. What are the appropriate communication structures at circuit and logical level for NoC. In best cases these communication links can be encapsulated as IPR-blocks (includes then both the dynamic interconnect library concepts for wires, driver receiver circuitry, and basic link protocol and media access control) in similar manner as processors or memories. 6. In addition, we will develop innovative techniques for mixed-signal isolations, signal and power distributions; integrate these techniques in our interconnect-centric design method and implement them in innovative mixed-signal SoC architectures. The above listed problems are general to all DSM SoCs. With a particular focus, we will study these issues on NoCs (Network-based SoCs), with a close cooperation with another research group leaded by Prof. A. Jantsch in applicants laboratory on project Design Methodology of NoC. That project (we refer to as NoC project hereafter) focuses on high level communication architecture and synthesis issues, and this work focuses on physical level issues and is a complementary one in the frame of NoC research at KTH. The methods and techniques developed from this work will be directly used and demonstrated in the NoC project, providing good opportunity to interdisciplinary co-operation and enhancing mutually the quality and international recognition of the work performed.

2: Problem solutions and limitations

Our solution to the problems consists of three aspects: explore the main constraints, perform a priori interconnect estimation, and define the design method and supporting tools and design flow concepts.

For many years, we have studied the electrical properties of DSM interconnects and developed some necessary models or algorithms for signal integrity and power distribution design. In addition to adopting many existing models in open literatures, our study on interconnectconstraints on system architectures will be much based on our own developed models and methods, giving us a unique competitive advantage. We focus particularly the global interconnects since global wires are most critical to chip performance in DSM circuits. In order to perform a priori interconnect estimation, our basic assumption is that in the future SoC design, reuse of IPRs will be very common. In a chip with billions of transistors, only a limited number of modules (each around 50K-200K gates) will be fully synthesized. The remaining modules will be largely decided by IPR vendors. Based on that, we can first generating a physical hierarchy with placement plan and global interconnect plan, preceding a priori signal integrity, power integrity, and performance estimation. Information of area, power consumption, interfaces for each module is obtained either from IPR vendors or from early estimation algorithms. Concept of such a method has been introduced in our early papers [2-3]. Next, the wring requirements will be estimated based on Rents rule or architecture specific comparable principles or semi-empirical rules. Currently, several algorithms exist for various circuitry types such as microprocessors, memories, CMOS gate-array, and logic chips. However, an SoC consists from many functional blocks, which include microprocessors, memories, logic, gate array, and maybe RF/analog front-end. Besides, SoCs can have different architectures such as busbased SoCs or network oriented NoCs. Therefore, the existing algorithm can not be used directly, new algorithms and tools must be developed. This may be done by recursively applying the existing algorithms for individual circuitry types and integrating them. Thus, proper studies of interconnectivity and Rents rule related principles need to be performed in close interaction with the other KTH NoC architecture project, where the architectural templates will be developed and refined based on feedback from the work in this project. For interconnect plan, two main subjects will be studied: (1) plan for performance and (2) plan for noise immunity. We have developed several models for a priori crosstalk estimates and power supply noise estimates for DSM circuits [2,4]. However, our previous methods need to be extended to asynchronous cases for global communications in NoCs. The performance estimator in our early paper [5] will be modified and used. As for the design method, we will use the dynamic interconnect library (DIL) based method [3]. In this method, most of interconnect issues are externally linked to the state-of-the-art circuit design

method, and hence has the lowest impact of the existing methodology. As we mentioned in above, we will describe the physical properties and constraints as interconnect IPRs. However, the conventional fixed- and precharacterized library approach used for transistors will not work for interconnects, because in SoCs, there will be millions of interconnect nets and their characteristics are strongly layout-dependent. The DIL will facilitate this issue. This is because the DIL is a collection of hierarchical interconnect models and transceivers. By integrating some automated algorithms and user constraints, it will allow us to automatically select the best wire (virtual wires) for interconnecting various modules (with changeable wire width and spacing, optimal repeater insertion, and best signaling schemes). Currently, a preliminary version of dynamic interconnect library has been developed by the applicants and it was successfully applied for early estimates in a protocol processor IPR module [5]. In this work, we aim to extend this library particularly the efficient and automated algorithms for interconnect synthesis and various signaling schemes such as LVDS and single-end terminated signaling etc.. Based on the a priori estimates and the new design method, we are hence able to evaluate various communication architectures and system performance. Such a performance modeling environment and system simulator need to be developed and we have taken some initial steps to this directions already [5]. We need to study different communication schemes under the established interconnect constraints and find appropriate circuit and architecture solution. Much of this work can capitalize our earlier strong background in ATM and wireless link area established during 1990s. As for the novel mixed-signal isolation techniques, our special focus will be: (1)Low noise power distribution strategies with self-decoupling and area array I/O distribution; (2)Optimal decoupling allocations and their early estimates; and (3)Trade-off analysis of quality factors and mixed-signal isolations for RF/mixed signal integration. (4)Architectural strategies for reducing the power distribution constraints (e.g. based on randomization feasible within GALS (globally asynchronous, locally synchronous concepts [10]) The above four issues will be integrated into our interconnect-centric design techniques. Besides, we need to mention that early power distribution analysis and decoupling allocation are essential for accurate system plan. This is because in future DSM circuits power distribution will consume a large number of wiring resources as well as the chip area. On the communication link plan our focus will be on selecting the proper driver design schemes (transmitter/receiver), communication 4

protocol schemes and their performance analysis with NoC content, and local MAC (media access controller) structures and their encapsulation as IPRs. Due to different performance requirements, a few such schemes need to be established. Based on NoC platform concepts, packet switched topologies will be under main focus instead of circuit switched (or bus) structures. Limitations: We can only focus on a small portion of the interconnect-related design problem. For example, our method is so far limited to hardware design issues. Principally this may also be extended to hardware/software partitioning but that will need much additional work [6]. In addition, we only consider the physical hierarchy at global level. Local optimization for system structure and communication is out of this work. However, as stated in many recent papers that in future DSM circuits, the local interconnect is not as bad as that because length of these interconnects scales down when the module size scales. The problems for global interconnects are dramatically increasing as the number of modules integrated in an SoC increases. Packet oriented communication schemes are not well established at chip level, so some pioneering work will be required involving obvious risks. The role of performance modeling will be emphasized due to this.

3: What is new in the presented approach?

Interconnect-centric SoC design is an emerging area. To our knowledge, most of previous activities of interconnect-centric design are focused on random logic circuits or microprocessors [7]. Many of the existing interconnect models (include some new developed ones such as the wire distribution model by J. D. Meindl [8],GeorgTech.) are not applicable to complex SoCs particularly the network-based SoC architecture. As for the deign method, a research group in UCLA (J.Cong) proposed a completely new flow for interconnect-centric design [9]. They are also making significant efforts in developing new algorithms to support such a design flow. However, our DIL-based method is innovative. In this method, there are least changes from the todays circuit design flow. The interconnect IPRs externally link to the existing design flow and hence, we believe this method will be at the lowest cost and the lowest risk. Besides, this work closely cooperates with projects on NoC architectures and Design Methodology leaded by Prof. Axel Jantsch, KTH (as a supporting team of this project). Our physical-based models, methods, and algorithms will be directly used and examined in that work. The combination of these two projects will create many innovative researches and may bring us as a leading group in NoC 5

research. The performance estimation tools and concepts as well as communication link structures and performance will be very valuable issues for the other KTH NoC methodology project.

4: Why will this project succeed?

As outlined above, we have gained much knowledge in DSM interconnect modeling and analysis in our previous studies as well as in our ongoing projects. From 1996-2001, we had 5~7 Ph.D. students working in a reverent research area such as mixed-signal design, interconnect modeling and estimate, signal and power distribution, and clock distribution. We are also collaborating with UTU and TUT in Finland in the project COMPLAIN with special focus on SoC communication circuit design. Furthermore, we have an industrial partner Mentor Graphics, who is cooperating with us in signal integrity studies and interconnect synthesis. We believe they will provide us useful directives in our research. Besides, we will also get useful directives from the NoC project and their partners (VTT, Ericsson Radio, Nokia, Saab Dynamic, Spirea). On international collaboration, we are a partner of EU 6th Framework Innovative Research Project on Interconnect-centric SoC Design. We already have well-established collaboration with other partners such as IMEC, University of Ghent, Philips, Infinion etc.

5: Impact if succeed
We try to address the interconnect issues in early system decisions without big changes of the existing circuit design flow. If this is successful, it will be a lowest risk solution in coping with the interconnect constraints and reduce the design iteration thus greatly improve SoC productivity and reduce design cost. In addition to its potential applications in SoC design community and business opportunities, we may also be a leading research group internationally in interconnect-centric design and interconnect IPR development.

6: Measurable mid-term and final goals

after 24 months a. Develop a network-based wiring model for NoC; b. Complete an efficient power distribution algorithm with focus on asynchronous circuits and a priori decoupling allocation; c. Complete an algorithm of repeater insertion with crosstalk and via resistance constraints; d. Studies on various on-chip signaling techniques in terms of bandwidth, wiring demand, power consumption, and robustness; e. Comparative studies of various on-chip communication architectures in terms of bandwidth, wiring demand, power consumption, and robustness; provide physical-level guidelines to 6

the NOC project in defining the communication protocol stack of NOCs. f. Proposals for communication link architectures from interface circuits to MAC. after 54 months a. Implementation of the algorithms in the dynamic interconnect library; b. Manual demonstration of interconnect IPRs; c. Define and manual demonstrate the interconnect-centric design method; d. Demonstrate application examples of the method in global communication design of NOCs.

8: Metrics of success
a. International publications and patents (we expect roughly 5 peerreviewed papers and 1 patent). b. Methods and tools for interconnect and communication link performance analysis, where some of these will be used outside the research group; c. Methods and algorithms will be used for system architecture definition and performance analysis in early design stages for SoCs and NOCs; d. Exploitation of results and concepts in industrial designs towards end of the project.

References:
1) L. -R. Zheng, H. Tenhunen, Physical issues in Network-on-Chip,
presented as a tutorial lecture in the workshop of European Solid-State Circuit Conference (ESSCIRC01), Villach, Austria, Sept. 18-20, 2001. (http://www.ele.kth.se/~lrzheng/papers/physicalissueNOCs_lirong.pdf) deep submicron system-on-chip circuits, Analog Integrated Circuits and Signal Processing, vol. 30. no.1, pp.15-30, 2002. (http://www.ele.kth.se/~lrzheng/papers/Norc_ALOG.pdf) signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design, In Proc. 2000 Europe Solid State Circuit Conference, pages 324-327, Stockholm Sweden, September 2000. Frontier Group, ISBN 2-86332-249-4. (http://www.ele.kth.se/~lrzheng/papers/ESSCIRC00_final.pdf) distributed LRC power grid in ULSI circuits, IEEE Transactions on

2) L.-R. Zheng, H. Tenhunen, Design and analysis of power integrity in

3) L. -R. Zheng, D. Pamunuwa, and H. Tenhunen, Accurate a priori

4) L. -R. Zheng, H. Tenhunen, Fast modeling of core switching noise on

Advanced Packaging, 24(3):245-254, 2001. (http://www.ele.kth.se/~lrzheng/papers/EPEP_IEEE_AP.pdf).

5) T. Nurmi, L. -R. Zheng, J. Isoaho, and H. Tenhunen, Early estimation of

interconnect effects on the operation of system-on-chip platforms, In Proc. European Conference on Circuit Theory and Design, pages 197-202, Espoo, Finland, August 2001. (http://www.ele.kth.se/~lrzheng/papers/ecctd_cam.pdf) methodology for System-on-Chip, In Proc. of the 17th IEEE NORCHIP Conference, pages 197-204, Oslo, Norway, Nov 1999.

6) A. Postula, A. Hemani, and H. Tenhunen, Interconnect centered design 7) D. Sylvester, K. Keutzer, System-level performance modeling with

BACPAC Berkeley Advanced Chip Performance Calculator, Workshop on system-level interconnect Prediction, pp.109-114, Monterey, CA, April 10-11, 1999. scale integration, IEEE Trans. Electronic Devices, vol.45, no.3, 1998. IEEE Proceedings, vol.89, no.4, pp.505-528, April 2001.

8) J. A. Davis, J. D. Meindal, A stochastic wire length distribution for gaga9) J. Cong, An interconnect-centric design flow for nanometer technologies, 10)
A. Hemani, T. Meincke, A. Postula, T.Olsson, P.Nilsson, J. berg, P.Ellervee, and D. Lundqvist, Lowering power consumption in clock by using globally asynchronous locally synchrounus design style, in Proc. of the 36th IEEE/ACM Design Automation Conference (36th DAC), pages 873878, New Orleans, LA, USA, Jun 1999. (http://www.ele.kth.se/ESD/doc/ar99/ahmed/dac99final.ps.gz)