Technology aspects of a CMOS Neuro-Sensor:
Back End Process and Packaging
Franz Hofmann1, Björn Eversmann1, Martin Jenkner1, Alexander Frey1, Matthias Merz2,
Tamara Birkenmaier2, Peter Fromherz2, Matthias Schreiter3, Reinhard Gabl3, Kurt Plehnert3,
Michael Steinhauser3, Gerald Eckstein3, and Roland Thewes1
1
Infineon Technologies, Corporate Research, Otto-Hahn-Ring 6, D-81730 Munich, Germany
2
Max-Planck-Institute for Biochemistry, Martinsried, Germany, 3 Siemens AG, Munich Germany,
Franz.Hofmann@Infineon.com
Abstract
A CMOS-compatible process is presented which
allows to realize sensor arrays for non-invasive,
extracellular, high density, long term recording of neural
activity. A highϑpermittivity bio-compatible dielectric is
used to capacitivly couple nerve cell-induced biological
signals to the CMOS circuitry-based electronic world.
The transducer consists of a multi layer of TiO2 and
ZrO2 and is fabricated in the backend of a 0.5 µm
standard CMOS technology. Living cells are cultured
within a specific package on top of the sensor chip. First
measurements reveal proper operation of the chip.
1. Introduction
Neuro-sensor arrays monitor signals of living nerve
cells or neural tissue. They are a key tool in
neurosciences and offer an approach to fast and
statistically significant cell-based pharma screening.
The elementary signals of neurons (action potentials)
are temporal changes of the transmembrane voltage
associated with K+ and Na+ currents through ion
channels within the cell membrane [1]. When neurons
within a grounded electrolyte are brought in intimate
contact with an extracellular electrode covered by a
dielectric layer, a cleft of order 50 nm between cell
membrane and dielectric is obtained. Membrane currents
that flow through the cleft lead to a potential drop due to
the resistance of the electrolyte within the cleft. As
shown in [1], this voltage signal can directly be used to
control the charge within a transistor channel. However,
until today usually only comparatively simple sensor
structures are used, which consist of bulk silicon with
diffused junctions and channel areas directly covered by
the sensor dielectric.
Recently, a large sensor array with 128 ⌠ 128 pixels
within an area of 1 mm2 has been published [2].
Realization of such arrays requires full CMOS
interconnect options and on-chip circuitry. In this work,
processing issues are discussed in detail.
2. Sensor Setup
In Fig. 1a), the realized neuro-sensor principle is
schematically depicted. The sensor is comprised of an
integrated CMOS circuit connected to an electrode
coated with an isolating dielectric layer. Neurons can be
cultivated upon the sensor and adhere to the dielectric
layer.
As shown in the equivalent circuit of the sensor
(Fig. 1b)), the electrolyte potential within the cleft is
coupled to the gate of a MOSFET via a capacitve voltage
divider consisting of the sensor electrode and the gate
capacitance itself. Modulation of the cleft potential
induced by an action potential of the cell leads to
modulation of the transistor gate voltage. The resulting
modulation of the drain current is further amplified and
transferred to the outputs of the chip.
a) b)
firing neuron
cleft
neuron resistance
RC
cleft
dielectric via
electrode dielectric
capacitance
CD
MOSFET M
CG
standard CMOS process
Figure 1: Schematic cross section of a CMOS chip with
a neuron cell on top (a) and equivalent circuit
diagram (b).
Due to the range of the extracellular signal between
100 µVpp and 5 mVpp, a high sensitivity of the sensor
circuit is required. Sensor transistor mismatch, noise and
drift have to be considered. As the transistor mismatch
(″(Vth) of 4.2 mV at an area of 11 µm²) is larger than the
actual signal, an auto-calibration technique of the pixel is
used [2]. Fig. 2 shows a schematic of the pixel circuit sputtered. The pads are opened using photo-lithography
including neuron, electrode, pixel transistor, and and reactive ion etch of TiO2 with a stop at the Pt layer,
switches used for selection of a pixel (sel), calibration which cannot be etched by RIE satisfactory. Metalization
(cal), and readout (read). of the pads is performed by evaporation of Au in a lift-
In the calibration mode, switch 'read' is open, off process. This process module circumvents etching of
switches 'cal' and 'sel' are closed. The pixel transistor the metal with a stop on the dielectric layer to avoid
works in a diode configuration and a drain current is damage of this layer. Fig. 4a) shows a SEM cross section
forced into the device by a constant current source. of the sensor. The transistors below the pixel can clearly
When switch 'cal' is opened, the charge stored on the be identified. The tilted SEM in Fig. 4b) illustrates a part
gate node of the pixel transistor exactly corresponds to of the fabricated sensor array. Pixel electrode diameter is
the current forced in, independently of the transistor’s 4.5 µm, sensor pitch is 7.8 µm.
individual device parameters. In the readout mode, TiO2 /ZrO2
switch 'read' is closed, the drain voltage is kept constant, a) b) Cr/ Pt c)
and changes of the drain current represent the Si3N4
modulation of the electrolyte voltage within the cleft. SiO2
Al2
In order to provide high signal sensitivity, the
electrode capacitance should be sufficiently high to W
reduce the noise and ensure signal integrity. Furthermore Al1
SiO2
the transfer-function depends on the capacitve voltage
Gate
divider CD/CG. Using a high-permittivity dielectric Si-wafer
increases the signal swing at the transistor gate.
Figure 3:
The leakage current of the sensor dielectric should be d)
Au a) CMOS process
below 30 nA/cm2. This value results from choosing the TiPt b) photo technique; etch nitride/
leakage current of switch transistor 'cal' in Fig. 2 as oxide; deposit barrier Ti/TiN;
tolerable maximum. tungsten fill; CMP tungsten,
Ti/TiN; photo technique;
evaporate Cr/Pt; lift off Cr/Pt
pixel c) sputter TiO2/ ZrO2
neuron d) photo technique; (only at pads):
V etch TiO2/ ZrO2 ; evaporate
pixel Pt/Au; lift off Pt/Au.
transistor

cal
sel a) preparation nitride

read TiO2 /ZrO2 -dielectric

constant nitride
current amplifier electrode
IDC via
for calibration
metal 2

Figure 2: Simplified schematic of a pixel circuit. preparation

artefact metal 1

3. Process gate
1 µm
In Fig. 3, the process used to provide the passivated
electrodes is schematically depicted. We start with a b)
CMOS process specifically optimized for analog pixel electrode
applications (high-ohmic poly-silicon resistors, poly-
poly-capacitors), with Lmin = 0.5 µm, tox = 15 nm, VDD
= 5 V, n-well, LATID-n-MOS, and LDD-pMOS devices.
The sensor-related extra process starts after fabrication
of the second aluminum layer and nitride passivation. A
via is etched down to the Al layer, which is filled with a
Ti/TiN barrier and tungsten. Then, a CMP process step CMOS layer
planarizes the wafer surface with an etch stop at the
nitride layer. A Cr adhesion layer (20 nm) and a Pt
electrode layer (25 nm) are deposited and structured in a Figure 4: a) SEM cross section within the pixel array,
lift-off process. As sensor dielectric modified TiO2 is b) tilted SEM photograph with circular pixels.
4. Dielectric
-6
1,1x10

Capacitance [F/cm ]
2
During cell cultivation the sensor dielectric is
operated under the condition, that neurons are kept in an
environment of media upon the sensor for at least several 1,0x10
-6

days. The electrolyte and the cells are highly corrosive.

Thus a bio-compatible, leak-proof and absolutely inert
-7
dielectric must be used, which does not affect the growth 9,0x10
of the biological tissue by formation of corrosion
products of either the dielectric or of subjacent CMOS -7
process related materials. As the dielectric is fabricated 8,0x10
1 2 3 4 5 6
in the backend of a CMOS process, processing 10 10 10 10 10 10
temperature must be below 400°C. For optimum sensor
Frequency [Hz]
circuit operation high capacitance and low leakage Figure 6: Frequency response of the TiO2/ZrO2
current are required. dielectric sandwich.
Whereas pure TiO2 looks promising for this -7
10
application due to the inertness and the very high
dielectric constants reported between 60 and 80 [3], a
modified TiO2-based dielectric is used here in order to

Leakage [A/cm ]
2
-8
reduce leakage currents without application of annealing 10
steps. We implemented a multi layer sandwich consisting
of TiO2 and ZrO2. ZrO2 is bio-compatible as well and
provides a relativly high dielectric constant between 10
-9

20 and 30 [4]. A stack of 10 nm TiO2, 5 nm ZrO2, 10 nm

TiO2, 5nm ZrO2, and 10 nm TiO2 is sputtered. The
stacked layer has very low leakage current, similar to -10
stacks in the former generation DRAM memory 10
-1,00 -0,75 -0,50 -0,25 0,00 0,25 0,50 0,75 1,00
dielectrics, where ONO was used. A cross section of the
V [V]
dielectric sandwich is given in Fig. 5.

Figure 7: Leakage current of the TiO2/ZrO2 dielectric.

TiO2
ZrO2
40 nm TiO2
ZrO2
TiO2 5. Package
Fig. 8 shows a cross section of the sensor package of
nitride the CMOS neuro-chip [5]. The sensor temperature must
be precisely controlled since neural activity is a strong
function of this parameter. The sensor die is bonded with
Figure 5: TEM image of the TiO2/ZrO2 sandwich. an isotropic conductive adhesive to a ceramic package in
Fig. 6 shows the frequency response of this TiO2/ZrO2 order to obtain a good thermal conductivity, which is
stack. Up to 1 Mhz only a slight decay occurs, which is a mandatory for sufficient temperature control of the
necessary property to completely charge the gate node in sensor die and of the cell cultures.
Fig. 2 during the short calibration phase. The ⁄r extracted
for this 40 nm dielectric is 45, which approximately
amounts to 50 % of pure TiO2. The equivalent oxide
thickness (EOT) is 3.4 nm. outer shell
Fig. 7 shows the leakage current of the stacked
dielectric with a top electrode of Pt/Au, formed in a
modified process run. The leakage current in the inner shell
interesting voltage range (<100 mV) is lower than
10-9 A/cm2. This corresponds to a value of 0.1 fA/pixel,
which is much lower than the leakage current of the
calibration transistor. With an electrode area of 16 µm2
and a gate area of 11 µm2, the coupling ratio CD/CG is bonding chip epoxy
socket
about 6, so that 90% of the electrolyte voltage drops at area fill
the gate capacitance. Thus the stacked TiO2 dielectric
fulfills the requirements of high ⁄ and low leakage. Figure 8. Package of the neuron sensor chip.
 The compartment contains the media and shields the
bond wires, the pads, and the socket from the electrolyte
and moisture to avoid corrosion and electronic
malfunction. It is self-evident that the compartment must
not influence the biology itself. This comparment
consists of two plexiglass shells. The inner shell is glued
to the die area and the bigger outer shell to the socket. In
the space between these two shells the bonding pads of
the socket and the chip, and the bonding wires are
located. This volume is filled with an epoxy resin to seal
the bonds. The whole assembly yields a robust package
of the sensor.
6. Neural activity
Fig. 9 depicts the measurement set-up. In the top
figure, the sensors with readout-circuitry, compartment
and package are schematically depicted. A neuron within
the electrolyte, which is cultured on top of the sensor
area, is contacted with a microelectrode. The
microelectrode is used to apply a stimulation current to
elicit action potentials. The bottom photograph shows
snail neurons on top of the sensor chip. One neuron is
contacted with a micro electrode.
First measured data are presented in Fig. 10. There, a
constant stimulation current of 100 pA is applied to the
cell for 0.5 s. The intracellular potential is detected by an
invasive micro electrode is depicted in the upper plot.
The lower plot shows the extracellular response of the
neuron recorded by the CMOS sensor. The higher
sensitivity needed in the extracellular case is achieved by
arranging active CMOS circuitry below the pixel.
I operated as input devices within a detection chip system.
stim
V
intra
micro
electrode
amplifier V Array for Extracellular Recording of Neural Activity
extra
micro
electrode
cell
100µm
Figure 9: Schematic set up (top) and living neuron
cells above.
intracellular potential
a)
Vcell
50 mV
extracellular potential
b)
Vsensor
1 mV
time
100 ms
Figure 10: intracellular signal (a)
extracellular sensing of a firing neuron (b)
7. Conclusion
Processing and packaging issues of a CMOS sensor
array for extracellular recording of neural signals are
presented. A process module to provide a bio-compatible
high-⁄ dielectric with a sandwich structure of TiO2 and
ZrO2 is integrated in the backend of a CMOS
technology. Living cells are cultured on top of the
sensor. Action potentials of firing neurons are
capacitively coupled to the gates of MOS transistors
References
[1] P. Fromherz, “Electrical Interfacing of Nerve Cells
and Semiconductor Chips” CHEMPHYSCHEM 3,
2002, p. 276 – 284.
[2] B. Eversmann et al, “A 128 x 128 CMOS Bio-Sensor
”, ISSCC, Digest of Tech. Papers, 2003, p. 222-223.
[3] S. A. Campbell et al, “Titanium dioxide based gate
insulators”, IBM J. RES. DEVELOP. Vol 43, 1999,
p. 383-391.
[4] H. I. Iwai et al, “Advanced Gate Dielectric Materials
for Sub 100 nm CMOS”, IEDM Tech. Digest 2002,
p. 625-628.
[5] B. Besl and P. Fromherz, “Transistor array with an
organotypic brain slice: field potential records and
synaptic currents”, European J. of Neuroscience, Vol.
15 2002, p. 999-1005.