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VLSI PROJECTS LIST

1. Design and Implementation of Viterbi Encoding and Decoding Algorithm on FPGA 1. A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA blocks 1. Low Power State-Parallel Relaxed Adaptive Viterbi Decoder Adaptive Viterbi Decoder

1. Fpga Implementation For Humidity And Temperature Remote Sensing System 2. Based Multi-Interface Module (I2m) For Industrial Processes Automation
1. A configurable Motion Estimation Architecture for block matching Algorithms. 2. A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture. 3. FPGA based Implementation of High Performance Architectural level Low Power 32-bit RISC Core 4. 5. FPGA Implementation of AES Encryption and Decryption(AES Algorithm). Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST.

VLSI IEEE 2010 PROJECTS 1. New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter.

2. Design of SHA-1 Algorithm based on FPGA 3. 4. FPGA Implementation of efficient FFT algorithm based on complex sequence Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology Algorithm Of Binary Image Labeling And Parameter Extracting Based On Fpga A Pipeline Vlsi Architecture For High-Speed Computation Of The 1-D Discrete Wavelet Transform Design Of A Low Power Flip-Flop Using Cmos Deep Submicron Technology An Fpga-Based Architecture For Linear And Morphological Image Filtering Dual Stack Method A Novel Approach To Low Leakage And Speed Power Product Vlsi Design

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VLSI PROJECTS LIST


10. Fpga Based Real-Time Adaptive Fuzzy Logic Controller 11. Hardware Realization Of Shadow Detection Algorithm In Fpga 12. Image Edge Detection Based On Fpga 13. Test Data Compression Using Efficient Bitmask And Dictionary Selection Methods 14. Concatenated Reed-Solomon Code with Hamming Code for DRAM Controller 15. Design and Implementation of a Parallel Processing Viterbi Decoder Using FPGA 16. General-Purpose FPGA Platform for Efficient Encryption and Hashing 17. Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C 18. Implementing Rainbow Tables in High-end FPGAs for Super-fast Password Cracking 19. Prototyping Platform for Performance Evaluation of SHA-3 Candidates 20. A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders 21. A Reconfigurable Wireless Stepper Motor Controller Based On FPGA Implementation 22. An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading; 23. High Density FPGA Based Waveform Generation for Radars; 24. Low-Power Reconfigurable Acceleration of Robust Frequency-domain Echo Cancellation on FPGA 25. PI-like Fuzzy Control Implementation using FPGA Technology 26. Self-Adaptive Frequency Agility Realized with FPGA

VLSI IEEE 2011 PROJECTS 1. 2. 3. A Median Filter Fpga With Harvard Architecture Detecting Background Setting For Dynamic Scene Design And Fpga Implementation Of Modified Distributive Arithmetic Based Dwt-Idwt Processor For Image Compression

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VLSI PROJECTS LIST


4. A Lightweight High-Performance Fault Detection Scheme For The Advanced Encryption Standard Using Composite Fields A Rotation-Based Bist With Self-Feedback Logic To Achieve Complete Fault Coverage Adiabatic Technique For Energy Efficient Logic Circuits Design Efficient Weighted Modulo 2n+1 Adders By Partitioned Parallel Prefix Computation And Enhanced Circular Carry Generation An Autonomous Vectorscalar Floating Point Coprocessor For Fpgas Design And Characterization Of Parallel Prefix Adders Using Fpgas

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10. High Speed Asic Design Of Complex Multiplier Using Vedic Mathematics 11. High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications 12. Implementation And Performance Analysis Of Seal Encryption On Fpga, Gpu And Multi-Core Processors 13. Lossless Implementation Of Daubechies 8-Tap Wavelet Transform 14. A fully pipelined implementation of Monte Carlo based SSTA on FPGAs 15. An Efficient Implementation of Floating Point Multiplier 16. High Level Power Estimation Models for FPGAs 17. Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain 18. FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder 19. Inter-Packet Symbol Approach To Reed-Solomon FEC Codes For RTPMultimedia Stream Protection 20. Novel Hardware Architecture for implementing the inner loop of the SHA-2 Algorithms 21. A Flexible Hardware Implementation of SHA-1 and SHA-2 Hash Functions 22. Design of Low Power Column Bypass Multiplier using FPGA 23. FPGA implementation of modified architecture for adaptive Viterbi decoder
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VLSI PROJECTS LIST


24. Design of FPGA-Based Traffic Light Controller System VLSI IEEE 2012 PROJECTS 1. High-Speed Low-Power Viterbi Decoder Design For Tcm Decoders

2. A New Fault Injection Approach for Testing Network-on-Chips 3. An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm 4. Channel Estimation Algorithms for OFDMIDMA High-Valency Ling Adders 5. Design and implementation of an optical OFDM baseband receiver in FPGA 6. Design and Implementation of High-Performance High-Valency Ling Adders 7. Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA 8. Design and Realization of Serial Front Panel Data Port (SFPDP) Protocol 9. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA implementation 10. Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder 11. FPGA Based Controller for Large Port Count Optical Packet Switches 12. 1FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator A Comparative Study 13. FPGA Implementation of BASK-BFSK-BPSK Digital Modulators 14. FPGA Implementation of Chaotic Pseudo-Random Bit Generators 15. Implementation of DFT filter banks based on FPGA 16. Implementation of VLSI-Oriented FELICS Algorithm Using Pseudo Dual-Port RAM 17. Performance Analysis of MC-CDMA System 18. Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors
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VLSI PROJECTS LIST


19. VLSI Implementation of a Bio-Inspired Olfactory Spiking Neural Network

VLSI IEEE PROJECTS 1. 2. Area and Power Efficient VLSI Architecture for DCT Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits

3. Low power dissipation using FPGA architecture 4. Low-power dissipation using FPGA architecture 5. Generalized Secure Hash Algorithm SHA-X

VLSI IEEE PROJECTS

1. Implementation of FIFO design for UART using VHDL 2. VLSI based Pattern generator and MISR for BIST using VHDL 3. LFSR for lower power optimization using VHDL 4. Practical asynchronous interconnect designing of a transmitter with parity 5. VLSI design of single chip stepper motor controller using VHDL 6. Single chip Encryptor core implementation of key scheduling for AES algorithm 7. Implementation of hash algorithm used for cryptography and security 8. FPGA implementation of USB transmitter macro cell interface 9. Practical asynchronous interconnect designing of an receiver with a parity 10. FPGA based designing of SPI and PSI Architectures 11. An efficient VLSI design of convolution encoder for satellite communication 12. Single chip Encryptor Decryptor core implementation of key scheduling for DES algorithm 13. A single chip designing of Arithmetic Logic Unit using VHDL 14. Implementation of Dual Port RAM for ATM applications 15. Implementation of RAM,ROM and instruction decoder of Pipelined RISC processor for parallel processing 16. Enhancement of BIST for Faulty circuit Techniques on FPGA 17. VLSI design of single chip Traffic Light Controller 18. Implementation of Scrambler and Descrambler in fiber optic communication systems for OTN using VHDL 19. VLSI design of pipelined module of RISC processor for parallel processing
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VLSI PROJECTS LIST


20. VLSI based finite state machine for AES implementation using VHDL 21. An improved Hash Algorithm with the same structure of cryptography and security. 22. VLSI based round module for advanced encryption standard implementation using VHDL 23. Implementation of Scrambler and Descrambler in fiber optic communication systems for SONET using VHDL 24. Efficient VLSI Design of Basic RSA encryption engine 25. Designing of Universal Asynchronous Receiver and Transmitter using VHDL 26. A single chip VLSI based designing of comparator using VHDL 27. Efficient design of butterfly architecture for radix 4 fast Fourier transform 28. VLSI design of sbox for AES and DES using VHDL 29. Single chip design of event manager for RISC processor 30. Single chip design of PRBS generator using VHDL 31. Design and implementation of Bluetooth using VHDL 32. FPGA implementation of USB receiver macro cell interface 33. Implementation of SHA algorithm used for cryptography and security 34. Design and implementation of Discrete Cosine Transform(DCT) Design in VHDL 35. Design and implementation of Floating Point Unit (FPU) Design in VHDL 36. Design and implementation of VGA (Video Graphics Array) Controller in VHDL 37. Design and implementation of LCD Interface 38. Design and implementation of PS2 Keyboard 39. Design and implementation of WIFI MAC TRANSMITTER 40. Design and implementation of Ethernet Media Access Control Design in VHDL 41. Design and implementation of UART with bist capability 42. Design and implementation of lossless high speed parallel data compression 43. Design and implementation of Content Addressable Memory 44. Design and implementation of I2C controller core 45. Design and implementation of Dual Elevator Controller 46. Design and implementation of Cyclic Redundancy Check (CRC) Generator/Checker in VHDL 47. Design and implementation of CAN using VHDL 48. Design and implementation of Triple Des for SECURE COMMUNICATION in VHDL 49. Design and implementation of Digital Code Lock 50. Implementation of real time Candy mechanic using VHDL

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VLSI PROJECTS LIST


51. Implementation of FIFO design for UART using VHDL 52. VLSI based Pattern generator and MISR for BIST using VHDL 53. LFSR for lower power optimization using VHDL 54. Practical asynchronous interconnect designing of a transmitter with parity 55. VLSI design of single chip stepper motor controller using VHDL 56. Single chip Encryptor core implementation of key scheduling for AES algorithm 57. Implementation of hash algorithm used for cryptography and security 58. FPGA implementation of USB transmitter macro cell interface 59. Practical asynchronous interconnect designing of an receiver with a parity 60. FPGA based designing of SPI and PSI Architectures 61. An efficient VLSI design of convolution encoder for satellite communication 62. Single chip Encryptor Decryptor core implementation of key scheduling for DES algorithm 63. A single chip designing of Arithmetic Logic Unit using VHDL 64. Implementation of Dual Port RAM for ATM applications 65. Implementation of RAM,ROM and instruction decoder of Pipelined RISC processor for parallel processing 66. Enhancement of BIST for Faulty circuit Techniques on FPGA 67. VLSI design of single chip Traffic Light Controller 68. Implementation of Scrambler and Descrambler in fiber optic communication systems for OTN using VHDL 69. VLSI design of pipelined module of RISC processor for parallel processing 70. VLSI based finite state machine for AES implementation using VHDL 71. An improved Hash Algorithm with the same structure of cryptography and security. 72. VLSI based round module for advanced encryption standard implementation using VHDL 73. Implementation of Scrambler and Descrambler in fiber optic communication systems for SONET using VHDL 74. Efficient VLSI Design of Basic RSA encryption engine 75. Designing of Universal Asynchronous Receiver and Transmitter using VHDL 76. A single chip VLSI based designing of comparator using VHDL 77. Efficient design of butterfly architecture for radix 4 fast Fourier transform 78. VLSI design of sbox for AES and DES using VHDL 79. Single chip design of event manager for RISC processor 80. Single chip design of PRBS generator using VHDL 81. Design and implementation of Bluetooth using VHDL 82. FPGA implementation of USB receiver macro cell interface 83. Implementation of SHA algorithm used for cryptography and security 84. Design and implementation of Discrete Cosine Transform(DCT) Design in VHDL
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VLSI PROJECTS LIST


85. Design and implementation of Floating Point Unit (FPU) Design in VHDL 86. Design and implementation of VGA (Video Graphics Array) Controller in VHDL 87. Design and implementation of LCD Interface 88. Design and implementation of PS2 Keyboard 89. Design and implementation of WIFI MAC TRANSMITTER 90. Design and implementation of Ethernet Media Access Control Design in VHDL 91. Design and implementation of UART with bist capability 92. Design and implementation of lossless high speed parallel data compression 93. Design and implementation of Content Addressable Memory 94. Design and implementation of I2C controller core 95. Design and implementation of Dual Elevator Controller 96. Design and implementation of Cyclic Redundancy Check (CRC) Generator/Checker in VHDL 97. Design and implementation of CAN using VHDL 98. Design and implementation of Triple Des for SECURE COMMUNICATION in VHDL 99. Design and implementation of Digital Code Lock 100. Implementation of real time Candy mechanic using VHDL

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