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1. Design and Implementation of Viterbi Encoding and Decoding Algorithm on FPGA 1. A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA blocks 1. Low Power State-Parallel Relaxed Adaptive Viterbi Decoder Adaptive Viterbi Decoder
1. Fpga Implementation For Humidity And Temperature Remote Sensing System 2. Based Multi-Interface Module (I2m) For Industrial Processes Automation
1. A configurable Motion Estimation Architecture for block matching Algorithms. 2. A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture. 3. FPGA based Implementation of High Performance Architectural level Low Power 32-bit RISC Core 4. 5. FPGA Implementation of AES Encryption and Decryption(AES Algorithm). Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST.
VLSI IEEE 2010 PROJECTS 1. New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter.
2. Design of SHA-1 Algorithm based on FPGA 3. 4. FPGA Implementation of efficient FFT algorithm based on complex sequence Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology Algorithm Of Binary Image Labeling And Parameter Extracting Based On Fpga A Pipeline Vlsi Architecture For High-Speed Computation Of The 1-D Discrete Wavelet Transform Design Of A Low Power Flip-Flop Using Cmos Deep Submicron Technology An Fpga-Based Architecture For Linear And Morphological Image Filtering Dual Stack Method A Novel Approach To Low Leakage And Speed Power Product Vlsi Design
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VLSI IEEE 2011 PROJECTS 1. 2. 3. A Median Filter Fpga With Harvard Architecture Detecting Background Setting For Dynamic Scene Design And Fpga Implementation Of Modified Distributive Arithmetic Based Dwt-Idwt Processor For Image Compression
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10. High Speed Asic Design Of Complex Multiplier Using Vedic Mathematics 11. High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications 12. Implementation And Performance Analysis Of Seal Encryption On Fpga, Gpu And Multi-Core Processors 13. Lossless Implementation Of Daubechies 8-Tap Wavelet Transform 14. A fully pipelined implementation of Monte Carlo based SSTA on FPGAs 15. An Efficient Implementation of Floating Point Multiplier 16. High Level Power Estimation Models for FPGAs 17. Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain 18. FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder 19. Inter-Packet Symbol Approach To Reed-Solomon FEC Codes For RTPMultimedia Stream Protection 20. Novel Hardware Architecture for implementing the inner loop of the SHA-2 Algorithms 21. A Flexible Hardware Implementation of SHA-1 and SHA-2 Hash Functions 22. Design of Low Power Column Bypass Multiplier using FPGA 23. FPGA implementation of modified architecture for adaptive Viterbi decoder
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2. A New Fault Injection Approach for Testing Network-on-Chips 3. An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm 4. Channel Estimation Algorithms for OFDMIDMA High-Valency Ling Adders 5. Design and implementation of an optical OFDM baseband receiver in FPGA 6. Design and Implementation of High-Performance High-Valency Ling Adders 7. Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA 8. Design and Realization of Serial Front Panel Data Port (SFPDP) Protocol 9. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA implementation 10. Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder 11. FPGA Based Controller for Large Port Count Optical Packet Switches 12. 1FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator A Comparative Study 13. FPGA Implementation of BASK-BFSK-BPSK Digital Modulators 14. FPGA Implementation of Chaotic Pseudo-Random Bit Generators 15. Implementation of DFT filter banks based on FPGA 16. Implementation of VLSI-Oriented FELICS Algorithm Using Pseudo Dual-Port RAM 17. Performance Analysis of MC-CDMA System 18. Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors
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VLSI IEEE PROJECTS 1. 2. Area and Power Efficient VLSI Architecture for DCT Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
3. Low power dissipation using FPGA architecture 4. Low-power dissipation using FPGA architecture 5. Generalized Secure Hash Algorithm SHA-X
1. Implementation of FIFO design for UART using VHDL 2. VLSI based Pattern generator and MISR for BIST using VHDL 3. LFSR for lower power optimization using VHDL 4. Practical asynchronous interconnect designing of a transmitter with parity 5. VLSI design of single chip stepper motor controller using VHDL 6. Single chip Encryptor core implementation of key scheduling for AES algorithm 7. Implementation of hash algorithm used for cryptography and security 8. FPGA implementation of USB transmitter macro cell interface 9. Practical asynchronous interconnect designing of an receiver with a parity 10. FPGA based designing of SPI and PSI Architectures 11. An efficient VLSI design of convolution encoder for satellite communication 12. Single chip Encryptor Decryptor core implementation of key scheduling for DES algorithm 13. A single chip designing of Arithmetic Logic Unit using VHDL 14. Implementation of Dual Port RAM for ATM applications 15. Implementation of RAM,ROM and instruction decoder of Pipelined RISC processor for parallel processing 16. Enhancement of BIST for Faulty circuit Techniques on FPGA 17. VLSI design of single chip Traffic Light Controller 18. Implementation of Scrambler and Descrambler in fiber optic communication systems for OTN using VHDL 19. VLSI design of pipelined module of RISC processor for parallel processing
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