EE 332 Lab3 v2 - 1

2012
Multi-stage Amplifiers
EE332 Laboratory
Group 13 Class 09ECE 15-Nov-12
EE332 Laboratory
Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin
Report lab 3
Multi-Stage Amplifiers
Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin
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EE332 Laboratory
Group 13 09ECE Nguyn Ngc Minh Ng Trn c Thng Nguyn Xun Tin
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EE332 Laboratory
Contents
INTRODUCTION ..................................................................................................................................................... 4 COMMENT ............................................................................................................................................................. 4 PROCEDURE 1: NPN COMMON-EMITTER STAGE CHARACTERISTICS.................................................................................. 6 Comments ............................................................................................................................................................6 Set-Up...................................................................................................................................................................6 Measurement-1 ....................................................................................................................................................8 Question-1 ..........................................................................................................................................................18 PROCEDURE 2 ACTIVE LOADS---A SIMPLE OPAMP ...........................................................................................................19 Comment ............................................................................................................................................................19 Set-Up.................................................................................................................................................................19 Measurement-2 ..................................................................................................................................................20
Sub-measurement 2-1: ................................................................................................................................................... 21 Sub-measurement 2-2: ................................................................................................................................................... 22 Sub-measurement 2-3: ................................................................................................................................................... 23 Sub-measurement 2-4: ................................................................................................................................................... 23
Question-2 ..........................................................................................................................................................25 PROCEDURE 3 COMPLEMENTARY CLASS-AB OUTPUT STAGE .............................................................................................26 Comment ............................................................................................................................................................26 Set-Up.................................................................................................................................................................26 Measurement 3 ..................................................................................................................................................27
Sub-measurement3-1: .................................................................................................................................................... 27 Sub-measurement 3-2: ................................................................................................................................................... 28 Sub-measurement 3-3: ................................................................................................................................................... 29
Question3 ...........................................................................................................................................................30 PROCEDURE 4 : HIGH GAIN CASCODE ...........................................................................................................................31 Comment: ...........................................................................................................................................................31 Set-Up:................................................................................................................................................................31 Measurement-4 ..................................................................................................................................................31
Sub-measurement 4-1: ................................................................................................................................................... 32 Sub-measurement 4-2: ................................................................................................................................................... 32 Sub-measurement 4-3: ................................................................................................................................................... 33
Question-4 ..........................................................................................................................................................34
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Introduction
The objectives of this experiment are to examine the characteristics of several multi-stage amplifier configurations. Several of these will be breadboarded and measured for voltage gain, frequency response and signal swing. In addition to the performance measurements, you should also pay attention to how the biasing of each amplifier stage is achieved, how the signal is coupled from stage to stage, and what design strategy has been adopted to desensitize the amplifier performance to variations in the transistor parameters. For each amplifier in this experiment, try to answer the question: What has been achieved by connecting the transistors in this configuration? To begin to answer this question, first identify whether a particular transistor is providing bias stabilization for other transistors, or is a gain stage in the signal path. Some transistors may simultaneously function in both roles. Then try to determine what components set the voltage gain of the amplifier. Track the path of the signal through the different stages of the amplifier and try to understand how much voltage gain is produced across each stage, how big the signal is at each node along the path, and what limits the signal swing at each node. Draw a schematic of the amplifier in your lab notebook and mark it up extensively to show the DC bias voltage at each node, the path that the signal takes from input to output, and anything else that is of interest to you. The amplifier circuits described in this experiment are not as simple as those previously used in this lab. While all of the component values are fairly close to the values needed to make the circuits work, normal variations in transistor parameters will require that each amplifier circuit be tuned-up slightly to center the signal swings or trim out the gain. This is left for you to do without any explicit instructions and is intended to force you to understand how the circuits work and to gain skill in electronic troubleshooting. Similarly, the procedures will only ask you to measure certain performance parameters without giving explicit instructions. At this point, you should be comfortable making all of these measurements. Refer back to experiments 2 and 3 if you need to refresh your memory on making gain and frequency response measurements.
Comment
Some of the procedures in this experiment will utilize the CA3046 npn BJT array. The CA3046 is an RCA part number, and it is the same as the National Semiconductor part number LM3046. This integrated circuit comprises five npn BJTs which are fabricated on the same piece of silicon, and is a first approximation to the behavior of BJTs that one would find in a bipolar integrated circuit. The first two BJTs are tied together with a common emitter (pin 3), and the last BJT has its emitter tied to the substrate (pin 13), as shown in Fig. E5.0 below. All five npn BJTs have their collectors embedded into a common p-type substrate, which is connected to pin 13. In order to keep the collector-substrate pn-junctions reverse biased so that the BJTs will remain
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electrically isolated, the substrate on pin 13 MUST be tied to the lowest potential in the circuit, even if the fifth transistor is not being used. Any circuits using the fifth BJT of the CA3046 array MUST tie the emitter of this transistor to the lowest potential power supply rail. Failure to tie pin 13 to the lowest circuit potential will result in very unpredictable behavior for the circuit. Be warned!!
1 Q1 Q2
8 Q3
11 Q4
6 7 14
9 10
12
Q5 SUBSTRATE 13
Figure E3.0
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Electronic part
4 BJT 2N3904, 2N3906 R 330, 5K, 100K, 15K, 43K, 630 Ohm, 3.3K , 100Ohm, 5Ohm, 4.7K Bien tro 1K 3 Tu 10uF N4148 Tip29, Tip30
Procedure 1: NPN common-emitter stage characteristics

Comments
With in input signal delivered to the base terminal and the output signal pulled from the collector terminal, the emitter terminal of the BJT is common to the input and output ports. Thus, this configuration is termed a common-emitter transistor stage. In the following circuit a potentiometer R3 will be used to adjust the value of the collector resistor. To keep the value of this resistance from accidentally being reduced all the way to zero, an additional pot-stop resistor R2 is added in series to establish a minimum resistance for this branch. This is always good practice for potentiometers to avoid producing unwanted short circuits which could cause serious circuit problems, in this case destroying the transistor. Whenever you design a circuit with a potentiometer in it, always consider the worst cases that will occur at each of the two endpoints of the potentiometers settings. A little forethrought here will save you lots of parts and frustration later!
Set-Up
Using the solderless breadboard, construct the circuit shown in Fig. E3.1 using the following components: R1 = 100 k 5% 1/4 W R2 = 330 5% 1/4 W R3 = 5 k potentiometer Q1 = 2N3904 npn BJT
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+10V
+10V
VDD PPS1
R3 5k POT
R2 330 OUTPUT V1 Signal generator GND R1 100k Q1 2N3904 GND SCOPE GND SCOPE CH-2
INPUT
SCOPE CH-1
Figure E3.1
Configure the PPS1 DC power supply to implement the VCC DC source in Fig. E5.1. Adjust the PPS1 power supply output to +10.0 V. Initially adjust the R3 potentiometer for a value of zero ohms, i.e. the series combination of R2 + R3 should be just R2 = 330 . Configure the signal generator to output a +3.0 V amplitude, +1.5 V DC offset, 60 Hz sinewave. Set the output impedance to a large value. Connect a 10 probe to the BNC connectors on each of the two input channels of an oscilloscope. Connect the probe from Ch-1 to the input end of R1 to monitor the input signal, and connect the probe from Ch-2 to the output node between R2 and Q1 to monitor the output signal, as shown in Fig. E3.1. Both oscilloscope probe ground leads and the ground lead from the DC power supply should all be connected to the emitter lead of transistor Q1. Configure the oscilloscope to display both channels with a vertical scale of 5 V/div, which includes the attenuation of the 10 probes. Set the input coupling of both channels to DC, and make sure that channel-2 is not inverted. Set the timebase to 5 ms/div. Set the trigger mode to AUTO with a source of Ch-1. Finally center both traces on the center of the screen by switching the input coupling for each channel to GND, moving each trace to the center hairline of the screen using the position controls, and then returning the input coupling switches to the DC position. Yellow: input signal Blue: output signal
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EE332 Laboratory
Measurement-1
Next, turn the laboratory transformer ON. At this point, the oscilloscope should show a sinewave input for Ch-1 and only the positive half cycles of a sinewave output for Ch-2. Sketch both of these waveforms on the same set of axes in your lab notebook.
The oscilloscope will now be used to directly display the voltage transfer characteristics (VTC) of this circuit. Do not change any of the connections from those of Fig. E3.1 and simply reconfigure the oscilloscope to display Ch1 versus Ch-2 in an X-Y mode. Ground the inputs to both channels by setting the coupling switches to GND, and then switch the oscilloscope into the X-Y mode. (On Tektronix oscilloscopes, all you need to do is push the X-Y button in; on Hewlett-Packard oscilloscopes, you will need to access the X-Y mode through the MATH function menu.) Use the position controls to move the dot onto the cross-hairs in the exact center of the screen. Change the input coupling on each of the two channels back to DC and the display should now
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EE332 Laboratory
show the VTC. Sketch the VTC shown on the oscilloscope screen in your notebook.
Using the built-in meter on the DC power supply, vary the output voltage VCC over the range of 0.0 to +10 V. Switch back and forth between the voltage versus time and VTC (X-Y) modes of the oscilloscope to observe the effect on the output waveforms and the VTC. (On Tektronix oscilloscopes, you can do this by simply pushing the X-Y button in and out.) Jot down in your notebook the effect of varying the power supply voltage. Case 1: VCC = 0V
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Case 2: VCC = 2V
Case 3: VCC = 4V
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Case 4: VCC = 6V
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Case 5: VCC = 8V
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Case 6: VCC = 10V
Now examine how the VTC is affected by the value of collector resistance, R2 + R3. Vary the R3 potentiometer from 0 to 5 k and switch the oscilloscope back and forth between displaying the VTC and displaying the voltage versus time waveforms to better appreciate what is happening in the circuit and how this is represented on the VTC. For larger values of R2 + R3, the VTC should have three distinct segments. Identify the region of transistor operation for each of these as: {cutoff, forward active, reverse active, or saturated}.
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Case 0: R3 = 0k
Case 1: R3 = 1k
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Case 2: R3 = 2k
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Case 3: R3 = 3k
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Case 4: R3 = 4k
Case 5: R3 = 5k
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Question-1
(a) From the measured VTC, is the npn common emitter stage inverting or non-inverting? => Answer: the npn common emitter stage is inverting.
(b) Explain why the VTC does not exhibit a saturation segment when the value of R2 + R3 is reduced to below a certain point. => Answer: (c) Explain why R1 is needed in the circuit of Fig. E3.1. I.e., why cant the lab transformer be directly connected to the base of Q1? If this totally stumps you, short out R1 in the circuit and see what happens; just be prepared to buy a new 2N3904 from the stockroom, along with some new transformer fuses! => Answer: The ac source itself has a certain internal impedance (about 50), so we use R1 to make the input resistance become higher. This will server 3 purposes: - With high value of input resistance, when using the voltage division, we can see that almost voltage from the ac source will be transferred to BJT, means that vsource vin. The power could be reduced, since: The lager the value of R is, the smaller the value of power is. Larger value of input resistance will make the current going to the BJT more stable.
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Procedure 2 Active loads---a simple opamp

Comment
An active load usually refers to the use of a transistors output characteristics (IC versus VCE) to provide a high output resistance but at a much larger level of DC current than what a passive resistor alone could provide. Using an active load for a common-emitter stage greatly increases the voltage gain since the collector resistance for the CE amplifier stage is now the output resistance of the active load transistor. In the circuit of Fig. E5.2, an active load is used on both collector legs of an npn differential pair. When connected like a current mirror as shown, the pair of active loads also has the benefit of routing both sides of the differential signal into the next stage, the base of Q6. The active loads in this case form a differential to single-ended converter. Transistor Q3 provides an improved current source for the differential pair which greatly increases the common-mode rejection ratio. Transistor Q6 implements a simple common-emitter stage with a load resistor of R8. This adds some final gain and current drive to the output pin. Resistors R5-R6-R7 provide bias stabilization for this output stage. R4 is an optional trimpot between the emitters of Q1 and Q2. This will lower the voltage gain of this stage slightly, but it will allow the input differential amplifier to be balanced to help bias the circuit so that the output voltage will be about zero when the differential input voltage is also zero. This may or may not be necessary. If R4 is used, its value should not be more than 1.0 k, or the gain of the differential amplifier will be lowered too much.
Set-Up
Construct the circuit shown in Fig. E3.2 on your solderless breadboard using the following components: R1 = 10 k 5% 1/4 W R2 = 100 k 5% 1/4 W R3 = 1.0 k 5% 1/4 W R4 = 1.0 k trimpot (if needed to balance the amplifier) R5 = 15 k 5% 1/4 W R6 = 43 k 5% 1/4 W R7 = 620 5% 1/4 W R8 = 3.3 k 5% 1/4 W Q1, Q2, Q3 = 2N3904 npn BJT Q4, Q5, Q6 = 2N3906 pnp BJT
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+10V
+10V
Q4 2N3906 Q5 2N3906 R5 15k R7 620 Q6 2N3906 VINQ1 2N3904 Q2 2N3904 VIN+ R6 43k VOUT R4 R2 100k 1k POT
VCC PPS1
GND
GND
VEE PPS2 R1 10k
Q3 2N3904 R3 1.0k
R8 3.3k
-10V
-10V
Figure E3.2 Configure the PPS1 DC power supply to +10.0 V DC and the PPS2 DC power supply to -10.0 V DC. This is to implement the VCC = +10.0 V and VEE = 10.0 V DC power supply rails, as shown in Fig. E4.2. Connect the PPS1 and PPS2 outputs to the breadboard. The GND terminals on PPS1/PPS2 are the system ground. Because of the high gain of this circuit, you may need to adjust the DC balance of the input differential amplifier. First check the balance by grounding both inputs to the bases of Q1 and Q2. Make certain that these grounds go to the system ground labeled GND in Fig. E3.2. With both inputs grounded, measure the voltage on the output pin, connected to the collector of Q6. This should be within a volt or so of ground, also. If it is not, then you may need to add in the optional trimpot R4 between the emitters of Q1 and Q2. Power down the circuit, install R4, and then fire it back up to re-measure the DC output voltage. If the output voltage is still not sufficiently close to zero, adjust the trimpot to center the output voltage to zero. You may need to readjust this balance as you go through the rest of this procedure.
Measurement-2
Ground the () input of the amplifier and apply a sinewave to the (+) input, relative to the system ground. Adjust the amplitude of the input to produce a non-distorted sinewave at the output. Adjust the frequency so that the maximum voltage gain is obtained. You will have to use a very small amplitude sinewave on the input, since the voltage gain of this circuit is rather high, and the frequency that you use may need to be fairly low to obtain the maximum voltage gain. Measure and record the amplitude of the input and output sinewaves, and take their ratio to determine the differential-mode voltage gain.
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Sub-measurement 2-1:
Adjust the amplitude of the input to produce a non-distorted sinewave at the output. Measure and record the amplitude of the input and output sinewaves. The simulation circuit
Maximum input voltage that no clip is 0.2 Vpp Maxgain Vout pp = 15.8Vpp
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Sub-measurement 2-2: Increase the amplitude of the function generator to where the output
waveform is clipped at both the positive and negative peaks. Measure and record the output voltage levels at which the clipping occurs. The input voltage that output begins to clip is 0.3Vpp in or 0.15V ampl
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Sub-measurement 2-3: Decrease the amplitude of the function generator to again produce an
undistorted sinewave at the output and then increase the frequency to where the voltage gain drops to 70 percent of its maximum value. Measure and record this frequency as the -3 dB differential-mode bandwidth. We already calculated the maximum gain 79 at 0.1 Vamp; 70% maximum gain is 0.7 x 79 = 65.8 Vpp = 0.2 x 65.8 = 11.06 V Hence, we will increase the input frequency to get the output of 11.06 Vpp within Vinput is 0.1Vampl The below result is at frequency equal 169.4kHz
Sub-measurement 2-4: Release the () input from ground and apply the function generator
output to both the (+) and () inputs simultaneously, adjusting the amplitude to produce an undistorted sinewave at the output. Measure and record the amplitude of the input and output sinewaves and take their ratio to determine the common-mode voltage gain.
Simultaneously input represent for in_phase noise Set Vpp + = V pp- = 0.2V, 100Hz
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Question-2
(2a) From your measured data, calculate the differential-mode voltage gain of the amplifier in decibells (dB). Max gain is = 37.95 dB
(2b) From your measured data, calculate the common-mode voltage gain of the amplifier in decibells (dB). The common-mode voltage gain Acc = 0.02 / 0.2 = 0.1 = - 20 dB (2c) Calculate the common-mode rejection ratio (CMRR) for this amplifier, expressing the result in decibells (dB).
(2d) Explain what determines the clipping voltage levels. The DC supply voltage determines the clipping voltage levels. Normally, when the BJT be able to amplifier the input voltage but the DC cannot supply enough power, the signal will be clipped. So the high supply power, the high clipping level. In addition, this is only right when the BJTs and other devices work well. (2e) Calculate the gain-bandwidth product for this amplifier. The gain-bandwith product
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Procedure 3 Complementary class-AB output stage

Comment Emitter followers (or common-collector) stages were shown to be a nice means
for increasing the output current level of an amplifier and buffering voltage gain stages. However, when a large bias current runs continuously through such a stage, it dissipates far more power than it delivers to the load, resulting in poor power efficiency. One way to correct this is to only operate the transistor when it is delivering current to the load, termed class-AB operation. Using two transistors of opposite sex but driven by the same input signal is termed a complementary output stage and provides a power efficient configuration for output buffering or current boosting. This circuit can be used to boost the output current of an opamp. Putting the output stage inside the feedback loop causes the gain of the opamp to linearize the characteristics of the output stage.
Set-Up
Construct the circuit shown in Fig. E3.3a

+10V +10V R1
VCC PPS1 + C1 10 uF
4.7k
Q1 Q3
TIP29 2N3904 1N4148
D1
R3 5.0 R4 Q4
5.0
GND
GND
VIN R5 + C2 10 uF 100k
VOUT RL
100
1N4148 2N3906
D2
VEE PPS2 -10V -10V
Q2 R2
4.7k
TIP30
Figure E5.3a Configure PPS1 and PPS2 to implement the VCC = +10.0 V and VEE = 10.0 V DC power supply rails, as shown in Fig. E5.3a. Turn the PPS power supplies ON. The center ground terminal is the system ground. Configure the AWG to produce a 1.0 kHz 5.0 Vpp amplitude sinewave and apply this sinewave across the input resistor R5.
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Measurement 3
Sub-measurement3-1: Use an oscilloscope to monitor the input and output voltage
waveforms. Record sketches of the input and output waveforms in your lab notebook. Result from pspice with 1.0 kHz 5.0 Vpp amplitude sinewave input.
The below is channel 1 (the orange curve) is output signal
The below is channel 2 (the blue curve) is input signal
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Sub-measurement 3-2: Increase the amplitude of the input signal until the output voltage
waveform is clipped on both the positive and negative peaks. Measure and record the output voltage clipping levels. Increase to 20Vpp
The result from pspice with 10V ampl
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In piespce with 7.3V the output signal begin to clip but 10V(above) it does not clip anymore.
Comment: actually, in pspice, we just need to increase the amplitude to 7.3V to get the clipping at both sides of the sinwave. From measurement, to get clipping both sides, we have to increase the amplitude of the input to 10V.
Sub-measurement 3-3: Restore the input signal to a 1.0 kHz 5.0 Vpp amplitude sinewave
and increase the frequency until the output voltage waveform falls to 70 percent of its previous amplitude. This is the -3 dB bandwidth of the output stage. 70%Vpp_initial = 70%(4.80V) = 3.36V To get this value, we adjust the frequency of input until approximately 2.4MHz
From pspice, 70%Vampl_initial = 70%(2.3611) = 1.653V => need adjust the frequency to 6MHz.
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Hereunder is the output waveform if we use the frequency got from measurement, means 2.4MHz.
Question3
(3a) Calculate the voltage gain for this output stage.
(3b) Comment on any distortion that is seen in the output voltage waveform. Answer: there is no distortion appears in the output voltage. In compare with the clas-A or B amplifiers, each transistor in the class AB-amplifier conducts for more than the 1800 of the class-B amplifier but less than the full 3600 of the class A-amplifier. (3c) Calculate the limited value of output current when the short-circuit protection becomes active.
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Answer:
Procedure 4 : High gain cascode

Comment: The input resistor R1 in the previous two amplifiers establishes the voltage gain
and the input impedance. This stabilizes the gain against variations in transistor , but produces a rather low value of voltage gain. By rearranging the first stage of the circuit, the input can be directly applied to the base of the input CE stage, greatly increasing its gain.
Set-Up:
Modify the circuit of Fig. E3.3 to that of Fig. E3.4 by altering the connections and bias resistors around Q1 and Q2.
Figure E3.4
Measurement-4
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Sub-measurement 4-1: Adjust the circuit and signal generator to produce clean 1.0 kHz
sinewaves on the input and output. Measure and record the amplitude of both input and output, and then take the ratio to determine the voltage gain. Answer: The maximum input voltage is 0.005Vampl, 1kHz to get the perfect sinwave output voltage
Compare result to pspice
Sub-measurement 4-2: Increase the frequency of the signal generator until the voltage
gain falls to 70 percent of its value at 1.0 kHz. Measure and record this -3 dB bandwidth of the amplifier. The Gain at 1kHz is 376 70% of 376 is 0.7x376 = 263.2 Vpp out = 263.2 x 0.01 = 2.63 V The result from measure is 2.5 with frequency is 3.507MHz
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Sub-measurement 4-3: Restore the frequency to 1.0 kHz, and increase the amplitude of
the signal generator until the output signal is clipped at both the positive and negative peaks. Measure and record the output voltage levels at which clipping occurs. Answer: Increase voltage to 0.08 Vampl
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Question-4
(4a) Using your measured data, calculate the voltage gain of the amplifier in decibells (dB).
(4b) Compare the bandwidth of this amplifier to that of procedures 1 and 2 and explain the cause for the differences or similarities. The bandwidth of this amplifier is so small when compare to the first and the second circuits. The first No required calculation The second 0.1 Vampl The fourth 0.005Vampl
V input begin to distorsion
The differences of fourth circuit are two capacitors connect to input and output of the circuit. These capacitors act like highpass filters. (4c) Explain what function Q1 provides in this new configuration, if any. The function of Q1 is connect directly the current to Base of input CE stage. This will increase the volgate gain much. Another point for noting is that the BJT Q1 only works at low frequency because at hight frequency, the capacitor that C3 will be shorted to ground. In addition, from measurement, the frequency that less than 3.507MHz is low frequency.
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2012

Group 13 Class 09ECE 15-Nov-12

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Procedure 1: NPN common-emitter stage characteristics

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Case 6: VCC = 10V

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Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Procedure 2 Active loads---a simple opamp

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Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

VEE PPS2 R1 10k

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Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Group 13 | Nguyn Ngc Minh | Ng Trn c Thng | Nguyn Xun Tin

Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

Procedure 3 Complementary class-AB output stage

Construct the circuit shown in Fig. E3.3a

TIP29 2N3904 1N4148

VEE PPS2 -10V -10V

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Dr.Nguyn Vn Tun - TA: Nguyn Trung Kin

The below is channel 1 (the orange curve) is output signal

The below is channel 2 (the blue curve) is input signal