04 CMOS Layout

Class update
Nanosystem Design Lecture 4: CMOS Layout

Prof. R. Iris Bahar EN291-S10 (makeup class) September 21, 2005
Class will take place as schedule next week! The course webpage us up:
http://www.lems.brown.edu/~iris/en291s10-05/index.html
Mickey will be presenting Thursdays lecture Please see the webpage to access the papers
For ITRS paper, please focus on pages 39-44, though you may
find other parts interesting reading as well.
Im looking for two volunteers for scribes on Thursday

EN291-S10: Nanosystem Design Lecture 3-2
CMOS Inverter:
Steady State Response
VDD VDD Rp Vout = 1 Rn Vout = 0
Full rail-to-rail swing high noise margins
CMOS Properties
Logic levels independent of device sizes ratioless
Always a path to Vdd or GND in steady state low

Vin = 0
Vin = V DD
output impedance (output resistance in k range) Less sensitive to noise Extremely high input resistance (gate of transistor is near perfect insulator) nearly zero steady-state input current Can theoretically drive large fan-out No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors
CMOS Inverter:
Switch Model of Dynamic Behavior V V
DD DD
CMOS Inverter VTC

2.5 2
NMOS off PMOS res NMOS sat PMOS res
Rp Vout CL Rn Vout CL Vout (V)

1.5 1 0.5
NMOS res PMOS sat NMOS res PMOS off NMOS sat PMOS sat
Vin = 0
Vin = V DD
0 0 0.5 1 1.5 2 2.5
Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)
Vin (V)
Relative Transistor Sizing

When designing static CMOS circuits, balance the
driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics NMOS device has approximately 3.5X the drive strength of PMOS device Mainly due to differences in mobility of carriers In practice, a ratio of 2-2.5X is reasonable
Impact of Process Variation on 2.5 VTC Curve

2
Good PMOS Bad NMOS
Vout (V)
1.5 1 0.5 0 0 0.5 1 1.5 2 2.5

Nominal Bad PMOS Good NMOS
Vin (V) Process variations (mostly) cause a shift in the switching threshold
EN291-S10: Nanosystem Design Lecture 3-7 EN291-S10: Nanosystem Design Lecture 3-8
Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)
VDD PMOS transistors only In1 In2 InN In1 In2 InN PDN PUN pull-up: make a connection from VDD to F when F(In1,In2,InN) = 1 F(In1,In2,InN) pull-down: make a connection from F to GND when F(In1,In2,InN) = 0 NMOS transistors only
Construction of PDN
NMOS devices in series implement a NAND function
AB A B
PUN and PDN are dual networks

DeMorgans theorems
A+B=AB AB=A+B [!(A + B) = !A !B or !(A | B) = !A & !B] [!(A B) = !A + !B or !(A & B) = !A | !B]
a parallel connection of transistors in the PUN corresponds to

a series connection of the PDN
Complementary gate is naturally inverting (NAND,

NOR, AOI, OAI)
Number of transistors for an N-input logic gate is 2N

NMOS devices in parallel implement a NOR function

A+B A B
PUN and PDN are dual logic networks

Dual PUN and PDN

A B
CMOS NAND
A 0 0 AB A B A B 1 1 B 0 1 0 1 F 1 1 1 0
CMOS NOR
B A A+B A B A 0 0 1 1 B 0 1 0 1 F 1 0 0 0
Complex CMOS Gate

B A C D OUT = !(D + A (B + C)) A D
A B
Inverter Propagation Delay

Propagation delay is proportional to the time-constant of the network
formed by the pull-down resistor and the load capacitance. VDD
Modeling Propagation Delay

Model circuit as first-order RC network
vout (t) = (1 et/)V
R vout C vin
tpHL = f(Rn, CL)
where = RC Time to reach 50% point is t = ln(2) = 0.69 Time to reach 90% point is t = ln(9) = 2.2
Rp
Rn = Req =
Vout = 0 Rn CL
3 VDD 5 (1 VDD ) 4 I DSAT 6
CL = Cint + Cext + Cwire
Vin = V DD
Want to have equal rise/fall delays Make Rn=Rp

t p = (t pHL + t pLH ) / 2 = 0.69C L ( Rn + R p ) / 2

Design for Performance

Increase W/L ratio of the transistor
the most powerful and effective performance optimization tool in
the hands of the designer
Input Pattern Effects on Delay

Delay is dependent on the pattern of
Rp A Rn A Rn B Cint B CL Rp
inputs
Low to high transition

both inputs go low
delay is 0.69 Rp/2 CL since two p-resistors
are on in parallel
Reduce CL
keep drain diffusions small limit interconnect capacitance limit fan-out Increase VDD trade-off energy for performance increasing VDD above a certain level yields minimal improvements reliability concerns enforce a firm upper bound on VDD
one input goes low
High to low transition

both inputs go high
delay is 0.69 Rp CL
Adding transistors in series (without

sizing) slows down the circuit
delay is 0.69 2Rn CL
Transistor Sizing
Rp 1 A Rn 2 2 A Rn B Cint Rn A B Rp 1 CL 2 B 2 Rp A Rn B 1 CL Cint Rp
Transistor Sizing a Complex Gate

B A 2 6 C D 2 A D 1 B 2C 2 6 OUT = !(D + A (B + C)) 2 4 12 4 12
Fan-In Considerations
A B A B C D C3 C2 C1 C D CL tp (psec)
1250 1000 750 500 250 0
tp as a Function of Fan-In
quadratic function of fan-in tpHL tp tpLH
2 4 6 8 10 12 14 16
Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case.
linear function of fan-in
fan-in
Gates with a fan-in greater than 4 should be avoided.

Symbolic Layout
V DD In
Layout structure may be

3 Out
cumbersome to draw
Standard Cell Layout

Routing channel VDD
Instead use a symbolic

layout approach
Each of the different layers is
1
GND
Stick diagram of inverter
represented with sticks All entities are dimensionless Positioning is most important Avoid dealing with rule checks
at this stage
signals
Useful for 1st-order drafting of

new cells
GND
What logic function is this?

Layout Planning for Complex Gates

Want layout to be as dense (area efficient) as
possible. Try to realize all NMOS and PMOS transistors in an unbroken row of devices Requires only single strip of diffusion in both wells Careful ordering of inputs is important to help achieve this Use a systematic approach identifying Euler paths
OAI21 Logic Graph

A j B X = !(C (A + B)) C A i B A B C GND X B i j A PDN C X C VDD PUN
Two Stick Layouts of !(C (A + B))

A B C A B C
An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X
Consistent Euler Path
A VDD
C VDD
A B
C
C
ABC
VDD
X
B
i B j GND A
GND
GND
uninterrupted diffusion strip

For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
OAI22 Logic Graph

A B C D X = !((A+B)(C+D)) C A D B X B A B C D GND A PDN D X C VDD PUN VDD
OAI22 Layout
A B D C
GND
Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)
Interface between designer and process engineer Guidelines for constructing process masks
Minimum width Minimum spacing constraints Requirement on same or different layers Unit dimension: Minimum line width and minimum spacing constraints scalable design rules: parameter absolute dimensions: micron rules Three parts to design rules: Set of layers Intra-layer: Relations between objects on same layer Inter-layer: Relation between objects on different layers
Design Rules
CMOS Process Layers

Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation
Intra-Layer Design Rules

Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2
Metal2 3
Inter-Layer Design Rule Origins

1. Transistor rules transistor formed by overlap of active
and poly layers
Catastrophic error
Different Potential 9 Polysilicon 2 Metal1 3

4
Well
Transistors
3
Unrelated Poly & Diffusion

Thinner diffusion, but still working
Minimum dimensions and spacings (using rules) Note that =1/2 L

Interlayer Constraints: Transistor Layout

Transistor 1
Interlayer: Vias and Contacts

Contact to contact
2
Diffusion to 1 contact
m2 Via
1
4 5
Metal to Active Contact
Metal to Poly Contact 3 2
2
Transistor 2 to contact
m1
2
Select Layer (well and substrate contacts)

2 3 2 1 3 3 Select
What Does Real Layout Look Like

Out metal1 metal2 In metal1-poly contact polysilicon VDD
P-FET
P-diffusion metal1-diff contact
PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) N-diffusion N-FET
Substrate
Well
GND metal2-metal1 via


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Class update

Nanosystem Design Lecture 4: CMOS Layout

Im looking for two volunteers for scribes on Thursday

Full rail-to-rail swing high noise margins

Logic levels independent of device sizes ratioless

Always a path to Vdd or GND in steady state low

CMOS Inverter VTC

Rp Vout CL Rn Vout CL Vout (V)

0 0 0.5 1 1.5 2 2.5

Relative Transistor Sizing

Impact of Process Variation on 2.5 VTC Curve

1.5 1 0.5 0 0 0.5 1 1.5 2 2.5

Static Complementary CMOS

PUN and PDN are dual networks

a parallel connection of transistors in the PUN corresponds to

Complementary gate is naturally inverting (NAND,

Number of transistors for an N-input logic gate is 2N

NMOS devices in parallel implement a NOR function

PUN and PDN are dual logic networks

Dual PUN and PDN

EN291-S10: Nanosystem Design Lecture 3-12

Complex CMOS Gate

EN291-S10: Nanosystem Design Lecture 3-13

EN291-S10: Nanosystem Design Lecture 3-14

Inverter Propagation Delay

Modeling Propagation Delay

tpHL = f(Rn, CL)

3 VDD 5 (1 VDD ) 4 I DSAT 6

CL = Cint + Cext + Cwire

Want to have equal rise/fall delays Make Rn=Rp

t p = (t pHL + t pLH ) / 2 = 0.69C L ( Rn + R p ) / 2

Design for Performance

Input Pattern Effects on Delay

Low to high transition

one input goes low

High to low transition

Adding transistors in series (without

delay is 0.69 2Rn CL

EN291-S10: Nanosystem Design Lecture 3-17

Transistor Sizing a Complex Gate

EN291-S10: Nanosystem Design Lecture 3-19

EN291-S10: Nanosystem Design Lecture 3-21

linear function of fan-in

Gates with a fan-in greater than 4 should be avoided.

Layout structure may be

Standard Cell Layout

Instead use a symbolic

Each of the different layers is

Useful for 1st-order drafting of

What logic function is this?

Layout Planning for Complex Gates

OAI21 Logic Graph

EN291-S10: Nanosystem Design Lecture 3-27

Two Stick Layouts of !(C (A + B))

Consistent Euler Path

uninterrupted diffusion strip

EN291-S10: Nanosystem Design Lecture 3-29

OAI22 Logic Graph

CMOS Process Layers

EN291-S10: Nanosystem Design Lecture 3-34

Intra-Layer Design Rules

Inter-Layer Design Rule Origins

Different Potential 9 Polysilicon 2 Metal1 3