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PIC18MICROCONTROLLER {SerialCommunicationProtocol}
MohamadFauziZakaria http://fkee.uthm.edu.my/mfauzi

Basic Serial Communication

Communication Method
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SYNCHRONOUS
transfers a BLOCK of data at a time use SEPARATE CLOCK and DATA LINE

ASYNCHRONOUS
g transfers a single BYTE at a time has NO SEPARATE CLOCK accompanying the data

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Basic Serial Communication

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Data Transmission

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PART PART1
UART

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RS232 Standard
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Was set by the Electronics Industries Association (EIA) in 1960, before the advent of TTL logic family. Therefore, logic 1 is represented by -3 to -25V, and logic 0 is +3 to +25V +25V. Two types of RS232 pins: DB-25 and DB-9. Most important pins are Tx, Rx Tx Rx, and ground ground. To interface with PIC, we need line driver such as MAX232 (need capacitors) or MAX233 ( capacitors). it ) (no it )

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UART
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>>PIC18 and PC-RS232

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UART REGISTER
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>>PIC18F4550 UART REGISTER

Normal USART has 7 major registers: TXSTA (Transmit status and control register) RCSTA (Receive status and control register) BAUDCON (Baud rate control) SPBRG (serial port baud rate generator) TXREG (Transfer register BUFFER) RCREG (Receive register BUFFER) PIR1 (peripheral interrupt request register 1)

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EUSART
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The Enhanced USART module implements additional features, including: automatic baud rate detection and calibration automatic wake up on Sync Break reception wake-up 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network y bus (LIN bus) systems.

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PINsConfiguration PINs Configuration

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InordertoconfigureRC6/TX/CKand RC7/RX/DT/SDOasanEUSART: RC7/RX/DT/SDO as an EUSART:

bitSPEN(RCSTA<7>)mustbeset(=1) bitTRISC<7>mustbeset(=1) bitTRISC<6>mustbeset(=1) bit TRISC<6> must be set (= 1)

Note:TheEUSARTcontrolwillautomatically g p p p reconfigurethepinfrominputtooutputas needed.

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TXSTA
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TRANSMIT STATUS AND CONTROL REGISTER

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RCSTA
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RECEIVE STATUS AND CONTROL REGISTER

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BAUDCON
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BAUD RATE CONTROL REGISTER

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BaudRateGenerator(BRG) Baud Rate Generator (BRG)

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By default, the BRG operates in 8-bit mode. Setting the S tti th BRG16 bit (BAUDCON 3 ) selects 16 bit (BAUDCON<3>) l t 16-bit mode.

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Calculating the Baud Rate Error

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ASYNCHRONOUSTRANSMITTER ASYNCHRONOUS TRANSMITTER

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Tosetupan

ASYNCHRONOUSTRANSMITTER
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1.

2. 3. 4. 5. 5

6. 7. 8. 8 9.

Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. , q , Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If the signal from the TX pin is to be inverted, set the TXCKP bit. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired set transmit bit TX9 Can be used as 9 bit desired, TX9. address/data bit. Enable the transmission by setting bit TXEN which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). transmission) If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON 7:6 ) (INTCON<7:6>) are set.

ASYNCHRONOUSRECEIVER ASYNCHRONOUS RECEIVER

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Tosetupan

ASYNCHRONOUSRECEIVER
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1.

2. 3. 4. 5. 6. 7.

8.

9. 10. 11.

Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. , q , Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If the signal at the RX pin is to be inverted, set the RXDTP bit. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. Enable the reception by setting bit CREN CREN. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCIE was set bit RCIE, set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing enable bit CREN. If using interrupts, ensure that th GIE and PEIE bit iin th INTCON register i i t t th t the d bits the i t (INTCON<7:6>) are set.

Example1 Example 1
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USARTFUNCTIONLIBRARY USART FUNCTION LIBRARY

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Example2 Example 2
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PART PART2
SPI

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MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

Is a serial interface, useful for communicating with other peripheral or microcontroller devices devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. di l d i t t The MSSP module can operate in one of two modes:
Serial Peripheral Interface (SPI) Inter-Integrated Circuit (I2C)

The I2C interface supports the following modes in hardware:

Master mode Multi-Master mode Slave mode
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MSSP Control Registers

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has three associated registers: a status register (SSPSTAT) control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode.

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SPIPins SPI Pins

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To accomplish communication, typically three pins are used:

Serial Data Out (SDO) RC7/RX/DT/SDO Serial Data In (SDI) RB0/AN12/INT0/FLT0/SDI/SDA Serial Clock (SCK) RB1/AN10/INT1/SCK/SCL ( )

Additionally, fourth i Additi ll a f th pin may be used when iin a Sl b d h Slave mode of operation:
Slave Select (SS) RA5/AN4/SS/HLVDIN/C2OUT

SPI SPI
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Block Block g Diagram

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SPIRegisters SPI Registers

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The MSSP module has four registers for SPI mode operation. operation These are:
MSSP Status Register (SSPSTAT) MSSP Control Register 1 (SSPCON1) Serial Receive/Transmit Buffer Register (SSPBUF) MSSP Shift Register (SSPSR) Not directly accessible

SSPSTAT
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MSSPSTATUSREGISTER

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SSPCON1
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MSSPCONTROL REGISTER1

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EnablingSPI Enabling SPI

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To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. Pins t b h Pi to behave as the seriall port function: th i t f ti
SDI is automatically controlled by the SPI module SDO must have TRISC<7> bit cleared SCK (Master mode) must have TRISB<1> bit cleared SCK (Slave mode) must have TRISB<1> bit set SS must have TRISA<5> bit set

TypicalConnection Typical Connection

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SPIMODEWAVEFORM
(MASTER)
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SPIFunctionLibrary SPI Function Library

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PART 3 PART3
I2C

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Inter-Integrated Circuit (I2C)

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Two advantages I2C:

1.

I2C needs only two wires (SCL and SDA) SDA). I2C supports multi-master multi master.

2. 2

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Data Transmission
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I2C is Half-Duplex data transmission transmission. Data is transmitted with the MSB first first. The Th I2C bus is designed for the three-data t b i d i d f th th d t transmission speed: i i d
Low Speed: The data can be transmitted from 0 to 100 kbps. Fast S Speed: The data can be transmitted up to 400 kbps. High-Speed: The data can be transmitted up to 3.4 Mbps.

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I2C in PIC18F4550
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The I2C module implements the standard mode specifications as well as 7-bit and 10-bit addressing. 7 bit 10 bit Two pins are used for data transfer:
Serial clock (SCL) RB1/SCL Serial data (SDA) RB0/SDA

The Th user must configure th t fi these pins as inputs through the i i t th h th TRISB<1:0> bits.

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I2C Registers in PIC18F4520

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The MSSP module has six registers for I2C operation. These are:
MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer Register (SSPBUF) MSSP Shift Register (SSPSR) Not directly accessible MSSP Address Register (SSPADD)

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I2C MODE BLOCK DIAGRAM

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Note: SLAVE MODE SSPADD register holds the slave device address. MASTER MODE The lower seven bits of SSPADD act as the Baud Rate Generator reload value. l

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Operation
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The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). (SSPCON 5 ). The SSPCON1 register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected:
I2C Master mode clock = FOSC/(4 x (SSPADD + 1)) mode, 1)). I2C Slave mode (7-bit address). I2C Slave mode (10 bit address) (10-bit address). I2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled. I2C Slave mode (10 bit address) with Start and Stop bit interrupts enabled (10-bit enabled. I2C Firmware Controlled Master mode, slave is Idle.
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Operation
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Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are open drain, programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins pins.

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I2C DATA TRANSFER

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I2C DATA TRANSFER

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Master Mode
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Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are open drain, programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins pins.

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Configuration
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1. 2. 3. 4. 5. 5 6. 7.

SSPSTAT = ?; SSPADD = ? ?; //Baud Rate //B d R t SSPCON1 = ?; SSPCON2 = ?; SSPCON1bits.SSPEN= SSPCON1bits SSPEN= 1; TRISCbits.TRISC3 = 1; TRISCbits.TRISC4 = 1;

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I2CFunctionLibrary I2C Function Library

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