Adv Digital Design

By Dr. Shoab Ahmed Khan

shoab@avaz.com

Fall 2002

Sequencing and Control

Engineering Education Trust Center for Advanced Studies in Engineering 5-A Constitution Avenue, Software Technology Park. Islamabad, Pakistan.

The art of algorithm to architecture mapping

Adv. Digital Design By Dr. Shoab A. Khan

Register-based Controller with Nested Subroutine Capability

TOP OF STACK POINTER up En
SYSCLK

SUBR OUTINE RETURN A DDRESS REGISTER

uPC REGISTER

FULL ADDER Incrementer n bits

MICROPROGRAM MEMORY 0 1N. 2A 3

words

Second Address Register

ADDRESS

0 cond0

0 1 COND 2 MUX

DATA out
POLARITY NEXT ADDRESS LOGIC NEXT ADDRESS POLARITY SELECT BRANCH BRANCH COND OTHER ADDRESS SELECT

cond1 3 1

To Architecture

Adv. Digital Design By Dr. Shoab A. Khan

Subroutine return address stack

From PC

4 levels of nesting 1 stack

Incremented
Enable

10

Return Address Stack

Decoder

Stack Pointer Reg.

Current
2

/
10

Push SP2

Pop SP2

To Next Address Generation Unit

Incremented Current

Stack Pointer
reset clk

Adv. Digital Design By Dr. Shoab A. Khan

Hardware Loop Machine

Push SP1

ARn 10

Down Counter 10

\ \

4 levels of nesting
Enable

From PC 10/

Start Address Stack

Push SP1

From Microcode End Address 10/ Stack

Enable

10/
PushSP1 or load SA Enable

Loop Count Stack

3 stacks
incremented

Decoder
incremented

Decoder
incremented or Current

Decoder

ARn Current

Stack Pointer Reg.

Push SP1 PopSP1 or Loop End Flag

/
10

Current

Current Push SP1

2 PC

10

10

10

/ Stack Pointer /
2 reset clk

To Next Address Generation Unit

Current Incremented

Comparator

XOR 10 NOR

reset clk

Down Counter
Dec load

10

Zero Check Logic

NOR

To Next Address Generation Unit & To Loop Count Stack

AND
load Start Address

AND
To Stack Pointer Loop End Flag

reset

clk

reset

clk

Adv. Digital Design By Dr. Shoab A. Khan

/
\
10
To Down Counter

Counter, 10 bit
\
\

\ \ \

PushSP1 OR Loop End Flag

Rise Delay

Gate output transition to a 1 from another value

0, x or z t_rise

Adv. Digital Design By Dr. Shoab A. Khan

Fall Delay

Gate output transition to a 0 from another value

1, x or z

t_fall

Adv. Digital Design By Dr. Shoab A. Khan

Turnoff Delay

Gate output transition to the high impedance value (z) from another value

Adv. Digital Design By Dr. Shoab A. Khan

$setup and $hold check clock data Setup hold time time

The setup time is the minimum time the data must arrive before the active clock edge. The hold time is the minimum time the data cannot change after active clock edge

Adv. Digital Design By Dr. Shoab A. Khan

Mix/Typ/Max Values

The delay values ranges between min and max because of the IC process fabrication variation Min val
The min value is the minimum delay value that the designer expects the gate to have

Typ val
The typical delay value the desingner expects the gate to have.

Max value
The max delay value the designer expects the gate to have.
Adv. Digital Design By Dr. Shoab A. Khan

Types of Delays: Distributed Delay

Delays are specified on a per element basis module M(out, a, b, c, d); output out; M e a input a, b, c, d; #5 b assign #5 e = a & b; #4 assign #7 f = c & d; c f assign #4 out = e & f; #7 d endmodule

out

Adv. Digital Design By Dr. Shoab A. Khan

Lumped Delay Delay is specified on per module basis module M(out, a, b, c, d); output out; input a, b, c, d; assign e = a & b; assign f = c & d; assign #11 out = e & f; endmodule

a b c d

e out f

Adv. Digital Design By Dr. Shoab A. Khan

Pin-to-pin Delays
Delay are assigned individually from each input to each output

aM b c d

e out f

Path a-e-out, delay = 9 Path b-e-out, delay = 9 Path c-f-out, delay = 11 Path d-f-out, delay = 11
Adv. Digital Design By Dr. Shoab A. Khan

Pin-to-pin Delays- Path Delays

Delay are assigned individually from each input to each output
A delay between a source pin and a destination pin of a module is called a module path delay Keyword specify and endspecify is used for assigning path delays

module M(out, a, b, c, d); output out; input a, b, c, d; specify (a => out) = 9; (b => out) = 9; (c => out) = 11; (d => out) = 11; endspcify assign e = a & b; assign f = c & d; assign #11 out = e & f; endmodule

Adv. Digital Design By Dr. Shoab A. Khan

Inside specify block: Parallel Connection

(<source_field> => <destination_field>) = <delay_value>; bit to bit connection, a and out are single-bit
(a => out) = 9

Vector connection, a[3:0], out[3:0]

(a => out) = 9 the above statement is the shorthand notation for (a[0] => out) = 9 (a[1] => out) = 9 0 0 (a[2] => out) = 9 1 1 (a[3] => out) = 9 Source Field

Destination 2 Field

Adv. Digital Design By Dr. Shoab A. Khan

Inside specify block: Full Connection

(<source_field> *> <destination_field>) = <delay_value>; Each bit in the source filed connects to every bit in the destination field

module M(out, a, b, c, d); output out; input a, b, c, d; specify (a, b *> out) = 9; (c, d *> out) = 11; 0 endspcify 1 assign e = a & b; Source assign f = c & d; Field 2 assign out = e & f; endmodule
Adv. Digital Design By Dr. Shoab A. Khan

0 1 Destination 2 Field

specparam statement

Special parameters is used inside a specify block specify specparam d_to_q = 9; specparam clk_to_q = 11; (d => q) = d_to_q

Adv. Digital Design By Dr. Shoab A. Khan

Rise, fall and turn-off delays

Pin-to-pin timing can be expressed in more detail by specifying rise, fall and turn-off delay values. specparam t_rise = 9, t_fall=13; (clk => q) = (t_rise, t_fall); specparam t_rise = 9, t_fall=13, t_turnoff=11; (clk => q) = (t_rise, t_fall, t_turnoff);

Adv. Digital Design By Dr. Shoab A. Khan

Min, max and typical delays

Min, max and typical values can also be specified for pin-to-pin delays. Specparam t_rise=8:9:10, t_fall=12:13:14, t_turnoff=10:11:12; (Clk => q) = (t_rise, t_fall, t_turnoff);

Adv. Digital Design By Dr. Shoab A. Khan

An example of Min, max and typical delays Module VAND(out, in0, in1); input in0; input in1; output out; //timing information Specify (in0 => out) = (0.26:0.513:0.955,0.255:0.503:0.936); (in1 => out) = (0.26:0.513:0.955,0.255:0.503:0.936); endspecify and(out,in0,in1); endmodule

Adv. Digital Design By Dr. Shoab A. Khan

FPGA

Most common is a lookup table (LUT) containing storage cells used to implement a small logic function Each storage cell holds a 0 or 1 LUT size is determined by the number of inputs LUT with n inputs can implement any logic function of n variables

Adv. Digital Design By Dr. Shoab A. Khan

Logic block

Interconnection switches I/O block

I/O block

I/O block

I/O block

Structure of an FPGA
Adv. Digital Design By Dr. Shoab A. Khan

x1 0/1 0/1 0/1 0/1 x2 (a) Circuit for a two-input LUT f x1 x2 0 0 1 1 0 1 0 1 f1 1 0 0 1

(b) f 1 = x1 x2 + x1 x2

x1 1 0 0 1 x2 (c) Storage cell contents in the LUT f1

Adv. Digital Design By Dr. Shoab A. Khan

x1 x2 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 x3 f

Figure 3.37 A three-input LUT Adv. Digital Design By Dr. Shoab A. Khan

Example

How would you implement f = abc + ac in a LUT abc 000 001 010 011 100 101 110 111 f 0 0 1 0 0 1 0 1
a b 0 0 1 0 0 1 0 1 c
Adv. Digital Design By Dr. Shoab A. Khan

Often a DFF is included in the logic block to store the value of the D Input
Select

Out In1 In2 In3 Clock LUT Flip-flop D Q

Inclusion of a flip-flop with a LUT

Adv. Digital Design By Dr. Shoab A. Khan