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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO.

2, MARCH 1998

273

A New Power-Factor-Correction Circuit for Electronic Ballasts with Series-Load Resonant Inverter
Chin S. Moo, Ying C. Chuang, Ching R. Lee
Abstract This paper presents an efcient, small-sized, and cost-effective power-factor-correction (PFC) scheme for high-frequency series-resonant electronic ballasts. The proposed scheme introduces additional small energy tanks processing partial power and thus can perform the function of input current shaping. Theoretical and experimental results prove that the electronic ballast incorporating with only few reactive components can achieve nearly unity power factor and very low harmonic distortion. Index Terms Electronic ballast, harmonic, power factor, power-factor correction, resonant inverter.

I. INTRODUCTION

IGH-FREQUENCY electronic ballasts, instead of electromagnetic ballasts, are increasingly used to drive uorescent lamps for improving the light performance [1], [2]. An electronic ballast, when extracting power from the ac-line source, needs a diode rectier bridge with a bulk capacitor to provide a smooth dc-link voltage for the high-frequency inverter stage. Such a rectier circuit inevitably draws a high-peak input current, which is notoriously of very poor power factor and serious harmonic distortion. Therefore, with growing concern on the input power quality, a lter circuit for power-factor correction (PFC) and harmonic reduction becomes a requirement in the design of electronic ballasts. Many ltering methods have been employed for improving input power factor and reducing line current harmonics [3][7]. Among which, the passive lter designed for specied input power is the most simple one. It can shape the input line current into an acceptable waveform merely by adding few inductors and capacitors in front of or behind the rectier bridge [4], [5]. However, these inductors and capacitors are operated at the line frequency and hence are large both in value and size. Therefore, when a power factor greater than 0.9 is required, the use of the overweighted and oversized reactive components makes this method impracticable. On the other hand, by using sophisticated control techniques, the active lter with relatively small circuit components can achieve nearly unity power factor and very low harmonic distortion [6], [7]. These assets, however, are at the expense
Manuscript received July 18, 1996; revised May 1, 1997. Recommended by Associate Editor, F. D. Tan. The authors are with the Power Electronics Laboratory, Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, R.O.C. (e-mail: mooxx@ee.nsysu.edu.tw). Publisher Item Identier S 0885-8993(98)01951-6.

of higher circuit complexity and lower overall efciency resulting in higher product cost. In the attempt to overcome this disadvantage, many efforts have been made to search a less expensive ltering method for the electronic ballast to offer a competitive price in the consumer market [8][13]. This paper presents a relatively simple PFC scheme for the electronic ballast with the series resonant inverter, which is the most economical circuit topology commonly used for driving low power uorescent lamps [14], [15]. In the proposed approach, a passive network is interposed between the rectier and the inverter for shaping the input current waveform. With the added circuit, the electronic ballast can achieve high power factor without any additional power switch and control circuitry. II. CIRCUIT DESCRIPTION The typical half-bridge series-resonant electronic ballast with the proposed lter circuit is shown in Fig. 1. The inverter consists of two controllable power switches. Each switch is composed of a transistor and an antiparallel diode and thus can carry either positive current or negative current. The uorescent lamp in series with an inductor and a capacitor forms is connected in the resonant load circuit. The capacitor parallel with the lamp for the starting purpose. The two power switches are alternately turned on and off at a frequency higher than 20 kHz. The inverter is recommended to operate with inductive load [16], [17]. Therefore, the switching frequency of the inverter should be above the resonant frequency of the load functions as a large energy tank circuit. The bulk capacitor providing a smooth dc voltage source for the inverter. This large energy tank draws one narrow peaked current every half line-cycle resulting in low power factor and high harmonic distortion. As shown in Fig. 1, the added PFC circuit enclosed by dash lines consists of an inductor, two capacitors, and a pair of energy transfer diodes. The inductor acts like an energy conveyor owing through the input current. It also performs boost function resulting in a step-up dc-link voltage. The capacitors and serve as two small energy tanks processing a part of power. These two additional energy tanks are charged and discharged in a high-frequency manner and hence could be small in size. The charging and discharging functions of the high-frequency capacitors make use of the inverter switches. The two energy transfer diodes and conduct the inductor current into the large energy tank

08858993/98$10.00 1998 IEEE

274

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 2, MARCH 1998

TABLE I CONDUCTING SWITCHES FOR EACH INTERVAL AT

!s t

= =8

TABLE II CONDUCTING SWITCHES FOR EACH INTERVAL AT Fig. 1. Series-resonant electronic ballast with the proposed PFC circuit.

!s t = =2

Fig. 2. Simplied equivalent circuit of Fig. 1.

During the turn-on period of the transistor , a resonant current ows from the line source through the boost inductor and transistor charging (3)

or into the load. The PFC circuit arranged in this way can draw current from the ac line in every switching cycle of the inverter. As a result, the input line current becomes a high-frequency pulsating waveform with a sinusoidal envelope which is in phase with the input voltage. The high-frequency contents in the input current can be removed simply by a small lter at input terminal. Consequently, a nearly unity power factor can be obtained. III. CURRENT-SHAPING OPERATION In order to facilitate the analysis of the current-shaping operation, the electronic ballast circuit in Fig. 1 can be simplied to a schematic circuit as shown in Fig. 2. The rectier bridge and is the rectied line is represented by the diode voltage (1) where is the voltage amplitude and is the frequency of the line source. For a well-designed electronic ballast, as stated in [16] and [17], the resonant circuit represents an inductive load and can be equivalent to a sinusoidal current source with the inverter switching frequency (2) where is the amplitude of the load current. In fact, the inverter frequency is relatively high in comparison with the line frequency so that the variation at the input line voltage can be neglected during one switching cycle.

where and

and and

are the initial conditions with respect to is the resonant frequency (4)

The voltage across

is

(5) At the low voltages of the rectied line source, the peak is less than the dc-link voltage . The inductor values of current resonates over one-half cycle and stays at zero. Under such a condition, the inductor current is discontinuous and hence the input current. At the high voltages of , the inductor current tends to be continuous and can reach . Beyond this point, turns on and is clamped at . Since is greater than the peak value of , the inductor current charges the dc-link capacitor and decreases linearly (6) Figs. 3 and 4 illustrate the simulated results at a low voltage and at the peak of the rectied line source of ), respectively. The conducting switches in each ( time interval are listed in Tables I and II. The simulations are based on the circuit parameters given by the following design example. As shown in Fig. 3, the maximum voltage of is less than , and the inductor current is discontinuous. The

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275

Fig. 3. Calculated waveforms at

!s t

= =8.

Fig. 4. Calculated waveforms at

!s t = =2.

waveforms are depicted from the instant at which a positive load current starts to ow. During Interval I, the bottom transistor is turned on and carries both the load current and the inductor current. The capacitor is charged by this inductor current and the voltage of is clamped at zero. At the end of this time interval, the inductor current resonates to zero, and the voltage across increases to its maximum. At turn off. During this instant, the rectier and the diode Interval II, the load current ows through and the inductor current stays at zero. At the beginning of interval III, is switched off. Then, the energy stored in is transferred declines. When the rectied line voltage to the load and becomes greater than the rectier diodes are forward biased and the line source starts to charge and through the inductor. This charging current, however, is always less is discharged. Therefore, than the load current by which decreases continuously during Interval IV and eventually falls to zero. Then, turns on and carries the freewheeling current which is equal to the difference between the load current and the inductor current. At the end of interval V, the freewheeling current comes to zero and the transistor is turned on. Since the power switches are operated symmetrically and is equal to , the operation of the next half cycle is similar. , the inductor current is continuAt the peak voltage of ous with very small ripple as shown in Fig. 4. During Interval I, is switched on. Prior to this time, has been charged up and clamped at . Since is very large as compared with , most of the inductor current ows through . Therefore, carries only the load current. At the beginning of Interval II, is switched off and the energy stored in is discharged

to the load. Meanwhile, is charged by the inductor current. At this operating voltage, the inductor current is at its peak, the voltage of increases rapidly. In this case, the sum of and may reach and then becomes forward biased. As stated above, the inductor current mostly ows through during Interval III and is continuously discharge by the load current. When is completely discharged, turns on and carries the freewheeling current. Since the discharging period is much longer, only a short duration of freewheeling is found and the freewheeling current is smaller as compared . At the moment with the operation at low voltages of is switched on when the freewheeling comes to an end, and the next half cycle ensues. Fig. 5 shows the calculated input current waveform over half a cycle of the line source. In this gure, the inverter frequency is made low and the high-frequency contents are not ltered for the purpose of illustration. It can be found that the input current is discontinuous over the lower range of the ac-line voltage while becoming continuous over the higher voltage range. The pulsating current dithers around a sinusoidal fundamental wave, which is in phase with the input voltage. Removing the high-frequency contents, a nearly sinusoidal input current can be obtained. IV. DESIGN CONSIDERATION In order to achieve unity power factor, the average inductor current should be made to follow its fundamental wave which is in phase with input line voltage. The fundamental current can be determined by the input power and the voltage speci-

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 2, MARCH 1998

Fig. 5. Calculated input current waveform.

cations. Then, the optimum capacitance can be calculated (7) where and denote the specied input power and voltage, is the inverter switching period. respectively and This optimum capacitance is chosen to sustain the power factor close to unity. Then, the switch-off angle can be determined accordingly. However, it should be reminded that the high-frequency capacitor can not be too large since they has to be completely deenergized before the transistor on the same side has been turned on. Otherwise, the residual charge would be short circuited at the switching on of the transistor. This brings about a current spike that may damage the circuit components. Since the maximum voltage of the high-frequency capacitor is limited to the dc-link voltage, the maximum energy stored in the capacitor is (8) The capacitor energy begins to discharge at the instant of switching off the opposite transistor. The discharging rate is proportional to the difference between the load current and the boost inductor current. The load current is with constant amplitude while the average current of the boost inductor substantially follows the input line voltage. This implies that the lowest discharging rate happens at the peak of the input line current. In practice, as illustrated in Fig. 4, the boost inductor current around the peak point is with a very small ripple so that can be assumed to be a constant. Fig. 6 illustrates that the available discharging interval is approximately from to . Within this interval, the load current has risen up and becomes greater than the inductor current. In other words, the transistor can only be turned off after , but should be turned on before . This gure reveals that the circuit can work properly only when the amplitude of the load current is greater than that of the input current. For the specied input power and the load current, the maximum capacitance can be calculated (9)

Fig. 6. Relationship between io (t) and

iL (t) at !s t = =2.

The selected capacitance is restricted by this maximum value if it is less than the optimum capacitance calculated from (7). Under this condition, the power factor would be deteriorated. As described above, the boost inductor also serves as a current smoothing reactor. A larger inductor can make a smaller ripple in the input current. However, the inductance should be small enough so as to ensure that the half-cycle resonance can be completed and the capacitor voltage can be charged to its maximum value before the opposite transistor has been switched off. Therefore, once the capacitance and the switching-off angle are given, the inductance can then be obtained (10) On the other hand, the switching-off angle may be predetermined in some practical designs. In this case, the design procedure can be carried out inversely. V. DESIGN EXAMPLE
AND

EXPERIMENT

An example of the PFC circuit is designed for the series resonant electronic ballast loaded with a 36-W compact uorescent lamp. The ballast is supplied by the line source of 220 V, 60 Hz. The inverter stage of the ballast is designed to operate at a switching frequency of 38 kHz under a dc-link voltage of 320 V. For easy implementation, the two power switches of the inverter are self-excited and turned off at the positive and negative peaks of the load current, respectively. Under this operation, the maximum capacitance of the small energy tanks is limited to 7.86 nF, while the optimum value is 4.89 nF. Therefore, the two parameters of the PFC circuit are chosen as follows: nF mH. Fig. 7 shows two measured waveforms of boost inductor currents and high-frequency capacitor voltages corresponding to line voltage angles of and , respectively. As compared with those in Figs. 3 and 4, these waveforms agree with the simulated results very well. Fig. 8 shows the current waveforms of the transistor and its antiparallel diode along

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The measured power factor is greater than 0.99 and the total harmonic distortion is lower than 8%. VI. CONCLUSIONS A new PFC circuit designed for the high-frequency halfbridge series-resonant electronic ballast has been presented. The proposed approach employs additional small energy tanks for shaping the input current into the desired sinusoidal waveform by processing a part of power. The high-frequency operation is described for designing circuit parameters. Experimental results prove that nearly unity power factor can be achieved by properly choosing circuit parameters. The PFC circuit involves virtually no loss since it consists of only reactive components and the energy transfer diodes are turned on and off softly. The added inductors and capacitors are operated at the high frequency and thus can maintain the attributes of small volume and light weight as those in the active lters. More importantly, preventing the use of additional active power switches and sophisticated control circuit, the electronic ballasts incorporating the proposed PFC scheme are obviously cost effective. REFERENCES
[1] E. E. Hammer, High frequency characteristics of uorescent lamps up to 500 kHz, J. Illum. Eng. Soc., pp. 5261, 1987. [2] E. E. Hammer and T. K. McGowan, Characteristics of various F40 uorescent systems at 60 Hz and high frequency, IEEE Trans. Ind. Applicat., vol. 21, no. 1, pp. 1116, 1985. [3] J. Spangler and A. K. Behera, Power factor correction techniques used for uorescent lamp ballast, in Proc. IEEE-IAS Annu. Meet., 1991, pp. 18361841. [4] S. B. Dewan, Optimum input and output lter for a single-phase rectier power supply, IEEE Trans. Ind. Applicat., vol. 17, no. 3, pp. 282288, 1981. [5] F. C. Schwarz, A time-domain analysis of the power factor for a rectier lter system with over- and subcritical inductance, IEEE Trans. Ind. Electron., vol. 20, no. 2, pp. 6168, 1973. [6] M. Kazerani, P. D. Ziogas, and G. Joos, A novel active current waveshaping technique for solid-state input power factor conditioners, IEEE Trans. Ind. Electron., vol. 38, no. 1, pp. 7278, 1991. [7] J. C. Salmon, Techniques for minimizing the input current distortion of current-controlled single-phase boost rectiers, IEEE Trans. Power Electron., vol. 8, no. 4, pp. 509520, 1993. [8] J. L. Freitas Vieira, M. A. Co, and L. D. Zorzal, High power factor electronic ballast based on a single power processing stage, in IEEE PESC95, 1995, pp. 687693. [9] M. Madigan, R. Erickson, and E. Ismail, Integrated high quality rectierregulator, in IEEE PESC92, 1992, pp. 10431051. [10] H. Matsuo, N. Aoike, F. Kurokawa, and A. Hisako, A new combined voltageresonant inverter with high power factor and low distortion factor, in IEEE PESC94, pp. 331335. [11] C. S. Moo, Y. C. Chang, and J. C. Lee, A new dynamic lter for the electronic ballast with the parallel-load resonant inverter, in Proc. IEEE-IAS Annu. Meet., 1995, pp. 25972601. [12] C. Licitra, L. Malesani, G. Spiazzi, P. Tenti, and A. Testa, Single-ended soft-switching electronic ballast with unity power factor, IEEE Trans. Ind. Applicat., vol. 29, no. 2, pp. 382387, 1993. [13] E. Deng and S. Cuk, Single stage, high power factor, lamp ballast, in IEEE APEC94, pp. 441449. [14] R. King, A normalized model for the half-bridge series resonant converter, IEEE Trans. Aerosp. Electron. Syst., pp. 190198, Mar. 1981. [15] W. J. Gu and K. Harada, Novel self-excited PWM converters with zerovoltage-switched resonant transition using a saturable core, in IEEE APEC92, pp. 5865. [16] M. K. Kazimierczuk, Class D voltage-switching MOSFET power amplier, in IEEE Proc. B, Electron. Power Appl., Nov. 1991, pp. 285296. [17] M. K. Kazimierczuk and W. Szaraniec, Electronic ballast for uorescent lamps, IEEE Trans. Power Electron., vol. 8, no. 4, pp. 386395, 1993.

(a)

(b)

Fig. 7. Measured waveforms of inductor current and capacitor voltage at (a) !s t =8 and (b) !s t = =2.

(a)

(b)

Fig. 8. Current waveforms of transistor, antiparallel diode, and load current at (a) !s t = =8 and (b) !s t = =2.

Fig. 9. Experimental waveforms of input line voltage and current.

with the inverter load currents. In Fig. 8(a), it is found that the transistor carries a current slightly larger than that without PFC circuit. This is because that the transistor has been turned on to ow a part of charging current before the load current becomes positive. A larger transistor current results in more conduction , the transistor carries loss. However, at a high voltage of only the load current as shown in Fig. 8(b). On the other hand, the freewheeling currents become much smaller for both cases. Besides, the energy stored in the high-frequency capacitors discharge directly into the load, but not through the power switches. This makes a merit of reducing the losses on the switches. The measured overall efciency of the electronic ballast is 93.0%. It is only slightly less than that of the original design (93.8%). The crest factor of the lamp current is 1.38, which is the same as the original design without the PFC circuit. This implies that the added PFC circuit does not affect the output characteristics of the inverter stage. The measured input line current of the electronic ballast is shown in Fig. 9. The high-frequency pulsating currents have been ltered out by a small capacitor at the input terminal.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 2, MARCH 1998

Chin S. Moo was born in 1953. He received the B.S. degree in electrical engineering in 1976, the M.S. degree in 1984, and the Ph.D. degree in 1990, all from National Chen-Kung University, Taiwan, R.O.C. He worked for eight years as an Electrical Engineer with South-East Cement Co., Kaohsiung, Taiwan. Currently, he is an Associate Professor of the Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan. His research interests include power electronic converters and their applications.

Ching R. Lee was born in Kimmen, Taiwan, R.O.C., on June 6, 1964. He received the B.S.E.E. and M.S.E.E. degrees from the National Sun YatSen University, Kaohsiung, Taiwan, in 1986 and 1991, respectively, and is currently working toward the Ph.D. degree at the same university. His main research interests include PFC and electronic ballasts.

Ying C. Chuang was born in Kaohsiung, Taiwan, R.O.C., in 1962. He received the B.S. degree in electrical engineering in 1988 from National Taiwan Institute of Technology, Taipei, Taiwan, and the M.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1990. He is currently working towards the Ph.D. degree at National Sun Yat-Sen University, Kaohsiung, Taiwan. His elds of interests are electronic ballasts and power electronic drive systems.

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