Networking aligned to CISCO certification A SEMINAR REPORT Submitted In partial fulfillment For the award of the degree of Bachelor

of Technology In Department Of Electronics and Communication Engineering

Submitted To: Department of Electronics and Communication

Submitted By: Kamal Deo Prasad Enroll.no.-2009/00660 Roll No.-7-EC-37

Department of Electronics and Communication Engineering Jaipur National University,Jaipur. October 2012

ACKNOWLEDGEMENT

I would like to express my sincere gratitude to Ms. Shruti Sharma Training Officer of HP EDUCATIONAL SERVIES,JAIPUR for their constant inspiration and support during the problems in Training. I am thankful for their valuable suggestions and technical helps.

I am also thankful to Prof. R. L. Dua (H.O.D, Department of Electronics and Communication),Mr. Naresh Soni, Ms. Nisad Anjum, Mr. Sunil Jorewal (Lecturer,Electronics and Communication) and ,Jaipur National University, Jaipur who have contributed in same manner to make the training a success.

Kamal Deo Prasad

TABLE OF CONTENT

TOPIC
1.

PAGE NO. 1-5 1 2 2-5 6-

VLSI Design Overview

1.1 Design Overview 1.2 Design Flow Using HDL 1.3 Steps in VLSI Design

2.

Introduction to VHDL 23
2.1 Basic Language Element

6-

2.2 Describing a Design

10-14

2.3 Architecture Body

14-23

3. Introduction to Synthesis 25 4. VHDL: A Logical Synthesis Approach 5. Design Units 6. Simulation Cycle

24-

26 27 28

7. Combinational Circuit Design 38

7.1 Adder

29-

29-

33
7.2 Decoder

34-

35
7.3 Multiplexer

36-

38 8. Sequential Circuit Design 46 9. Bibliography 47 39-

LIST OF FIGURES

Figure Name

Page No.

Figure.1.1 Design Flow using HDL Figure1.2 Sequential Control Figure 2.1 Structure of an Entity Figure 2.2 Dataflow Modeling Figure 2.3 Structural Modeling Figure3.1 Synthesis Flow Figure4.1 VHDL Design Flow Figure 6.1 Simulation Cycle Figure7.1 Half Adder (Truth Table, Symbol, Equations, Circuit) Figure7.2 Full Adder (Truth Table, Equations, Circuit) Figure7.3 Full adder:(a)truth table;(b)circuit;(c)logic symbol Figure7.4 Ripple Carry Adder Figure7.5A 3-to-decoder:(a)truth table;(b)circuit;(c)logic symbol Figure7.6A 3-to-8 decoder implemented with seven 1-to-2 decoder Figure7.7A 2-to-1 multiplexer:(a)truth table;(b)circuit ;(c)logic symbol Figure 8.1 Block Diagram of Sequential Circuit Figure8.2 Simulation trace for the positive-edge-triggered D flip-flop 14

2 3 14

19 22 24 26 29 30 31 32 33 34 36

44 45

Figure8.3A 4-bit serial-to-parallel shift register logic symbol (a)circuit;(b)operation table Figure8.4 Sample simulation trace for the

46