Software for Embedded Systems

CS424
KCS Murti, Chandra.kavuri@gmail.com

Embedded platform Architecture

Embedded Platform architecture

Outline
Constituent components that make up on ES How are they physically connected? Software/processing view of the components. Expand the capabilities of the SOC device through interfaces

History

VME bus

Multi bus

History

System on Chip(SoC)

SoC expansion

Basic system architecture

System with Core-2 Duo processor

System with Core i7 processor

System with Atom processor

The Front Side Bus (FSB)

Uses source synchronous clocking. data is quad pumped (ex) 1333 Mega Transfers per second (MT/s) based on a 333 MHz base clock Maintains cache coherency Bus supports split transactions

Memory controller (MCH)

CPU connects to the MCH through the FSB FSB unit in the MCH is responsible for the CPU cache coherency 64 bit data transfers (width of L2 cache) DMI(Direct Media Interface ):4 lanes supporting 2.5 GT/s PCI Express interface: 16 lanes @2.5 Gb/s per lane

IO controller Hub (ICH)

Extensive I/O support. Support for legacy peripherals. Power sequencing ACPI power management Fan speed control Reset timing. Integrates numerous support peripherals Real Time Clock (RTC) High Precision Event Timers Advanced Programmable Interrupt Controller (APIC)

Modern IO interfaces
ICH acts a bridge PCI interface (33 Mhz) PCI Express (2.g gb/s per lane differential ) Serial ATA (1.5Gb/s ) Integrated Drive Electronics (IDE): control hard drives, CDs Universal Serial Bus (USB): (480 Mb/s) General Purpose I/O (GPIO): system customization, interrupts, events System Management Bus (SMB): Compatible with I2C bus. Connects to SMBUS slaves. Serial Peripheral Interface (SPI): interface to BIOS flash devices. (defacto standard) Low Pin Count Interface (LPC): replaces the ISA bus. Interface for low speed controllers like floppys, serial ports etc.

IO controller Hub

System Controller Hub (SCH)

Integrates most of the MCH and ICH functionality Optimized for low power applications Advanced power management capabilities Major differences: SDIO Secure Digital Input / Output Usually used for media cards. MMC Multi-Media Card Usually used for media cards. SDVO Serial Digital Video Out display interface. LVDS Low Voltage Digital Signaling flat panel display interface.

Processor
Normally 32 bit RISC/CISC instruction set architectures (ISA) Scalar/Super scalar Sustain execution of more than one instruction per clock cycle Trend for ES is super scalar Supporting hardware: Memory sub system Interrupt controller Timers IO access

Intel Atom Processor

Low power, Low cost and low performance processors compared to regular core-duo, i3/i5/i7... For example: Z510P (512K Cache, 1.10 GHz, 400 MHz FSB) One core, two threads 32-bit x86 with MMX, SSE, SSE2, SSE3 and SSSE3 extensions Many other processors of Atom series

System memory map

List of physical addresses of all resources IA-32 have distinct memory and IO spaces System and MMIO address ranges TOLM: Top of local memory MMIO divided into sub regions

Interrupt controller
Gathers all hardware interrupt events and presents to the processor.

Interrupt ack and priority schemes

Legacy interrupt controller

Cascaded PICs Master/slave behavior High latency(--)

APIC
Advanced PIC Local APIC for each hardware thread Local APIC is integral part of processor. Receives interrupts from Local IO devices Externally connected IO devices Inter processor interrupts (IPI) Timer generated interrupts. Thermal sensor interrupts APIC internal error interrupts

Local APIC
Registers memory mapped to 4KB region Must be uncacheble LVT: associates int source to a vector. Accepts interrupts from PCIe devices IO APIC collects interrupts and routes to Local APIC

Interrupt controller hierarchy

Timers
Timer infrastructure Legacy 8253/54 timer block High precision Event timers(64 bit) and mapped to processor address space. Local APIC interrupt timer Watch dog timer

DRAM controller

Pipelining DRAM access

SRAM controllers
Density is far lower than DRAM Read/write access is faster

Non volatile storage

Most common is Flash memory NOR flash and NAND flash NAND flash has higher density

NAND flash

Device interface
Connect to an external application-specific I/O device Capabilities: Transaction mapping Allow mapping of address space from the processor to the device Inbound transactions: Allow the external devices to read and write resources in the SOC Interrupts: Ability to route interrupts from the device to the processor. Physical standard: allows the system to be expanded with many different capabilities.

Evolution of PC buses

PCI express
Introduced in 2004 Compatibility with the PCI addressing model . Transaction: packet-based, splittransaction protocol Link layer: sequencing and CRC. Physical: dual simplex channel Lane: one Tx and Rx pair Provides 250MB/s to shared device.

Physical layer
consists of two low-voltage ACcoupled differential pairs of signals 2.5 Gb/s/direction (likely to reach 10 Gbps/direction) Links two PCI Express agents. linearly scaled by adding signal pairs to form multiple lanes physical layer provides 1-32 lane widths splits the incoming data packets among these lanes The expansion boards and the lane widths should match. Role: Encoding(8b/10b), decoding Reset, initialization Configuration: speed, lane width, Lane mapping

DataLink layer
Responsible for data integrity Adds a sequence number and a CRC Packets are initiated at the transaction layer Credit-based, flow-control Retries a packet that was signaled as corrupted

Transaction layer
Receives read and write requests from the software layer Creates request packets All requests are implemented as split transactions Receives response packets from the link layer. Packet has attributes (viz): no-snoop, relaxed ordering, and priority Provides four address spaces three PCI address spaces (memory, I/O, and configuration) and message space Message signaled interrupt (MSI): Uses a message space to accept signals like interrupts, powermanagement requests, and resets etc. virtual wire concept Avoids sideband signals

Software layer
Initialization OS can discover all of the add-in hardware devices present and then allocate system resources. Programmability of I/O devices Run time Load-store, shared-memory model

PCI Express 8

PCI Express 16

Graphics board with PCI X16 I/F

PCI physical hierarchy

Evolved from a 32-bit parallel bus to a high-speed lower-pin-count serial bus. PCI Express (PCIe) is the third generation of the PCI standard. Capability to identify devices attached to a PCIe bus at runtime. System software can allocate resources to these devices.(bus enumeration) Transactions occur from Requester to Completer

Memory read CPU to Endpoint

PCI configuration header

Each device must have a base configuration header. Allows the system software to identify the device type and to assign memory and interrupts PCI device can read and write payloads (bus mastering) Uses circular buffers software sets up the descriptor with a pointer to the packet to be transmitted. tail pointer is updated in the device device reads the descriptor and finds a pointer to a packet to be transmitted

Universal Serial Bus (USB)

Low-voltage differential pair serial bus. Support real-time data transfer of video, audio, and data Tiered star physical topology. Two types of USB device, hubs and functions. Hubs provide additional fan-out for the bus. Functions provide a capability such as a mass storage or mouse. USB bus is hot-pluggable USB 2.0 speeds:1.5,12 and 480 MBPS. A system may act as controller or a device.

USB Protocol
Polled bus. Host controller initiates all data transfers. Endpoint is a logical channel identifier at the device. 15 endpoints within a device Pipe: A logical connection between a software element running on the host and an endpoint in a device.

USB-Data transfer types

Control Transfers used to configure the device. set up endpoints Bulk Data Transfers: used for large-scale transfer of data Interrupt Data Transfers: used for timely delivery of data . used for events such as mouse movements. Isochronous Data Transfers: transfers are allocated a guaranteed bandwidth and delivery latency constraint. used for real-time transfers of audio and video

Device descriptors
Vendor identification Device class Power management capabilities Endpoint description with configuration information

Programming Interface
UHCI Universal Host Controller Interface EHCI Extended Host Manages the transmission and reception of frames on the bus Controller Interface. Memory mapped registers: Capability registers capabilities of a host controller implementation. Operational registers interact with the operational state of the host controller

ECHI controller

EHCI controller
periodic transfers(isochronous and interrupt traffic) Asynchronous transfers (control and bulk transfers). periodic schedule is based on a timeoriented frame list that represents a sliding window of time of host controller work items

Software stack

Asynchronous transfers

Low performance Device interconnects

Low-speed, low-pin-count, low-performance interface types. Inter-Integrated Circuit (I2C) bus System Management Bus (SMB) Serial Peripheral Interface (SPI) bus Inter IC Sound (I2S) Universal Asynchronous Receiver/Transmitter (UART) High-Speed Serial

Inter-Integrated Circuit Bus

Multiple masters on the bus Two-wire bus consisting of a serial clock line (SCL) and a serial data line (SDA). Bidirectional and driven by open collector gates Low clock speeds States: Bus Not Busy Start Bus Transfer Data Transfer An acknowledge bit/cycle Stop Bus Transfer

Bluetooth
Low cost, low power, radio frequency technology for short-range communications Specs: 2.4GHz ISM band, Frequency hopping Gaussian shaped BFSK Modulation 723Kbps Data rate Operating range 10m~100m Power 0.1W (Active) Security -Link layer authentication and encryption RF: Carrier frequency: f=2402+k MHz k=0...78 Hopping rate: 1 hop/packet. 1600 hop/s for 1 slot packet Channel bandwidth: 1MHz(-20dB) 220KHz(-3dB) uses spread spectrum

Network topology
Point-to-point and point-tomultipoint connections Unit that initiates the connection acts as the master. 7 active slaves 256 parked slaves Several bluetooth devices sharing the same channel (hopping sequence) form a piconet. Every device has a unique 48-bit Bluetooth Device Address

MAC scheme
Each piconet has a unique frequency hopping sequence Hopping sequence is determined by the Bluetooth Device Address of the master. Channel is time divided to slots of length 625 S. Slave synchronizes its clock to the master whenever it receives a packet from the master. Two types of physical links: SCO (Synchronous Connection-Oriented) link and ACL (Asynchronous Connection-Less) link MAC:centralized TDD scheme totally controlled by the master unit

Link states

Connection establishment

References
Modern embedded Computing- Chap 4 Overview of Bluetooth Technology, Hongfeng Wang, penn state More on USB can be found from www.usb.org