SAN JOSE STATE UNIVERSITY College of Engineering

DEPARTMENT OF ELECTRICAL ENGINEERING

EE271

Tutorial on Using Synopsys Verilog Compiler Simulator

This tutorial basically describes how to use the Synopsys Verilog Compiler Simulator (vcs) to simulate a Verilog description of a design and how to display graphical waveforms. Apply for An Account If you already have an account on Cadence lab then use it. There is no need for having multiple accounts. If youre an engineering student or are taking an engineering class, you already have one UNIX account. You can (re)set your password by following the instruction at http://unix.engr.sjsu.edu Once you have already had an account, you can login to your account from workstations in room ENGR289 and room ENGR291. You can remote login to your account from you PC by using SSH remote Secure Shell together with the X-Server for Window software, the Exceed Hummingbird. The Synopsys VCS Simulator VCS (Verilog Compiler Simulator) is a tool suite from Synopsys. It includes VirSim, a graphical user interface to VCS for debugging and viewing waveforms. The methodology of debugging your project design involves three steps: 1) 2) 3) Compiling your verilog source code, Running the simulation, and Viewing the generated waveforms.

The VCS tools will allow you to combine these steps to debug your design interactively. VCS works by compiling your Verilog source code into object files, or translating them into C source files. VCS invokes a C compiler (cc, gcc, or egcs) to create an executable file that will simulate your design. This simulator can be executed on the command line, and can create a waveform file. Alternately, the design can be simulated interactively using VirSim, and the waveforms can be viewed as you step through the simulation. The rest of this document will give a brief overview of the tools and show you how to compile and simulate a down-counter example.

Initial Setup The VCS package is installed at /apps/synopsys/A-2008.09/bin. For convenience, set the following environment variables to your .cshrc file. Remember that anytime you changed/modified .cshrc file, you must source it (by command source .cshrc) or by logging-out and then logging back in. setenv MYPATH $PATH setenv SYNOPSYS /apps/synopsys setenv SNPSLMD $SYNOPSYS/SYNTH setenv VCS_ARCH_OVERRIDE linux setenv SYNOPSYS_SIM $SYNOPSYS/VCSMX_NEW setenv CLS_CSD_COMPATIBILITY_LOCKING NO setenv SKIP_CDS_DIALOG setenv VCS_HOME $SYNOPSYS_SIM set path=($path $SNPSLMD/linux/bin ) set path=($path $SYNOPSYS ) set path=($path $SYNOPSYS/SYNTH/linux/syn/bin ) source $SYNOPSYS_SIM/bin/environ.csh Create a directory where you want to do the tutorial and create the following three text files named count.v, test_count.v, and main_count.f in that directory. Listings of count.v and test_count.v are at the end of this tutorial. The main_count.f file has only 1 line as shown below: test_count.v count.v Compiling and Simulating in post-processing mode 1. Change to test directory that contains count.v, test_count.v, and main_count.f (in this tutorial it is tutorial) Compile the verilog source code by typing the following at the machine prompt /home/kr/kris9112/sanjay/EE271> vcs +v2k -f main_count.f The -f option means that the file specified (main_count.f) contains a list of command line options for vcs. In this case, the command-line options are just a list of file names and note that the testbench is listed first. The following command line would have the same effect: /home/kr/kris9112/sanjay/EE271> vcs +v2k test_count.v count.v

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/home/kr/kris9112/sanjay/EE271> vcs +v2k -f main_count.f

Chronologic VCS (TM) Version A-2008.09-SP2 -- Fri Oct 29 19:25:45 2010 Copyright (c) 1991-2008 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc.and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file 'count.v' Parsing design file 'test_count.v' Top Level Modules: test_count No TimeScale specified Starting vcs inline pass... 1 module and 0 UDP read. recompiling module test_count make: Warning: File `filelist' has modification time 2.9e+03 s in the future gcc -pipe -m32 -O -I/apps/synopsys/VCSMX_NEW/include rmapats.c if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv -melf_i386 -m32 5NrI_d.o 5NrIB_d.o wx0S_1_d.o rmapats_mop.o rmapats.o SIM_l.o /apps/synopsys/VCSMX_NEW/linux/lib/libvirsim.a /apps/synopsys/VCSMX_NEW/linux/lib/librterrorinf.so /apps/synopsys/VCSMX_NEW/linux/lib/libvcsnew.so /apps/synopsys/VCSMX_NEW/linux/lib/ctype-stubs_32.a -ldl -lc -lm -ldl /usr/bin/ld: warning: libstdc++.so.5, needed by /apps/synopsys/VCSMX_NEW/linux/lib/librterrorinf.so, may conflict with libstdc++.so.6 ../simv up to date make: warning: Clock skew detected. Your build may be incomplete. -c -o rmapats.o

CPU time: .070 seconds to compile + .043 seconds to elab + 1.459 seconds to link

You should now have an executable file called simv in your working directory. 3. Execute simv on the command line with no arguments. You should see output from both vcs and the simulation and it should produce a waveform file called count.dump in your working directory.

/home/kr/kris9112/sanjay/EE271>./simv
Chronologic VCS simulator copyright 1991-2008 Contains Synopsys proprietary information. Compiler version A-2008.09; Runtime version A-2008.09; Oct $finish called from file "test_count.v", line 17. $finish at simulation time V C S Time: 136 CPU Time: Fri Oct 0.030 seconds; 29 19:28:00 2010 Data structure size: 0.0Mb S i m u l a t i o n 136 R e p o r t 29 19:28 2010

/home/kr/kris9112/sanjay/EE271>

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We are now going to re-invoke vcs to view the waveform. At the prompt, type: /home/kr/kris9112/sanjay/EE271> vcs -RPP count.v

/home/kr/kris9112/sanjay/EE271> vcs -RPP count.v

VirSim B-2008.12-B Virtual Simulator Environment Copyright (C) 1993-2005 by Synopsys, Inc. Licensed Software. All Rights Reserved. Use "virsim [help_arg]" for usage information. help_arg: -help or -verilog_help or -vhdl_help or -epic_help

The -RPP option tells vcs that we are opening it in post-processing mode. This should open up a new window as below:

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In this window, click on open under the File menu option. Change the file type that you want to open to VCD (not VCD+). (VCD has .dump file extension and VCD+ has .vcd file extension). They are both waveform files but VCD files are text files, and VCD+ are condensed binary files.

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Select and open the file count.dump and then click OK (also click O.K. on the information pop-up screen). Click on the test_count button, and you should see all signals instantiated in the signal window: clock, dec, in[3:0], load, and zero.

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Click on New Waveform Window to open a waveform window as below:

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In the Hierarchy window, highlight all signals in the signal list with the left mouse button. Then with the middle mouse button, drag the selected signals over to the black space in the waveform window. At this point, you should see the waveforms starting at time 0 of the simulation.

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In the waveform window, the menu option Display -> Time Scale can be used to change the display unit and the display precision. You can also use Zoom on the menu to change the appearance as shown below:

10. Because we used the system command $dumpvars(0,test_count) in our verilog simulation, we should be able to view all signals at any hierarchical level of

the design. Hence if you go back to the hierarchy window and click on the green arrow next to the test_count button, you can traverse down the hierarchy and select more signals to view. Before exiting the waveform viewer, you can save your settings in a configuration file under the File -> Save Configurations option. Compiling and Simulating in interactive mode 1. Now we are going to simulate the design again but in interactive mode. First let's exit VirSim if you have not already done so. Recompile your source code with the following command line: vcs -RI -Mupdate -f main_count.f The -Mupdate is a compile-time option that tells vcs to compile incrementally. When you use this option, it will create a sub-directory called csrc. This directory will contain a Makefile and object files for each module that is compiled. When you compile incrementally, only the modules that change between compilations will need to be recompiled. The -RI means we are going to simulate in interactive mode. As soon as the code is compiled, VirSim will be invoked and the simulation will start. /home/kr/kris9112/sanjay/EE271> vcs -RI -Mupdate -f main_count.f
Chronologic VCS (TM) Version A-2008.09 -- Fri Oct 29 19:35:24 2010 Copyright (c) 1991-2008 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. ***** Warning: ACC/CLI capabilities have been enabled for the entire design. For faster performance enable module specific capability in pli.tab file Parsing design file 'count.v' Parsing design file 'test_count.v' Top Level Modules: test_count No TimeScale specified Starting vcs inline pass... 1 module and 0 UDP read.

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recompiling module test_count because: Some compilation options have been changed. make: Warning: File `filelist' has modification time 9.1e+02 s in the future gcc -pipe rmapats.c -m32 -O -I/apps/synopsys/VCSMX_NEW/include -c -o rmapats.o

if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv -melf_i386 -m32 5NrI_d.o 5NrIB_d.o wx0S_1_d.o rmapats_mop.o rmapats.o SIM_l.o /apps/synopsys/VCSMX_NEW/linux/lib/libvirsim.a /apps/synopsys/VCSMX_NEW/linux/lib/librterrorinf.so /apps/synopsys/VCSMX_NEW/linux/lib/libvcsnew.so /apps/synopsys/VCSMX_NEW/linux/lib/ctype-stubs_32.a -ldl -lm -lc -ldl /usr/bin/ld: warning: libstdc++.so.5, /apps/synopsys/VCSMX_NEW/linux/lib/librterrorinf.so, libstdc++.so.6 ../simv up to date make: warning: Clock skew detected. Your build may be incomplete. may needed conflict by with

VirSim B-2008.12-B Virtual Simulator Environment Copyright (C) 1993-2005 by Synopsys, Inc. Licensed Software. All Rights Reserved. Use "virsim [help_arg]" for usage information. help_arg: -help or -verilog_help or -vhdl_help or -epic_help

The Interactive window of VirSim should have popped up by now. In the History panel, it says $stop at time 0. Whenever you invoke vcs with the RI option, the simulation will always be paused at time 0.

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2.

Now you can open the Hierarchy window, open the Waveform window, either load your configuration file (using Ctrl-L) or browse through the hierarchy to select signals to view as in GUI part described above. The time scale can be changed by Step Time button in the Simulator Control panel in the Interactive window. When you simulate interactively, the waveforms are only recorded for the signals that appear in the Waveform Window. Hence you should select any signals of interest before the simulation time that you want to view them. If at any time you want to restart the simulation, select Re-exec or Invoke Sim under the Sim option in the Interactive window. You can also view your source code in the following manner. Select Source under Window menu of the Interactive window to open a Source Window and Select

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Hierarchy under Window menu of the Interactive window to open a Hierarchy window. Then in the Hierarchy window, select a module instance, say test_count, and drag it (using the middle mouse button) to the large black panel in the Source window as shown below. If you want to edit your code, VCS will then invoke a text editor.

module test_count; reg reg reg [3:0] wire clock; load, dec; in; zero;

initial begin $dumpfile("count.dump"); // save waveforms in this file $dumpvars (0, test_count); // saves all waveforms clock = 0; load = 0; dec = 0; in = 4'b0110; #16 load = 1; // switch to 1 after the clock edge to reduce confusion #10 load = 0; // wait for 1 clock cycle #10 dec = 1; #100 $finish; end

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always #5 clock = ~clock; // Make 10ns clock counter u1 (clock, in, load, dec, zero); endmodule /* downcounter with zero flag */ module counter (clock, in, load, dec, zero); input input [3:0] input input output reg [3:0] wire clock; in; load; dec; zero; value; zero;

assign zero = ~|value; always @ (posedge clock) begin if (load) value <= in; else if (dec && !zero) value <= value - 1'b1; end endmodule

Updated on October 31 2010 --Sanjay Krishnan & Asmita Kulkarni

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