XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

Flip Flops Learn the Basics First!

Chapter 5, Paper 2

1) Flip-flop is a semiconductor circuit. It is made up of logic gates. It has two stable states. It can store a single bit (binary digit), in the form of memory. 2) Clock is a periodic waveform, particularly a square wave. It is basically used to synchronize digital circuits. It may be symmetrical or asymmetrical. 3) Combinational logic circuits are the special types of circuits, in which, the output at any instant of time depends on the inputs present at that instant of time. A CLC does NOT contain memory. 4) Active HIGH is a state in digital circuit, when the output of a logic circuit is at logic1, so it can give source current to the load at the output. 5) Active LOW is a state in digital circuit, when the output of a logic circuit is at logic0, so it can take sink current into its output. 6) De Morgans theorem states that (1) The complement of product is equal to the sum of the complements. (2) The sum of complements is equal to the product of the complements. 7) Synchronize means to make two or more actions simultaneously. Thus, if two digital circuits are connected to same clock, their actions become synchronous. When two different circuits produce identical waveforms with equal frequency, amplitude and phase, then the circuits are said to be synchronized. RS Flip-flop using NOR gate consider the following circuit. Here two NOR gates are used such that the output of one is the input of other. Also, one input of each gate is taken out as SET and RESET. The two outputs are Q and Q .
R 0 0 1 1 S 0 1 0 1 Q

Last State 1 0 0 1 Forbidden state

1) When R = S = 0, the flip-flop does NOT change its output state. It remains in last state. Hence, it is called no change or last state condition. 2) When R = 0 and S = 1, gate1 is enabled and gate2 is disabled. The flip-flop is now SET. 3) When R = 1 and S = 0, gate1 is disabled and gate2 is enabled. The flip-flop is now RESET. 4) When R = S = 1, both NOR gates are disabled. But practically there is race between two NOR gates. Now we cannot determine output conditions. Hence, it is called FORBIDDEN state. It is also called as the RACE condition. RS Flip-flop using NAND gates consider the following circuit. Here two NAND gates are connected such that the output of one is the input of other. And one input of each gate is taken out as SET and RESET input. The two outputs are Q and Q .
R 0 0 1 1 S 0 1 0 1 Q

Forbidden State 1 0 0 1 Last State

1) When R = S = 0, one input of each gate is HIGH. So Q = Q = 1. This is contradictory. Hence, this state is called forbidden state of flip-flop. 2) When R = 0, and S = 1, gate1 is enabled and gate2 is disabled. The flip-flop is now SET. 3) When R = 1, and S = 0, gate2 is enabled and gate1 is disabled. The flip-flop is now RESET. 4) When S = R = 1, the flip-flop will NOT change its state and will remain in LAST STATE. Hence, it is called no change or last state condition. Note: The RS FF using NAND gates is never used as memory storage circuit, because its first state is forbidden state.
Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com

XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

28

Concept of 1-bit memory cell the electronics memory is a semiconductor medium, in which one bit of information can be stored, for infinite time UNTIL IT IS CHANGED. Such kind of memory cell can be produced using two NAND gates RS flip-flop as follows. When R = 0, and S = 1, gate1 is enabled and gate2 is disabled. Hence, at output we get Q = 1 and
Q = 0. The flip-flop is now SET. When R = 1, and S = 0, gate2 is enabled and

gate1 is disabled. Hence, at output we get Q = 0 and Q = 1. The flip-flop is now RESET. The data can be entered in the circuit, from S and R inputs. Concept of clock a clock is a periodic waveform, particularly a square wave. It is used to synchronize digital circuits. It may be symmetrical or asymmetrical. The time required for one complete cycle of clock is called cycle time. A clock has TWO SHARP EDGES, they are the leading edge or the +ve edge and falling edge or the ve edge. This is shown in following figure. Remember that the state of a flip-flop changes only at +ve or ve edge of clock. It NEVER changes when clock signal is parallel to x-axis.

Concept of positive & negative logic Positive logic in a digital circuit, when logic1 state is treated as more positive than logic0 state, it is called positive logic. Negative logic in a digital circuit, when logic1 state is treated as more negative than logic0 state, it is called negative logic. This can be explained with examples as follows Suppose there are two voltage levels in a logic circuit: 2V and 5V. Then in positive logic system, logic1 means 5V and logic0 means 2V. Similarly, in negative logic system, logic1 means 2V and logic0 means 5V. In another example, suppose there are two voltage levels in a logic circuit: 0V and 5V. Then in positive logic system, logic1 means 0V and logic0 means 5V. Similarly, in negative logic system, logic1 means 5V and logic0 means 0V. The positive and negative logics are very useful in electronics. With their help, we can convert AND gate into OR gate and vice versa. It is also useful in other applications. Clocked RS flip-flop: the basic problem of above flip-flops is that they produce necessary effect of input signal at output without any controlling signal. This problem is overcome in clocked flip-flops. The clocked RS flip-flop is a controlled flip-flop circuit. It has three inputs SET input, RESET input and the CLOCK input

Clock 0 1 1 1 1

R x 0 0 1 1

S x 0 1 0 1

Q Last State

Q
Last State

The block contains NOR gate RS FF

Last State Last State 1 0 0 1 Forbidden State

Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com

XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

29

Working Here one input of each AND gate is connected to clock signal (clk). So when clock is LOW, both AND gates are disabled and when clock is HIGH, they are enabled. Thus, the working of circuit is as follows 1) When clk = 0 and R = S = x (i.e. either 1 or 0), then there will be no change at the output of flipflop. The circuit remains silent. 2) When clk = 1 and R = S = 0, outputs of both AND gates are LOW. Therefore, again there is no change at the outputs. 3) When clk = 1 & R = 0 & S = 1, the output of AND gate2 is HIGH and output of AND gate1 is LOW. Due to this, the flip-flop is SET and hence, we get Q = 1 and Q = 0. 4) When clk = 1 & R = 1 & S = 0, then output of AND gate1 RESETs the flip-flop and hence, we get Q = 0 and Q = 1. 5) Lastly, when clk = R = S = 1, then output of both AND gates are HIGH. So the flip-flop will be in forbidden state. Clocked D flip-flop: the D flip-flop avoids two major disadvantages of RS flip-flop. They are 1) When we want to store some data in it, both inputs should be changed at a time. Generating two input signals simultaneously is sometimes not possible. 2) There is the problem of forbidden state in general-purpose flip-flop.
Clock 0 1 1 D x 0 1 Q Last State 0 1

Q
Last State 1 0

Working 1) When clk = 0 and input D = either 0 or 1, then the output of the circuit does not change i.e. remain in last state. This is because, the two AND gates are in disabled conditions. 2) When clk = 1 and D = 0, the output of AND gate2 is HIGH and flip-flop is RESET. 3) When clk = 1 and D = 1, the output of AND gate1 is HIGH and flip-flop is SET. The JK flip-flop this flip-flop is a special type of flip-flop in digital electronics. It toggle state of output. Its circuit and symbols are given below

Working 1) Suppose the circuit is in last state when power supply is switched on. Let the outputs be Q = 1 and Q = 0 and J = x and K = x with clock = . Then there will be no change at the output. 2) 3) 4) 5) Now let J = 0 and K = 0 with clock = . Then S = R = 0. So the outputs are in last state (N/C). Now we make J = 0 and K = 1 with clock = . Then S = 0 and R = 1. So the flip-flop RESET. Now we make J = 1 and K = 0 with clock = . Then S = 1 and R = 0. So the flip-flop SET. However, when J = K = 1 with clock = , then the flip-flop toggles because the AND gates are disabled alternately.
Clock J x 0 0 1 1 K x 0 1 0 1 Q

N/C N/C N/C N/C 0 1 1 0 Toggle state

When output of FF changes, due to change in clock ONLY, it is called toggle state.

Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com

XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

30

The T flip-flop when the JK flip-flop is permanently used in toggle mode, it is called as T flip-flop (Tmeans toggle). It has only one input called Tinput. This circuit divides frequency of clock signal to half at the output. Hence, it is called divide-by-two flip-flop. When T = J = K = 1, the flip-flop remains in toggle mode and on every ve edge of clock pulse, the flip-flop toggles (this is because the flip-flop is ve edge triggered). Therefore, the clock frequency at the output is half of input frequency. For example if clock input frequency is 10 kHz then the output frequency at Q will be 5 kHz. This is shown in following waveforms. JK (M/S) Master-Slave flip-flop it is a circuit of two JK flip-flops cascaded together. The first flipflop is positive edge triggered and is called Master flip-flop. The second is negative edge triggered flip-flop (see the bubble at its clock input) and called Slave flip-flop. Working the master flip-flop works normally as JK flip-flop, when clk = 1. However, at the same time, clock input of slave clk = 0. So master works and slave rests. Now suppose, in a particular condition, outputs of master are Q = 1 and Q = 0, when clk = 1. Now we make clk = 0. So, output of master remains locked at Q = 1 and Q = 0 because master has stopped working. These outputs of master become inputs of slave and slave starts working. So the outputs of slave become Q = 1 and Q = 0. Thus, every action, which performs master during positive edge of clock signal, the slave copies it during negative edge of clock signal. Thus, slave follows master. This flip-flop is used to produce delayed effect of input at output. It is thus, used in digital echo chamber circuit to produce different time delays in musical signals.

Registers
Introduction A group of flip-flops used to store or rotate a large data is called a register. In register, the number of flip-flops is connected together such that, when a binary number is entered in the circuit, it can shift in the register (from one flip-flop to next) bitbybit and shifts out of the register bitbybit. The register, which performs the process of data shifting either from MSB to LSB or LSB to MSB is called shift register. Left shift register left shift register means the data in it shifts from LSB to MSB. Here four D flip-flops are used. All flip-flops are positive edge triggered type. The D0 input of flip-flop1 is the data input (Din). Here the data is connected, which is to be stored in the register. The four flip-flops are cascaded. The clock inputs are driven in parallel. Initially assume that all flip-flops are empty, i.e. Q3Q2Q1Q0 = 0000. Now clock pulses are applied to the circuit, keeping Din = 1. Then at first +ve edge of clock, flip-flop1 will change its output state and we get Q3Q2Q1Q0 = 0001. At the second +ve edge, the 1 stored in flip-flop1 will shift to flip-flop2 and a new 1 will be stored in flip-flop1. Now the outputs will be Q3Q2Q1Q0 = 0011. At third +ve edge we get Q3Q2Q1Q0 = 0111. Lastly, the outputs will be Q3Q2Q1Q0 = 1111.

Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com

XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

31

Right Shift Register right shift register means the data in it shifts from MSB to LSB. Here four D flip-flops are used. All flip-flops positive edge triggered type. Input D3 of flip-flop1 is connected to data input (Din). Here the data is connected, to store it in the register memory. The four flip-flops are cascaded. The clock input terminals are driven in parallel with single clock signal. Initially assume that all the four flip-flops are empty, i.e. Q3Q2Q1Q0 = 0000. Now clock signal is applied, keeping Din = 1. Then at first +ve edge of clock, flip-flop1 will change its output state the four outputs will be Q3Q2Q1Q0 = 1000. When second +ve edge, the 1 stored in flip-flop1 will shift to flip-flop2 and a new 1 will be stored in flip-flop1. Now the outputs will be Q3Q2Q1Q0 = 1100. Lastly, outputs will be Q3Q2Q1Q0 = 1111.

Counters
Introduction the counter is a combination of flip-flops that counts the number of clock pulses connected to it. It produces equivalent binary output in BCD sequence. It has M number of output states. The M is called modulus of counter or natural count of counter. Modulus (MOD) of counter (M) = 2
n n

Where n = number of flip-flops required

th

Maximum count = 2 1 This is because the 0 count is ignored. Example: in a counter, suppose we need binary states of output from 000 to 111. So there are eight possible states. Thus, we require MOD8 counter. Its maximum count = 2 1 = 7 because the first count 000 is ignored. Asynchronous counter (MOD16) Here four JK flip-flops are ve edge triggered and used in toggle mode. The flip-flops are cascaded in same sequence. Their outputs, on which we get binary count, are taken out as Q3Q2Q1Q0. Initially assume that the outputs Q3Q2Q1Q0 = 0000. When first negative edge arrives, the output of flip-flop1 becomes HIGH and Q3Q2Q1Q0 = 0001. Now at second ve edge, the output of flip-flop1 changes from 1 to 0. This is the negative edge for the clock input of flip-flop2. So the output of flip-flop2 becomes HIGH. Thus, the outputs will be Q3Q2Q1Q0 = 0010. When the third clock pulse arrives, the output of flip-flop1 again changes form 0 to 1. This is the positive edge for the clock input of flip-flop2. Therefore, its output remains unchanged and Q3Q2Q1Q0 = 0011. In the same way, the counter will count the clock pulses from 1 to 16 i.e. the outputs will change from 0000 to 1111. However, this circuit has large propagation delay, because the clock inputs of all the flip-flops are connected one after another.
3

Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com

XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

32

Synchronous counter (MOD8) here all the flip-flops are triggered simultaneously; hence it is called as synchronous counter. Here three JK flip-flops are used. They are negative edge triggered, because NOT gate is connected at their clock inputs. Two AND gates are used which drive the clock input of flip-flop2 and flip-flop3. All the flip-flops are used in toggle mode. The flipflop1 changes its output at every negative edge of clock pulse. Hence, the frequency at Q0 is of clock frequency. Now the output of AND gateA goes HIGH when Q0 = clk = 1. Therefore, flip-flop2 changes its output Q1 at every alternate clock pulse. Hence, the frequency at Q1 is of clock frequency. The output of AND gate-B goes HIGH, when clk = Q0 = Q1 = 1. Therefore, flip-flop3 changes its output Q2 at every alternate state of Q0. Hence, the frequency at Q2 is 1/8 of clock frequency or of the frequency at Q0 or of the frequency at Q1. When first clock pulse arrives, at its negative edge, flip-flop1 changes its output and we get Q2Q1Q0 = 001. When second clock pulse arrives at its positive edge the AND gateA is enabled and its output becomes HIGH. When the negative edge of second clock pulse appears, flip-flop1 and flip-flop2 both change their outputs and we get Q2Q1Q0 = 010. In this way, the counter counts from 000 to 111 in BCD sequence and continues repeatedly. Decade counter (MOD10) it is the modified version of MOD16 counter. In this, feedback from NAND gate is used, so that last six steps of MOD16 counter are cut off, hence, it is called MOD10. Here all the flip-flops are ve edge triggered and in toggle mode. Suppose initially the outputs Q3Q2Q1Q0 = 0000, i.e. the counter is in RESET state. Now the clock pulses are applied to flip-flop1. Then output Q0 changes at every negative edge. So we get Q3Q2Q1Q0 = 0001. Now at second negative edge, Q0 changes from 1 to 0. This is negative change for flip-flop2. So we get Q3Q2Q1Q0 = 0010. In this way, at third ve edge we get Q3Q2Q1Q0 = 0011 and so on. Lastly at the tenth ve edge we get Q3Q2Q1Q0 = 1010. But this is a momentary state. Now Q3 = Q1 = 1. So output of AND gate, goes HIGH and all the flip-flops are CLEARed i.e. RESET to 0000. In this way, the cycle repeats continuously.

Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com

XII Standard Electronics Notes (Updated as per Amravati Board Pattern), 201011

33

Up-Down counter the output of up-down counter is incremented and decremented in sequence hence, the name up-down counter. Here the flip-flops are in toggle mode and are ve edge triggered. Both outputs Q and Q of previous flip-flop are connected to clock input of the next flip-flop in OR combination. The circuit has upcontrol input and downcontrol input separately connected to two AND gates. When UP = 1 and DOWN = 0, the outputs Q2Q1Q0 change from 000 to 111 i.e. in up sequence. Similarly when DOWN = 1 and UP = 0, the outputs Q 2 Q1 Q0 are connected to clock inputs through gates. So the outputs Q2Q1Q0 change from 111 to 000 i.e. in down sequence.

In up counting the BCD counting starts from 000 and ends up at 111, and then repeats again. However, in down counting the BCD counting starts from 111 and ends up at 000, and then repeats again. This change in the counting style takes place when Up-mode input = 1 OR Down-mode input = 1. Ring counter this counter circuit is very different from the counter circuits we have studied. In this counter, a single 1 rotates through a number of flip-flops, like a ring hence, the name ring counter. Here four D flipflops are cascaded one after another. The output of flip-flop4 is connected back to the input of flip-flop1. Also, the output of flip-flop1 is connected to the input of flip-flop2, output of flip-flop2 is the input of flip-flop3 and so on. Thus, it is similar to left shift register, because the data (i.e. a 1) is shifted bitbybit from one flip-flop to another at each positive edge of the clock. However, finally when the 1 comes out of Q3 it is again fed back to D0 to produce the ring, hence, this action is like rotate left ring. Suppose there is a 1 stored in the first flip-flop. This happens because when power supply is connected, all the flip-flops are automatically cleared and a 1 is stored in first flip-flop. Hence the output of the circuit will be Q3Q2Q1Q0 = 0001. Now when the first clock pulse arrives, flip-flop1 changes its output state at positive edge of the clock and the data at shifts from LSB to MSB position. Hence, other bits also shift left by one position. Therefore, we get Q3Q2Q1Q0 = 0010. At the positive edge of second clock pulse, the data moves one bit further. So we get the output as Q3Q2Q1Q0 = 0100. At the third clock pulse we get Q3Q2Q1Q0 = 1000. Lastly at the forth clock pulse the circuit comes back to the original data position of Q3Q2Q1Q0 = 0001. This happens because output Q3 gives the feedback of 1 to the input D0. In this way, a 1 constantly circulates through all the flip-flops and onebyone, we get each output high, one at a time. The following truth table shows the output conditions

The End
Helpline for electronic students: www.dsvidyasagar.com, Email: dsvakola@hotmail.com