FINITE STATE MACHINE

A state machine is often used to control a digital system that carries out a step-bystep procedure or algorithm. As an alternative to using state graphs, a special type of flowchart, called a state machine flowchart, or SM chant, may be used to describe the behavior of a state machine. SM charts are often used to design control units for digital systems. In this chapter we first describe the properties of SM charts and how they are used in the design of state machines. Then we show examples of SM charts for a multiplier and a dice game controller. We construct VHDL descriptions of these systems from the SM charts, and we simulate the VHDL code to verify correct operation. We then proceed with the design and show how PLA tables and logic equations can be derived from SM charts. Finally, we show how alternative designs can be obtained by transforming the SM charts. STATE MACHINE CHARTS Just as flowcharts are useful in software design, flowcharts are useful in the hardware design of digital systems. In this section we introduce the SM chart, which is also called an ASM (algorithmic State machine) chart. We will see that the SM chart offers several advantages over state graphs. It is often easier to understand the operation of a digital system by inspection of the SM chart instead of the equivalent state graph. The conditions for a proper state graph are automatically satisfied for an SM chart. A given SM chat can be converted into several equivalent forms, and each form leads directly to a hardware realization An SM chart differs from an ordinary flowchart in that certain specific rules must be followed in constructing the SM chart. When these rules are followed, the SM chart is equivalent to a state graph, and it leads directly to a hardware realization. Figure 5-1 shows the three principal components of an SM chart. The state of the system is represented by a state box. The state box contains a state name, followed by a slash (/) and an optional output list. After a state assignment has been made, a state code may be placed outside the box at the top. A decision box is represented by a diamond-shaped symbol with true and false branches. The condition placed in the box is a Boolean expression that is evaluated to determine which branch to take. The conditional output box, which has curved ends, contains a conditional output list. The conditional outputs depend on both the state of the system and the inputs. An SM chart is constructed from SM blocks. Each SM block (Figure 2) contains exactly one state box, together with the decision boxes and conditional output boxes associated with that state. An SM block has one entrance path and one or more exit paths. Each SM block describes the machine operation during the time that the machine is in one state. When a digital system enters the state associated with a given SM block, the outputs on the output list in the state box become true. The conditions in the decision boxes are evaluated to determine which path (or paths) are followed through the SM block. When a conditional output box is

encountered along such a path, the corresponding conditional outputs become true. If an output is not encountered along a path, that output is false by default. A path through an SM block from entrance to exit is referred to as a link path. For the example of Figure 2, when state S1 is entered, outputs Z1 and Z2 become 1. If input X1 = 0, Z3 and Z4 also become 1. If X1 = X2 =0 , at the end of the state time the machine goes to the next state via exit path 1. On the other hand, if X1 = 1 and X3 = 0, the output Z5 is 1, and exit to the next state will occur via exit path 3. Since Z3 and Z4 are not encountered along this link path, Z3 = Z4 = 0 by default.

Fig 1: Components of SM Chart

Fig 2: Example of a SM Block

A given SM block can generally be drawn in several different forms. Figure 3 shows two equivalent SM blocks. In both (a) and (b). the output Z2 = 1 if X1 = 0; the next state is S2 if X2 = 0 and S3 if X2 = 1. As illustrated in this example, the order in which the inputs are tested may affect the complexity of the SM chart.

Fig 3: Equivalent SM blocks Certain rules must be followed when constructing an SM block. First, for every valid combination of input variables, there must be exactly one exit path defined. This is necessary since each allowable input combination must lead to a single next state. Second, no internal feedback within an SM block is allowed. Figure 5 shows incorrect and correct ways of drawing an SM block with feedback.

Fig 5: SM blocks with feedback

As shown in Figure 6(a), an SM block can have several parallel paths that lead to the same exit path, and more than one of these paths can be active at the same time. For example, if X1 =X2 =1 and X3 = 0, the link paths marked with dashed lines are active, and the outputs Z1 ,Z2 and Z3 are1l. Although Figure 6(a) would not he a valid flowchart for a program for a serial computer, it presents no problems for a state machine implementation. The state machine can have multiple-output networks that generate Z1, Z2 and Z3 at the same time. Figure 6(b) shows a serial SM block, which is equivalent to Figure 6(a). In the Serial block only one active link path between entrance and exit is possible. For any combination of input values, the outputs will be the same as in the equivalent parallel form. The link path for X1 =X2 =1andX3 = 0 is shown with a dashed line, and the outputs encountered on this path are Z1, Z2, and Z3. Regardless of whether the SM block is drawn in serial or parallel form, all the tests take place within one clock time. In the rest of this text, we use only the serial form for SM charts.

Fig 6: Equivalent SM Blocks

It is easy to convert state graph for a sequential machine to an equivalent SM chart. The state graph of Figure 7(a) has both Moore and Mealy outputs. The equivalent SM chart has three blocks - one for each state. The Moore output (Za, Zb, Zc) are placed in the state boxes, since they do not depend on the input. The Mealy outputs (Z1, Z2) appear in conditional output boxes, since they depend on both the state and input. In this example, each SM block has only one decision box, since only one input variable must be tested. For both the state graph and SM chart, Zc is always 1 in state S3. If X = 0 in state S2, Z1 =1 and the next state is S0. If X=1, Z2=1 and the next state is S2. We have added a state assignment (S0 = 00, S1 = 01, S2 = 10) next to the state boxes. Figure 8 shows a timing chart for the SM chart of Figure 7 with an input sequence X= 1,1,1,0,0,0. In this example all state changes occur immediately after the rising edge of the clock, Since the Moore outputs (Za, Zb, Zc) depend on the state. they can change only immediately following a state change. The Mealy output (Z1, Z2) can change immediately after state change or an input change. In any case, all outputs will have their correct value at the time of the active clock edge.

Fig 7: Conversion of State Graph to an SM Chart

Figure 8: Timing Chart for Fig 7

DERIVATION OF SM CHARTS The method used to derive an SM chart for a sequential control network is similar to that used to derive the state graph. First, we should draw a block diagram of the system we are controlling. Next we should define the required input and output signals to the control network. Then we can construct an SM chart that tests the input signals and generates the proper sequence of output signals. In this section we give two examples of SM charts. The first example is an SM chart for control of the binary multiplier. The add-shift control generates the required sequence of add and shift signals. The counter counts the number of shifts and outputs K = 1 just before the last shift occurs. The SM chart for the binary multiplier is shown in Figure 9. In state S0, when the start signal St is 1, the registers are loaded. In S1, the multiplier bit M is tested. If M = 1, an add signal is generated and the next state is S2. If M = 0, a shift signal is generated and K is tested. If K = 1, this will be the last shift and the next state is S3. In S2, a shift signal is generated, since a shift

must always follow an add. If K = 1, the network goes to S3 at the time of the last shift; otherwise, the next state is S1. In S3, the done signal is turned on. Conversion of an SM chart to a VHDL process is straightforward. A case statement can be used to specify what happens in each state. Each condition box corresponds directly to an if statement (or an elsif). Figure 10 shows the VHDL code for the SM chart in Figure 9. Two processes are used. The first process represents the combinational part of the network, and the second process updates the state register on the rising edge of the clock. The signals Load, Sh, and Ad are turned on in theappropriate states, and they must be turned off when the state changes. A convenient way to do this is to set them all to 0 at the start of the process.

Fig 9: SM Chart for Binary Multiplier

VHDL Program for SM Chart of fig 9

entity Mult is port(CLK,St,K,M: in-bit; Load, Sh,Ad, Done: out bit); end Mult; architecture Smbehave of Mult is signal State, Nextstate: integer range 0 to 3; . begin . process(St, K, M, State) --start if state or inputs change begin Load <= 0'; Sh <= 0'; Ad <= `0; case State is when 0 => if St = 1 then --St (state 0) Load <= '1'; Nextstate <=1; else Nextstate <= 0; end if; when 1 => if M = 1 then Ad <= '1'; Nextstate <= 2; else Sh <= '1'; if K = '1' then Nextstate <= 3; else Nextstate <= 1; end if; end lf; . when 2 => Sh <= '1'; -- (state 2) -- K -- K' -- M' -- M (state 1) --St'

if K = 1' then Nextstate <= 3; else Nextstate <= 1; end if; when 3 => Done <= '1'; Nextstate <= 0; end case; end process; process(CLK) begin if CLK = '1' then State <= Nextstate; end if; end process; ' end SMbehave; `

-- K -- K'

-- (state 3)

-- update state on rising edge

As a second example of SM chart construction, we will design an electronic dice game. Figure 11 shows the block diagram for the dice game. Two counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2, .... Thus, after the "roll" of the dice, the sum of the values in the two counters will be in the range 2 through 12. The rules of the game are as follows: 1. After the first roll of the dice, the player wins if the sum is 7 or 11. The player loses if the sum is 2, 3, or 12. Otherwise, the sum the player obtained on the first roll is referred to as a point, and he or she must roll the dice again. 2. On the second or subsequent roll of the dice, the player wins if the sum equals the point, and he or she loses if the sum is 7. Otherwise, the player must roll again until he or she finally wins or loses.

Fig 11: Block diagram of Dice Game

The inputs to the dice game come from two push buttons, Rb (roll button) and Resets. Reset is used to initiate a new game. When the roll button is pushed, the dice counters count at a high speed, so the values, cannot be read on the display. When the roll button is released, the values in the two counters are displayed, and the game can proceed. If the Win light or Lose light is not on, the player must push the roll button Figure 12 shows a flowchart for the dice game. After rolling the dice, the sum is tested. If it is 7 or 11, the player wins; if it is 2, 3, or 12, he or she loses. Otherwise the sum is saved in the point register, and the player rolls again. If the new sum equals the point, the player wins; if it is 7, he or she loses. Otherwise, the player rolls again. After winning or losing, he or she must push Reset to begin a new game. We will assume at this point that the push buttons are properly debounced and that changes in Rb are properly synchronized with the clock.

Fig 12: Flowchart of Dice Game

The components for the dice game shown in the block diagram (Figure 11) include an adder, which adds the two counter outputs, a register to store the point, test logic to determine conditions for win or lose, and a control network. Input signals to the control network are defined as follows: D7 = 1 if the sum of the dice is 7 D711 =1 if the sum of the dice is 7 or 11 D2312 = 1 if the sum of the dice is 2, 3, or 12 Eq =1 if the sum of the dice equals the number stored in the point register Rb = 1 when the roll button is pressed Reset = 1 when the reset button is pressed Outputs from the control network are defined as follows: Roll = 1 enables the dice counters Sp = 1 causes the sum to be stored in the point register Win = 1 turns on the win light Lose = 1 turns on the lose light We now convert the flowchart for the dice game to an SM chart for the control network using the control signals defined above. Figure 13 shows the resulting SM chart.

The control network waits in state S0 until the roll button is pressed (Rb = 1). Then it goes to state S1, and the roll counters are enabled as long as Rb = 1. As soon as the roll button is released (Rb = 0), D711 is tested. If the sum is 7 or 11, the network goes to state S2 and turn on the Win light; otherwise, D2312 is tested. If the sum is 2, 3, or 12, the network goes to state S3 and turns on the Lose light; otherwise, the signal Sp becomes 1 and the sum is stored in the point register. It then enters S4 and waits for the player to "roll the dice" again. In S5, after the roll button is released, if Eq = l, the sum equals the point and state S2 is entered to indicate a win. If D7 = 1, the sum

is 7 and S3 is entered to indicate a loss. Otherwise, control returns to S4 so that the player can roll again. When in S2 or S3, the game is reset to S0 when the. Reset button is pressed. Instead of using an SM chart, we could construct an equivalent state graph from the flowchart. Figure 14 shows a state graph for the dice game controller. The state graph has the same states, inputs, and outputs as the SM chart. The arcs have been labeled consistently with the rules for proper state graphs. The arcs leaving state S1 are labeled Rb, Rb'D711, Rb'D711D2312, and Rb'D711D2312.

Fig 13: SM Chart for Dice Game

Fig 14: State Graph for Dice Game Controller

Before proceeding with the design, it is important to verify that the SM chart (or state graph) is correct. We will write a behavioral VHDL description based on the SM chart. Initially let us write a dice game module that contains the control network, point register, and comparator (see Figure 11). Later, we will add the counters and adder so that we can simulate the complete dice game. The VHDL code for the dice game in Figure 15 corresponds directly to the SM chart of Figure 13. The case statement in the first process tests the state, and in each state nested if-then-else (or elsif) statements are used to implement the conditional tests. In State 1 the Roll signal is turned on when Rb is 1. If all conditions test false, Sp is set to 1 and the next state is 4. In the second process, the state is updated after the rising edge of the clock, and if Sp is 1, the sum is stored in the point register.

entity DiceGame is port (Rb, Reset, CLK: in bit; Sun: in integer range 2 to 12; Roll, win, Lose: out bit); end DiceGame; library BITLIB; use BITLIB.bit_pack.all; architecture Dicehehave of DiceGame is signal State, Nextstate: integer range 0 to 5; signal Point: integer range 2 to 12; signal Sp: bit; begin process(Rb, Reset, Sum, State)

begin Sp <= '0'; Roll <= '0'; win <= '0'; Lose <= '0'; case State is when 0 => if Rb = '1' then Nextstate <= 1; end if; when 1 => if Rb = '1' then Roll <= 1'; elsif Sum = 7 or Sum = 11 then Nextstate <= 2; elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3; else Sp <= 1'; Nextstate <= 4; end if; when 2 => win,<= '1'; if Reset = '1' then Nextstate <= 0; end if; when 3 => Lose <= '1; if Reset = '1' then Nextstate <= 0; end if; when 4 => if Rb = '1' then Nextstate <= 5; end if; when 5 => if Rb = '1' then Roll <= '1'; elsif Sum = Point then Nextstate <= 2; elsif Sum = 7 then Nextstate <= 3; else Nextstate <= 4; end if; end case: end process; process(CLK) begin if rising_edge(CLK) then

State <= Nextstate; if Sp = '1' then Point <= Sum; end if; end if; end process; end DiceBehave;

REALIZATION OF SM CHARTS Methods used to realize SM charts are similar to the methods used to realize state graphs. As with any sequential network, the realization will consist of a combinational sub network, together with flip-flops for storing the state of the network. In some cases, it may be possible to identify equivalent states in an SM chart and eliminate redundant state. However, an SM chart is usually incompletely specified in the sense that all inputs are not tested in every state, which makes the reduction procedure more difficult. Even if the number of states in an SM chart can be reduced, it is not always desirable to do so, since combining states may make the SM chart more difficult to interpret. Before deriving next-state and output equations from an SM chart, a state assignment must be made. The best way of making the assignment depends on how the SM chart is realized. As an example of realizing an SM chart, consider Figure 7(b). We have made the state assignment AB = 00 for S0, AB = 01 for S1, and AB = 11 for S2. After a state assignment has been made, output and next-state equations can be read directly from the SM chart. Since the Moore output Za is 1 only in state 00, Z1 =A'B'. Similarly, Zb = A'B and Zc =AB. The conditional output Z1 =ABX', since the only link path through Z1 starts with AB = 11 and takes the X = 0 branch. Similarly, Z2 = ABX. There are three link paths (labeled link 1, link 2, and link 3 in Figure 7(b)), which terminate in a state that has B = 1. Link 1 starts with a present state AB = 00, takes the X = 1 branch, and terminates on a state in which B = 1. Therefore, the next state of B (B+) equals 1 when A'BX = 1. Link 2 starts in state 01, takes the X = 1 branch, and ends in state 11, so B+ has a term A'BX. Similarly, B+ has a term ABX from link 3. The next state equation for B thus has three terms corresponding to the three link paths: B+ = ABX + ABX +ABX Similarly, two link paths terminate in a state with A = 1, so

A+ = ABX +ABX These output and next-state equations can be simplified with K maps using the unused state assignment (AB = 10) as a don't care condition. As illustrated above for flip-flops A and B, the next-state equation for a flip-flop Q can be derived from the SM chart as follows: 1. Identify all of the states in which Q = 1. 2. For each of these states, find all the link paths that lead into the state. 3. For each of these link paths, find a term that is l when the link path is followed. That is, for a link path from Si to Si, the term will be 1 if the machine is in state Si and the conditions for exiting to Si are satisfied. 4. The expression for Q+-(the next state of Q) is formed by ORing together the terms found in step 3. Next, consider the SM chart for the multiplier control (Figure 5-9). We can realize this SM chart with a PLA or ROM and two D flip-flops. As indicated in Table 1, the PLA has five inputs and six outputs. Each row in the table corresponds to one of the link paths in the SM chart. Since S0 has two exit paths, the table has two rows for present state S0. The first row corresponds to the St = 0 exit path, so the next state and outputs are 0. In the second row, St = 1, so the next state is 01 and the other PLA outputs are 1000. Since St is not tested in states S1, S2, and S3, St is a don't care in the corresponding rows. The outputs for each row can be filled in by tracing the corresponding link paths on the SM chart. For example the link path from S, to S2 passes through conditional output Ad, so Ad = 1 in this row. Since S2 has a Moore output Sh, Sh = 1 in both of the rows for which AB = 10.

Table 1: PLA Table for multiplier control

if a ROM is used instead of a PLA, the PLA table must be expanded to 2 5 = 32 rows since there are five inputs. To expand the table, the dashes in each row must be replaced with all possible combinations of 0s and 1s. If a row has n dashes, it must be replaced with 2n rows For example, the fifth row in Table 5-1 would be replaced with the following four rows

By inspection of the PLA table, the logic equations for the multiplier control are A+ =A'BM'K+ABM + ABK = A'B(M + K) + AB'K B+ =A'B'St +A'BM'(K' + K) +AB'(K' + K) =ABSt + A'BM' + AB' Load = AB'St Sh =ABM'(K'+K)+AB'(K'+K) = A'BM'+AB' Ad = A'BM' Done = AB

ALTERNATIVE REALIZATIONS FOR SM CHARTS USING MICROPROGRAMMING In applications where the number of inputs to the control network is large, the number of inputs to the PLA, ROM, or PAL will be large. Several methods can be used to reduce the number of inputs required. These methods generally require more states in the SM chart and more output functions to be realized. In figure 26, the only inputs to the PLA come from the state register. The control network inputs go into a MUX instead of into the PLA. The PLA output has four fields: TEST, NSF, NST, and OUTPUT. TEST controls the input MUX, which selects one of the inputs to be tested in each state. If this input is 0 (false), then the second MUX selects the NSF Held as the next state. If the input is 1 (true), it selects the NST field as the next state. The OUTPUT field is the same as for the standard realization. However, the SM chart must have only Moore outputs, since the outputs can be a function only of the state. (Figure 26 could be modified to allow Mealy outputs by replacing the OUTPUT field with OUTPUTF and OUTPUTT, and adding a MUX to select one of the two output fields.)

Fig 26: Control network using an input MUX to select the Next State

Figure 27 shows a modified version of the dice game SM chart. First, all the outputs have been convened to Moore outputs. Second, only one input variable is tested in each state. This corresponds directly to the block diagram of Figure 26, since the TEST field can select only- one input to test in each state and the output depends only on the state.

Fig 27: SM Chart with Moore Outputs and One Test per State

Next we derive the PLA table (Table 3) using a straight binary state assignment. The variables Rb, D711, D2312, Eq, D7, and Reset must be tested, so we will use an 8:1 MUX (Figure 28). When TEST = 001, Rb is selected, etc. In state S13 the next state is always 0111, so NSF= NST= 0111 and the TEST field is dont care. Each row in the PLA table corresponds to a link path on the SM chart. For example, in S2, the test field 110 selects Reset. If Reset = 0, NSF = 0100 is selected, and if Reset = 1, NST= 0000 is selected. In S2, the output Win = 1 and the other outputs are 0.

Table 3: PLA/ROM Table for fig 27

Fig 28: MUX for SM Chart of fig 27

Fig 29: Control Network using a Counter for the State Register

The block diagram of Figure 29 is similar to Figure 26, except the state register has been replaced with a counter. The NSF field has been eliminated from the PLA output. As before, the TEST field selects one of the inputs to be tested in each state. If the selected input is 1 (true), the NST field is loaded into the counter. If the selected input is 0, the counter is incremented. This requires that the SM chart be modified as shown in Figure 30 and that the state assignment be made in a special way. For each condition box, for the false branch, the next state is assigned in sequence if possible. If this is not possible, extra states (called X-states) must be added. The required number of X-states can be reduced by assigning long strings of states in sequence. To facilitate this, it may be necessary to complement some of the variables that are tested. In Figure 31, Rb and Reset have each been complemented in two places, and the 0 and 1 branches have been interchanged accordingly. With this change, states 0000, 0001, , 1000 are in sequence. S3 has been assigned 1001, and before

adding an X-state, NSF was 0000 and NST was 1001, so neither next state was in sequence. Therefore, X-state Sx was added with a sequential assignment 1010; the next state of Sx is always 0000. If we assign 1011 to S2, the next states would be 1011 and 0000, and neither next state would be in sequence. We could solve the problem by adding an X-state. A better approach is to assign 1111 to S2, as shown. Since incrementing 1111 goes to 0000, one of the next states is in sequence, and no X-state is required. The inputs tested by the MUX in Figure 31 are similar to Figure 26 except D7 and Reset have been complemented, and both Rb and Rb' are needed. Since NST is always 0101 in state S13, a 1 input to multiplexer is needed. The corresponding PLA table is given in Table 4.

Fig 30: SM Chart with Serial State Assignment and Added X-State

Fig 31: MUX for SM Chart of fig 30

Table 4: PLA Table for fig 31

The minimum logic equations for a PAL, derived from Table 4 with don't care outputs assigned to the unused states, are as follows: Test (2) = BCD+ BCD + A Test (1) = B'C + BCD+ AD Test (0) = ABD +BD' + AD' NST (3) = A'B'C + CD + AD NST (2) = A'CD' + B + AC 'D' NST (1) = A'CD' + BC NST (0) = D +A'B'C+BC' +AC' Roll = ABC'D +BCD SP = BC'D' LOSE = ABD Note that each of these equations requires at most four variables, whereas some of Equations require up to nine variables The methods we have just studied for implementing SM chart are examples of microprogramming techniques. The counter in Figure 28 is analogous to the program counter in a computer, which provides the address of the next instruction to be executed. The PLA or ROM output in a microinstruction, which is executed by a remaining hardware. Each microinstruction is like a condition branch instruction that tests an input and branches. To the different address if the test is true; otherwise, the next instruction in sequence is executed. The output field in the microinstruction is bits that control the operation of the hardware.

LINKED STATE MACHINES

When n sequential machine becomes larger and complex, it is desirable to divide the machine up into several smaller machines that are linked together. Each of the smaller machines is easier to design and implement. Also one of the sub machines may be "called" in several different places by the main machine. This is analogues to dividing a large software program into procedures that are called by the main program. Figure 32 shows the SM chart for two serially linked stat machines. The main machine (machine A) executes a sequence of "some states" until it is ready to call the sub machine (machine B). When state SA is reached, the output signal ZA activates machine B. Machine B then leaves its idle state and executes a sequence of other states" When it is finished, it outputs ZB before returning to the idle state. When machine A receives ZB, it continues to execute "other states. Figure 32 assumes what the two machines have a common clock.

Fig 32: SM Charts for Serially Linked State Machines

As an example of using linked slate machines, we split the SM chart of Figure 13 into two linked SM charts. In Figure 13, Rb is used to control the roll of the dice in states

S0 and S1 and in an identical way in states S4 and S5. Since this function is repeated in two places, it is logical to use a separate machine for the roll control (Figure 33(b)). Use of the separate roll control allows main dice control (Figure 33(a)) to be reduced from six states to four states. The main control generates an En_roll (enable roll) signal in T0 and then waits for 1 Dn_roll (done rolling) signal before continuing. Similar action occurs in T1. The roll control machine waits in state S0 until it gets an En_roll signal from main dice control. Then, when the roll button is pressed (Rb = 1), the machine goes to S1 and generates a Roll signal. It remains in S1 until Rb = 0, in which case the Dn_roll signal is generated and the machine goes back to state S0.

Fig 33: Linked SM Chart for Dice Game

STATE MACHINES State machines provide formalism for sequential logic. Finite state machines (FSM), as the name implies, have a finite amount of memory. The next state of any FSM depends on its present state and its inputs. There are two types: the Moore, or state output machine, in which the output depends strictly on the present state, and the Mealy, or transition output machine, in which the output depends on both the current state and the inputs. Encoded State Machines If a state machine has n states, we need a minimum of logn(2) bits to hold the current state. There are a variety of ways of encoding state, i.e., assigning bit patterns for each state. Once assigned, we can determine the logic for determining the next state in terms of the present state and the inputs. Example: A state machine has two input channels, X and Y, and an output, Z. It is required to output "1" whenever a multiple of three 1s have been received on either or both inputs, otherwise the output must be "0." Figure 34 shows a suitable state diagram for this Moore-type FSM. Figure 35 shows the state assignments and logic equations.

Fig 34: State Diagram Moore type FSM

Fig 35: Encoded State Machine

One-hot" State Machines Encoded-state implementation is optimum in state storage, but since many FPGA architectures have a generous supply of flip-fops, other factors need to be considered. FPGAs may have limited fan-in to the associated combinational logic, and need extra space for decoding state. We can often reduce the amount of combinational logic and improve the speed of operation at the same time. In addition, the design procedure is very straightforward. One-hot coding uses one bit- per state, that is, there is no encoding. Figure 36 shows a flip-flop for a particular state. The D input is driven from an OR gate, which combines inputs for: 1. Previous states: Any state that can transition into this state, such as P1 or P2 in Figure 37, provides an input. If it is unconditional, just the state signal is sufficient. If conditional, we create an AND gate for the combination of state and conditioning signals, for example, P1 with I1 and I2 2. Default condition: If there is a default condition in which the state machine remains in this state provided the exit conditions are not satisfied, we provide another AND gate fed by the state itself and the inverted OR of the exit conditions. The upper left OR gate would be fed by logic corresponding to the conditions for exit to N1, N2, or N3.

Fig 36: State flip-flop circuit for one-hot encoding

Some FPGA architectures have a global reset signal that resets all flip-flops. This can Fig 37: State Machine for state must be asserted, we use an inverter be used to advantage, but since the initial One-Hot Encoding on the output of the flip-flop concerned, thus maintaining the "onehot" basis. Since the number of possible states could considerably exceed the number of valid states, there is a risk of the state machine entering an invalid state, whereupon it would remain there indefinitely. While the risk is small, it is straightforward to arrange for a presence in one state to reset the flip-flops of others; For example, State A may reset the flip-flop for State B, provided A is not the immediate predecessor of B. Figure 38 shows the state assignments and equations. Extensive studies have been carried out for a set of benchmark circuits, and have confirmed the benefits of this form of implementation for at least one popular FPGA architecture.

Fig 38: One-Hot State Encoding

PETRI NETS FOR STATE MACHINES The finite state machines described earlier are sequential machines: only one state can be active at a time. This makes it difficult to design an FSM that is required to control parallel processes. One approach is to divide the specification into a number of sequential machines, which are linked together to implement a parallel controller. However, this does not explicitly represent the concurrency, and so makes it difficult to detect synchronization errors such as deadlock (when two processes are waiting for each other). A more satisfactory method of representing the concurrency is to use a single parallel controller that can have several states active simultaneously. Such a parallel controller can be represented using a Petri net model. This gives a clear specification of the parallelism in the design. The specification can then be analyzed for correctness, and used as a basis for the implementation. Basle Concepts A Petri net is a directed graph comprising nodes of two kinds - places and transitions and directed arcs that connect places to transitions and vice versa. Places are commonly represented by circles and transitions by bars. A place can contain a token, which is depicted as a black dot. A marking of a Petri net is a mapping of a set of tokens to places in the net. The behavior of the system represented by the Petri net is defined by the movement of tokens. A simple Petri net is shown in Figure 39.

Fig 39: Simple Petri net

In the general case, arcs can be labeled with integer numbers that describe how many tokens are carried through a particular arc when the tokens move around the net. Petri nets involving arcs that are able to carry only one token at a time are called ordinary Petri nets. Tokens can proceed through a Petri net according to a certain rule called a transition firing rule. To define this rule some other definitions have to be introduced. The input places of a transition are the places that are connected to the transition by arcs leading from those places to the transition. Similarly, the output places of a transition are the places connected to the transition by arcs leading from the transition to those places. A transition is enabled if each of its input places contains at least one token. If a transition is enabled, it may fire. A firing of a transition removes a token from each of its input places and adds a token to each of its output places. Figure40 shows a Petri net before and after the firing of transition T2.

Fig 40: Petri net before (a) and after (b) transition T2 fires

All enabled transitions fire asynchronously, subject to the rule presented previously with the restriction that tokens are indivisible. In Figure 40(b) both transition T4 and transition T5 are enabled, but only one of them can fire since they share an input place holding a token. Firing either of them disables the other. Such a situation is called a conflict. When a conflict arises in a net, the choice of which transition to tire is arbitrary. lf a system that is represented by a Petri net is to be deterministic, all conflicts must be removed from the net. Basic Properties A Petri net representation of a system can be used as an input for analyzing behavioral properties of the system. Two properties are essential to ensure that a system described by a Petri net is to work correctly. The properties are liveness and boundedness (or safeness). Both liveness and boundedness are strictly connected not only with a structure of a net but also with an initial marking. A Petri net with a marking is called a marked Petri net. A Petri net is said to be live if for any marking reached from the initial marking it is possible to fire any transition of the net by progressing through a firing sequence. If a Petri net representation of a system is live, it means that there is no deadlock in the system. The Petri nets shown in Figures 39 and 40 are live. Figure 41 gives an example of a nonlive Petri net.

Fig 41: Nonlive Petri net

It is nonlive because when P1 and P4 have tokens and T2 fires no further firing is possible. The net would be live if it could be guaranteed that whenever the marking is P1, P4 only T1 could fire. A marking M is said to be reachable in a Petri set N with the initial marking M0 if there exists a firing sequence that transforms M0 to M. A Petri net is said to be bounded (or k-bounded) if the number of tokens in each place does not exceed a finite number (a finite number k) for any reachable marking. Safeness is a special case of boundedness. A Petri net is said to be safe if the number of tokens in each place never exceeds one. Figure 42 shows Petri nets that are safe, 2-bounded, and unbounded, respectively. Some bounded although nonsafe, or even unbounded Petri nets can be considered as bounded ones when some restrictions are imposed on the transition, firing rule.

Fig 42: Safe (a), 2-bounded (b), and unbounded(c) Petri nets

Extended Petri Nets for Parallel Controllers To describe digital controllers using the Petri net model, each place is used to represent a local state in the controller. The marking, or global state, is obtained by concatenating these local states and mapping them onto the controllers state register. Transitions map onto the combinatorial logic block. Resetting the .controller returns the Petri net to its initial marking. The model is extended in the following three ways: Transition enabling is modified by optionally attaching a predicate to each transition, where each predicate is a Boolean function of the controllers input signals. A transition is now enabled if all of its input places are marked and its predicate, if present, is asserted. The Petri net is synchronously clocked so that its marking is only updated at the start of each clock cycle. Transitions fire when the clock is active provided the inputs and other conditions enable the transitions to fire. This will then create a new marking in the net. The controllers output signals are attached to selected nodes in the Petri net, and are asserted whenever any of their associated places are marked (for Moore outputs) or transitions are enabled (for Mealy outputs).

Metastability Characteristics The theory of synchronous sequential circuits assumes that all signals, whether external or internal, are stable during a "decision window" around the time of clock transitions. The manufacturer of any flip-flop specifies setup and hold times before and after the clock edge, as illustrated in Figure 2-19, during which the input signals, such as D, should be stable, along with a propagation delay for any output change, Q. Many systems have to cope with real-time inputs that are not synchronized to the

system clock, and so this requirement cannot be guaranteed. If an input changes within the decision window defined by these values, the effect may be to cause the flip-flop to change state, but with insufficient energy to make a complete transition. If a partial transition takes the flip-flop output voltage to a central region midway between the supply rail voltages, there may be little or no feedback to complete the transition or return to the previous state. Consider the experiment suggested by Figure 2-20. The logic threshold voltage Vinv is that for which the input and output voltages are identical. Given identical inverters, if we set the upper input voltage to Vinv and closed the switch before removing the voltage source, the circuit would remain poised at Vinv, for ever! This only appears to be a stable state, since the slightest disturbance is reinforced by positive feedback around the loop and drives the circuit voltages to stable values, high or low. Accordingly the third state is referred to as metastable. The longer we wait after a clock edge, the more likely the output will have reached one of the true stable states, but we can only express this in terms of probability. Theoretical and experimental studies have confirmed this phenomenon and related it to parameters that can be determined for any flip-flop. Assume that the clock rate is fc and the D input experiences asynchronous edge transitions uniformly distributed over the clock period at a lower frequency f. We will not see any change in the flip-flop output until the nominal propagation delay tP is over. If we wait a given time tr, (measured from the rising clock edge), we will occasionally find that the Q output is neither a good "0" nor a good "1" that is. it is metastable. The mean time between such events will be cr,/r m Tuff} where Tg and r are constants for the flip-Hop concemed, assuming operation at f, fc. Figure 2-2l shows the improvement brought about by a few nanoseconds of extra delay for an intemal Hip-flop of a particular FPGA. It is based on [Alfke92] and includes the nominal propagation delay.-Fortunately, the small size and high speed of flip-flops realized intemal to FPGAs has considerably improved the situation, compared with earlier small-gcale integration (SSI) parts. Although metastability cannot be eliminated for synchronous systems subject to asynchronous inputs, its effects can be reduced by 4

 keeping clock frequencies as low as possible using a synchronizer for each asynchronous input using extra clock cycles for resolution

Fig 43: Improvement of metastability resolution with added delay

All these points delay the processing of data slightly but the alternative of unreliability is unacceptable.