Lecture 12

Digital Circuits (II)

MOS INVERTER CIRCUITS

Outline
NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up
Complementary MOS (CMOS) inverter Static analysis of CMOS inverter

Reading Assignment:
Howe and Sodini; Chapter 5, Section 5.4

6.012 Spring 2009

Lecture 12

1. NMOS inverter with resistor pullup: Dynamics

CL pulldown limited by current through transistor
[shall study this issue in detail with CMOS]

CL pullup limited by resistor (tPLH RCL) Pull-up slowest

VDD

VDD

R VOUT: HI LO VIN: LO HI CL VIN: HI LO

R VOUT: LO HI CL

pull-down

pull-up

6.012 Spring 2009

Lecture 12

1. NMOS inverter with resistor pullup: Inverter design issues

Noise margins |Av| R |RCL| slow switching gm |W| big transistor
(slow switching at input)

Trade-off between speed and noise margin.

During pull-up we need: High current for fast switching But also high incremental resistance for high noise margin.

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Lecture 12

2. NMOS inverter with currentsource pullup

IV characteristics of current source:
iSUP + ISUP 1 roc

vSUP

iSUP

_ vSUP

Equivalent circuit models :

iSUP +

vSUP

ISUP

roc

roc

large-signal model

small-signal model

High current throughout voltage range vSUP > 0 iSUP = 0 for vSUP 0 iSUP = ISUP + vSUP/ roc for vSUP > 0 High small-signal resistance roc.
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6.012 Spring 2009

NMOS inverter with currentsource pullup VDD Static Characteristics

iSUP VOUT VIN CL

Inverter characteristics :
iD

VDD ISUP + r oc

3 2

VIN = VGS

1 VDD (a) VOUT 1 2

vOUT = vDS

4 VIN

(b)

High roc high noise margins

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PMOS as currentsource pullup

IV characteristics of PMOS:
+ S+ VSG _ G IDp VG + _ D + V D ID(VSG ,VSD) VSD B + 5V

(a)

VSG = 3.5 V 300 250 200 IDp (A) 150 100 50 (saturation region) VSG = 25 VSG = 0, 0.5, 1 V (cutoff region) VSG = 2 V VSG = 1.5 V 1 2 (b) 3 4 5 VSD (V) VSD = VSG + VTp = VSG 1 V VSG = 3 V

(triode region)

Note: enhancement-mode PMOS has VTp <0. In saturation:

IDp VSG + VTp

6.012 Spring 2009

Lecture 12

PMOS as currentsource pullup:

Circuit and load-line diagram of inverter with PMOS current source pull-up:
VDD
-IDp=IDn PMOS load line for VSG=VDD-VB VDD

VB VOUT VIN CL
0 0 VDD VOUT VIN

Inverter characteristics:
NMOS cutoff PMOS triode

VOUT VDD

NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation

VTn

VDD
Lecture 12

VIN
7

6.012 Spring 2009

PMOS as currentsource pullup:

NMOS inverter with current-source pull-up allows high noise margin with fast switching High Incremental resistance Constant charging current of load capacitance But When VIN = VDD, there is a direct current path between supply and ground power is consumed even if the inverter is idle.
VDD
-IDp=IDn PMOS load line for VSG=VDD-VB VDD

VB VOUT:LO VIN:HI CL
0 0 VDD VOUT VIN

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Lecture 12

3. Complementary MOS (CMOS) Inverter

Circuit schematic:
VDD

VIN CL

VOUT

Basic Operation: VIN = 0 VOUT = VDD

VGSn = 0 < VTn VSGp = VDD > - VTp NMOS OFF PMOS ON NMOS ON PMOS OFF

VIN = VDD VOUT = 0

VGSn = VDD > VTn VSGp = 0 < - VTp

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Lecture 12

VOUT VDD 1 2

CMOS Inverter (Contd.): 3

Output characteristics of both transistors:
4 5 VDD VIN

IDn = IDp

IDp = IDn

VIN 3 4 5 n-channel (a) 2 1 VDD VOUT 5 p-channel (b) 4 3 2 1 VDD VOUT

Note: VIN = VGSn = VDD -VSGp VSGp=VDD - VIN VOUT = VDSn = VDD -VSDp VSDp=VDD - VOUT IDn = -IDp Combine into single diagram of ID vs. VOUT with VIN as parameter

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10

CMOS Inverter (Contd.):

ID

VDD-VIN

VIN

0 0 VOUT

No current while idle in any logic state Inverter Characteristics:

NMOS cutoff PMOS triode

VOUT VDD

NMOS saturation PMOS triode

NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff

VTn

VDD+VTp VDD VIN

railtorail logic: logic levels are 0 and VDD High |Av| around logic threshold good noise margins
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2. CMOS inverter: noise margins

VOUT VDD

NML

VM

Av(VM)

VILVM VIH NMH

VDD VIN

Calculate VM Calculate Av(VM) Calculate NML and NMH

Calculate VM (VM = VIN = VOUT)

At VM both transistors are saturated:

I Dn =

Wn 2 nCox (VM VTn ) 2Ln Wp = pCox VDD VM + VTp 2Lp

Lecture 12

IDp
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CMOS inverter: noise margins (contd.)

Define:
W kn = n n Cox ; Ln kp = W
p L
p

p Cox

Since :

I Dn = IDp
Then:

1 1 2 kn (VM VTn ) = kp VDD VM + VTp 2 2

Solve for VM:

kp V + VTp VTn + k
DD n VM = kp 1+ kn

Usually, VTn and VTp fixed and VTn = - VTp VM engineered through kp/kn ratio.

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CMOS inverter: noise margins (contd..)

Symmetric case: kn = kp
VM = VDD 2
Wp

This implies:
Wp kp L = 1 = Wp kn n C n ox Ln

pCox

Lp Wn 2 p Ln

Wp W 2 n Lp Ln

Since usually Lp Ln = Lmin Wp 2Wn Asymmetric case:

kn >> kp , or W Wn >> p Ln Lp

VM VTn
NMOS turns on as soon as VIN goes above VTn. Asymmetric case:
kn << kp , or W Wn << p Ln Lp

VM VDD + VTp
PMOS turns on as soon as VIN goes below VDD + VTp.
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CMOS inverter: noise margins (contd) Calculate Av(VM)

Small signal model:
S2
+

vsg2=-vin
-

gmpvsg2

rop
D2 D1 +

G2

G1 + vgs1
-

vin
-

gmnvgs1 S1

ron

vout
-

G1=G2
+

D1=D2 +

vin
-

gmnvin S1=S2

gmpvin

ron//rop

vout
-

Av = g mn + gmp ron // rop

This can be rather large.
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)(

)
15

CMOS inverter: calculate noise margins (contd.)

VOUT VDD

NML

VM

Av(VM)

VILVM VIH NMH

VDD VIN

Noise-margin low, NML:

VIL = VM VDD VM Av

NM L = VIL VOL = VIL = VM

VDD VM Av

Noise-margin high, NMH:

1 + 1 VIH = VM Av

NM H = VOH VIH

1+ 1 = VDD VM Av
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What did we learn today?

Summary of Key Concepts

In NMOS inverter with resistor pull-up, there is a trade-off between noise margin and speed Trade-off resolved using current source pull-up
Use PMOS as current source.

In NMOS inverter with current-source pull-up: if VIN = High, there is power consumption even if inverter is idling. Complementary MOS: NMOS and PMOS switch on alternatively.
No current path between power supply and ground No power consumption while idling

Calculation of CMOS
VM Noise Margin

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