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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.

4, August 2012

EFFECT OF EQUAL AND MISMATCHED SIGNAL


TRANSITION TIME ON POWER DISSIPATION IN GLOBAL VLSI INTERCONNECTS
Devendra Kumar Sharma*, Brajesh Kumar Kaushik#, and R.K.Sharma$
* #

Department of ECE, Meerut Institute of Engineering and Technology, Meerut, INDIA Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, INDIA $ Department of ECE, National Institute of Technology, Kurukshetra, Haryana, INDIA
{d_k_s1970@yahoo.co.in,bkk23fec@iitr.ernet.in,mail2drrks@gmail .com}

ABSTRACT
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.

KEYWORDS
Equal / Unequal rise time, Power dissipation, simultaneous switching, Signal Skew

1. INTRODUCTION
The growth of VLSI circuits is largely dependent on technology scaling. The integration of more and more functionalities on chip causes die size to increase which results in complex geometry of interconnect wires on chip. With technology advancement, on chip interconnects have turned out to be more and more important than transistor resource [1], [2]. As per international technology roadmap for semiconductors (ITRS) [3], the gap between interconnection delay and gate delay will increase to 9:1 and on-chip wire length is expected to increase to 2.22 km/cm2 for future nanometer scale integrated circuits. So, for high speed high density chips, the chip performance is mostly affected by the interconnections rather than device performance. The decrease in interconnect width and thickness leads to increase in resistance while short spacing between them progressively increases the parasitic capacitance. With high clock speed, faster signal rise time and longer wire lengths, the inductance of interconnect significantly plays a major role in on-chip circuit performance [4]. Due to the presence of these line parasitics effect, the RLC distributed model or transmission line model [2], [5] is more effective in current technology. The short spacing between interconnect wires, longer wire lengths and high operational frequency causes significant value of coupling parasitics i.e. mutual inductance (M) and coupling capacitance (CC) in the circuit. The resulting effect of these parasitics is crosstalk noise, propagation delay and power dissipation. These performance parameters affect the signal integrity.
DOI : 10.5121/vlsic.2012.3410 111

International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012

The denser designs of integrated circuits introduce problems of power dissipation. So, the power analysis of integrated circuits becomes an important issue of study. Small power consumption makes the circuit/device more reliable. The CMOS circuits are best known for its low power consumption. Below submicron technology, the power consumption per unit area of CMOS chip has risen tremendously. Some of the factors affecting the power consumption are input voltage level, input transition time, output loading and power dissipation capacitances. The power dissipation in CMOS circuit consists of two components i.e. static and dynamic dissipation. The static power component is the result of leakage currents and sub-threshold currents and is quite low. The dynamic power dissipation, which is due to charging and discharging of parasitic capacitive load of interconnects and devices, contributes dominantly. The dynamic power dissipation may be written as

P = KCT Vdd f

(1)

In Eq.(1), CT comprises of various capacitances i.e. interconnect parasitic capacitance, load capacitance (CL) and drain and source capacitances. The Vdd is power supply voltage, f is operating frequency and K is switching activity factor. There are two factors affecting the dynamic power dissipation viz. clock speed and transistor density. If the transistors are switching more rapidly, the power dissipation will be more. The dynamic power dissipation is due to switching current and through current. The through current is due to short circuit path between supply and ground rails during switching and is dependent on the input rise/fall time, the load capacitance and gate design [6]. The power dissipation due to through current is always substantially smaller than switching power. To obtained the total power dissipation (Eq.(2)), the three dissipation components may be added [6], PTotal = PStatic + PDynamic + PShort circuit

(2)

A great deal of research has been done on the analysis of crosstalk noise and delay [7], [8], [9], [10], [11], [12]. However, researchers have reported the power dissipation in interconnects considering different aspects. Power related issues of CMOS in nanometer regime are reported in [13]. The analysis of power consumption in optimally buffered single line RC model is reported in [14]. The power dissipation is analyzed against variations in interconnect width for uncoupled line [15]. Power dissipation is analyzed against variations in load for capacitively coupled interconnects [16]. A method for analyzing power distribution using reduced order model is reported in [17]. This paper is an extended version of [18]. Firstly, this paper re-addresses the power dissipation dependencies on equal and unequal transition time of inputs in capacitively and inductively coupled interconnects. The analysis is equally important because of the fact that the two inputs may have different transition time due to different length of interconnects. Secondly, this paper addresses the effect of skew on signal transition time. Skew is the difference between actual and expected arrival time of the pair of signals. Some of the factors affecting signal skew are process variation, wire and coupling parasitics, clock loading. The signal skew is dependent on wire delay which in turn depends on many factors. The impact of signal skew on delay and overshoot noise is presented in [9]. The effects of coupling parasitics on skew are analyzed in [19]. This paper is organized in four sections. Section 2 describes the simulation setup of interconnect model under consideration. The effects of equal and unequal (mismatched) transition time of inputs to two interconnect lines on power dissipation are observed and discussed in section 3. The analysis of the effects of skew on signal transition time is presented in section 4. Finally, section 5 concludes this paper.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012

2. SIMULATION SETUP
For analysis, two uniformly distributed RLC lines coupled capacitively and inductively as shown in Fig. 1. are simulated. . The length of each interconnect is taken as 4mm and each line of coupled structure is 2 m wide, 0.68 m thick and separated by 0.24 m [12]. The global interconnect is taken into consideration and it is assumed that there are several metal layers available for the interconnects

Vdd Interconnect line R, L, C tr1 CL Input Vdd Interconnect line R, L, C tr2 CL M, CC

Figure 1. Coupled lines


12,500 0 R= 12,500 0

C=

190 p 64 p

64 p 190 p

1.722 L= 1.4

1.4 1.722

Figure 2. Line parasitic matrices It is well accepted that the simulations of a distributed RLC interconnect line matches more accurately the actual behavior as compared to lumped model [2]. So, fifty distributed lumps of gamma type are taken for the length of interconnect under consideration. The parasitics values are obtained from expressions reported in [20], [21]. The far end of interconnect lines are terminated by a capacitive load of 30 fF. The interconnect parasitics matrices for one meter length are shown in Fig. 2. The simulations use an IBM 0.13 m technology node with copper interconnect process (MOSIS) with a power supply voltage of 1.5 V. The width of driver PMOS and NMOS are taken as 70 m and 35 m respectively. To carry the analysis, results are obtained through SPICE simulations and waveforms are generated.

3. IMPACT OF EQUAL AND UNEQUAL TRANSITION TIME OF INPUTS


The transition time is defined as the time for a signal to go from 10 % to 90 % of its final value. The power dissipation is dependent on the supply current which in turn is sensitive to input transition time. In this section, the impact of equal rise time (tr1 = tr2) and unequal rise time (tr1 tr2) of inputs to the two interconnect lines (Figure 1) are observed. The unequal rise time is because of different lengths of wire which maps into different parasitic values. For analysis, the rise time of both the inputs is varied equally from 10 to 760 ps. In case of unequal rise time of inputs, the difference i.e. tr = tr1 ~ tr2 is varied from 0 to 750 ps. The interconnect model under consideration is SPICE simulated for equal and unequal transition time of inputs. The two cases of simultaneously switching inputs are taken into consideration i.e.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012

Case I: Both inputs are switching in same phase i.e. from high to low or from low to high. Case II: Both inputs are switching in opposite phase i.e. aggressor input in switching from high to low and victim input is switching from low to high.

3.1 Results and Observations


To show the impact of equal and unequal rise time of inputs on power dissipation, the waveforms are generated as shown in Figure 3-6. From these figures, following observations are drawn. (i) For in-phase switching of inputs, it is observed from Figure 3 that there is wide variation of power dissipation for high to low switching. However, the power dissipation is quite low for low to high switching. This is from the fact that for high to low switching of driver inputs, the parasitics are charging. After the parasitics get charged, the power dissipation is minimum. Also, for low value of rise time, the inductive effect becomes prominent. For low to high switching of driver inputs, the parasitics are discharging. So, power consumption is low. Furthermore, it is observed that the peak value of power dissipation for in-phase switching of inputs is 14.1mW for the specified range of rise time under consideration.

16.00 14.00 12.00 Power dissipation (mw) 10.00 8.00 6.00 4.00 2.00 0.00 10

Sam e phase sw itching of inputs Equal rise tim e High to low sw itching Low to high sw itching

160

310 460 Rise tim e (ps)

610

760

Figure 3. Power dissipation as function of rise time for in-phase switching

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
Sam e phase sw itching of inputs Unequal rise tim e High to low sw itching Low to high sw itching

16 14 Power dissipation (mw) 12 10 8 6 4 2 0 0

150 300 450 600 Difference in rise time (ps)

750

Figure 4. Power dissipation as function of tr for in-phase switching

10.00 9.00 Power dissipation (mw) 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 10

Opposite Phase Sw itching of inputs Equal rise tim e

160

310

460

610

760

Rise time (ps)

Figure 5. Power dissipation as function of rise time for out-of-phase switching (ii) Figure 4 shows the simulation results for in-phase switching wherein difference in rise time ( tr) is varied by taking into consideration both the transitions from high to low and low to high. It is observed that, for inputs switching from high to low, the power dissipation first increases and then starts decreasing monotonically. However, the power dissipation when inputs are switching from low to high is quite low as compared to high to low for the specified range of tr under consideration. The reason can be explained in the similar way as explained earlier. Furthermore, it is observed from Figure 4 that the maximum power dissipation for this case is 13.8 mW.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012
9.00 8.00 7.00 Power dissipation (mw) 6.00 5.00 4.00 3.00 2.00 1.00 0.00 0 150 300 450 600 Difference in rise tim e (ps) 750 Opposite Phase Sw itching of inputs Unequal rise tim e

Figure 6. Power dissipation as function of tr for out-of-phase switching (iii) For opposite phase switching and equal rise time of inputs (Figure 5), it is observed that the power dissipation decreases with increasing rise time. In this case, it is observed that the maximum power dissipation is 8.66 mW which is reasonably smaller than the value of maximum power dissipation observed in case of same phase switching of inputs. However, at large values of rise time in the specified range, the power dissipation for the two cases of simultaneous switching (Case I and Case II) is quite low. (iv) From Figure 6, it is observed that, with increasing tr, the power dissipation decreases dramatically and a minima of value 0.0423 mW occurs at 600ps difference in rise time.

4. EFFECT OF SIGNAL SKEW ON TRANSITION TIME


Skew is the time difference () between the actual and expected arrival times of a pair of signals as illustrated in Figure 7. Signal skew is dependent on wire delay. Since, wire delay is dependent on many factors, one of those is signal transition time, so, signal skew will have some effect on signal transition time. In this section, the analysis of the effect of skew on signal rise time is carried out for the two cases of simultaneously switching lines. To observe the effects, skew is varied from 5ps to 95ps in steps of 10ps. The coupled model is simulated and the rise time (10% to 90% of signal final value) is observed at far end of lines.


In-phase switching Out-of-phase switching

Figure 7. Signal Skew


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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012

4.1 Results and Observations


The rise time observed for in-phase and out-of-phase switching of lines with growing signal skew is shown in Figure 8. From this figure, it is observed that the rise time increases with increasing signal skew for the two cases of simultaneous switching of lines under consideration. This is from the fact that with increasing skew, the overlapping in the transition region of the two signals decreases, so, inductive coupling reduces. It is further observed from the figure that, for opposite phase switching of inputs, the rise time is large as compared to in-phase switching at all values of signal skew for the specified range.

Same phase sw itching 160 140 120 Rise time (ps) 100 80 60 40 20 0 5 15 25 35 45 55 65 75 85 95 Skew (ps) Opposite phase sw itching

Figure 8. Rise time as function of signal skew

5. CONCLUSION
This paper addressed the power dissipation issues in inductively and capacitively coupled VLSI interconnects for simultaneously switching inputs. The results have been analyzed for equal and unequal (mismatched) rise time variations. For in-phase switching of inputs, it is observed that the maximum value of power dissipation is 14.1 mW for the specified range of rise time. However, the power dissipation is quite low for low to high switching mode. Furthermore, for opposite phase switching of inputs, the power dissipation decreases monotonically with increase in rise time of inputs equally. It has also been shown that the signal transition time is dependent on skew. It is observed that the signal rise time increases with increasing skew for simultaneously switching lines.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012 [4] smail, Y.I., Friedman, E.G, Figures of Merit to Characterize the Importance of On-Chip Inductance, IEEE Trans. on VLSI Systems, vol. 7, no. 4, pp. 442-449, 1999. Ismail, Y.I., On-chip Inductance Cons and Pros, IEEE Trans. on Very Large Scale Integration Systems, vol. 10, no. 6, pp. 685-694 , 2002. Weste, Neil H.E., Eshraghian K, Principles of CMOS VLSI Design: A System Perspective. Addison Wesley, 1998. Kaushik, B.K., Sarkar, S., Agarwal, R.P., Joshi, R.C, Crosstalk Analysis and Repeater Insertion in Crosstalk Aware Coupled VLSI Interconnects, Microelectronics International, vol. 23, no. 3, pp. 5563, 2006. Elgamel, M.A., Bayoumi, M.A, Interconnect Noise Analysis and Optimization in Deep Submicron Technology, IEEE Circuits and Systems Magazine, Fourth quarter, pp. 6-17, 2003. Roy, A. Jingye, Xu., Chowdhury, M.H, Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns, IEEE Trans. on VLSI Systems, vol. 18, no. 2, 2010.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.4, August 2012 [21] Lu, Y., Banerjee, K., Celik, M., Dutton, R.W., A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance, Proc. IEEE Custom Integrated Circuits Conf., pp. 241244, 2001
Authors D.K.Sharma received his B.E degree in Electronics Engineering from M. N. R Engineering College, Allahabad and M.E degree from University of Roorkee in 1989 and 1992 respectively. Currently, he is pursuing his Ph.D in VLSI design from NIT Kurukshetra, India. He served various PSUs in different positions for more than 8 years in Q.A & Testing /R & D departments. He joined department of Electronics and Communication Engineering, Meerut Institute of Engineering & Technology, Meerut, India in 2000 and presently working as Assistant Professor. His current interests include VLSI design, Circuit testing, Signal processing and Bio medical electronics.

B.K.Kaushik received his BE degree in Electronics and Communication Engineering from C.R.State College of Engineering, Murthal, Haryana in 1994; M.Tech in Engineering Systems, from Dayalbagh Educational Institute-Agra, in 1997; and PhD under AICTE-QIP scheme from IIT Roorkee, India. Presently, he is serving as Assistant Professor in Department of Electronics and Computer Engineering, IIT-Roorkee. He has extensively published papers in reputed journals and conferences. His research interests are in Electronic simulation, Low power VLSI Design, Microprocessor based system design and Digital Signal Processing. He is reviewer of many reputed international journals. Presently, he holds the position of Editor in Chief of International Journal on VLSI and Embedded System (IJVES) and International Journal of VLSI Design & Communication Systems (VLSICS), and Editor of Journal of Electrical and Electronics Engineering Research, Academic Journals

R.K.Sharma received B.Sc. (Engg) Degree in Electrical Engineering from Dayalbagh Educational Institute Agra in 1986, the M.Tech Degree in Electronics and Communication Engineering from Kurukshetra University Kurukshetra (through REC Kurukshetra) in 1992, and the Ph.D. Degree in Electronics from Kurukshetra University Kurukshetra (through National Institute of Technology Kurukshetra) in 2007. He has been working at NIT Kurukshetra since 1989 and is currently holding the position of Professor in Electronics and Communication Engineering Department. Dr R.K.Sharma has published several research articles in international journals and conference proceedings. He has chaired sessions in international conferences. He received ISA-VSI Technoinventor award for outstanding doctorate research in 2007. His current interest includes low power design of configurable and embedded systems. Dr R.K.Sharma is a member of IEEE, fellow IETE and life member ISTE.

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