DESCRIPTION 1551-ROF 137 5062/1 Uen A

ELU33
Contents 1 General description 2 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.4 3.5 3.5.1 3.6 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 4 4.1 4.2 4.3 4.3.1 4.3.2 4.4 5 5.1 5.2 5.3 6 Glossary Functional description Extension Line supervision Line interface Transmission Loop current feeding Filter and OVP The PCM bus System/backplane signalling Revision information Firmware Firmware download. Front connector Indicator Board inactive - Red Error - Red Flash Startup/Upgrade/Manually blocked - Alternating Red Green OK/Busy/Traffic - Green Flash OK/Idle - Green Special circuit solutions Line circuit Loop current feeding Filter and OVP OVP Filter FPGA / ASIC Technical data Power dissipation Power consumption Line current References

General description

ELU33 is a digital extension board used in the PABX ASB 501 04 and ASP 113 01. Each board can connect up to 32 digital 2 wire 1B+D extension lines. The ELU33 occupies 16 or 32 time-slots of the switch. The selection is done with a parameter of the software signal ACTVTB. If the board is activated as an ELU33, with 32 lines, the 32 timeslots are assigned as B1 channels. If ELU33 is activated in 16 line mode, only 16 time-slots are selected and only the B1 channels are used. If both B1 and B2 channels are selected only Line 0 to 15 can be used. The B

channels are situated in the following way in the backplane, first 16 B1 and then 16 B2. The ELU33 can also handle enhanced signalling on the extension line. Firmware download to both the board and the extension lines is supported. A block diagram of the board is shown below see Figure 1-1 . There is a line block (L0 - L31), for each of the 32 lines, consisting of a line circuit (one quarter of a QDASL), a transformer, an overvoltage protection, filter and some passive components. The control block consists of the device processor, SDRAM, FLASH, oscillator, reset and some glue logic. The logic for synchronization of the line circuits, the two LCA-16 with totally eight USARTs and some other logic are placed in the DP FPGA. ELU33 has a standardized interface towards the switch and the signal processor of the LIM, this interface is implemented in the FPGA. The block "loop current feeding" consists of circuits for protection and supervision of the loop current feeding of the lines. The board contains filters and over-voltage protection for each of the lines.

Figure 1-1. Block structure of the hardware

Glossary

ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array DASL Digital Adapter for Subscriber Loops DP Device Processor ELU Extension Line Unit FET Field Effect Transistor LCA Line Circuit Adapter MPU Micro Processor Unit OVP Over Voltage Protection PCB Printed Circuit Board PRPG Pseudo Random Pattern Generator QDASL Quad DASL SSW System Soft Ware USART Universal Synchronous Asynchronous Receiver Transmitter

Functional description

3.1

Extension Line supervision

The DP on the board is a 32 bit RISC processor implemented in an FPGA / ASIC. Also included are two uWIRE (synchronous serial channel), one UART/HDLC controller, one debug UART, backplane logic, reset logic, memory controller and general purpose I/O lines. The uWIRE interfaces are used to communicate with the line circuits on the board. The UART/HDLC is used for the serial interface between the board and the LIM-processor. The state of each line circuit can be read using the I/O lines and by using uWIRE. The line interface block for each individual (L0-L31) consists of one quarter of a QDASL circuit, a line transformer, OVP-circuit and a radio frequency filter circuitry.

3.2
3.2.1

Line interface
Transmission

The transmission part of the board consists of a digital line circuit and a connection to the extension line in the form of a line transformer and line termination. The digital transmission is implemented by burst signalling. That means that the line circuit of ELU33, called MASTER, and the line circuit of the unit that is connected to the line, called SLAVE, communicates time division multiplexed. The MASTER sends a "burst", consisting of 37 bits, on the line. The burst reaches the SLAVE, after having been delayed (t') and attenuated. The SLAVE waits for a time, corresponding to five bit intervals (called guard time T1), and sends a burst to the MASTER. This procedure is repeated every 250 us. see Figure 3-1

Figure 3-1. Signal propagation. One bit of the 37 bits of a burst, is used for synchronization of the receiver of the MASTER and the SLAVE respectively. 16 bits are used for the B1-channel (64 kbit/s) and 16 bits for the B2-channel. The remaining four bits are used for the 16 kbit/s signalling channel (the Dchannel). see Figure 3-2

Figure 3-2. Frame All transmitted bits, excluding the start bit of the burst, are scrambled to provide good spectral spreading with a strong timing content. The received bits are descrambled to recreate the original bit stream.

3.2.2

Loop current feeding

The digital extension line is current fed from -48 Volt power rail through the line transformer. For details see 4.2 Loop current feeding

3.2.3

Filter and OVP

The board contains filters and over-voltage protection for each of the lines. For details see 4.3 Filter and OVP

3.3

The PCM bus

The board is connected to the PCM bus of the system via the signals PCMA0 and PCMB0. The signals P0 (256 kHz) and U0 (8 kHz) are received from the system. These are fed into the LCA that generates the synchronization pulses for the QDASL circuits for clocking of the B-channels in appropriate time-slots. The clocking of the B-channels is done with 2.048 Mbit/s.

3.4.1

System/backplane signalling

The signalling towards the system is synchronous 2.048 Mbit/s HDLC. Asynchronous UART signalling is not supported.

3.5

Revision information

The board provides a secure sector in the FLASH for storage of product number and revision status. Storage of a 40 byte string is supported. The revision string can be updated in the system if an update of the board is necessary. The revision string can also be read by the system for maintenance purposes.

3.6

Firmware

The firmware ELF33 is mostly written in C language, only low level FW is written in assembler. The ELF33 has no operating system, only an easy scheduler is used. The Firmware on ELU33 is divided into two programs; application and boot code. The application program is stored compressed in Flash in order to save space in Flash and to decrease time to perform a Firmware download. The boot code cannot be compressed since it is the first code that are executed after a reset or power on.

3.6.1

Firmware download.

The ELU33 offers the possibility to do a FW download, both the application and boot code can be downloaded. The ELU33 also provides the option to do a FW download to the telephones.

3.7

Front connector

Figure 3-3. Front view

3.8

Indicator

There is a LED indicating the board status on the front. The LED can show 5 different states: Type RED RED Flash Description Board inactive (HW controlled state) ERROR - no operation possible

RED/GREEN alternating Startup/upgrade/manually blocked = controlled state but no traffic possible GREEN Flash OK/Busy/Traffic GREEN OK/Idle

3.8.1

Board inactive - Red

This state is HW controlled. It is the first state entered when the board is powered up. No FW is running on the board.

3.8.2

Error - Red Flash

When the LED is flashing red a problems has occurred in the HW. A TESTFUNCREQ signal can be sent to the board to see what the problem is.

3.8.3

Startup/Upgrade/Manually blocked - Alternating Red Green

When the LED is flashing red alternate green this is a warning. This state is also entered during FW-download.

3.8.4

OK/Busy/Traffic - Green Flash

The LED is flashing green when the board is receiving or sending signals to SSW. This is one of the normal states.

3.8.5

OK/Idle - Green

This is a normal state but the board has nothing to do, no incoming or outgoing signals.

4
4.1

Special circuit solutions

Line circuit

To implement the digital transmission a digital line circuit, QDASL, has been used. One QDASL handles four lines. This circuit has four types of interfaces: (number of blocks per circuit). 1. 2. 3. 4. Analogue, to/from the line LO/LI (4). Interface for the B-channels (1). Interface for the D-channel (1). Interface for control and status of the circuit (1).

The QDASL circuit and the functions are described more detailed in the product specification. 1301-RYT 121 322

4.2

Loop current feeding

The line feed units are designed to drive currents up to 75 mA per extension.The current limiting circuitry consists of three parts. The first stage is a permanent current limiter, it limits the maximum current that flows through the extension line to 350 mA. This will only happen when the DP is disabling the second protection stage. see Figure 4-2 The second stage protects the components on the board from overheating and switches off the linefeed to the extension line if the current limit of about 150 mA is exceeded. The DP disables this protection in 20 ms every third second. This is to boost current to the extension lines during the startup of the board and in the connection phase of a telephone. see Figure 4-1 The third stage controller receives pulses from the DP, the signal is isolated by a opto coupler. The signal goes to a binary counter and it is protected from long disable pulses from the processor with a monostable multivibrator. The counter is connected to a decoder which 16 outputs are buffered by transistors. Each of the transistor is connected to two extension lines e.g. 1&16,2&17. This technique provide a low start current from the backplane during plugin.

Figure 4-1. Boost current pulse 20 < t1 < 25 ms 2.5 < t2 < 3.5 s Imax < 400 mA Inductors are used to filter the -48 V supply. see Figure 4-2

Figure 4-2. Current feeding block

4.3
4.3.1

Filter and OVP

OVP

Each line is equipped with two kinds of over-voltage protect solutions. It will protect the board from over-voltage from the extension lines. To protect from mains voltage a PCB current limiting device on each branch is used. The strapping instruction describes how to repair the board when the PCB current limiting device has been burned. To protect from transient over-voltage a diode solution with a thyristordiode is used. It will be activated at an over-voltage of 100 V and handles over-voltages up to 1.5 kV. A diode on each line is applied for under voltage protection.

4.3.2

Filter

The radio frequency filter is a common mode LC-link, which reduces the longitudinal disturbance without affecting the transversal signals. The filter attenuation is about 20 dB at 300 kHz and 30 dB at 1 Mhz and retains there up to 300 MHz.

4.4

FPGA / ASIC

The device processor is included in an FPGA / ASIC. The circuit also consists of the two LCA-16 blocks that handle the backplane interface to the board and communication to the DASL. The DP block includes the following functions: 32 bit processor. Memory controller. SDRAM controller. Microwire. HDLC/UART. Clock generation. Linefeed clock. Reset. The two LCA-16 (Line Circuit Adapter for 16 lines) blocks includes the following functions: Power up reset. Clock and synchronization pulse generation. Address decoding. Backplane interface. Time-slot assignment. D-channel USARTs (Universal Synchronous Asynchronous Receiver and Transmitter). Control/status registers. PRPG (Pseudo Random Pattern Generator).

5
5.1

Technical data
Power dissipation

Building height 20 mm, without front 13.5 mm (6 M).

ELU33 is connected to +5 V and -48 V. The power dissipation of ELU33 with 32 telephones (D4 or D3 telephones) ELU33 5 V max 5 V typ 2.3 W 2.1 W

-48 V max 1.8 W -48 V typ 0.8 W total max 4.1 W total typ 2.9 W

OBSERVE that the table above shows the power dissipation and not the power consumption.

5.2

Power consumption

The power consumption of ELU33 with 32 telephones (D4 or D3 telephones) ELU33 5 V max 5 V typ 2.5 W 2.2 W

-48 V max 64.8 W -48 V typ 53.8 W total max 67.3 W total typ 56 W

5.3

Line current

The maximum current with retained transmission to the extension lines is 75 mA for each line. The maximum allowed line length with the cable EKKX 0.5 mm is 1 km.

References
Strapping instruction Product specification

1911- ROF 137 5062/1 Uen Rev. A Circuit Diagram 155 12- ROF 137 5062/1 Uen 1301 - RYT 121 322 1551 - CAA 158 0032 Uen Rev. A Firmware Description