Assignment 2: EE 671

Pawan kumar pareek(123070035)

Problem 2a:Id vs vgs graph is shown below

Ngspice netlist for the following problem is given below NMOS characterization *inculding tech file .include tsmc_spice_180nm.txt * the N-transistor * name D G S B model L W mn1 2 1 0 0 cmosn L=0.18u W=20u * voltage sources. vds 2 0 dc .05 vgs 1 0 dc 1.8 .dc vgs 0.0 1.8 0.1 .end

Finding VT from the graph as we can see from the graph that as the value of gate voltage increases the current remains zero till .38volt after current starts to flow so we can say that .38 is the threshold voltage.

Problem 2b:id vs vgs graph shown below

Ngspice net list is given below NMOS characterization *inculding tech file .include tsmc_spice_180nm.txt * the N-transistor * name D G S B model L W mn1 2 1 0 0 cmosn L=0.18u W=20u * voltage sources. vds 2 0 dc 1.8 vgs 1 0 dc 1.8 .dc vgs 0.0 1.8 0.1 .end Finding VT and explanation of difference observed as we did in the last part if we fine the threshold voltage it will be .41 volts which is more then the first case. The change is vt could be explained by the increase in vds because in 1st it was 50mv in 2nd case the value is 1.8 so drop on semiconductor in 2nd case is more then the first case and we know that vt is proportional to drop on semiconductor as well as depletion charge(which also increases as drop on semiconductor increases) thats why vt increases.

Problem 2c:Id vs vgs curve is show below

Ngspice net list is given below NMOS characterization *inculding tech file .include tsmc_spice_180nm.txt * the N-transistor * name D G S B model L W mn1 2 1 0 3 cmosn L=0.18u W=20u * voltage sources. vds 2 0 dc 1.8 vbs 3 0 dc -0.9 vgs 1 0 dc 1.8 .dc vgs 0.0 1.8 0.1 .end

Explanation
By the same way as we did in last two part if we calculate the threshold voltage this time we will get 0.6volts the increase in threshold could be explained by the body effect. If we apply a voltage between source and body and vsb>0 then the threshold voltage increases.

Problem 2d:Id vs vds curve is given below

Ngspice net list is given below NMOS characterization *inculding tech file .include tsmc_spice_180nm.txt * the N-transistor * name D G S B model L W mn1 2 1 0 0 cmosn L=0.18u W=20u * voltage sources. vds 2 0 dc vgs 1 0 dc 1.8 .dc vds 0.0 1.8 0.1 .end

Explanation of +ive slope:After nmos enters in saturation region still as we incress the drain voltage drain current increases because by increasing the drain voltage channel length reduces (channel length modulation) a better approximation of current in saturation could be

Which can explain +ive slope

Problem 3a:Id vs vds curve for the combination of two nmos is given below

Ngspice netlist is given below series combination *inculding tech file .include tsmc_spice_180nm.txt * the N-transistor * name D G S B model L W mn1 2 3 1 0 cmosn L=0.18u W=1.8u mn2 1 3 0 0 cmosn L=0.18u W=1.8u * voltage sources. vgs 3 0 dc 1.8 vds 2 0 dc .dc vds 0.0 1.8 0.1 .end

Problem 3b:Id vs vds curve of a single nmos with double length is given below

Ngspice netlist is given below NMOS characterization *inculding tech file .include tsmc_spice_180nm.txt * the N-transistor * name D G S B model L W mn1 2 1 0 0 cmosn L=0.36u W=1.8u * voltage sources. vds 2 0 dc vgs 1 0 dc 1.8 .dc vds 0.0 1.8 0.1 .end

Comparison As we can see from the graph for the same gate voltage the series combinatio n of two nmos offers more current then a singl e transistor.