Fair Record First Sem

M.
Tech 2010-12
LMV 108 VLSI Design and Signal Processing Lab
CYCLE I
LIST OF EXPERIMENTS
1. Adders 2. Subtracter 3. Multiplexer & Demultiplexer 4. Decoder & encoder 5. Shift register-1 6. Shift register-2 7. Counters 8. Arithmetic and Logic Unit
9. Finte State Machine Sequence Detector
Page 1 of 70 Department of Electronics and Communication Engineering
S.N.G.C.E. Kadayiruppu
M.Tech 2010-12 Experiment No: 1
LMV 108 VLSI Design and Signal Processing Lab Date: 11/11/2010
HALF ADDER, FULL ADDER AND RIPPLE CARRY ADDER

AIM
Write a verilog code to implement 1. HALF ADDER 2. FULL ADDER 3. RIPPLE CARRY ADDER
SOFTWARES USED
1. ModelSim (XE III 6.2d) 2. Xilinx (ISE 8.1i)
CIRCUIT DIAGRAM
HALF ADDER
TRUTH TABLE Inputs A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 Outputs C 0 0 0 1
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FULL ADDER
TRUTH TABLE
Inputs a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c1 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1
Outputs c0 0 0 0 1 0 1 1 1
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RIPPLE CARRY ADDER
PROGRAM
1) HALF ADDER module halfaddder (A,B,S,C); input A; input B; output S; output C; xor x1(S,A,B); and a1(C,A,B); endmodule 2) FULL ADDER module fulladder(a, b, c1, s , c0); input a; nput b; input c1; output s; output c0; wire s1,s2,s3; xor x1(s,a,b,c1); and a1(s1,a,b); and a2(s2,a,c1); and a3(s3,c1,b); or o1(c0,s1,s2,s3); endmodule
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3) RIPPLE CARRY ADDER module ripple(a, b, cin, sum, cout); input [3:0] a,b; input cin; output [3:0] sum; output cout; wire c1,c2,c3; fulladder fa0(a[0],b[0],cin,sum[0],c1); fulladder fa1(a[1],b[1],c1,sum[1],c2); fulladder fa2(a[2],b[2],c2,sum[2],c3); fulladder fa3(a[3],b[3],c3,sum[3],cout); endmodule
OBSERVATION
HALF ADDER
FULL ADDER
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RIPPLE CARRY ADDER
RESULT Verilog code for half adder, full adder and ripple-carry adder were simulated and the waveforms were observed.
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Experiment No: 2
Date: 15/11/2010
HALF SUBTRACTOR AND FULL SUBTRACTOR

AIM
Write a verilog description code to implement: 1)HALF SUBTRACTOR 2)FULL SUBTRACTOR SOFTWARES USED 3. ModelSim (SE 6.2d) 4. Xilinx (ISE8.1i) CIRCUIT DIAGRAM HALF SUBTRACTOR:
TRUTH TABLE:
Inputs A 0 0 1 1 b 0 1 0 1 d 0 1 1 0
Outputs b0 0 1 0 0
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FULLSUBTRACTOR:
TRUTH TABLE:
Inputs A 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 d 0 1 1 0 1 0 0 1
Outputs bout 0 1 1 1 0 0 0 1
PROGRAM
Page 8 of 70 Department of Electronics and Communication Engineering S.N.G.C.E. Kadayiruppu
M.Tech 2010-12
1) HALF SUBTRACTOR:
module halfsub(a, b, d, b0); input a; input b; output d; output b0; wire c; xor x1(d,a,b); not n1(c,a); and a1(b0,c,b); endmodule
2) FULL SUBTRACTOR:
module fullsub(a, b, b1, d, b0); input a; input b; input b1; output d; output b0; wire c1,c2,c3; halfsub hs0(a,b,c1,c2); halfsub hs1(c2,b1,d,c3); or o1(b0,c1,c3); endmodule
OBSERVATION
HALF SUBTRACTOR:
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FULL SUBTRACTOR:
RESULT
The verilog description codes for half subtractor and full subtractor were simulated and the waveforms were observed.
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Experiment No: 3
Date: 18/11/2010
UP-DOWN COUNTER
AIM
Write a verilog code to implement: UP-DOWN COUNTER
SOFTWARES USED
1. ModelSim (XE III 6.2d) 2. Xilinx (XE III 6.4b)
CIRCUIT DIAGRAM
TRUTH TABLE mode 1 1 1 1 0 0 0 0 0 0 clk 0 1 2 3 4 5 6 7 8 9 q[3] 0 0 0 0 0 0 0 1 1 1 q[2] 0 0 0 0 0 0 0 1 1 1 q[1] 0 0 1 1 1 0 0 1 1 0 q[0] 0 1 0 1 0 1 0 1 0 1

M.Tech 2010-12
PROGRAM
module updowncntr(clk, mode, reset, q); input clk; input mode; input reset; output reg [3:0]q; initial q=4'b0000; always @ (posedge clk) if (reset==1) q=4'b0000; else begin if(mode==1) q=q+1'b1; else q=q-1'b1; end endmodule
OBSERVATION
RESULT
Verilog code for Up-Down counter was simulated and waveforms were observed.
M.Tech 2010-12
Experiment No: 4
Date: 22/11/2010
MULTIPLEXER AND DEMULTIPLXER

AIM
Write a verilog code to implement 1. MULTIPLEXER 2. DEMULTIPLEXER
SOFTWARES USED
1. ModelSim XE III 6.4b 2. Xilinx ISE 8.1i
CIRCUIT DIAGRAM
1) MULTIPLEXER
TRUTH TABLE
Select Inputs s1 0 0 1 1 s0 0 1 0 1 Output q i0 i1 i2 i3
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2) DEMULTIPLEXER
TRUTH TABLE
Data Input d i i i i
Select Inputs s1 0 0 1 1 s0 0 1 0 1 y3 0 0 0 i
Outputs y2 0 0 i 0 y1 0 i 0 0 y0 i 0 0 0
PROGRAM
1) MULTIPLEXER module mux4_1(y,d,sel); input [3:0] d; // 4 bit data input input [1:0] sel; // 2 bit select input output y; // Selected input reg y; always @(sel,d) begin case(sel) 2'b00:y=d[0]; 2'b01:y=d[1]; 2'b10:y=d[2]; 2'b11:y=d[3];
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endcase end endmodule OBSERVATION
2) DEMULTIPLEXER module demux1_4(y,sel,d); input[1:0] sel; // 2 input select lines input d; // data to be directed to the selected output output[3:0] y; // output: the selected output line reflects input value // rest of the output lines are '0' reg [3:0] y; // Selection logic always@(sel,d) begin case(sel) 2'b00: begin y[0]<=d;y[1]<=0;y[2]<=0;y[3]<=0; end 2'b01: begin y[0]<=0;y[1]<=d;y[2]<=0;y[3]<=0; end 2'b10: begin y[0]<=0;y[1]<=0;y[2]<=d;y[3]<=0; end 2'b11:
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begin y[0]<=0;y[1]<=0;y[2]<=0;y[3]<=d; end endcase end endmodule
OBSERVATION
RESULT
Verilog code for 4:1 multiplexer and 1:4 demultiplexer were simulated and the waveforms were observed.
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Experiment No: 5
Date: 25/11/ 2010
ENCODER AND DECODER

AIM
Write a verilog code to implement 1. 4:2 ENDOER 2. 2:4 DECODER
SOFTWARES USED
1. ModelSim XE III 6.4b 2. Xilinx ISE 8.1i
CIRCUIT DIAGRAM
1. ENCODER
d0 d1 1 d2 d3
y0
4:2 Encoder
y1
TRUTH TABLE
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2. DECODER
y0
Inputs d1 0 0 1 1 TRUTH TABLE 2:4 d0 Decoder y3 0 1 0 1 0 0 0 1 y2 0 0 1 0
Outputs y1 0 1 0 0 0 0 y0 1
d0 d1
y1 y2 y3
Inputs d3 0 0 0 1 d2 0 0 1 0 d1 0 1 0 0 d0 1 0 0 0
Outputs y1 0 0 1 1 y0 0 1 0 1
PROGRAM
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1. ENCODER module encoder(d_in,d_out); input[3:0] d_in; // inputs to be encoded output[1:0] d_out; // encoded output reg [1:0]d_out; always@(d_in) begin case(d_in) 4'b0001:d_out<=2'b00; 4'b0010:d_out<=2'b01; 4'b0100:d_out<=2'b10; 4'b1000:d_out<=2'b11; endcase end endmodule
OBSERVATION
2 . DECODER module decoder1_4(d_out,d_in); input [1:0]d_in; // Input bits to be decoded output [3:0]d_out; // Decoded output reg [3:0]d_out; always @ (d_in) case(d_in)
M.Tech 2010-12
2'b00:d_out<=4'b0001; 2'b01:d_out<=4'b0010; 2'b10:d_out<=4'b0100; 2'b11:d_out<=4'b1000; endcase endmodule
OBSERVATION
RESULT Verilog code for 2:4 encoder and 4:2 decoder were simulated and the waveforms were observed.
M.Tech 2010-12
Experiment No: 6
Date: 29/11/2010
SHIFT REGISTER - 1
AIM
Write a verilog program to implement a SHIFT REGISTER to perform the following functions: serial-in-serial-out-shift-right, serial-in-serial-out-shift-left, parallel-in-parallelout.
SOFTWARES USED
1. ModelSim (XIII6.0d) 2. Xilinx (ISE8.1i)
CIRCUIT DIAGRAM
reset clock left_in right_in select parallel_in
data_out Universal Shift Register
TRUTH TABLE Select inputs S1 S0 0 0 0 1 1 0 1 1 Operation No change Right shift Left shift PIPO
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PROGRAM
module universalshift(S1, S0, Rin, Lin, Pin, CLK, RST,Q); input S1; // S1:S0 decides parallel/serial in, shift right/left operation input S0; input Rin; // Input to be shifted in for right shift input Lin; // Input to be shifted in for left shift input CLK; input RST; input [3:0]Pin; output reg [3:0]Q; always @(posedge CLK,posedge RST) begin if (RST==1) Q =4'b0000; else case({S1,S0}) 2'b00: Q=Q; // No change 2'b01: Q={Rin,Q[3:1]}; // Right shift 2'b10: Q={Q[2:0],Lin}; // Left shift 2'b11 : Q=Pin; // Parrallel-in, parallel-out endcase end endmodule
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OBSERVATION
RESULT
Verilog code for a shift register to perform serial-in-serial-out with shift-left, shiftright and parallel-in-parallel-out operations was simulated and the waveforms were observed.
M.Tech 2010-12
Experiment No: 7
Date: 02/12/2010
PARALLEL-IN-SERIAL-OUT SHIFT REGISTER

AIM
Write a verilog code to implement PARALLEL IN SERIAL OUT SHIFT REGISTER.
SOFTWARES USED
1. ModelSim (XE III 6.4b) 2. Xilinx (ISE 8.1i) CIRCUIT DIAGRAM
TRUTH TABLE Input data clk 1 D_IN [3:0] 2 3 4 q D_IN[0] D_IN[1] D_IN[2] D_IN[3]
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PROGRAM
module parallel_in_serial_out (clk,reset,d_in,q); input clk; input reset; input [3:0] d_in; // Parallel input data output reg q; // serial data out reg [3:0]d; reg [1:0] cnt; reg reg_ready; // the shift register // tracks if new data can be loaded // ready to load new data
always @(posedge clk or posedge reset) begin if(reset==1) begin q=1'b0; d=3'b0; cnt=2'b0; end else begin if (~reg_ready) // do not load new data into the shift register while shift is on begin q=d[0]; d=d>>1; cnt=cnt+2'b1; // count the number of bits shifted end else begin d=d_in; cnt=3'b0; end end end always @ (*) begin if (cnt==2'b11) // Once all bits of a word are shifted out, indicate ready to load new data reg_ready=1'b1; else reg_ready=1'b0; end endmodule
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OBSERVATION
RESULT
Verilog code for shift register to perform parallel-in-serial-out with right shift was simulated and the waveforms were observed.
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Experiment No: 8
Date: 09/12/2010
SEQUENCE DETECTOR
AIM
Write a verilog program to detect the following sequence 0110111 and assert the output high if the next bit in the sequence is 1 immediately after the sequence is detected.
SOFTWARES USED
STATE DIAGRAM
`` 0/0 0/0 ` 1/0 0/0
B_Got0
0/0
1/0
C_Got01
1/0
D_Got01 1
0/0
E_Got011 0
1/0
A_Wait0
0/0 1/0
H_Got011011 1
0/0
1/0
F_Got0110 1
1/0
G_Got011 011
1/0
0/0
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PROGRAM
module sequence_detector (clock_in, reset_n, d_in, d_out); // port definitions input clock_in, reset_n, d_in; output d_out; //Definition of states, self explanatory parameter [2:0] A_Wait0 = 3'd0, // Waiting for the first 0 of the sequence B_Got0 = 3'd1, // Received the first 0, waiting for first 1 C_Got01 = 3'd2, // Received the pattern "01" D_Got011 = 3'd3, // Received the pattern "011" E_Got0110 = 3'd4, // Received the pattern "0110" F_Got01101 = 3'd5, // Received the pattern "01101" G_Got011011 = 3'd6, // Received the pattern "011011" H_Got0110111 = 3'd7; // Received the pattern "0110111" reg d_out; reg [2:0] Sreg, Snext; // state register and next state
// Current state is assigned the value of next_state at the clock edge always @ (posedge clock_in , negedge reset_n) if (!reset_n) Sreg <= A_Wait0; else Sreg <= Snext; always @ (Sreg, d_in) // Next-state logic begin case (Sreg) A_Wait0: // Receive '0' --> Got to next state, else wait for 0 if (~d_in) Snext = B_Got0; else Snext = A_Wait0; B_Got0: // Got first 0 in sequence, go to next state, on receiving 1 if (d_in) // remain in the same state, if 0 is received Snext = C_Got01; else Snext = B_Got0; C_Got01: // Got the input pattern "01", go to D_Got011 state on '1' if (d_in) // else, go to B_Got0 state on '0' Snext = D_Got011; else
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Snext = B_Got0; D_Got011: // Got "011", go to E_Got0110 on receiving '0' if (~d_in) // else, go to A_Wait0 state on '1' Snext = E_Got0110; else Snext = A_Wait0; E_Got0110: // Got "0110" pattern, go to B_Got0 on receiving '0' if (d_in) // else, go to F_01101 on receiving '1' Snext = F_Got01101; else Snext = B_Got0; F_Got01101: // Got "01101" pattern, go to G_Got011011 on receiving '1' if (d_in) // go to B_Got0 on receiving '0' Snext = G_Got011011; else Snext = B_Got0; G_Got011011: // Got "011011" pattern, go to H_Got0110111 on receiving '1' if (d_in) // else, go to E_Got0110 on receiving '0' Snext = H_Got0110111; else Snext = E_Got0110; H_Got0110111: // Got the final bit of the pattern to be detected, if (d_in) // Go to B_Got0 on receiving a '0', else A_Wait0 on receiving '1' Snext = A_Wait0; else Snext = B_Got0; default: Snext = A_Wait0; endcase end // output is the value on the input when the pattern "0110111" is just detected always @ (*) begin case (Sreg) H_Got0110111: d_out <= d_in; default: d_out <= 1'b0; endcase
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end endmodule STIMULUS module tb_seq_detect (); reg tb_clock, tb_reset_n, tb_d_in; wire tb_d_out; wire [49:0] expectd, in_data; // array storing the input data sequence and expected output integer i; // array index //initialize the input data sequence and expected output arrays assign in_data = 50'b00110110110111101110110111000111111011011110110111; assign expectd = 50'b00000000000001000000000000000000000000000100000001; sequence_detector DUT ( .clock_in(tb_clock), .reset_n (tb_reset_n), .d_in (tb_d_in), .d_out (tb_d_out) ); // instantiate sequence_detector module task check_output; // To check output value and print info if wrong input bit_num; integer bit_num; begin if (expectd[bit_num] != tb_d_out) begin $display($time,"ERROR: expected %d, received %d", expectd[bit_num] , tb_d_out); $stop(1); end end endtask // Free running clock generation of 100KHz, 50% duty-cycle always begin #5 tb_clock = 1'b0; #5 tb_clock = 1'b1; end // Initialize with reset active initial begin
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tb_reset_n = 1'b0; #25 tb_reset_n = 1'b1; end // Transfer data from the array to the DUT at each clock initial begin i = 49; // initialize the array index end always @ (posedge tb_clock, negedge tb_reset_n) begin if (!tb_reset_n) tb_d_in = 1'b0; else if (i >= 0) begin tb_d_in = in_data[i]; i = #2 i - 1; end end // Check the output by comparing with the expected value from the array always @ (tb_d_out) begin check_output (i+1); // the index advances at each clock edge, so, the output data should be the previous one end endmodule
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OBSERVATION
RESULT
Verilog code for a FSM-based sequence detector to detect the sequence 0110111 was simulated and the waveforms were observed.
M.Tech 2010-12 Experiment No: 9
LMV 108 VLSI Design and Signal Processing Lab Date: 16/12/2010
ARITHMETIC LOGIC UNIT

AIM
Write a verilog program to implement an ALU functionality for computing AND, OR, INVERT, ADD on two single-bit input variables and output the result on the output line.
SOFTWARES USED
CIRCUIT DIAGRAM
A B OUT ALU
S1:S0
2:4 Decoder
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PROGRAM
module decoder_2to4(d,y); // 2:4 Decoder logic implementation input[1:0] d; output[3:0] y; wire d0bar,d1bar; not(d0bar,d[0]); not(d1bar,d[1]); and(y[0],dobar,d1bar); and(y[1],dobar,d[1]); and(y[2],d[0],d1bar); and(y[3],d[0],d[1]); endmodule // ALU block module alu_block(a,b,d,out); input a,b; // Arguments data inputs input [1:0]d; // Function select to ALU output out; // Output of selected function wire out1,out2,out3,out4,out5,out6; wire and0,or0,add,not0; wire[3:0] dec0; // Function Implementation or(or0,a,b); // OR and(and0,a,b); // AND xor(add,a,b); // ADD not(not0,a); // INVERT decoder_2to4 d1(.d(d),.y(dec0)); // Decode the function select // Output of the desired function and(out1,dec0[0],and0); and(out2,dec0[1],or0); and(out3,dec0[2],add); and(out4,dec0[3],not0); or(out5,out1,out2); or(out6,out3,out4); or(out,out5,out6); endmodule
// dec0[0] = 1 => AND is selected // dec0[1] = 1 => OR is selected // dec0[2] = 1 => ADD is selected // dec0[3] = 1 => INVERT is selected // Direct the selected function result to // the output of ALU // Final output
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OBSERVATION
RESULT
Verilog code for an ALU to perform inversion, addition, AND and OR functions was simulated and the waveforms were observed.
M.Tech 2010-12
CYCLE II
LIST OF EXPERIMENTS
1. Generation of signals 2. Operation of signal 3. Response of system 4. Linear convolution & Circular convolution 5. DFT &IDFT 6.Butterworth Digital Low Pass Filter 7. Butterworth Digital High Pass Filter 8. Chebyshev Digital Low Pass Filter 9. Chebyshev Digital High Pass Filter 10. FIR Low Pass Filter Using Window Technique
M.Tech 2010-12
Experiment No : 1
Date:07/01/2011
1. GENERATION OF SIGNALS
AIM
To generate the following signals using MATLAB a) b) c) d) e) f) unit sample sequence unit step sequence ramp signal sine wave cosine wave exponential signal
THEORY A signal is defined as any physical quantity that varies with time, space, or any other independent variable. Classification of signals
1) Unit sample sequence : A unit sample sequence (unit impulse) is defined as
(n) = 1 for n = 0 = 0 for n 0 2) Unit step sequence : A unit step sequence is defined as u (n) = 1 for n 0 = 0 for n<0 3) Unit ramp sequence : A unit ramp sequence is defined as r (n) = n for n 0 = 0 for n<0 4) Exponential sequence : An exponential signal is a sequence of the for X(n)=n
FUNCTIONS USED
M.Tech 2010-12
Sin(x): Calculates sinx with x in radians Cos(x): Calculates cosine x with x in radians Exp(x): Calculates e^x
ALGORITHM
Step1: start Step 2: enter the length of sequence from -5 to 5 Step3: for sample signal output is obtained when input n=0 Step4: for step signal output is high only when n>=0 Step6: for ramp signal output is equal to input Step7: sine wave is generated using the function sin(n) Step8: cosine wave is generated using cos(n) Step9: exponential wave is generated using exp(x)
PROGRAM
clc; clear all; close all; n=-5:5; x= [n==0]; //unit sample sequence definition.
Subplot (3,3,1); stem (n,x); title('unit sample sequence'); xlabel('n'); ylabel('x(n)'); x=[n>=0]; subplot(3,3,2);
//unit step sequence
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stem(n,x); title('unit step sequence'); xlabel('n'); ylabel('x(n)'); x=n; subplot(3,3,3); stem(n,x); title('unit ramp sequence'); xlabel('n'); ylabel('x(n)'); n=-5:.5:5 a=5; x=a*sin(n); subplot(3,3,4); stem(n,x); title('sine wave'); xlabel('n'); ylabel('sin (x)'); n=-5:.5:5 a=5; x=a*cos(n); subplot(3,3,5); stem(n,x); title('cosine wave'); xlabel('n'); ylabel('cos (x)'); x= exp (n); //exponential signal definition
// unit ramp squence
//definition of sine wave
//definition of cosine signal
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subplot(3,3,6); stem(n,x); title('exponential wave'); xlabel('n'); ylabel('exp(n)');
OUTPUT
u n it s a m p le s e q u e n c e 1 1 u n it s te p s e q u e n c e 5 u n it ra m p s e q u e n c e
x (n)
x(n)
0 -5
0 n s in e w a ve
0 -5
x (n) 0 n c o s in e w a ve 5
0 .5
0.5
-5 -5
0 n e x p o n e n t ia l w a ve
150 100
c os (x)
ex p(x ) 0 n 5
sin (x)
50 0 -5
-5 -5
0 n
-5 -5
0 n
RESULT
Generated the given sequences using MATLAB
Experiment No: 2
Date 12/01/2011
M.Tech 2010-12
2.OPERATIONS ON INPUT SIGNAL

AIM
a) Generate and plot each of the following sequences over the indicated interval. 1) x(n) = 2(n+2)- (n-4) : -5<=n<=5 0<=n<=20
2)x(n) = [u(n)-u(n-10)]+10exp(-3(n-10))[u(n-10)-u(n-20)] b) Let x(n) = u(n)-u(n+10) Decompose x(n) into even and odd components.
THEORY
A signal s(t) or s(n) is called even signal if it is identical to its folded(time-reversed) counter part .Time-reversal of a signal means its reflection about the origin(t=0 or n=0) For continous-time signal s(t), If s(-t)=s(t),then s(t) is even signal If s(-t)=-s(t),then s(t) is odd signal For discrete-time signal s(n), If s(-n)=s(n),then s(n) is even signal If s(-n)=-s(t),then s(n) is odd signal An odd signal must be zero at t=0 or n=0.Even and odd signals are also called symmetric and anti-symmetric signals respectively. Any signal can be decomposed into a sum of two signals, one of which is even(symmetric) and other odd(asymmetric). Even[s(t)]=1/2[s(t)+s(-t)] Odd[s(t)]= 1/2[s(t)-s(-t)] where Even[s(t)] and Odd[s(t)] are called even and odd parts of s(t) respectively.
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ALGORITHM
a) i) Step 1:select range of n as -5 to 5 Step 2: x=2 for n=-2 Step 3: y=1 for n=4 Step 4: z=x-y Step 5: plot z as a function of n Step 6: stop ii) Step 1:select range from 0 to 20 Step 2: d=1 for n>=0 Step 3: e=1 for n>=10 Step 4: f=10*e^-3(n-10) Step 5: g=1 for n>=20 Step 6: h=d-e Step 7:i=e-g Step 8: j=(n*h)+(f*i) Step 9: plot j as a function of n Step 10:stop b) Step1:select range of n as -20 to 20 Step 2:a=1 for n>=0 Step 3:b=1 for n>=10 Step 4:e=a-b Step 5:Lflip c and store in d. Step 6:for odd perform (c - d)/2 Step 7:for even perform (c + d)/2 Step 8:plot even and odd signals Step 9:stop PROGRAM // Problem a -1 n=-5:5 x =2*[n = = -2] // signal definition for 2 (n+2) subplot(2,3,1) stem(n,x) title(x) xlabel('n') ylabel('x(n)') y = [n==4] //signal dfinition for (n-4) subplot(2,3,2) stem(n,y) title(y) xlabel('n')
M.Tech 2010-12
ylabel('x(n)') z=x-y //signal gnration of 2 (n+2)- (n-4) subplot(2,3,3) stem(n,z) title(z) xlabel('n') ylabel('x(n)') //Problem a-2 n1=0:20 d= [n1>=0] //signal definition for u(n) e= [n1>=10] //signal definition for u(n-10) f=10*exp (-.3*(n1-10)) // signal definition for 10 exp(-3(n-10)) g= [n1>=20] // signal definition u(n-20) h=d-e // generation of u(n)-u(n-10) i=e-g // generation of u(n-10)-u(n-20) j=h+ (f.*i) //generation of [u(n)-u(n-10)]+10exp(-3(n-10)[u(n-10)-u(n-20)] subplot(2,3,4) stem(n1,j) title(j)
xlabel('n') ylabel('x(n)')
Problem b n2=-10:10 a=[n2>=0] // signal definition for u(n) b=[n2>=10]// signal definition for u(n-10) c=a-b // signal definition for u(n)- u(n-10) d=fliplr (c) x1=(c+d)/2 // to find even function subplot(2,3,5) stem(n2,x1)
title('even function') xlabel('n') ylabel('x(n)')
y1=(c-d)/2 // to find odd function subplot(2,3,6) stem(n2,y1)

title('odd function') xlabel('n') ylabel('x(n)')
M.Tech 2010-12
OUTPUT
x 2 1.5 x(n) x(n) 1 0.5 0 -5 0 n j 5 1 0.8 x(n) 0.6 0.4 0.2 0 -5 0 5 n even function -1 -5 0 5 n odd function 1 0 y 2 z
10 8 x(n) x(n) 6 4 2 0 0 10 n 20
1 0.8 x(n) 0 n 10 0.6 0.4 0.2 0 -10
0.5
-0.5 -10
0 n
10
RESULT
Thus performed the operations on input signals and generated the sequences
Experiment No: 3
Date 14/01/2011
M.Tech 2010-12
3. RESPONSE OF SYSTEM
AIM
a) Given a system with the following difference equation y (n) - y (n-1) +0.9 y (n-2) = x (n) a) Calculate and plot the impulse response h (n) at n=-20 to 100 b) Also calculate and plot step response at n=-20......100 in the system.
THEORY
Output of a discrete time LTI system when we apply unit impulse sequence (n) as input is called unit- impulse response Where, unit impulse sequence, (n) is defined as (n)= 1, n=0 0, n0 The step response of a system in a given initial state consists of the time evolution of its outputs when its control inputs are step functions
ALGORITHM
Step 1: START Step 2: Select range of n between -20 to 100; Step 3: The impulse response of a system is given by Z= filter (b, a, x); Where b: coefficient of x (n); a :coefficient of y(n); x : impulse step function Step 4: Plot the response Step 5: Plot the step response of the system Step 6: Stop
PROGRAM
M.Tech 2010-12
n=-20:100 b= [1] // coefficient of x(n) a= [1 -1 .9] // coefficient of y(n) x= [n==0] // unit impulse response s= filter (b,a,x) //impulse response of the system subplot (2,1,1) stem (n ,s) title(impulse response) xlabel('n(impulse response)') ylabel('x(n)') x=[n>=0] s=filter(b,a,x) //step responseof the system subplot(2,1,2) stem(n,s) title(step response) xlabel('n(step response)') ylabel('x(n)')
M.Tech 2010-12
OUTPUT
impulse response 1 0.5 h(n) 0 -0.5 -1 -20 0 20 40 60 n(impulse reponse) 80 100
2.5 2 h(n) 1.5 1 0.5 0 -20 0 20 40 n(step response) 60 80 100
RESULT Calculate and plot the impulse response and step response
Experiment No: 4
Date 19/01/2011
M.Tech 2010-12
4. LINEAR CONVOLUTION AND CIRCULAR CONVOLUTION

AIM
Find linear convolution and circular convolution of two sequences with and without in built function.
THEORY
Linear convolution Let x(n) be the input to LTI system and y(n) be the output of system.Let h(n) be the response of the system to an impulse. The output y(n) can be obtained by convolving the impulse response h(n) and the signal x(n)
y(n) =x(k)h(n-k) - The above equation that gives the response y(n) of an LTI system as a function of input signal x(n) and the impulse response h(n) is called a convolution sum. Circular convolution Let x1(n) and x2(n) are finite duration sequences both of same length with DFTs X1(k) and X2(k) .We can find a sequence x3(n) for which DFT is X3(k) where
X3(k) =X1(k) X2(k) The sequenxe x3(n) can be obtained by circularly convolving x1(n) and x2(n).ie X3(n) = X1(n) x X2(n) Linear convolution and circular convolution using matrix method
M.Tech 2010-12
Circular convolution Let us consider two finite duration sequences x(n) and h(n).The duration of x(n) is L samples and that of h(n) is M samples then circular convolution of x(n) and h(n) will contain N=Max (L,M) samples. In matrix method circular convolution of two sequences x(n) and h(n) can be obtained by representing the sequence in matrix form
Linear convolution using matrix method Let us consider two finite duration sequences x(n) and h(n).The duration of x(n) is L samples and that of h(n) is M samples then linear convolution of x(n) and h(n) will have N= L+M-1 samples . Increase length of sequences x(n) and h(n) to L+M-1 and then do the matrix multiplication as shown above to get the linear convolution.
ALGORITHM
Step1. Enter the sequences x(n) and h(n) Step2. Find length of both the sequences Step3. Find linear convolution using inbuilt function conv(x(n),h(n)) Step4. Display the result. Step5. Find length of two sequence.[L=length of x(n),M=length of h(n) ]
M.Tech 2010-12
Step6.Append M-1 zeros in x(n) and L-1 zeros in h(n)( linear convolution of x(n) and h(n) will have N= L+M-1 samples] Step7.Find transpose of h(n) and multiply it with x(n).this gives linear convolution Step8.Display the result. Step9: Append zeroes toequalise the two sequence Step10: Same matrix operation as linear convolution Step11: display
PROGRAM
X1=input(enter the first sequence); X2=input(enter the second sequence); y=conv(X1,X2); display(linear convolution with function); display(y); L1=length (X1); L2=length(X2); K=L1+L2-1; A=[X1,zeros(1,L2-1)]; B=[X2,zeros(1,L1-1)]; for(j=1:K) C=circshift(B,j-1); D(:,j)=C; end; display(D); Q=D*A; display(linear convolution without function); display(Q);
M.Tech 2010-12
L=max(L1,L2); X=[X1,zeros(1,L-L1)] H=[X2,zeros(1,L-L2)]; for(i=1:L) Z1=circshift(H,i-1); W(:,i)=Z1; end; O=(W*X); display(Circular convolution); display(O);
OUTPUT
Enter the first sequence [1 2 3] Enter the second sequence [4, 5] Linear convolution with function [4 13 22 15] Circular convolution [19 33 22] Linear convolution without inbuilt function [[4 13 22 15]
RESULT
Obtained linear convolution and circular convolution of two sequences with and without inbuilt function.
Experiment No: 5
Date 21/01/2011
M.Tech 2010-12
5. DFT AND IDFT USING DEFINITION

AIM
To calculate the DFT and IDFT of input sequence
THEORY
DFT transforms one function into another, which is called the frequency domain representation, or simply the DFT, of the original function (which is often a function in the time domain). But the DFT requires an input function that is discrete and whose non-zero values have a limited (finite) duration. The DFT is obtained by sampling one period of the Fourier transform at a finite number of frequency points. Apart from determining the frequency content of a signal, DFT is used to perform linear filtering operations in the frequency domain. The DFT of a finite duration sequence x n is defined as
The IDFT of X k is defined as
ALGORITHM
1. 2. 3. 4. Start Input the sequence x[n] Input the value of N Implement the DFT of x[n] using the following equations w=exp(-j*2*pi/N) X(K)=X(K)+x(n)*w^(K-1)(n-1)
M.Tech 2010-12
5. Display the DFT X(K) 6. Implement the IDFT of X(K) using the following equations y(n)=y(n)+X(K)*w^(-(K-1)(n-1)) y=y/N 7. Display the IDFT y(n) 8. Stop
PROGRAM
clc; clear all; close all; x=input('Enter the input sequence x[n]= '); N=input('Enter the value of N= '); w=exp(-j*2*pi/N); for K=1:N X(K)=0; for n=1:N X(K)=X(K)+x(n)*w^((K-1)*(n-1)); end end display(X); for n=1:N y(n)=0; for K=1:N y(n)=y(n)+X(K)*w^(-(K-1)*(n-1)); end end
M.Tech 2010-12
y=y/N; display(y);
OUTPUT
Enter the input sequence x[n]=[1 1 0 0] Enter the value of N= 4 X(K)=[2 1-i 0 1+i] y(n)=[1 1 0 0]
RESULT
Calculated the DFT and IDFT of input sequence.
Experiment No :6
Date: 28/1/11
M.Tech 2010-12
6.BUTTERWORTH DIGITAL LOW-PASS FILTER

AIM
a) Generate and plot each butterworth digital low-pass filter with given specifications. 1) Pass band attenuation - 0.4 db 2) Stop band attenuation - 30 db 3) Pass band frequency - 400 Hz 4) Stop band frequency - 800 Hz 5) Sampling frequency - 2000 Hz
THEORY
The Butterworth filter designed to have a flat frequency response in the pass band so that it is also termed a maximally flat magnitude filter. It was first described by the British engineer Stephen Butterworth ,hence the name. Butterworth showed that low pass filters could be designed whose frequency response (gain) was
where is the angular frequency in radians per second and n is the number of reactive elements (poles) in the filter. Butterworth only dealt with filters with an even number of poles Butterworth low pass filter is given in terms of the transfer function H(s) as;
n = order of filter c = cutoff frequency G0 is the DC gain (gain at zero frequency
M.Tech 2010-12
ALGORITHM
1. Start 2. Input the Parameters 3. Converting frequency into radians 4. 5. 6. 7. PROGRAM clc; clear all; rp= input ('Enter the passband ripple : '); rs= input ('Enter the stopband ripple : '); wp= input ('Enter the passband frequency : '); ws= input ('Enter the stopband frequency : '); fs= input ('Enter the sa w1 = 2*wp/fs; w2 = 2*ws/fs; [n,wn]= buttord (w1,w2,rp,rs); [b,a]=butter(n,wn); w= 0:0.01:pi; [h,om]= freqz(b,a,w); m=20*log10(abs(h)); an=angle(h); subplot(2,1,1);
Calculate Cutoff frequency and order of the filter Calculate System function of the filter Display the response Stop
M.Tech 2010-12
plot(om/pi,m); ylabel('Gain in dB'),xlabel('Normalised frequency'),title('MAGNITUDE PLOT'); subplot(2,1,2); plot(om/pi,an); xlabel('Normalised frequency'),ylabel('Phase in radians'),title('PHASE PLOT');
OUTPUT
Enter the passband ripple : .15 Enter the stopband ripple : 60 Enter the passband frequency : 1500 Enter the stopband frequency : 3000 Enter the sampling frequency : 7000
M.Tech 2010-12
RESULT A butterworth low pass filter for given specifications was generated
M.Tech 2010-12
Experiment No :7
Date:28/01/2011
7.BUTTERWORTH DIGITAL HIGH-PASS FILTER

AIM
a) Generate and plot each butterworth digital high-pass filter with given specifications. 1) Pass band attenuation - 0.4 db 2) Stop band attenuation - 30 db 3) Pass band frequency - 800 Hz 4) Stop band frequency - 400 Hz 5) Sampling frequency - 2000 Hz
THEORY
The Butterworth filter designed to have a flat frequency response in the pass band so that it is also termed a maximally flat magnitude filter. It was first described by the British engineer Stephen Butterworth ,hence the name. The transition band is more in butterworth filter.The poles of a butterworth filter lie on a circle and the number of poles is more compared to Chebyshev filter. The transfer function of a Butterworth filter is given by H(j) = 1/(1+j(/c)N The order of the filter N=log(10 0.1s -1/ 10 0.1p-1) log (s/p)
ALGORITHM
1. Start 2. Input the Parameters 3. Converting frequency into radians 4. Calculate Cutoff frequency and order of the filter 5. Calculate System function of the filter 6. Display the response 7. Stop
M.Tech 2010-12
PROGRAM
clc; clear all; rp= input ('Enter the passband ripple : '); rs= input ('Enter the stopband ripple : '); wp= input ('Enter the passband frequency : '); ws= input ('Enter the stopband frequency : '); fs= input ('Enter the sampling frequency : '); w1 = 2*wp/fs; w2 = 2*ws/fs; [n,wn]= buttord (w1,w2,rp,rs); [b,a]=butter(n,wn,'high'); w= 0:0.01:pi; [h,om]= freqz(b,a,w,'whole'); m=20*log10(abs(h)); an=angle(h); subplot(2,1,1); plot(om/pi,m); ylabel('Gain in dB'),xlabel('Normalised frequency'),title('MAGNITUDE PLOT'); subplot(2,1,2); plot(om/pi,an); xlabel('Normalised frequency'),ylabel('phase in radians'),title('PHASE PLOT');
M.Tech 2010-12
OUTPUT
Enter the passband ripple : .15 Enter the stopband ripple : 60 Enter the passband frequency : 1500 Enter the stopband frequency : 3000 Enter the sampling frequency : 7000
RESULT A butter worth high pass filter for given specifications was generated
M.Tech 2010-12
Experiment No :8
Date: 02/02/2011
8.CHEBYSHEV DIGITAL LOW-PASS FILTER

AIM
a) Generate and plot each chebyshev digital low-pass filter with given specifications. 1) Pass band attenuation - 1 db 2) Stop band attenuation 15 db 3) Pass band frequency - 0.2* pi Hz 4) Stop band frequency - 0.3* pi Hz 5) Sampling frequency - pi Hz
THEORY
Chebyshev filters has magnitude response that exhibits ripple either in pass band or in stop band according to the type. Chebyshev type-I filters exhibits equiripple behavior in the pass band and a monotonic characteristics in the stop band. The gain (or amplitude) response as a function of angular frequency of the nth order low pass filter is
ALGORITHM
M.Tech 2010-12
PROGRAM
clear all; rp= input ('Enter the passband ripple :'); rs= input ('Enter the stopband ripple :'); wp= input ('Enter the passband frequency:'); ws= input ('Enter the stopband frequency:'); fs= input ('Enter the sampling frequency:'); w1 = 2*wp/fs; w2 = 2*ws/fs; [n,wn]= cheb1ord (w1,w2,rp,rs); [b,a]= cheby1(n,rp,wn); w= 0:0.01:pi; [h,om]= freqz(b,a,w); m=20*log10(abs(h)); an=angle(h); subplot(2,1,1); plot(om/pi,m); ylabel('Gain in dB'),xlabel('Normalised frequency'),title('MAGNITUDE PLOT'); subplot(2,1,2); plot(om/pi,an); xlabel('Normalised frequency'),ylabel('Phase in radians'),title('PHASE PLOT');
M.Tech 2010-12
OUTPUT
Enter the passband ripple :.2 Enter the stopband ripple :45 Enter the passband frequency:1300 Enter the stopband frequency:1500 Enter the sampling frequency:10000
RESULT
A Chebyshev lowpass filter for given specifications was generated
M.Tech 2010-12
Experiment No :9
Date: 02/02/2011
9.CHEBYSHEV DIGITAL HIGH-PASS FILTER

AIM
a) Generate and plot each chebyshev digital high-pass filter with given specifications. 1) Pass band attenuation - 1 db 2) Stop band attenuation 15 db 3) Pass band frequency - 0.2* pi Hz 4) Stop band frequency - 0.3* pi Hz 5) Sampling frequency - pi Hz
THEORY
Chebyshev filters has magnitude response that exhibits ripple either in pass band or in stop band according to the type. Chebyshev type-I filters exhibits equiripple behavior in the pass band and a monotonic characteristics in the stop band. The transfer function of Chebyshev filter is given by H(j) = 1/ [1+jCN(/p)] Where is a parameter of the filter related to ripple in the pass band and CN(x) is the Nth order chebyshev polynomial. The order N of a chebyshev filter is given by N = cosh-1 (10 0.1s- 1)/ (10 0.1p-1) cosh-1 (s/p)
ALGORITHM
M.Tech 2010-12
PROGRAM
clc; clear all; rp= input ('Enter the passband ripple :'); rs= input ('Enter the stopband ripple :'); wp= input ('Enter the passband frequency:'); ws= input ('Enter the stopband frequency:'); fs= input ('Enter the sampling frequency:'); w1 = 2*wp/fs; w2 = 2*ws/fs; [n,wn]= cheb1ord (w1,w2,rp,rs); [b,a]= cheby1(n,rp,wn,'high'); w= 0:0.01/pi:pi; [h,om]= freqz(b,a,w); m=20*log10(abs(h)); an=angle(h); subplot(2,1,1); plot(om/pi,m); ylabel('Gain in dB'),xlabel('Normalised frequency'),title('MAGNITUDE PLOT'); subplot(2,1,2); plot(om/pi,an); xlabel('Normalised frequency'),ylabel('phase in radians'),title('PHASE PLOT');
M.Tech 2010-12
OUTPUT
Enter the passband ripple :0.3 Enter the stopband ripple :60 Enter the passband frequency:1500 Enter the stopband frequency:2000 Enter the sampling frequency:9000
RESULT
A Chebyshev high pass filter for given specifications was generated
M.Tech 2010-12
Experiment No :10
Date: 04/02/2011
10.FIR LOW PASS FILTER USING WINDOWING TECHNIQUE

AIM
To design a 25-tap lowpass filter with cutoff frequency 0.5pi using hanning window
THEORY
The FIR filters are of non recursive type where by the present output sample depends on the present input sample and previous input samples. There are three methods for designing FIR filter : Windowing technique, frequency sampling method and optimal design method. One possible way of obtaining FIR filter is to truncate the infinite Fourier series at n=(N1)/2 where N is the length of the desired sequence. But abrupt truncation of the fourier series will result in oscillations in pass band and stop band. To reduce these oscillations, the fourier coefficients of the filter are modified by multiplying the infinite impulse response by a finite weighing sequence w(n) called a window, where w(n) = w(-n) 0 = 0 for|n|<= (N-1)/2 for |n|> (N-1)/2
After multiplying w(n) by hd(n), a finite duration sequence h(n) that satisfies the desired magnitude response h(n) = hd(n)w(n) = 0 The equation for Hanning window is given by wHn(n) = 0.5+0.5 cos (2n)/ (N-1) =0 for (N-1)/2n(N-1)/2 otherwise for all |n|<(N-1)/2 for |n|>(N-1)/2
ALGORITHM
M.Tech 2010-12
1. Start 2. Calculate filter coefficients 3. Calculate hanning window sequence 4. Stop
PROGRAM
clear all; wc=.5*pi; N=25; alpha=(N-1)/2; eps=.001; n=0:1:N-1; hd=(sin(wc*(n-alpha+eps)))./(pi*(n-alpha+eps)); wr=hann(N); hn=hd'.*wr; w=0:0.01:pi; h=freqz(hn,1,w); plot(w/pi,abs(h),'red');
M.Tech 2010-12
RESULT A FIR filter for given specifications was generated

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M.

LMV 108 VLSI Design and Signal Processing Lab

Page 1 of 70 Department of Electronics and Communication Engineering

M.Tech 2010-12 Experiment No: 1

HALF ADDER, FULL ADDER AND RIPPLE CARRY ADDER

TRUTH TABLE Inputs A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 Outputs C 0 0 0 1

Page 2 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Page 3 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

RIPPLE CARRY ADDER

LMV 108 VLSI Design and Signal Processing Lab

Page 5 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

RIPPLE CARRY ADDER

Page 6 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

HALF SUBTRACTOR AND FULL SUBTRACTOR

Page 7 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

LMV 108 VLSI Design and Signal Processing Lab

Page 9 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Page 10 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

TRUTH TABLE mode 1 1 1 1 0 0 0 0 0 0 clk 0 1 2 3 4 5 6 7 8 9 q[3] 0 0 0 0 0 0 0 1 1 1 q[2] 0 0 0 0 0 0 0 1 1 1 q[1] 0 0 1 1 1 0 0 1 1 0 q[0] 0 1 0 1 0 1 0 1 0 1

Page 11 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Page 12 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

MULTIPLEXER AND DEMULTIPLXER

Page 13 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

LMV 108 VLSI Design and Signal Processing Lab

endcase end endmodule OBSERVATION

LMV 108 VLSI Design and Signal Processing Lab

begin y[0]<=0;y[1]<=0;y[2]<=0;y[3]<=d; end endcase end endmodule

Page 16 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Date: 25/11/ 2010

ENCODER AND DECODER

Page 17 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Inputs d1 0 0 1 1 TRUTH TABLE 2:4 d0 Decoder y3 0 1 0 1 0 0 0 1 y2 0 0 1 0

LMV 108 VLSI Design and Signal Processing Lab

LMV 108 VLSI Design and Signal Processing Lab

2'b00:d_out<=4'b0001; 2'b01:d_out<=4'b0010; 2'b10:d_out<=4'b0100; 2'b11:d_out<=4'b1000; endcase endmodule

Page 20 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

reset clock left_in right_in select parallel_in

data_out Universal Shift Register

Page 21 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Page 22 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

Page 23 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

PARALLEL-IN-SERIAL-OUT SHIFT REGISTER

Page 24 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab

LMV 108 VLSI Design and Signal Processing Lab

Page 26 of 70 Department of Electronics and Communication Engineering

LMV 108 VLSI Design and Signal Processing Lab