P.E.

S INSTITUTE OF TECHNOLOGY
(AUTONOMOUS INSTITUTE UNDER VTU)

100 Feet Ring Road, BSK III Stage, Bengaluru 560 085

Project proposal On

Design and verification of CMOS quaternary to analog converters

Submitted by:

Ashwath S M (1PI08EC024) Avinash M (1PI08EC026) Krishna Samethadka (1PI08EC054)

Under the Guidance of:

Ms. Nagamani
Lecturer, Department of ECE PES Institute of Technology, Bengaluru

Introduction
Integrated circuit (IC) design has been evolving from ages of small scale integration (SSI), which involves tens of transistors to the present days of very large scale integration (VLSI), that involves millions of transistors on a single chip. Several different circuit technologies have been used in this journey of IC design evolvement. Metal oxide semi-conductors (MOS) technology offered several key benefits along with an easy fabrication of basic transistor switch and allowed the scaling (sizing down the size of transistors) resulting in IC size reduction periodically. Complementary metal oxide semiconductor (CMOS) technology brought the low power consumption advantage which revolutionized semiconductor design applications. While analog designs heavily rely on continuous signal response of transistors, digital designs rely on discrete logic levels of the signals. The introduction microprocessor designs along with their surrounding applications significantly increased the realization of complex real world applications using digital ICs for the past couple of decades. Two level logic namely binary logic is the decoding method used heavily. Another advance in the logic decoding is the use of multiple levels namely more than two discrete levels representing the signals. Here we use the method of quaternary logic representation (four discrete levels).

Literature survey
Multiple-input floating gate MOSFETs and floating gate potential diagrams have been used for the conversion of quaternary-valued input into corresponding binary output in CMOS integrated circuit design environments. The method is demonstrated through the design of a circuit for conversion of quaternary inputs into the corresponding binary bits in a standard 1:5 mm digital CMOS technology. To design and simulate the CMOS quaternary digital to analog converter. Quaternery(four valued) logic offers the benefit of easy interfacing to binary logic because radix 4 allows for the use of simple encoding/decoding circuits. The research indicates that quaternary circuits do offer the benefit of lower power consumption compared to traditional binary(two valued) logic circuits.

Problem Statement
To design a quaternary digital to analog converters using CMOS technology. The scientific literature presents many works about multi valued logic(MVL) as examples the multi valued circuits have been presented: adders, multipliers, flip-flops, latches and logic gates. The needs of communication with the analog world imply multiple valued digital to analog converters(MVDAC). The multiple valued digital to analog converters is merely a particular case of the analog to digital and digital to analog converters with which we are already familiar. We are trying to implement the CMOS quaternary digital to analog converters with better efficiency and performance.

Platform, Tools, Techniques and Simulation Environment

Windows platform. Tanner tools. Additional environment/softwares if required.

Project Deliverables
Quaternary digital to analog converters with: o Low power consumption o Reduced complexity for larger circuits o Reduced area Simulation of the proposed QDAC

Project Time line

References
[1] Ishizuka, O.; Ohta, A.; Tannno, K.; Tang, Z.; Handoko, D.; VLSI design of a quaternary multiplier with direct generation of partial products Multiple-Valued Logic, 1997. [2] Thoidis, I.M.; Soudris, D.; Fernandez, J.M.; Thanailakis, A.; The circuit design of multiplevalued logic voltage-mode adders; Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on Volume: 4, 6-9 May 2001. [3] K. C Sith, Multiple-Valued logic: a tutorial and appreciation, IEEE Computers, vol. 21, pp. 17-27, Apr. 1988. [4] S.Han, Y Choi and H Kim, A 4-Digit CMOS Quaternary To Analog Converter with Current Switch and Neuron MOS Down-Literal Circuits, Proc 31st ISMVL pp. 67-71, Warsaw Poland,May 2001. [5] S.Han, Y Choi and H Kim, A Current-Mode Folding/interpolating CMOS Analog to Quaternary Using Binary to Quaternary Encoding Block, Proc 32st ISMVL, 2002. [6] Buck, A.E.; McDonald, C.L.; Lewis, S.H.; Viswanathan, T.R.; A CMOS bandgap reference without resistors, Solid-State Circuits, IEEE Journal of, Vol: 37. Jan/2002 [7] S. Nooshabadi, G. S. Visweswaran and D. Nagchodhurhi Current Mode Ternary D/A Converter, IEEE, pp. 244-248, 1997. [8] The Engineering Staff of Analog Devices, Analog-Digital Conversion Handbook, Prentice-Hall, Inc. 1986.
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