WAVE PIPELINING

Aneesh.R
Broadcast and Communication Group Centre for development of Advance Computing Thiruvananthapuram aneesh4tvm@gmail.com

Wave pipelining Aneesh.R

Usual determination of Clock Period

Clock period taken to be greater than or equal to critical path delay (delay of path with longest computation time). For a non critical path, delay may be much smaller than critical path delay. So, on clocking system, gates along non critical path remain idle for a major portion of clock period.

Wave pipelining Aneesh.R

Usual determination of Clock Period (contd)

Only 1 wave of data between register stages. Inputs to output register remain stable for a significant portion of clock cycle. Combinational block not operating at maximum rate.

Wave pipelining Aneesh.R

What is Wave Pipelining?

Also called maximum rate pipelining. Clock speed increased by reducing idle time of non critical paths. Clock frequency increased without increasing number of internal storage elements (latches or registers). Technique for pipelining digital system by equalizing delays in combinational logic circuit. Use of multiple coherent waves of data between storage elements by clocking system faster than propagation delay between registers.

Wave pipelining Aneesh.R

What is Wave Pipelining? (contd)

Wave pipelining Aneesh.R

What is Wave Pipelining? (contd)

New inputs can be applied to a combinational block before results of current inputs are available at output. Data values at first set of registers changed before old values have propagated to next set of registers. System and circuit level analysis done to determine time of application of new data. System level analysis accounts for clock period and clock skew.

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What is Wave Pipelining? (contd)

Circuit level analysis estimates minimum and maximum delays through combinational logic circuit. Clock period can be reduced as long as data from a clock cycle does not overwrite data from the previous clock cycle. Clocking at a frequency greater than maximum pipeline rate mixes the waves of data.

Wave pipelining Aneesh.R

What is Wave Pipelining? (contd)

Non pipelined system and data flow

Wave pipelined system and data flow

Wave pipelining Aneesh.R

What is Wave Pipelining? (contd)

Tclk (t max - t min) + t setup + t hold + Dt ei + Dteo + Dtli + Dtlo

What is Wave Pipelining? (contd)

(t max - t min) reduced for higher throughput. Requires balanced propagation paths for t max = t min. Balancing delays difficult in large circuits due to:

Wave pipelining Aneesh.R

Path variation due to logic depth in the architecture. Unequal rise/ fall times. Delay variations in the basic building blocks. Temperature and process variations.

Wave pipelining Aneesh.R

Requirements of an efficient wave pipelined systemA logic which provides equal propagation delay and
rise / fall times for all input combinations. A delay element which perfectly emulates combinational logic block delay. An architecture having identical propagation paths. Identical effect of temperature and process variations on all the propagation paths of the architecture.

Wave pipelining Aneesh.R

Implementation of Wave Pipelined Systems

Choice of appropriate logic style crucial. Mismatches in propagation delay at building blocks can cause system failure. Static CMOS offers good packing density but propagation delay is highly data dependent. NPCPL seems to be a better alternative for implementing wave pipelined system due to symmetric nature.

NPCPL (Normal Process Complementary Pass Transistor Logic)

Wave pipelining Aneesh.R

Wave pipelining Aneesh.R

NPCPL (contd)
Uses NMOS pass transistors. True and complementary inputs. 2 pass blocks generating true and complementary outputs. Level restoring inverters to restore degraded voltage levels at output of pass transistors to full CMOS levels. Threshold voltage of inverter (Vth) is most critical parameter in design.

Wave pipelining Aneesh.R

NPCPL (contd)
Increase in Vth increases fall time and transition delay of NPCPL building block, thereby affecting performance of wave pipelined circuit.

Vth controlled by adjusting

Wave pipelining Aneesh.R

NPCPL (contd)

W ratio determined to get equal 0->1 and 1->0 delays and equal rise/fall times. Can realize all the major 2-input boolean functions with identical propagation delays. Provides identical logic depth and hence equal delay for all logic gates, due to symmetric nature. Use as delay element to mimic delay of 2 input gates. Advantages: high throughput, low latency, low area. Disadvantage: poor noise margin.

Wave pipelining Aneesh.R

NPCPL (contd)

Wave pipelining Aneesh.R

Advantages of Wave Pipelining

Absence of pipeline latches leads to decrease in area and decrease in power consumption. Simpler clock distribution. Higher throughput, compared to corresponding synchronous designs.

Wave pipelining Aneesh.R

Disadvantages of Wave Pipelining

Requires special design algorithms to equalize lengths of all paths. Data dependent delay fluctuations cannot be fully eliminated, which degrade performance. Layout is critical for delay balancing and hence, an automatic layout cannot be used.

Wave pipelining Aneesh.R

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