730

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001

An On-Chip March Pattern Generator for Testing Embedded Memory Cores

Wei-Lun Wang, Kuen-Jong Lee, and Jhing-Fa Wang
AbstractIn this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead. Index TermsMarch algorithm, memory testing, system-on-a-chip (SOC), test pattern generator.

I. INTRODUCTION With the rapid progress in the VLSI fabrication process, a complex system can now be integrated into a system-on-a-chip (SOC). Embedded memory cores are essential to the performance of an SOC. However due to the limitation of the input/output (I/O) pins, it is difficult to test embedded memory cores externally. Thus, the built-in self test (BIST) schemes have been widely used to solve this problem [1]. Typical faults in memories include the address decoder faults (AFs), stuck-at faults (SAFs), transition faults (TFs), stuck open faults (SOFs), coupling faults (CFs), neighborhood pattern sensitive faults (NPSFs), and data retention faults (DRFs) [2]. The conventional BIST-based test pattern generators (TPGs) usually employ a single march algorithm, which can only test a subset of the memory faults. For example, in [3] the NairThatteAbraham procedure is employed in a BIST based TPG to detect the SAFs and CFs, while in [4], an extended 9N march algorithm is used targeting the SAFs, CFs, TFs, and NPSFs. In an SOC, to obtain a satisfactory high fault coverage, multiple march algorithms are required to test the various faults in different types of memory cores. Recently, two programmable systems have been proposed in which multiple march algorithms can be generated on chip [5], [6]. In [5], a microprogram-controlled BIST is developed which has great flexibility because the algorithms can be generated using software. However, it requires large area overhead and is not suitable for a memory core that is implemented as an intellecture property (IP). In [6], a simpler controller-based programmable BIST core for embedded dynamic RAM (DRAM) is presented. Predetermined test elements such as march elements (or march steps as will be described later) are implemented inside the memory core and thus the user can optimize the BIST hardware for a specific embedded DRAM with the set of predetermined test elements. This method, however, relies on an external device to provide test control signals to guide the generation of the various march algorithms. Thus, comprehensive external control is still needed. Another problem is on its requirement of predetermining the test elements, which may be difficult for a new product since the actual faults may be highly dependent on the production line. This is especially true for those products using a new fabrication process, where the actual faults are unknown.
Manuscript received July 29, 1999; revised February 21, 2000. The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. Publisher Item Identifier S 1063-8210(01)03644-7.

In this correspondence, we adopt a different strategy for generating march-based test algorithms. We try to develop a BIST core that can generate all known march algorithms with very little external control. We have included 40 march algorithms that we can find in literature in our core. All the information related to any march algorithm, including the up/down (u/d) address orders, the read/write (r/w) signals, the r/w data, and the number of march elements, is stored in the core such that the selection of a specific algorithm is as simple as giving an index to that algorithm. To reduce the space for saving the information, an efficient reduction procedure is developed. A pair of programmable cyclic shift registers (CSRs) are employed to generate the r/w operations of the march steps. Since these two CSRs can generate the various r/w operations, the proposed TPG is able to generate any march algorithm. Moreover, the CSR can also be used as a basis for generating the data backgrounds to test the word-oriented memory cores. We have implemented the proposed TPG using a Xilinx field programmable gate array (FPGA) chip and found that the gate overhead is comparable with that of the TPG in [6]. Since the area overhead of the TPG in [6] is about 1.3% for a 1-Mb embedded DRAM and is negligible for a larger DRAM core, our method provides a low cost but very powerful march algorithm generator. The organization of this paper is as follows. Section II reviews the commonly used notations of march algorithms and provides the required background information. The storage reduction procedure is described in Section III. Section IV details the architecture of the proposed TPG. Finally, the conclusions are given in Section V. II. NOTATIONS AND BACKGROUND OF MARCH ALGORITHMS An m-step march algorithm with each step (denoted by Si ) having at most k r/w operations can be expressed as

hmarch algorithmi ::= fhSi iji = 1; . . . ; mg hSi i ::= haddress orderi((hopj ijj = 1; . . . ; k)) or del haddress orderi ::=* (up) or + (down) or m (either up or down) hopj i ::= r0 or r1 or w0 or w1

(1)

where the notation r(w) is the read (write) operation and notation 0(1) is the noninverted (inverted) data backgrounds [1], [2], respectively. Thereafter, we call the r(w) and 0(1) of the above operations the r/w signals and the r/w data, respectively. The number of operations within a step is called its op length. For example, the march PS and G algorithms used to test the DRAM and static RAM (SRAM) cores, respectively, are expressed as follows. March PS algorithm [7]

fm (w0); * (r0; w1; r1; w0; r0; w1); * (r1; w0; r0; w1; r1); * (r1; w0; r0; w1; r1; w0); * (r0; w1; r1; w0; r0)g
and March G algorithm [8] (2)

fm (w0); * (r0; w1; r1; w0; r0; w1); * (r1; w0; w1); + (r1; w0; w1; w0); + (r0; w1; w0); del; m (r0; w1; r1); del; m (r1; w0; r0)g:
(3)

10638210/01$10.00 2001 IEEE

Authorized licensed use limited to: IEEE Xplore. Downloaded on December 23, 2008 at 20:09 from IEEE Xplore. Restrictions apply.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001

731

TABLE I THE ORIGINAL SEEDS OF MARCH PS AND G ALGORITHMS

the March G algorithm, OP W2 and OP W7 , are 413 241 and 413000, respectively. Definition 2: Let C Z (F ) be the number of consecutive zeros from the leftmost bit of a k -tuple vector F , the consecutive zero weight of two operation weights OP Wi and OP Wj , denoted as C Z W (OP Wi ; OP Wj ), is defined as
C Z W (OP Wi ; OP Wj )

C Z (OP Wi

OP Wj )

(5)

where OP Wi 8 OP Wj is defined as follows. Let (OP Wi )r be the th digit of the operation weight OP Wi , then
(OP Wi )r 0; max((OP Wi )r ; (OP Wj )r );

8 (OP Wj )r

if (OP Wi )r = (OP Wj )r if (OP Wi )r 6= (OP Wj )r .

Note that there are two delay (del) operations in the March G algorithm for testing the DRFs of the memory cells. During the delay operation, no r/w operations are applied to the memory cell, thus the delay operation can be regarded as an empty step with null operations. The time spent for the delay operation is dependent on the node capacitance and the leakage current of the memory cells [2]. Usually, the users will predetermine the length of the required delay time inside a chip. During the delay operation, the address generator in the proposed design is not used to generate the addresses but used as a timer to measure the length of delay time. The characteristics of a march algorithm, including the u/d address orders, r/w signals, r/w data, and op lengths, will be called the seeds of the algorithm in this paper. These seeds must be stored on chip (in a ROM) so that external control to generate test patterns can be minimized. By observing (2) and (3), we know that the op length of different steps may be unequal. To simplify the control of the r/w signals and data generation, we shall use dlog2 ke bits of memory to save the op length of each step, where k is the maximum number of operations in each step. The seeds of the March PS and G algorithms are tabulated in Table I. To reduce the space of r/w signals and data saved on chip, a reduction procedure is detailed in the following section. III. REDUCTION OF READ/WRITE OPERATIONS Before discussing the reduction procedure, some terminologies are defined. Definition 1: The operation weight (OPW) for the r/w operations of the ith step Si of a march algorithm is defined as
k
OP Wi

For example, the consecutive zero weight of the second and the seventh steps of the March G algorithm fr0; w1; r1; w0; r0; w1g and fr0; w1; r1g is three (i.e., C Z W (OP W2 ; OP W7 ) = C Z (413 241 8 413 000) = C Z (000 241)). A fundamental rule for generating the r/w operations by using the reduced r/w operations is now presented. For any pair of the r/w operations in the ith and j th steps, Si and Sj , with op lengths, s and t (s  t), respectively, if C Z W (OP Wi ; OP Wj ) = s then the operations of the ith step can be generated by a pair of programmable CSRs (this will be detailed in the next section) with the r/w operations of the j th step. The j th step Sj is called a dominant step (DS) and the r/w operations of the DS are called dominant operations (DOPs). For example, the op lengths of the second and the seventh steps of the March G algorithm are six and three, respectively. Because C Z W (OP W2 ; OP W7 ) = 3; S7 is the DS and the r/w operations of the S2 can be generated by a pair of programmable CSRs with r/w operations of the S7 . Since the delay operation is empty, no ROM space is required and the delay operations are excluded from the following reduction procedure. Reduction Procedure: Assume there are u nonempty steps among March algorithms. Step 1) Sort the u nonempty steps by their operation weights in a decreasing order. Let the sorted steps (SSs) be called SS1 ; SS2 ; . . . ; SSu where the SS1 is a step with the maximum weight. Step 2) Let two index variables i and j be both one and the first dominant step DS1 be SS1 . Step 3) Increase the value of i by one. If i > u then exit this procedure. Step 4) If C Z W (DSj ; SSi ) = min(op length (DSj ), op length(SSi )) then repeat from Step 3 else increase the value of j by one and let the j th dominant step DSj be SSi and repeat from Step 3. Table II shows the dominant steps of the March PS and G algorithms and Table III shows their dominant operations. Since the major time consuming factor of this procedure is the sorting process in Step 1, the time complexity of this procedure is O(ulogu). The reduced seeds of the March PS and G algorithms are tabulated in Table IV. From our experiment, we find that the total number of steps in the 40 March algorithms is 252. After reduction, the number of dominant steps is only seven. Thus a reduction of 97% memory space for saving the required steps can be achieved. IV. ARCHITECTURE OF THE PROPOSED TEST PATTERN GENERATOR Assume there are m steps among the multiple March algorithms and each step having at most k r/w operations. After using the reduction procedure, assume v dominant steps are obtained. Two main blocks, (A) a March pattern controller (MPC) and (B) a March pattern generator (MPG), are used to constitute the proposed TPG. The MPC block

=
j =1

w (opj )

310k0j

(4)

where w(opj ) is the weight of an operation opj of step Si and the weights for r0, r1, w0, w1, and null operation are defined as 4, 3, 2, 1, and 0, respectively, and k is the maximum op length among march algorithms. For example, the OPW of the second and the seventh steps of

Authorized licensed use limited to: IEEE Xplore. Downloaded on December 23, 2008 at 20:09 from IEEE Xplore. Restrictions apply.

732

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001

TABLE II THE DOMINANT STEPS OF MARCH PS AND G ALGORITHMS

TABLE IV THE REDUCED SEEDS FOR MARCH PS AND G ALGORITHMS

TABLE III THE r/w OPERATIONS OF THE FIVE DOMINANT STEPS

is used to control the overall control operation of the March algorithms while the MPG block is the kernel for generating the test patterns to test the memories. As shown in Fig. 1, the MPC consists of nine subblocks from (A1) to (A9) and the MPG consists of three subblocks from (B1) to (B3). The functionality of each subblock is explained in the following. The dominant operations of the v dominant steps, including the k -bit r/w signals and k -bit data, are saved in ROM 1 (A1) with a size of (v 32k )-bit. Since the m steps share the v dominant steps, a dlog2 v e-bit address for each step is used to indicate which dominant operation is used. ROM 2 (A2) stores the seeds of each step, including the 1-bit u/d address order, the dlog2 ke-bit op length, and the address of the dominant operation. The capacity of ROM 2 is thus m3(1 + dlog2 k e + dlog2 v e)-bit. For example, the contents of ROMs 1 and 2 for the March PS and G algorithms are shown in Tables III and IV, respectively. The total number of required memory bits is Total bits = v 32k + m3(1 + dlog2 ke + dlog2 v e): (6)

Fig. 1.

Block diagram of the proposed test pattern generator.

In the proposed design the steps of each March algorithm are arranged consecutively. If the first step location and step length of each March algorithm are given then all the seeds of the algorithms saved in the ROMs 1 and 2 can be fetched completely. The first step locations and step lengths of each March algorithm are implemented by the Offset Decoder (A3) and Step Decoder (A4), respectively. The

Data Counter (A5) is a programmable up counter with a size of B data bits, where B is the maximum data width of the memory cores, to count the number of the data backgrounds [1]. To test the word-oriented memory cores completely, the size of the data backgrounds G we used is dlog2 B e + 1, which will be detailed later. When the content of the counter is equal to the reference length, it means the present operation is completed and the op counter, r/w signal generator, and r/w data generator are triggered for the next operation. The OP Counter (A6) counts the number of r/w operations within a step. If the content of the op counter is equal to the op length in ROM 2, then an output signal will trigger the address counter to test the next memory cell. The Address Counter (A7) is a programmable binary up counter that has an all-zero initial state. The width of the counter is equal to the maximum address width of the memory cores. When the u/d in ROM 2 is 0(1), the address lines are taken from the Q (Q) outputs such that the addresses are from 000 . . . 0(111 . . . 1) to 111 . . . 1(000 . . . 0). If the op length in ROM 2 is zero, then the address counter becomes a timer

Authorized licensed use limited to: IEEE Xplore. Downloaded on December 23, 2008 at 20:09 from IEEE Xplore. Restrictions apply.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001

733

to measure the time length of delay operation. When the content of the counter (timer) is equal to the value of the addr ref (del ref ), the memory capacity of memory (waiting time of delay operation), it triggers the step counter and the TPG will start the r/w operations within the next step. The Step Counter (A8) is a binary up counter. When the content of the step counter is equal to the step length from the step decoder, all the steps of a March algorithm have been gone through. The Full Adder (A9) is used to sum up the first step location and the present content of the step counter to produce the address of the next step, such that the seed of the next step can be read from ROMs 1 and 2. On the other hand, the three subblocks of the MPG, R/W Data Generator (B1), R/W Signal Generator (B2), and Data Background Generator (B3), are constituted by the programmable CSRs. As shown in Fig. 2, a k -stage CSR is composed of (k -1) 2-to-1 multiplexers (MUXs) and k D flip-flops (F/Fs). Each MUX is controlled by the variable, ci (i = 1; 2; . . . ; k 0 1). Only the variable cL (where L is the op length and also called the cycle length) is one and the remaining variables are zero such that the output signal from Q1 is feedback to DL . Thus, two CSRs with a seed of dominant operation (DOP) can be used to generate the r/w operations of steps. As illustrated in the previous section, the r/w operations of the seventh step of the March G algorithm, (r 0; w1; r1), can be generated by a pair of 6-stage CSRs with a seed of DOP (r0; w1; r1; w0; r0; w1) (i.e., the r/w operations of the second step of the March G algorithm) and the variables (c1 ; c2 ; c3 ; c4 ; c5 ) = (0; 0; 1; 0; 0). Moreover, the CSR can be applied to the architecture of the data background generator as described next. Table V shows a generalized format of the inverted and noninverted data backgrounds for testing the word-oriented memory cores. Assume a memory core has B data bits per word, (D0 ; D1 ; . . . ; DB 01 ), then G(= dlog2 B e + 1) data backgrounds, B1 ; B2 ; . . . ; and BG , are required. When the r/w data is 1 (0), the G inverted (noninverted) data backgrounds are applied to test the memories. By observing Table V, we find that the data bits D0 ; D1 ; . . ., and DB 01 can be expressed by the following:
D

Fig. 2. A k -stage cyclic shift register. TABLE V GENERALIZED NON-INVERTED AND INVERTED DATA BACKGROUNDS

D0 D2 D3

f = f0 = f0
d12 d22 d32 d42

= 0; 0; 0
; ;

0; 1;

g 1g = 1g =

; D1

= 0; 1; 0
1

CS D1

(D1 )
D2

8
d15 d25 d35 d45

i=

f0 f0

; ;

0; 0; . . . ; 0 1; 0; . . . ;

p C S (D1 ); q

g 0g

; ;

if i = 0 if i = 1 if i = 2p ; 1  p  dlog if i 6= 2p ; i =
q (j )

2)

d10 d20 d30 d40

d11 d21 d31 d41

d13 d23 d33 d43

d14 d24 d34 d44

d16 d26 d36 d46

d17 d27 d37 d47

D (1)

D (2)

8 111

2B

= 8

D ( );

qr

r j =1
q (j ); r < B

0 = 0 0 0
D0 D2 D4

0 1 0 0

0 0 1 0

0 1 1 0
; D1

0 0 0 1

0 1 0 1

0 0 1 1

0 1 1 1

=2

w ; 0  w < dlog

2B

e
(7)

where C S P (D1 ) means the following operations on D1 are repeated p times: 1) the rightmost bit is saved into a temporary flag; 2) except the rightmost bit, all the remaining bits are shifted right a bit; and 3) load the value from the temporary flag into the leftmost bit. For example, the data backgrounds for B = 4 and B = 8 are given as follows:

1)
B

d10

d11 d21 d31

d12 d22 d32

d13 d23 d33

D6 D7

= 4

d20 d30

f = f0 = f0 = f0 = f0

= 0; 0; 0; 0
; ; ; ;

0; 1; 0; 0; 0; 1; 1; 1;

g 0g = 1g = 1g = 1g =

= 0; 1; 0; 0
1 2

g
;

CS CS D2 D1

(D1 ); (D1 );
D4 D2

D3 D5

f = f0

= 0; 1; 1; 0 = 1; 0;

g 1g =

D1 D1

8 8

D2 D4

8 8

D4 :

0 = 0 0

0 1 0

0 0 1

0 1 1

To accomplish the hardware implementation, the first data bit D0 is grounded. The D1 can be generated by a CSR with a cycle length of G and a seed of (0; 1; 0; 0; . . . ; 0). The remaining data bit Di (i = 2; 3; . . . ; (B 0 1)) is one of the outputs or a linear combination of the outputs of the CSR. For the purpose of illustration, Fig. 3 shows the

Authorized licensed use limited to: IEEE Xplore. Downloaded on December 23, 2008 at 20:09 from IEEE Xplore. Restrictions apply.

734

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001

TABLE VI THE 40 ALGORITHMS INTEGRATED IN THE UNIVERSAL TPG CHIP

Fig. 3.

The four-bit data background circuitry.

data backgrounds for testing 4(= B )-bit memory cores. The first data bit D0 is grounded. The second data bit D1 can be generated by a CSR with a cycle length of 3(= G) and a seed of (0, 1, 0). The values of D2 can be generated by the output of D1 with one clock delay. The last data bit D3 can be realized by a linear combination of D1 and D2 , i.e., D1 8 D2 . Note that the seeds of the vertical F/Fs are (0, 0, 0, 0). The MUXs attached to the vertical F/Fs are controlled by the value of r/w data to generate the noninverted/inverted four-bit data backgrounds. The working procedure of the proposed TPG shown in Fig. 1 is stated as follows: Step 1) Initialize all the counters to be all zero. Step 2) Provide the address size (delay time length) and data capacity of the memory under test via the inputs of addr ref (del ref ) and data width, respectively, and choose which March algorithm to be used via the algorithm code input. Step 3) The address of the first step is located by the offset decoder (A3) and the step length is given by the step decoder (A4). Step 4) The content of the step counter (A8) is added to the address of the first step in the full adder (A9) to generate the address of the step to be performed. Fetch the up/down address order, op length, and DOP address in the ROM 2 (A2) and the corresponding DOP, including the r/w signal and data, in the ROM 1 (A1). Step 5) If the op length is zero, the address counter (A7) is used as a timer to measure the length of delay time, else generate the up/down addresses and use a) data background generator (B3) to generate the inverted / noninverted data backgrounds; b) data counter (A5) to count the number of data backgrounds per each r/w operation; c) r/w data generator (B1) and r/w signal generator (B2) to generate the r/w data and signals, recursively; d) op counter (A6) to count the times of r/w operations within a memory address (cell). Step 6) If the r/w operations for a memory cell are completed, then a) if the addresses are not exhausted then trigger the address counter to generate the next up/down addresses and repeat from Step 5 b) else increase the step counter by one, if its content is equal to the step length then this algorithm is gone through else repeat from Step 4. The dominant hardware overhead of the proposed TPG, i.e., the number of F/Fs, can be estimated as follows. Assume v dominant

steps among multiple March algorithms (where the maximum op and step lengths are k and s, respectively) with m March steps are obtained and the maximum memory address and data bus capacity for the memory cores are N and B , respectively. As mentioned above, a dlog2 ke-stage op counter, dlog2 se-stage step counter, dlog2 B e-stage data counter and 23k F/Fs for the CSR based r/w signal and data generators are required in the proposed TPG. Besides, B + dlog2 B e F/Fs are used to constitute the data background generator. Thus, N + B + 23dlog2 B e + 23k + dlog2 se + dlog2 k e F/Fs are needed. Obviously, excluding the address and data width, the maximum op and step lengths play an important role. We have incorporated forty known March algorithms tabulated in Table VI into a Xilinx FPGA chip, XC4010E. Among these algorithms there are 252 steps, seven dominant steps, (w0), (w1), (r0; w1; r1; w0; r0; w1), (r1; w0; r0; w1; r1; w0), (r1; w0; w1; w0; r0), (r0; w1; w0; w1; r1), and (r0; w1; r1; w0; w1), and the maximum op and step lengths are 6 and 18 (i.e., the step length of the Algorithm A), respectively. It is reported that 4089 equivalent gates (including the ROMs) are required in the proposed TPG. Compared to the BIST logic proposed in [6], which requires between 2000 to 3000 gates, the hardware overhead of the proposed TPG is tolerably low. From Fig. 1, it can be seen that the extra pins needed are for the algorithm code, the addr ref , the del ref , and the data width, where the last three may be hardwired to VDD or Ground if the address space, the delay duration, and the word width of the memory are fixed. Therefore the external control can be minimized. V. CONCLUSION To raise the fault coverage of the embedded memory cores in an SOC, we have proposed an effective method to design a universal embedded TPG for multiple March algorithms. Instead of fetching and decoding the test instructions as in the processor based TPG [5], or using external signals to control the generation of March algorithms [6], all the seeds of the march steps are saved in two separate embedded ROMs such that the test patterns can be generated on chip in real time with little external control. We also presented a systematic procedure to reduce the required ROM space. Then two simple programmable CSRs together with some simple control logic are used to generate all the required read/write operations. With the proposed TPG, one may execute any March algorithm(s) to test a memory core to find out which algorithm(s) is most efficient. This is most useful when a new product is developed using a new manufacturing process since before the product is actually fabricated, the fault models that can best reflect the process defects may be unknown. Also in the SOC environment, many different types of memories may

Authorized licensed use limited to: IEEE Xplore. Downloaded on December 23, 2008 at 20:09 from IEEE Xplore. Restrictions apply.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001

735

exist. The ability to provide different algorithms for different memory modules clearly will make the whole system much easier to test. REFERENCES
[1] A. J. van de Goor, Testing Semiconductor Memories, Theory and Practice. Gouda, The Netherlands: ComTex, 1998. [2] R. Dekker, F. Beenker, and L. Thijssen, A realistic fault model and test algorithms for static random access memories, IEEE Trans. Comput.Aided Design, vol. 9, pp. 567572, June 1990. [3] P. Camurati, P. Prinetto, M. S. Reorda, P. di Torino, S. Barbagallo, A. Burri, and D. Medina, An industrial experience in the built-in self test of embedded RAMs, in Proc. 12th VLSI Test Symp., NJ, Apr. 1994, pp. 306311.

[4] G. M. Park and H. Chang, An extended march test algorithm for embedded memories, in Proc. 6th Asian Test Symp., Akita, Japan, Nov. 1997, pp. 404409. [5] J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, Processor-based built-in self-test for embedded DRAM, IEEE J. Solid-State Circuits, vol. 33, pp. 17311740, Nov. 1998. [6] C. T. Huang, J. R. Huang, C. F. Wu, C. W. Wu, and T. Y. Chang, A programmable BIST core for embedded DRAM, IEEE Design Test Comput., pp. 5969, Jan.Mar. 1999. [7] V. Yarmolik, Y. Klimets, and S. Demidenko, March PS (23N) test for DRAM pattern-sensitive faults, in Proc. 7th Asian Test Symp., Singapore, Dec. 1998, pp. 354357. [8] A. J. van de Goor, Using March tests to test SRAMs, IEEE Design Test Comput., pp. 814, Mar. 1993.

Authorized licensed use limited to: IEEE Xplore. Downloaded on December 23, 2008 at 20:09 from IEEE Xplore. Restrictions apply.