IAE

The Future of VLSI

Trends in VLSI
Will Moores Law continue? How far can CMOS go? Smaller feature size Lower operating voltages Higher clock speed Larger designs System on a chip What will come next? Asynchronous designs? Molecular electronics? Quantum electronics?
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100 nm 0.5 V 10 GHz 100 M transistors Logic, RAM, RF, Analog

Limits to CMOS Scaling

Lithography: How small can we pattern and align features? Current state of the art: ~ 200 nm. Near future: 70 nm Diffraction limits: Mask openings are diffractions slits. Light pattern on wafer has (sin x)/x pattern Reduced depth of field high image reductions Precision alignment required Transistors: reaching physical limits Very small distances cause high electric field densities. Electric field and conduction domains interfere Need better isolation between cells Gate oxide thickness approaching a few atoms Very small devices exhibit high leakage
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Improved Lithography
Diffraction limits resolution to approximately size of wavelength. Mask engineering: use mask reticule as beam-shaping lens
Reduce diffraction effects

Shorter-wavelength illumination sources

Visible spectrum range: 750 nm (red) to 350 nm (blue) Mercury-Xenon lamp: 248 nm Argon-fluoride laser: 157 nm Extreme ultraviolet: 13.4nm Note: ordinary glass optics are opaque to very small wavelengths; need new materials.

Improved optics
Better lens coatings, reflective optics

X-rays and E-beams

Basically sequential; draw features on wafer. Would lose the massively parallel properties of projection optics.
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Transistor Scaling
Goal: smaller transistors yield smaller packages, higher switching frequency, and lower power dissipation. Channel length (source-to-drain) ~ minimum feature size ()
Most common ASIC processes: 0.5, 0.35, and 0.25 m Current production state of the art: 0.18 m Next goal: 0.13 m By 2006: 0.01 m

Smaller size requires smaller voltages, to reduce E field densities.

1.0 m 0.5 m 0.25 m 0.2 m L 0.5 m 0.25 m 0.13 m 0.1 m VDD 5V 3.3 V 1.5 V 1.0 m Vt 2.5 V 1.7 V 0.75 V 0.5 m
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Transistor Engineering
Better Isolation Techniques
Separation by Implanted Oxygen (SIMOX) Build shallow trench oxide isolation barriers

Channel engineering
More complex doping profiles

Fundamental Limits to CMOS Scaling

Devices become so small that average quantum mechanical properties no longer apply. Gate oxide ~ 10 atoms thick; electrons tunnel through to channel. Channel so short, thermally generated electrons tunnel from source to drain (channel leakage) Interconnects: metallization does not scale down with transistors. Interconnects will dominate.
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VLSI Chip in Year 2005

By 2005, 10 of todays microprocessors will be able to fit on a single chip, and clock.speeds will exceed 1 GHz. Minimum feature size Total number of transistors Number of logic transistors Chip size Clock Frequency Number of I/O connections Number of metal layers Supply Voltage Supply Current Power dissipation 0.1 m 200 million 40 million 520 mm2 2.0-3.5 GHz 4000 7-8 0.9-1.2 V 160 A 160 W

Source: Barbara Chappell, Intel Corp., The Fine Art of IC Design, IEEE Spectrum, July 1999, pp. 30-34. 7

Design Challenges: Electrical

Electrical Properties: Low voltages and high currents.
Noise margins. Electromagnetic emissions, interaction between closely spaced structures. Threshold control. Interconnect voltage drops.

Major concern: high switching currents (di/dt).

In a synchronous circuit, 40,000 transistors may switch at the same time. Requires careful design of power and signal distribution. Danger of inducing noise on power and ground lines. Simple lumped RC model no longer adequate: Interconnects look like transmission lines. Characteristic impedance, reflections, EMI

CAD design tools must incorporate more sophisticated models to predict performance and complex component interactions.
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Design challenges: Managing Complexity

Extremely large designs will require design automation.
Todays high-performance designs (e.g. Pentium class) are still largely done manually. The market demand for performance is greater than the ability of CAD tools. Future designs will be too large to do manually; CAD tools must improve.

Design Re-use will be critical.

Standard cells, mega-functions and modules Re-use pre-built modules. Use module-builders (synthesis) to generate components. Soft cores (HDL libraries) will allow design to be mapped to new technology.

Designers will have to broaden their skills.

As the system migrates to the chip, system designer becomes a chip designer. The designer must understand and master all of the CAD tools. CAD tools will need better interfaces Ability to view project from many angles. More automation of most tasks, with designer control where needed.

Continuing education will be necessary for the engineer to keep up with changing skill needs.

Design Challenges: Interconnect

The challenge of interconnect
Comparison of integrated circuits in 1986 and 2004

1.0 micron
Drawn to the same scale

0.1 micron

Chart courtesy of Ted Denlin, Sandia National Laboratory

Future chips may have over 1 Km of wire. Minimizing gates and transistors is no longer the key optimization criterion.
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System on a Chip (SOC)

Challenge: to place Random Logic, Memory, and Analog on a single chip.
Motivation: Signal Bandwidth Disparity between internal and external signal bandwidth is growing. System on a Chip eliminates I/O bottleneck. Year Internal BW External BW 1997 1 1 1999 3.2 2.0 2002 19.5 3.6 2005 85.3 6.1 2008 375 10.5 2011 1623 17.2 2014 7133 29.0

Projected internal and external signal bandwidths (MHz).

Source: 1998 International Technology Roadmap for Semiconductors

Motivation: Economies of Scale Eliminate levels of packaging hierarchy, save cost. Challenge: todays processes are optimized for one of the three. Need multipurpose processes and new circuit design techniques.

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Challenge: Testing
Number of transistors is growing faster than number of I/O pins.
1990: 10,000 transistors/pin. 2005: 120,000 transistors/pin

Internal signal bandwidth is growing faster than external signal bandwidth. Built In Self Test (BIST) will be increasingly important.
Generate test vectors internally. Perform test and verify results internally, at full speed. Use I/O pins to report the test results.

BIST can be used throughout the life of the system.

Periodic self-testing can verify correct function, detect failures in the field. When coupled into the system, e.g. with JTAG, entire hierarchy of components can be tested periodically. Valuable for critical systems: aircraft navigation and control, medical equipment.

Self-test can extend to self-repair.

Programmable interconnects: e.g., bad memory row or column can be substituted.
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What will Follow CMOS?

Semiconductor Technology Roadmap terminates in 2017.
We cannot continue to scale CMOS structures when there are not enough atoms to form a gate!

Nano-scale technologies: Quantum devices

Quantum dots Resonant tunneling devices Single-Electron Transistors Problems: extreme fabrication difficulties; only operate at cryogenic temperatures.

Nano-scale technologies: Molecular electronics

Each organic molecule is a gate. Use molecular self-assembly to construct computational fabric. Can put equivalent of 109 to 1012 transistors on a chip. Will need new computational models, new design technique.
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