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Katholieke Universitit Leuven, ESAT-MICAS,
K.Mercierlaan 94, B-301 Leuven, Belgium
Te1.+32 16321078 FA +32 16321975
willy.sansen@esat.kuleuven.ac.be
Abstract
U submicron CMOS devices, short-channel efects lead
to shifts in threshold voltage, increased mismatch and
noise. The velocity saturation limits the obtainable
transconductance and hence also the high-speed
performance. Lower supply voltages require the
oprational amplifier building blok to operate rail-to-rail.
In delta-sigma converters this leads to very-low-power
converters.
Considerable attention goes to circuit design for
telecommunication applications, in which the inductor is
making a comeback. The ultimate challenge of analog
design however is the cointegration with digital blocks,
causing coupling noise and requiring sophisticated tools.
Introduction
For ever higher density, CMOS technology scales by a
factor of two every four years. This year production is in
0.35 llm minimum channel length, and will thus reach
the 0.1 /flandmark in the year 2007. On the other hand
the oxide thickness scales with the cnannel length L: it is
little (about 0.8 nm) larger than Ll50 and will thus be
about 3 H in 2007. Since an oxide can take about 800
V/llm, such oxide can tolerate about 2.4 V. As a result
the supply voltage will be a fraction e.g. 1.7 V.
Analog design requires precise MOST models [1].
What will be the I-V characteristics ? What will be the
maximum speed ? What will be the lIf noise ? What will
be their mismatch coeficients ? All these questions will
Dadssed frst.
The most representative analog circuit is undoubtedly
the operational amplifier. Most circuit tricks can be
illustrated in an operational amplifer. Therefore attention
is paid to low-voltage opamp design. The way rail-to-rail
performance is realized makes all the difference. The
second most representative circuit block is a delta-Sigma
converter. It is probably the most intimate integration of
analog and digital functions. As a result it is a benchmark
for mixed analog-digital simulators and it is a challenge
0-7803-3625-9/96/$5.00 " 1996 IEEE.
for every analog designer. Therefore it is discussed as
well.
The highest demand in analog circuit design goes
nowadays to telecommunication circuits. An integrated
transceiver is a goal for every design group of imprtance.
The diffculties however are numerous: they have to
realize high-precision circuitry with low noise and low
distortion and above all, at very high frequencies. The
newcomer in this feld is the inductor. High-Q filtering,
low-noise VCO, etc., all depend on the inductor. For this
reason the technology of the inductor is reviewed followed
by some circuit examples.
Finally the design methodology is discussed. The goals
have not changed. The analog designer, very much as his
digital counterpart, has to provide mOre designs in less
time with less errors. His tools don't go much further
tha SPICE. What can we promise him? How does reuse
work for him ? How will he be able to cope with the
complexity of real mixed analog-digital design? Moreover
putting analog and digital together generates coupling
noise. Can we cope wit this or do we have to separate
the analog and digital functions on different chips?
This text gives questions and some answers on each of
the classes of circuits mentioned.
Submicron MOST models
MOSTs models have started with only a few
parameters such as a threshold voltage VT, a current
parameter KP and a body-effect parameter ). The
continuous reduction in channel length has always
increased the number of parameters. Weak inversion
operation at low current and velocity saturation operation
at high currents have increased this number as well. At
this point the number has become unmanageable [2]. It
will become even worse in the future. Indeed when we
inspect the curve of the transconductance versus the
applied voltage VGS-VT, we see that for a conventional
long-channel-length device the transconduc-tance gm is
constant for a wide range of V GS-VT values (see Fig.la).
Indeed this is the stong inversion region. On the left the
transconductance decreases because of the weak inversion
72
operation. The limiting value of V G
s
is denoted by
Vasws
and is given by [3]
kT
Vasws - VI =
2
n

q
(1)
in which kT/q
2
6 mV at room temperature and n * +
CD/C
o
x, in which CD is the bulk depletion layer
capacitance under the channel and
C
ox the gate oxide
capacitance. Note that this value is about 80 mV and
doesnot depnd on channel length.
Be-1
6e-1
4e-1
2e-1
Oe+O
|
I ..
,. w.
l9
"
ldir
aa
r
xvv
P
-

.
*
f
I
. z .
'/
rvzv
f
.
...
+++
-
+

L
L
_1"

vvvv
v+v

'
^
w
- ~.
F >
.
l
. ..|....

&u
I

,

......... -
,
v v
.... "
vwvv
VV ~
] : !
0.0 0.2 0.4 0.6 O.B 1.0 1.2 1.4 1.6 1.8 2.0
Fig. 1 a: Gm versus V GS
for a long-channel MOST

gl
T'
8e-1
. ir. In tD
)"

,
+w+ ..

6e-1
4e-1
7
291
:
'
!

M
w
e
#
!

.. t-
i

..
=+=
;;
.
w.. .+

..
z.

w L
VGS(V] ~
r
I
P
Oe+O I I
0.0 0.2 0.4 0.6 O.B 1.0 1.2 1.4 1.6 1.B 2.0
Fig.lb: Gm versus VGS
for a short-channel MOST
On the right the transconductance also decreases,
mainly because of velocity saturation (see Fig.l b). The
limiting value of V GS is now denoted by V GSsv and is
given by [3]
Vsat
Vussv -
V
T
4nL

(2)
in which
Vsat
is about 10
7
cm/s and fl is the mobility.
For a channel length of about micrometer, this is about
73
10 V. The stong inversion region is thus easy to be
distinguished.
Tis is different for short-channel devices though. Ever
decreasing the channel lengths decreases the values
Vass
v
i.e. velocity saturaton occurs at lower and lower values of
V
GS (see Fig.1b). As a result the strong inversion region
cannot be distinguished any more. The transconductance
has nearly become constant wit a value
g
m,8al W
C
o
x
Vsat
(3)
Note that this value doesnot depend on the channel
length.
Moreover the defnition of the threshold voltge is lost.
The exponential characteristic in weak inversion region
goes directly into a velocity saturation characteristic
(constt transconduc-tance). Somewhere in between a
threshold voltage can de defined as the point of maximum
slope of gm. Moreover the MOST has become very
nonlinear. Models are not even in sight.
Future analog circuits will have to realize accurate
circuits with such non-linear devices. Distortion will be
the first specification to suffer.
Since the transconductce is decreasing maybe the
noise is decreasing as well allowing constant signal-to
noise ratio. The thermal noise of a transistor is descibed
by its equivalent input noise voltge given by [1,3,4]
8kT 1
dv " (rG ) df
I
' 3
g
m
(4)
in which ra is the series poly-gate resistor. It is clear
that for decreasing WfL or decreasing current and gm, the
noise increases. Low-noise low-power design tus requires
compromises .
The 1I[ noise is given by [3,4]
K
F
F U
dv.

'
WL C
ox
2
f
(5)
in which constant KFF depends on the FET used.
Empirical values are for a pMOST K
FF 10
-
32
C
2
/cm
2
and about 40 ... 60 times more for a nMOST. This has
been verified over many generations of MOST
technologies [4]. Substituting Cox by fox/lox and l
o
x by
USO shows that the input lIf noise will be inversely
proportional not to WL but to W/L, very much as the
thermal noise.
Pecision in analog circuit design relies on matching
between capacitmces, resistors and transistors. Moreover
design centering and yield optimization rely on knowledge
of mismatching. How is matching expected to change
with scaling?
Most mismatch models [5,6] show that both Oj_and
O arc inversely proportional to the size WL. For a
differential pair, a minimum size W is thus required to
achieve an upper limit in input offset voltge. However
for submicron devices, extended moels .required which
alter the dependence on W and as given by
A
IVT
2
cVT'
WL
(6)
in which AIVT
is about 11 mV/lfi for a nMOST and
18 mVllm for a pMOST. Such dependence is illustrated
in Fig.2.
: 20
.
15
<
b
10
5

.6_
16.
,

I/l
g -0. 0964+ 10.959
.7

V
/2.8

.8
t?
1/
(
.
+
V

>
~
+
!CCVB DR

imple R DCBl

X.!0 C|
.< .4 . 0.8 1 1.2 1.4
1/-(WL) r1/uml
Fig.2: Spreaing on VT versus transistor size
High-speed design with submicron devices
In submicron CMOS devices, the channel length has
become so small that nearly all electrons move at
maximum speed v
sat
. As a result the maximum speed f
T,
which for long-channel devices is [3]
1 g
m
1
II
fT (
V
as
- V
T) (7a)
21 C
GS
21 L
2
tus into
1 Vsat
f
Tsat
21
(7)
for short-channel devices. This comes out to be about
32 GHz for 0.5 Jf.
However the presence of the gate overlap capacitances
and the drain-bulk depletion layer capacitance have an
inceasing infuence [7]. They reduce the maximum useful
frequency fm to about half of this i.e. 16 GHz. This is
illustrated in Fig.3, which shows both frequencies f
T
,
f
Tsat
and also fm for a nMOST at V
as
-VT
" 1 V.
Frequency fm follows f
Tsat
at a distance.
74
Nz)
- ~ 1
-.
.

~
fIn!
P
-

"
j.

"
!!

L (um)
Fig.3: Maximumfequencies for nMOST
As a conclusion, submicron devices do allow higher
frequency operation indeed, al least if lage curent is no
problem. Care has to be ten however to reduce the
parasitic transistor capacitances and of course the
interconnect capacitnces. At best about half of the fT can
Drealized.
For a low current IDS in weak inversion, the
maximum frequency
frlow
is given by
f - -
L
g
m -L nkT/q
I
DS
Tlow
- 21 C
GS
-
21 50 t
ox
W
(8)
which is again independent of the channel length.
Reducing the channel length does not increase the
maximum frequency of operation at this low current.
Operational amplifier design
The design of an operational amplifer is still the apex
of good design practice. Two problems will be addressed.
How to obtain the maximum operating voltage range ?
How to obtain the maximum operating frequency range?
Maximum output swing is easily obtained by use of a
conventional two-tansistor output stage. Maximum input
range has been realized in several rail-to-rail input
opamps. The main dificulty however is to obtain a
constant g
m
and hence a constnt gain-bandwidth product
over the full input range. This is easy in bipolars [8]
because constant current leads to constant gm. Tis is far
from trivial in MOST opamps. Two recent solutions
realize this by operating the input devices close to weak
inversion [9] or by inserting a voltage reference [10].
The input stage of the 1.3 V opamp is shown in FigA.
^u ul0Ou QOV0I 5uQQ I0guulOI 5 u50Il0U Vlh a
extensive biasing block ensuring exact crossover from
pMOST to nMOST. The total gm varies over about 10
V.
___

Fig.4: Input stage of I.3V CMOS opamp j9]

Cll
11

M1
13
Fig.Sa: Feedforward in fold casod with gain boosting
jII]
i i
_ l.U __

.
. .. I: ,_,;
::1

., ,...

_..,.
`......... ,
..
.... ,
.
...... ,. : ..... j . . j
["" " `""'""-... - " .`
.
.
..
.
... .
.
\ .".`.
.. ,
..""

""

2
............... , .. . . . . . ..
0.1 ++7!8 "97 -- rHh
0
8
10
g, z [H] (CAJ)
Fig.5b: Pole-zeo position diagram
A very different problem is to obtain maximum gain
bandwidth. For this purpose, the input devices have to b
operated at high values of VOS-VT, pushing the input
devices in velocity saturation. As a result maximum g
m
is obtained. This increases the current in all stages
because the non-dominant poles have to b at two to three
times higher frequencies [3]. The only way to reduce the
70
current is to use feedforward [11]. A example is given in
Figur Sa. The pole-zero psition diagran shows the exact
cancellation.
Care has to be tken however to avoid pole-zero
doublets, which occur Uno exact cancellation is achieved.
Tey deteriorate the settling time [3].
A example of such feedforward amplifier yielding 850
MHz GBW is shown in Fig.6 [12].
It uses a folded casco de in fully differential
configuration. It uses 36 mA in 1.2 /m CMOS
technology, for which the limit is about 1 GHz (see
Fig.3).
a a
Fig.6 High-speed opamp using feedforard
Mixed A+D design with sigma.delta converters
The ideal circuit block to lea about mixed Analog
Digital design is a sigma-delta converter. It requires a very
intimate integration of sampled-data signal handling and
digital clocks. Moreover its performance is not readily
predicted by simulatons. Three aspects ask for attention:
their low-power behaviour, the band-pass filter
implementation and their simulation.
Reducing the power in the frst intgrator increases its
noise, reducing the SIN ratio. O the other hand te faster
stages need more power. A good compromise is reached
by using feedforward to reduce power and by chopping the
input current sources to reduce the input noise [13]. A
mere 0.2 m W is reached for a fourth-order converter
yielding 80 0 dynamic range. The sampling frequency is
0.5 MHz.
The demodulation of a 20 kHz band around te IF
carrier of to.7 MHz is a good example for use of
continuous-time bandpass L converter. Although such
blockhas been around for a while [14], it is still difficult
to design. Moreover a high oversampling ratio is required
for high SIN ratio, requiring a opamp with a GBW in
excess of 0.5 GHz, which takes a lot of power [15].
Very low power consumption can b reached provided
the supply voltage is drastically reduced. Switches with
MOSTs ten become very difcult to realize. A solution
is the use of switched-opamp techniques as shown in
Figure 7 [16].
r
Fig.7 Switched opamp Sigma-Delta converter stage [ 16J
Precise prediction of the performance of a L
modulator requires system-level simulation, extaction of
parasitics and transistor-level simulation. As a result it
requires a MAD simulation tool, which is not yet
available. More about this in the last section.
Design of telecommunication circuits
Because of the exploding market, considerable attention
is going to high-frequency design for telecommunication
applica-tions. A integrated transceiver is on the table of
every analog design group, preferably in CMOS because
of the lower cost [17, 18, 19]. Circuit blocks such as
low-noise amplifers, mixers, VCO's, etc., have to be
designed in the GHz region. A good example is the mixer
of Figure 8. It combines simplicity and high frequency
porformance [20]. Only nMOS transistors are used to
achiede the 1.8 GHz prfornce.
Fig.S Integrated CMOS mixr [20J
7
As a result such circuits are simple ad consume a lot
of current. Another good example is the VCO shown in
Fig.9 [21]. Both tansistors carry 1.8 rA.
Vnul+ 0--
Fig.9: Integrted VCO in standrd CMOS circuit
The spectral purity mainly depends on the inductors
used. As a result we are seeing a revival of the inductor.
Initially the silicon was etched out under the inductor by
means of micromachining [22], in order to reduce the
parasitic resistance and capacitance. Careful modeling of
the inductor by means of fnite-element methods allows
the use of a standard CMOS proces [23]. The resultant
phase noise is quite low i.e. -116 dBc/Hz at 600 kHz
offset.
In telecommunication circuits, distortion is iportant
as well. CMOS ofers a great advantage because the
distortion products are scaled to V
OS-
V
T
rather than to
kT/q as in biplar circuits. However the range in V
{b
V
T
values becomes more and more limited, as explained
above.
Systematic analog design
As in digital design, the analog designer must provide
more designs in less time with less errors. Reuse of
existing circuits is one solution. Analog synthesis is even
more a solution [24]. This is called systematic design.
From a circuit topology, it generates a moel by means of
a symbolic simulator [25], it provides sizing,
optimization and constraint-driven layout [26]. Such
analog module generators have been in use since shortly
[27]. A example is shown in Figure 10. It is the result
of a constraint-driven placement package in which
constraints are take into account such as capacitive
coupling, mismatch, etc.
In the future however, such design systems will have
to cop with hierarchy, requiring spcification translation.
This is the way to design real mixed analog-digital
systems. Examples of high-level b design are given in
[28].
In addition putting analog and digitl together generates
coupling noise. Digital spikes are generated on supply
lines and substate, which deteriorate te analog precision.
Models have been generated but design rules are failing as
yet.
Fig. 1 0 . Constaint-driven placement of opamp
Conclusion
As higher sped circuits are required with less noise and
distortion, more circuit techniques will be required.
However models m failing. On the other hand new design
tools are appag which alleviate the designers task.
Acknowledgement:
The author would like to thank the designers and the
design automation people of the ESAT-MICAS group for
te many fuitful discussions.
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7