Proceedings of the 13th WSEAS International Conference on CIRCUITS

A Fault Tolerant Threshold Logic Gate Design

Ashok kumar Palaniswamy, Manoj kumar Goparaju, Spyros Tragoudas Department of Electrical and Computer Engineering Southern Illinois University Carbondale Carbondale, IL 62901. US. {ashok, goparaju, spyros}@engr.siu.edu

AbstractThreshold Logic gate is used as design abstraction for most nano devices and perceived as an alternate emerging technology to CMOS implementation. It is vulnerable to manufacturing inaccuracies that alter weight values which inadvertently affect the functionality of the gate. Hence fault tolerance should be taken in to consideration during the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extent. In this work, a fault tolerant design methodology for threshold logic gate is presented.

and the output of threshold logic gate is zero, when N i=1 wi xi < w0 Example 1: Consider a function f =x5 x4 x3 x2 x1 is implemented using threshold logic gate with weight conguration (w5 , w4 , w3 , w2 , w1 : w0 ). Figure 1 depicts the threshold logic symbol for the function f having four positive weights (w4 , w3 , w2 , w1 ),one negative weight (w5 ) and the basic threshold value(w0 ). The polarity of the weight values indicates the unateness of the variable with respect to that function.
x1 x2 x3 x4 x5
Figure. 1.

I. I NTRODUCTION The enhancement of semiconductor technologies to achieve complexity reduction and size decrement for implementing digital circuits leads to the development of a special kind of logic gate known as Threshold logic gate, which works on threshold principle. Using threshold gates instead of conventional logic gates, the number of gate levels can be drastically reduced and complex Boolean functions are implemented with minimal number of gates. A Boolean function represented by a single threshold logic gate is called as threshold function[1]. Threshold logic gate is a multiple terminal device which determines its output by comparing the weighted sum of inputs with its basic threshold value[1]. Threshold logic gate is a logic gate in which each input xi is associated with a weight value wi and its output depends upon the relation between the weighted sum of its inputs and the basic threshold value w0 . Thus its functionality is more sensitive to its weight values. When the input variable x is active (logic one) it is represented as x and it will be represented as x, when it is not active (logic zero). The combination of all input variables (active or passive) is called as minterm or input pattern. The minterm which produces logic one as the output is called as on-set minterm and the minterm which produces logic zero as the output is called as off-set minterm. The operation of N-input threshold logic gate is explained as follows. The output of threshold logic gate is one, when N i=1 wi xi w0

w1 w2 w3 w4 w5

w0

TLG symbol of function f

Threshold logic gate can be implemented using a resistor-transistor element, a magnetic core element or a MOBILE element. Null convention logic gate[3] and pass transistor logic[4] are examples of CMOS implementation of threshold logic gate. Null convention logic gate has N number of inputs either in an asserted state or in null state. Its output switches to an asserted state, when the total number of asserted inputs exceeds the threshold number. A detailed study of CMOS implementation of threshold logic gate can be found in [4]. NeuMOS[4] and CTL[3] are examples of capacitive implementations of threshold logic gates. Capacitive implementation uses array of capacitors to implement the weighted sum of the inputs. Beyond pseudo -nMOS [2] and beyond output wired inverters[3] are examples of current or conductance implementations of threshold logic gate. Recent study on CMOS implementation clearly indicates the advantage of using threshold logic gates to implement complex designs[4]. Another promising aspect of threshold logic gate

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Proceedings of the 13th WSEAS International Conference on CIRCUITS

is that it can also be implemented in post CMOS technology using a MOBILE element or a magnetic core element [2]. The popular nano-technological implementation of threshold logic is using the MOBILE element[4]. A MOBILE is a pseudo-dynamic clocked logic circuit consisting of a FET that is monolithically integrated with a resonant tunneling diode(RTD)[4]. In dynamic circuits, the logic state is represented by the electrical charge on a capacitor. In contrast, MOBILE circuits are in a static self stabilizing state because of their inherent bistability. Eventually, precharging is unnecessary for the threshold logic gates and they are more robust against charge leakage[5]. Figure 2 shows the MOBILE implementation of threshold function f in Example 1. It consists of ve RTD-HFET devices (HFET and RTD are in parallel connection) with four positive weighted inputs (x1 , x2 , x3 , x4 ) and one negative weighted input (x5 ) and serially connected Load and Driver RTD.
CLK

X1

RTD HFET W1

X2

RTD HFET W2

X3

RTD HFET W3

X4

RTD HFET W4 I

LOAD RTD

X 1 X 2 X 3 X 4 POSITIVE WEIGHT INPUTS X5 X 5 NEGATIVE WEIGHT INPUT RTD HFET W5 DRIVER RTD

Figure. 2.

MOBILE Implementation of TLG

This paper is organized as follows. Section 2 gives preliminaries and previous work on fault tolerant design methodology for threshold logic gates. Section 3 presents proposed fault tolerant design methodology. Section 4 presents experimental results. II. P RELIMINARIES AND P REVIOUS W ORK There is a change in weight values of threshold logic gate due to process variations during manufacturing. It should be noted that irrespective of technology of implementation, process variation affects the weight values which in turn affects the functionality of threshold logic gate. Here MOBILE implementation has been considered for illustration purpose.The output of MOBILE depends upon current ow through the RTDs. The peak current through the RTD is the weight value which depends upon the current density and the device area of the RTD which is given by the equation I= J*A, where I is current ow through the RTD, A is the area of the RTD and J is the current density [7]. Since MOBILE is implemented with number of RTDs, the logic output of the MOBILE depends upon the area

of the RTDs due to the direct relationship between current and area. Thus change in area will have the impact on peak current ow through the RTD(weight values of threshold logic gate). RTD is vertical device, hence the I-V characteristics of RTD depends on the vertical device dimensions (epitaxial layer stack) with a high sensitivity in the sub-nanometer range[10]. The increasing impact of optical lithography and etching on lateral dimensions causes variation in RTD area. Another prominent factor of parameter variations is due to the impact of optical lithography[8].When threshold logic gate is implemented in deep sub-micron areas with FinFET or RTD, the impact of inefcient lithography is very high. The specications are usually in the nanometer scale, hence any accumulation of extra material during fabrication along the side length of RTD will drastically change the area specications of the material[9]. The layout is not exact replica of designed layout due to inefciency of photo masking[6]. Inefcient photo masking, poor diode overgrowth and temperature changes during fabrication cause variation in the area of RTD [6]. When the area of RTD varies, the peak current varies and results in weight value change. The change in current density has also an effect on the ow of current. In case of a double-barrier resonant tunneling diode, it has been experimentally proved that Doping Concentration ND, well thickness dB and barrier thickness dW have great impact on the peak current density[8]. A double-barrier resonant tunneling diode is composed of a low-band gap quantum well with thickness dW sandwiched between two wide band gap electronic barriers with the thickness dB. With the presence of impurities, there might be generation of unwanted electrons or holes in conduction band or valence band. This might disturb the balance of the band gap inuencing the current ow of the RTD[8]. Due to the inaccuracies occurring during manufacturing of threshold logic gates, the manufactured m weights (wi ) will be different from the actual desired design weight value (wi ). The absolute difference bem tween the manufactured weight(wi ) and actual desired design weight value(wi ) is called as deviation di and given by the equation m di = |(wi ) wi |. [16] If this deviation is very large, the functionality of gate will be change. Hence fault tolerance is the important aspect taken in to consideration during weight assignment of the threshold logic gate. Many methods are proposed for the weight assignment of threshold logic gates. ILP based method[17] and Decomposition method[14] are the prominent weight assignment methods for threshold logic gates. The problem of decomposition method is that it returns the weight values with zero fault tolerance for any function. The ILP based method can be adjusted, so that the design

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of threshold logic gate has maximum fault tolerance. The drawback of this method is that it cannot easily handle threshold logic gates that have more than ve inputs. The ILP based method is described below. Example 2: Consider a threshold function G=x2 x1 whose weight values and respective fault tolerance is obtained by ILP based method[17]. The input-output relationship of the function G is given in Table I.
x2 0 0 1 1 x1 0 1 0 1 G 0 0 0 1 Inequality 0 < w0 w1 < w0 w2 < w0 w2 + w1 w0 Inequality with di 0 < w0 d0 w1 + d1 < w0 d0 w2 + d2 < w0 d0 w2 d2 + w1 d1 w0 + d0

I NPUT-O UTPUT R ELATIONS OF G

TABLE I

equations due to the drastic increase in number of unknown variables and number of inequality equations. The ILP takes long time to nd the weight values. The number of inequality equations and number of unknown variables increases with increase in number of inputs which makes the ILP based method inefcient to nd the weight values for large N-input threshold functions. Thus ILP based method[17] is not scalable even though it gives better fault tolerance weight assignments. The fault tolerant design methodology proposed in this paper eliminates the drawbacks of ILP based method[17] and efciently determines the best weight assignment for N-input threshold logic gate which has room for maximum fault tolerance(for any value of N) in minimal time. III. T HE P ROPOSED D ESIGN M ETHOD The proposed fault tolerant design method assigns weight values with room for fault tolerance and it is explained with the following Example.
x5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 Order Sum 0 4 3 7 3 7 6 10 2 6 5 9 5 9 8 12 -1 3 2 6 2 6 5 9 1 5 4 8 4 8 7 11 Act Vars 0 1 1 2 1 2 2 3 1 2 2 3 2 3 3 4 1 2 2 3 2 3 3 4 2 3 3 4 3 4 4 5

A threshold logic gate with weight conguration(w2 ,w1 :w0 ) for the function G in Example 2 should satisfy all inequalities shown in column 4 of Table I. The inequality equations shown in column 4 of Table I can be rewritten by including deviation constraints for each weight value as shown in column 5 of Table I. The deviation in weight may be either positive or negative. Hence only the worst case which affect the functionality is taken. The inequalities in column 5 of Table I are solved using ILP tool[22] to get weight assignment in which di value for each weight is maximized. Although each weight value has a different deviation di , the lowest di value (d) is taken as fault tolerance (FT) of the given threshold function. Because it is the only value that can be used for all weight value deviation to satisfy all inequalities which determines the functionality. Hence different di values in column 5 of Table I can be replaced with single d. The satisfaction of these inequalities along with this deviation constraints conrm that the functionality of the gate is unaffected, even though the weight values have some deviation. This will result in a designed function having the weight values with maximum fault tolerance that tolerates the manufacturing defects to the maximum possible extent. For the function G in Example 2, ILP based method[17] with maximum weight limit between -25 to 25 gives (w2 ,w1 :w0 ) as (18,18:25) which results to fault tolerance of 3.49805. This weight assignment assures that the functionality of the gate is unaffected, when the deviation of weight value is 3.49805. Thus the ILP based method[17] gives weight values having optimum fault tolerance for the given threshold function. For N-input function, ILP requires to solve 2N number of inequality equations to nd N number of unknown input weight values and the basic threshold value. When the number of inputs increases beyond ve, ILP becomes inefcient to solve the inequality

I NPUT-O UTPUT R ELATIONS OF P

TABLE II

Example 3: Consider threshold function P = x1 (x2 (x3 + x4 + x5 ) + x3 (x4 + x5 ) + x2 x3 x4 is implemented using threshold logic with weight conguration (w5 ,w4 ,w3 ,w2 ,w1 :w0 ). The input-output relationship of the function P is given in Table II.

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Denition 1: The minterm which produces logic one as output, when the specic input variable or vector is active (logic one) is termed as active minterm of that particular variable. The minterm which produces logic one as output, when the specic input variable or vector is inactive (logic zero) is termed as passive minterm of that particular variable. To nd the relation between weight values of all input variables, we use two variables known as dominant value(Lx ) and order value(Ox ) for each input variable(x) for the given threshold function. Denition 2: The dominant value(Lx ) of a variable is the difference between number of active minterms and number of passive minterms of that particular variable. Lx = Ax Px , where Ax and Px are number of active minterms and passive minterms of x. For the function P in Example 3, the number of active minterms, number of passive minterms and dominant value for each variable is (A5 , A4 , A3 , A2 , A1 ) = (5, 8, 9, 9, 10) (P5 , P4 , P3 , P2 , P1 ) = (7, 4, 3, 3, 2) (L5 , L4 , L3 , L2 , L1 ) = (2, 4, 6, 6, 8) (|L5 |, |L4 |, |L3 |, |L2 |, |L1 |) = (2, 4, 6, 6, 8) The proposed method initially assigns the order value for each variable. This is assigned from their respective dominant value using the range table shown in Table III. To assign order values for each variable, only the magnitude of Lx is considered .The polarity of Lx is used in the later stage of the weight assignment.
|L| Range 0 |L| < 1 1 |L| < 2 2 |L| < 4 4 |L| < 8 8 |L| < 16 16 |L| < 32 2n1 |L| < 2n Order Value 0 1 2 3 4 5 n

R ANGE T ABLE

TABLE III

The principle behind the formation of the range table is same as the concept of number of minterms. The number of minterms for N-input function is 2N . For each inclusion of new variable, the number of minterms is twice of the previous stage. The number of minterms for three input function is eight which is twice the number of minterms for two input function. Same principle is used in the formation of range table. The rst range contains maximum value as one. This maximum value is doubled (two), then the order is increased by one. The order is increased by one for each doubling of the maximum value. The number of minterms is always an integer value. Thus the order value for each variable is assigned

from the dominant value using range table. The variable with lowest dominant value(greater than zero) will have order value as one and this range is taken as reference range to assign order value for other variables. For the function P in Example 3, the order values are (O5 , O4 , O3 , O2 , O1 ) = (1, 2, 2, 2, 3) If the order value of any variable is zero, then weight value of that variable is zero and that variable is dont care variable with respect to the given function. The order value for all variables is to be checked to nd whether all variables with same order value have same dominant value. If they have different dominant values but with same order value then reassignment to the order values of variables is needed. Starting from the lowest order variable, the variables having same order value but with different dominant values are identied rst. This order value is taken as reference value. The variable with lowest dominant value having reference order value retains the same order value and variables with high dominant value with reference order value is incremented by one. We also increment the order value of all variables having order value greater than the reference value. At this point, the ordering value of all variables with lowest order value has been nalized. These variables are removed and the process is repeated for remaining variables, until no other variables exist. For the above function P in Example 3, the dominant and order values are (O5 , O4 , O3 , O2 , O1 ) = (1, 2, 2, 2, 3) (|L5 |, |L4 |, |L3 |, |L2 |, |L1 |) = (2, 4, 6, 6, 8) Here inputs (x4 , x3 , x2 ) have same order values (3,3,3) but with different dominant values (4,6,6) need reassignment of order values. The order value three is taken as reference value. Variable x4 which has low dominant value retains the same order value. The order values of x3 and x2 having high dominant value is incremented by one and order value of x1 is also incremented by one because its order value is greater than the reference value. The nal order value of the input variables are (O5 , O4 , O3 , O2 , O1 ) = (1, 2, 2, 2, 3) After the order values have been reassigned for each variable, the polarity of the dominant value (Lx ) of each input variable is directly assigned to the polarity of the order value of each input variable. For the function P in Example 3 is (O5 , O4 , O3 , O2 , O1 ) = (1, 2, 3, 3, 4). The polarity of Lx value determines the polarity of the weight value of each input variable and it identies the unateness of the variable with respect to the function. For the function P in Example 3, the negative polarity of L5 tells that input variable x5 is negative unate. The assigned order values determines the relation between all weight values of the input variables. In

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particular, the order value of the variables is the ratio of weight value of each variable for the given threshold function. Thus all input weight values are related to a single variable z using order value of the input variables. If z is the unknown variable, then weight distribution for the above function will be (w5 , w4 , w3 , w2 , w1 ) = (1z, 2z, 3z, 3z, 4z). All weight values of input variables are integer multiples of their order values and z. For any threshold function, there will be one onset minterm and one offset minterm. The lowest weight sum of the onset minterm and the highest weight sum of the offset minterm are the upper bound and lower bound of the basic threshold value. Any value between greater than lower bound value and less than or equal to upper bound for basic threshold value will satisfy the threshold inequality. But this value should be carefully chosen in order to get high fault tolerance. In this proposed method, the order values of input variables gives direct relationship between the weights of all input variables, which easily identify the onset and offset minterms which in turn the bounds of the basic threshold value. The weighted sum of inputs is also the integer multiple of z and summation of order values. The summation of order value of active variables (Order Sum) and number of active variables (Act Vars) of each minterm for the function P in Example 3 are shown in last two columns of Table II. The onset minterm which has lowest order sum is the minterm which gives upper bound value for the basic threshold value. In order to nd the basic threshold value which has room for maximum fault tolerance, if more than one onset minterms has the same lowest order sum value(OL ), then the minterm which has more number of active variables(AO ) is taken. The offset minterm which has highest order sum is the minterm which gives lower bound value for the basic threshold value. As mentioned early, if more than one offset minterm has the same highest order sum value(OH ), then the minterm which has more number of active variables(AF ) is taken. The weights of all input variables are expressed as multiples of z and every manufactured weight has deviation(d) from desired design weight value due to process variations during manufacturing. By using the notation of inequality equation as used in the ILP formulation explained in Section 2, we are able to express upper bound equation of the basic threshold value as the an integer constant(OL ) multiplied by z minus an integer constant(AO ) multiplied by d which must be greater than or equal to w0 + d.Working similarly ,we derive the inequality for the lower bound of the basic threshold value as the an integer constant(OL ) multiplied by z plus an integer constant(AO ) multiplied by

d which must be lesser than w0 d. By solving these inequalities, we get the basic threshold value(w0 ) and maximum allowable deviation of weight values or fault tolerance(d) for this weight assignment is obtained for the given threshold function. For the function P in Example 3, the weight values are (w5 , w4 , w3 , w2 , w1 ) = (1z, 2z, 3z, 3z4z) and from the Table II we get (OL =7,OH =5,AO =6,AF =4). When the maximum limit of weight values is between -25 to 25,we get (w5 , w4 , w3 , w2 , w1 ) = (4, 8, 12, 12, 16) w0 =25 and fault tolerance(d) or maximum allowable deviation = 0.25 Here we can clearly see that, the basic threshold value and fault tolerance depend upon the weights of the input variables. The fault tolerance of any function is always less than the magnitude of the lowest weight value. IV. E XPERIMENTAL R ESULTS In this section, the experimental results are presented to demonstrate the performance of the proposed method for weight assignment of threshold logic gates. This method is implemented in C language. We are able to handle any N-input threshold function in minimal time. The performance of the proposed method is compared with the ILP based method[17] for all the threshold functions having inputs less than ve. We compare the threshold functions having inputs less than or equal to ve,because the ILP based method does not work for functions having inputs greater than ve. The fault tolerance(FT) obtained for the N-input functions (N 5) by the proposed method(M2) is compared with fault tolerance obtained by the ILP based method (M1) [17] and shown in Table IV. All these results are obtained by putting the maximum weight limit between 25 and 25. Table IV shows the actual deviation of fault tolerance values between two methods, where Actual Deviation = FT of M1 - FT of M2.
NI 2 3 4 5 Funcs 12 102 1880 62570 0 100 52.94 23.45 19.90 FT Deviation Range 0-0.4 0.4-0.8 0.8-1.3 0 0 0 26.48 14.72 5.88 57.92 15.51 0.93 62.75 15.77 0.57 TABLE IV Max 0 1.2143 1.2123 1.2123

A CTUAL D EVIATION OF FAULT T OLERANCE

The maximum deviation of fault tolerance is always constant for any N-input threshold function and the deviation of fault tolerance value is very minimal for all threshold functions. The results show that the proposed method is scalable and works for any Ninput threshold function and always obtain very high

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fault tolerance and relatively same as the ILP based method. The time taken by the proposed scalable method is very minimal when compared to ILP based method[17]. The proposed method takes 75-90 percent less time compared to the time taken by ILP based method[17] for two and three input functions. For 4 and 5 input functions, the proposed method takes 9098 percent less time as compared to the time taken by ILP based method[17]. R EFERENCES
[1] S. Muroga, Threshold Logic and its Applications, John Wiley, New York, NY, 1971. [2] V. Beiu, J. M. Quintana, and M. J. Avedillo,R. Andonie, Differential implementations of threshold logic gates, International Symposium on Signals,Circuits and Systems,pp. 489-492, July 2003. [3] V. Beiu, J. M. Quintana, and M. J. Avedillo, VLSI implementations of threshold logic - A comprehensive survey, IEEE Trans. Neural Networks, vol. 14, pp. 1217-1243, September 2003. [4] V. Beiu, J. M. Quintana, and M. J. Avedillo, M. Sulieman, Threshold logic: from vacuum tubes to nanoelectronics, IEEE International Symposium on Micro-NanoMechatronics and Human Science, pp. 930935, December 2003. [5] V. Lirigis, E. Dubrova,Evaluation and Comparison of Threshold Logic Gates, 37th International Symposium on Multiple-Valued Logic,pp. 52-52, May 2007. [6] J.M. Jerke, Semiconductor measuresment technology: Optical and dimensional-measurement problems with photomasking in microelectronics, Special Publication National Bureau of Standards, Washington, DC. Optical Physics Div, vol. 76, October 1975. [7] P. Glosekotter, C. Pacha, W. Prost, S. Kim,H. van Husen, T. Reimann, F. J. Tegude, K. F. Goser, Circuit and Application Aspects of Tunneling Devices in a MOBILE Conguration Journal on Circuit Theory and Applications: Special Issue on Nanoelectronic Circuits (invited paper), 2002 submitted [8] W. Prost et al., Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunneling diodes, Int. J. Circ. Theory Appl., vol. 28, no. 6, pp. 537-552, Nov. 2000. [9] X.L.E. Wernersson, N. Carlsson, B. Gustafson, A Litwin and L Samuelson, Lateral current-constriction in vertical devices using openings in buried lattices of metallic discs, Applied Physics Letters vol. 71, no. 19, pp. 2803-2805, 1997. [10] L. Dozsa, F. Riesz, Vo Van Tuyen, B. Szentpali, A. Muller, I-V Characterisation of Resonant Tunneling Diodes, In Semiconductor Conference, pp. 653-656, October 1998. [11] Gary D.Hatchtel and Fabio Somenzi, Logic Synthesis and Verication Algorithms Springer,New York,2006. [12] T. Gowda, S. Vrudhula, G. Konjevod, Combinational equivalence checking for threshold circuits, In Proc. of the ACM GLSVLSI, 2007. [13] T. Gowda, S. Vrudhula, G. Konjevod, A non-ilp based threshold logic synthesis methodology, In Proc. of the IWLS, 2007. [14] T.Gowda and S Vrudhula,A decomposition based approach for synthesis of multi-level threshold logic circuits,Proc. of ASP-DAC, pp. 125130, January 2008. [15] G.De Micheli, Synthesis and optimization of digital circuits, McGrawHill Inc., NJ, 1994. [16] M.Goparaju and S.Tragoudas,A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates,VLSI Test Symp.,pp.323-328,April 2008 [17] M.Goparaju and S.Tragoudas,Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations,Proc. of the 8th Intl. Symp. on Quality Electronic Design,pp.420-425,March 2007. [18] S. Dechu, M.Goparaju and S. Tragoudas, A metric of tolerance for the manufacturing defects of Threshold logic gates, The 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 318-326, October 2006. [19] R. Zhang, P. Gupta, L. Zhong and N.K. Jha, Threshold Network Synthesis and Optimization and Its Applications to Nano Technologies, IEEE Transactions on Computer-Aided Design Of Integrated Circuits And Systems, vol. 24, pp. 107-118, January 2005. [20] S.Borkar,T.Karnik,S.Narendra,J.Tschanz,A.Keshavarzi,V.De, Parameter variations and impact on circuits and microarchitecture,Design Automation Conference,pp.338-342 June 2003. [21] S.Natarajan,M.A.Breuer,S.K.Gupta, Process variations and their impact on circuit operation,Defect and Fault Tolerance in VLSI Systems, pp.73-81 November 1998. [22] M.Berkelaar,lp-solve,version4.0, www.cs.sunysb.edu/algorithm/implement /lp solve/.

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