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Introduction to Digital Circuits

Dr. Fadi R. Shahroury

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5.1.4 The Ebers-Moll BJT Model

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BJT Modes of Operation


Cutoff
Biasing: BE Reverse, BC Reverse

Saturation
Biasing: BE Forward, BC Forward
Lighter doping

VCE (SAT)=0.2V

Slightly larger than FA=0.7

(open switch) Forward Active


Biasing: BE Forward, BC Reverse
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(closed switch) Reverse Active


Biasing: BE Reverse, BC Forward
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BJT Saturation
Saturation Parameter:
How deep in saturation (at edge s =1)

e.g. Given Q is in saturation, bF=65 - Find the currents in the base and collector. - Find how deep in saturation is Q.

Easy analysis because transistors will be in either cutoff or saturation.

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5.10 The Basic BJT Digital Logic Inverter

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5.10.1 The Voltage Transfer Characteristic

VOH: Largest o/p voltage of gate (logic 1). VOL: Smallest o/p voltage of gate (logic 0). VIL: Maximum i/p voltage that results in VOH. VIH: Minimum i/p voltage that results in VOL.

Noise Margins Noise Margin for high i/p NMH = VOH-VIH Noise Margin for low i/p NML = VIL-VOL

Ideal case: VOH = VCC, VOL=0V, VIL=VIH=VCC/2, NMH=NML=VCC/2.


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5.10.1 The Voltage Transfer Characteristic


Find the critical voltages and noise margins for the BJT inverter shown. Assume b=50, VBE<0.6V cut off 0.6 VBE 0.7V active VBE(sat)=0.8V saturation VCE(sat)=0.2V

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Implementation Topologies - 1
Simple Switch

Transistors are used as switches.


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The Basic Principles of Operation of BJT

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Turn On Transient [Diffusion Capacitor]

Minority-carrier lifetime

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Turn OFF Transient [Diffusion Capacitor]

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Diffusion Capacitor Time Delay


the input logic 1 = 10V The input logic 0 =0.2 V VCE(sat)=0.2V VBE(sat)=0.8V tn=1ns b=50 s=1/5 a) Find the value of RB. b) Find ton c) Find toff
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1.7.7 Propagation Delay


Delay Definitions
Vin

50% t Vout t pHL t pLH 90% 50% 10% t

Propagation Time:

tf
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tr
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Ring Oscillator
v0 v1 v2 v3 v4 v5

v0

v1

v5

T = 2 tp N
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Power Dissipation
Power-Delay Product PDP=tpXPav= Energy dissipated per operation

PDP=0.5VccVswingC

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Definition of Noise Margins


"1" V OH Noise Margin High Noise Margin Low V OL "0" Gate Output
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NMH

V IH Undefined Region V IL

NML

Gate Input
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Fan-in and Fan-out


(a) Fan-out N

M N (b) Fan-in M

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