VLSI LAB ASSIGNMENT

Simulation of a Single Bit Full Adder Circuit using CMOS Transistor

SUBMITTED BY: RAHUL SAXENA, 09102253 TEJPAL SINGH, 09102334 A4 Batch

OBJECTIVE: 1.) To implement the 1-bit Full Adder using CMOS transistors (Mirror Adder Technique) SOFTWARE USED: Tanner Tools: T-Spice, S-Edit, W-Edit THEORY:
A one-bit full adder is a device with three single bit binary inputs (A, B, Cin) and two single bit binary outputs (Sum, C-out). Having both carry in and carry out capabilities, the full adder is highly scalable and found in many cascaded circuit implementations. The basic logic functions of the full adder can be summarized in the truth table (right). From the truth table it can be seen that the full adder can be trivially constructed with two half adders. The full adder can also be decomposed into the following logical relationships: One possible implementation of the full adder is the Mirror Full Adder. This circuit device consists of 28 total transistors (4 transistors used for the construction of two inverters).

Gate Level representation of a 1-bit Full adder

CIRCUIT DIAGRAM:

Implementation for a Full Adder at the transistor level (Mirror Adder)

DESIGN STEPS: 1. 2. 3. 4. 5. 6. 7. Go to S-Edit - Open New file. Draw the above shown MOSFET circuit of the Full-Adder. Mark the nodes and set the values for the voltage sources. Extract the design in T-Spice. Write the simulation conditions and the model parameters for the transistors. In T-Spice -> Run simulation. Cross check the obtained results with the Full-Adder Truth Table.

TSPICE CODE:
* SPICE netlist written by S-Edit Win32 7.00 * Written on Apr 24, 2012 at 19:52:20 * Waveform probing commands .probe .options probefilename="File0.dat" + probesdbfile="C:\Users\hp\Desktop\File0.sdb" + probetopmodule="Module0" * Main circuit: Module0 M4 5 B0 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M5 4 A0 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M6 4 B0 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M7 3 Cin 4 Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M8 3 A0 5 Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M9 Cout 3 Gnd N24 M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M10 8 A0 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M11 8 B0 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M12 8 Cin Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M13 7 3 8 Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M14 7 Cin 11 Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M15 11 A0 12 Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M16 12 B0 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M17 sum 7 Gnd Gnd M_N L=2u W=22u AD=66p PD=24u AS=66p PS=24u M18 3 Cin 1 Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M19 1 A0 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M20 1 B0 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M21 2 B0 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M22 3 A0 2 Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M23 Cout 3 Vdd N25 M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M24 7 3 6 Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M25 6 B0 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M26 6 A0 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M27 6 Cin Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M28 10 B0 9 Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M29 7 Cin 10 Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u M30 9 A0 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M31 sum 7 Vdd Vdd M_P L=2u W=22u AD=66p PD=24u AS=66p PS=24u v32 Vdd Gnd 2.0 v1 A0 Gnd pulse(0.0 5.0 0 0 0 20n 40n) v2 B0 Gnd pulse(0.0 5.0 0 0 0 10n 20n) v3 Cin Gnd pulse(0.0 5.0 0 0 0 5n 10n) .MODEL M_N NMOS (LEVEL=1 KP=5E-05 VTO=0.7 lambda=0.01) .MODEL M_P PMOS (LEVEL=1 KP=1.6E-05 VTO=-1.0 lambda=0.01) .tran .05n 40n .print V(A0) V(B0) V(Cin) V(sum) V(Cout) .END

OUTPUT WAVEFORM:

RESULT/ LEARNING OUTCOME: The Full adder circuit was designed and implemented and the waveforms obtained were in agreement with the truth table for the circuit.