PAR 17oct11

ERRORS: ======== ERROR - par: I/O initial placement is unsuccessful.
Please check the I/O placem ent constraints / user preferences (such as pin locking) carefully. ERROR - srio_subsys_top_u/rio_clk matches no nets in the design. ERROR - srio_subsys_top_u/refck2core matches no nets in the design. ERROR - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. ERROR - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. ERROR - srio_subsys_top_u/pcs_if_clk matches no nets in the design. ERROR - sys_clk matches no nets in the design. srio_subsys_top_u/refck2core matc hes no nets in the design. ERROR - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. srio_subs ys_top_u/pcs_if_clk matches no nets in the design. ERROR - srio_subsys_top_u/pcs_if_clk matches no nets in the design. srio_subsys_ top_u/tx_full_clk_c matches no nets in the design. ERROR - "srio_subsys_top_u/pcs_serdes/pcsd_inst" matches no asics in the design. ERROR - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. srio_subs ys_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_gen/full_clk_div8 match es no nets in the design. ERROR - srio_subsys_top_u/pcs_if_clk matches no nets in the design. srio_subsys_ top_u/rx_half_clk_ch0 matches no nets in the design. ERROR - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. srio_su bsys_top_u/pcs_if_clk matches no nets in the design. ERROR - *oplm2_mgt_1x_2x_nx_init_sm?init_state* matches no cells in the design. ERROR - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. sys_clk matches no nets in the design. ERROR - "*wrapper_srio_4x*rio_maintenance_module*bus_interface*mgt_a*" matches n o cells in the design. ERROR - <E0003> Port 'I_brd_clk' is not found. ERROR - <E0002> Net '*pcs_if_clk_reset_n' is not found. ERROR - <E0002> Net '*rio_clk_reset_n' is not found. ERROR - <E0005> Unknown Object 'CELL' '*wrapper*ollm_serial_tx_link_sched*local_ reset_n'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_3'. ERROR - <E0005> Unknown Object 'PORT' 'ADC_SYNC'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_HDS2_L'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_4'. ERROR - <E0005> Unknown Object 'PORT' 'RESET_RADIO_IF2'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_5'. ERROR - <E0005> Unknown Object 'PORT' 'PA_MEAS'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_6'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_7'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_8'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_0'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data_10'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_9'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_1'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_0'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data_11'. ERROR - <E0005> Unknown Object 'PORT' 'O_ARM_WAIT_n'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_2'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_1'. ERROR - <E0005> Unknown Object 'PORT' 'rx_clk'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_3'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_2'. ERROR - <E0005> Unknown Object 'PORT' 'spi_clk'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_4'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_3'.
ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR
<E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005>
Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object
'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT' 'PORT'
'clk_out'. 'SEQ_DATA_5'. 'tx_data2_4'. 'HPI_HRDY_L'. 'HPI_DATA_10'. 'SEQ_DATA_6'. 'tx_data2_5'. 'HPI_DATA_11'. 'SEQ_DATA_7'. 'tx_data2_6'. 'adc_obn_int_10'. 'HPI_DATA_12'. 'tx_data2_7'. 'TX_DAC_EN'. 'adc_obn_int_11'. 'HPI_DATA_13'. 'tx_data2_8'. 'adc_obn_int_12'. 'rxb_d_0'. 'FPGA_LED'. 'dac_b_clk'. 'HPI_DATA_14'. 'tx_data2_9'. 'adc_obn_int_13'. 'rxb_d_1'. 'HPI_DATA_15'. 'rxb_rdnwr'. 'rxb_d_2'. 'rxb_d_3'. 'HPI_DATA_0'. 'I_Rst_n'. 'rxb_d_4'. 'EN_DIS_DATA_PUMP2'. 'TX2_Lock'. 'HPI_DATA_1'. 'FRAME_SYNC1_0'. 'rxb_d_5'. 'HPI_DATA_2'. 'FRAME_SYNC1_10'. 'rxb_d_6'. 'FRAME_SYNC1_1'. 'HPI_HAS'. 'HPI_R_WL'. 'HPI_DATA_3'. 'FRAME_SYNC1_11'. 'rxb_d_7'. 'FRAME_SYNC1_2'. 'HPI_DATA_4'. 'FRAME_SYNC1_12'. 'SCL'. 'FRAME_SYNC1_3'. 'HPI_DATA_5'. 'FRAME_SYNC1_13'. 'iq_sel2'. 'FRAME_SYNC1_4'. 'spi_en2_0'. 'HPI_DATA_6'. 'PERIO_ATTN_EN_DIS2'. 'FRAME_SYNC1_5'. 'spi_en2_1'.
'spi_do2'. 'HPI_DATA_7'. 'DSP6748_SYNC_A'. 'FRAME_SYNC1_6'. 'spi_en2_2'. 'HPI_DATA_8'. 'DSP6748_SYNC_B'. 'FRAME_SYNC1_7'. 'spi_en2_3'. 'HPI_DATA_9'. 'GC_SYNC_A'. 'FRAME_SYNC1_8'. 'spi_en2_4'. 'GC_SYNC_B'. 'I_ARM_WE_n'. 'FRAME_SYNC1_9'. 'spi_en2_5'. 'TX1_Lock'. 'dac_a_clk'. 'dc_dc_sync'. 'spi_en2_6'. 'RF_enable'. 'I_ARM_Addr_1'. 'FPGA_TO_DSP_TS_INT'. 'spi_en2_7'. 'spi_clk2'. 'I_ARM_Addr_2'. 'RX_ADC_EN'. 'DIR_CTRL'. 'EN_DIS_DATA_PUMP'. 'I_brd_clk'. 'RESET_RADIO_IF'. 'RX1_Lock'. 'HPI_HCNTL_0'. 'B_ARM_Data_0'. 'txc_sleep2'. 'HPI_HCNTL_1'. 'B_ARM_Data_1'. 'B_ARM_Data_2'. 'HPI_HDS1_L'. 'B_ARM_Data_3'. 'rxb_dsrd'. 'O_ARM_INT_n'. 'B_ARM_Data_4'. 'ADC_TS_0'. 'EMIFENA'. 'B_ARM_Data_5'. 'ADC_TS_1'. 'rx_sync'. 'B_ARM_Data_6'. 'adc_obn_int_0'. 'ADC_TS_2'. 'B_ARM_Data_7'. 'timing_fs'. 'adc_obn_int_1'. 'B_ARM_Data_8'. 'spi_en_0'. 'adc_obn_int_2'. 'B_ARM_Data_10'. 'B_ARM_Data_9'.
ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR c'. ERROR
<E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005>
Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object
'PORT' 'spi_do'. 'PORT' 'spi_en_1'. 'PORT' 'TX1_MOD_EN_A'. 'PORT' 'adc_obn_int_3'. 'PORT' 'PERIO_ATTN_EN_DIS'. 'PORT' 'B_ARM_Data_11'. 'PORT' 'spi_en_2'. 'PORT' 'adc_obn_int_4'. 'PORT' 'tx_data_0'. 'PORT' 'B_ARM_Data_12'. 'PORT' 'spi_en_3'. 'PORT' 'SDA'. 'PORT' 'adc_obn_int_5'. 'PORT' 'ADC_MC_ADDR_0'. 'PORT' 'B_ARM_Data_13'. 'PORT' 'FPGA_TO_DSP_OBN_CLK'. 'PORT' 'adc_obn_int_6'. 'PORT' 'ADC_MC_ADDR_1'. 'PORT' 'tx_data_1'. 'PORT' 'B_ARM_Data_14'. 'PORT' 'adc_obn_int_7'. 'PORT' 'ADC_MC_ADDR_2'. 'PORT' 'tx_reset'. 'PORT' 'tx_data_2'. 'PORT' 'B_ARM_Data_15'. 'PORT' 'tx_data2_10'. 'PORT' 'TX2_MOD_EN_A'. 'PORT' 'adc_obn_int_8'. 'PORT' 'tx_data_3'. 'PORT' 'I_ARM_OE_n'. 'PORT' 'tx_data2_11'. 'PORT' 'adc_obn_int_9'. 'PORT' 'rxb_dtack_rdy'. 'PORT' 'tx_data_4'. 'PORT' 'rxb_cs'. 'PORT' 'iq_sel_a'. 'PORT' 'tx_data_5'. 'PORT' 'HPI_HCS_L'. 'PORT' 'I_ARM_CS_n'. 'PORT' 'iq_sel_b'. 'PORT' 'tx_data_6'. 'PORT' 'tx_data_7'. 'PORT' 'rx_data0'. 'PORT' 'iq_wrt2'. 'PORT' 'txdac_reset2'. 'PORT' 'T2RXC1'. 'PORT' 'RX2_Lock'. 'PORT' 'tx_data_8'. 'PORT' 'rx_data1'. 'PORT' 'PA_ON_OFF2'. 'PORT' 'tx_data_9'. 'PORT' 'PA_ON_OFF'. 'PORT' 'PA_MEAS2'. 'PORT' 'HPI_HHWIL'. 'CLOCK/CE/LSR NET' 'iq_clk_c'. 'CLKNET/CeLsrNET' 'FPGA_TO_DSP_OBN_CLKgen'. 'CLKNET/CeLsrNET' 'srio_subsys_top_u/tx_full_clk_
- <E0005> Unknown Object 'CLKNET/CeLsrNET' 'srio_subsys_top_u/refck2core'.
WARNINGS: ========= @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":310:14:310:27|OTHERS clause is not synthesized @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":396:14:396:27|OTHERS clause is not synthesized @W: CD326 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":409:2:409:9|Port almostempty of entity work.fifo_32_64_64 is unco nnected @W: CD326 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":426:4:426:11|Port almostempty of entity work.fifo_32_64_64 is unc onnected @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":518:5:518:18|OTHERS clause is not synthesized @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":597:14:597:27|OTHERS clause is not synthesized @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":31:30:31:39|Signal fifo_write is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":35:7:35:17|Signal wr_adc_data is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":37:7:37:13|Signal cs_read is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":37:16:37:23|Signal cs_write is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":42:7:42:22|Signal start_fifo1_read is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":42:24:42:39|Signal start_fifo2_read is undriven @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":280:14:280:17|Inconsistency in number of generics declared on componen t and2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":313:14:313:16|Inconsistency in number of generics declared on componen t inv (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":316:14:316:16|Inconsistency in number of generics declared on componen t or2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":330:14:330:17|Inconsistency in number of generics declared on componen t xor2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":297:14:297:20|Inconsistency in number of generics declared on componen t fd1p3bx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":301:14:301:20|Inconsistency in number of generics declared on componen t fd1p3dx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":309:14:309:20|Inconsistency in number of generics declared on componen t fd1s3dx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":305:14:305:20|Inconsistency in number of generics declared on componen t fd1s3bx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":287:14:287:19|Inconsistency in number of generics declared on componen t fadd2b (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":283:14:283:16|Inconsistency in number of generics declared on componen
t cu2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":292:14:292:19|Inconsistency in number of generics declared on componen t fsub2b (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":276:14:276:18|Inconsistency in number of generics declared on componen t ageb2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":324:14:324:16|Inconsistency in number of generics declared on componen t vhi (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":327:14:327:16|Inconsistency in number of generics declared on componen t vlo (0) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|Pruning Register wr_fifo_not_empty @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":450:5:450:6|Pruning Register ADC_fifo_op(63 downto 0) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":324:8:324:9|Pruning Register data_written @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":240:8:240:9|Pruning Register data_received @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(63) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(62) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(61) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(60) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(59) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(58) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(57) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(56) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(55) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(54) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(53) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(52) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(51) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(50) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(49) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(48) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(47) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(46) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(45) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A
DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(44) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(43) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(42) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(41) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(40) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(39) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(38) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(37) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(36) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(35) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(34) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(33) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(32) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(31) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(30) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(29) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(28) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(27) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(26) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(25) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(24) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(23) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(22) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(21) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(20) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(19) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(18) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(17) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(16) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(15) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A
DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(14) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(13) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(12) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(11) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(10) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(9) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(8) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(7) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(6) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(5) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(4) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(3) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(2) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(1) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(0) @W: CL111 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|All reachable assignments to both_fifo_not_empty assi gn '0', register removed by optimization @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":324:8:324:9|Initial value is not supported on state machine spi_w r_state @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":240:8:240:9|Initial value is not supported on state machine spi_r d_state @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":450:5:450:6|Initial value is not supported on state machine fifo_ rd_state @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|Initial value is not supported on state machine fifo_ wr_state @W: CL159 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":11:0:11:5|Input DAC_TS is unused @W: CL159 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":16:0:16:2|Input OBN is unused @W: MT420 |Found inferred clock ADC_SPI_RX|CLOCK with period 5.00ns. A user-defi ned clock should be declared on object "p:CLOCK" @W: MT420 |Found inferred clock ADC_SPI_RX|lnk_clk with period 5.00ns. A user-de fined clock should be declared on object "p:lnk_clk" @W: MT420 |Found inferred clock ADC_SPI_RX|DAC_SCLK_inferred_clock with period 5 .00ns. A user-defined clock should be declared on object "n:DAC_SCLK" @W: MT246 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1187:4:1187:14|Blackbox AGEB2 is missing a user supplied timin g model. This may have a negative effect on timing analysis and optimizations (Q uality of Results) WARNING - edif2ngd: Property mem_init_file has no value - ignoring... WARNING - edif2ngd: Property mem_init_file has no value - ignoring...
WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
edif2ngd: edif2ngd: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild:
Property mem_init_file has no value - ignoring... Property mem_init_file has no value - ignoring... logical net 'rx_fifo2/w_gctr_cia_S0_0' has no load logical net 'rx_fifo2/w_gctr_cia_S1_0' has no load logical net 'rx_fifo2/co2' has no load logical net 'rx_fifo2/r_gctr_cia_S0_0' has no load logical net 'rx_fifo2/r_gctr_cia_S1_0' has no load logical net 'rx_fifo2/co2_1' has no load logical net 'rx_fifo2/rfill_0_S0_0' has no load logical net 'rx_fifo2/rfill_3_BOUT_0' has no load logical net 'rx_fifo2/rfill_3_S1_0' has no load logical net 'rx_fifo2/empty_cmp_ci_a_S0_0' has no load logical net 'rx_fifo2/empty_cmp_ci_a_S1_0' has no load logical net 'rx_fifo2/a0_COUT_0' has no load logical net 'rx_fifo2/a0_S1_0' has no load logical net 'rx_fifo2/full_cmp_ci_a_S0_0' has no load logical net 'rx_fifo2/full_cmp_ci_a_S1_0' has no load logical net 'rx_fifo2/a1_COUT_0' has no load logical net 'rx_fifo2/a1_S1_0' has no load logical net 'rx_fifo2/af_set_ctr_cia_S0_0' has no load logical net 'rx_fifo2/af_set_ctr_cia_S1_0' has no load logical net 'rx_fifo2/co2_6' has no load logical net 'rx_fifo2/af_set_cmp_ci_a_S0_0' has no load logical net 'rx_fifo2/af_set_cmp_ci_a_S1_0' has no load logical net 'rx_fifo2/a4_COUT_0' has no load logical net 'rx_fifo2/a4_S1_0' has no load logical net 'rx_fifo2/af_clr_ctr_cia_S0_0' has no load logical net 'rx_fifo2/af_clr_ctr_cia_S1_0' has no load logical net 'rx_fifo2/co2_7' has no load logical net 'rx_fifo2/af_clr_cmp_ci_a_S0_0' has no load logical net 'rx_fifo2/af_clr_cmp_ci_a_S1_0' has no load logical net 'rx_fifo2/a5_COUT_0' has no load logical net 'rx_fifo2/a5_S1_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO10_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO11_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO12_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO13_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO14_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO15_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO16_0' has no load logical net 'rx_fifo2/pdp_ram_0_1_0_DO17_0' has no load logical net 'rx_fifo1/w_gctr_cia_S0' has no load logical net 'rx_fifo1/w_gctr_cia_S1' has no load logical net 'rx_fifo1/co2' has no load logical net 'rx_fifo1/r_gctr_cia_S0' has no load logical net 'rx_fifo1/r_gctr_cia_S1' has no load logical net 'rx_fifo1/co2_1' has no load logical net 'rx_fifo1/rfill_0_S0' has no load logical net 'rx_fifo1/rfill_3_BOUT' has no load logical net 'rx_fifo1/rfill_3_S1' has no load logical net 'rx_fifo1/empty_cmp_ci_a_S0' has no load logical net 'rx_fifo1/empty_cmp_ci_a_S1' has no load logical net 'rx_fifo1/a0_COUT' has no load logical net 'rx_fifo1/a0_S1' has no load logical net 'rx_fifo1/full_cmp_ci_a_S0' has no load logical net 'rx_fifo1/full_cmp_ci_a_S1' has no load logical net 'rx_fifo1/a1_COUT' has no load logical net 'rx_fifo1/a1_S1' has no load logical net 'rx_fifo1/af_set_ctr_cia_S0' has no load logical net 'rx_fifo1/af_set_ctr_cia_S1' has no load
WARNING - ngdbuild: logical net 'rx_fifo1/co2_6' has no load WARNING - ngdbuild: logical net 'rx_fifo1/af_set_cmp_ci_a_S0' has no load WARNING - ngdbuild: logical net 'rx_fifo1/af_set_cmp_ci_a_S1' has no load WARNING - ngdbuild: logical net 'rx_fifo1/a4_COUT' has no load WARNING - ngdbuild: logical net 'rx_fifo1/a4_S1' has no load WARNING - ngdbuild: logical net 'rx_fifo1/af_clr_ctr_cia_S0' has no load WARNING - ngdbuild: logical net 'rx_fifo1/af_clr_ctr_cia_S1' has no load WARNING - ngdbuild: logical net 'rx_fifo1/co2_7' has no load WARNING - ngdbuild: logical net 'rx_fifo1/af_clr_cmp_ci_a_S0' has no load WARNING - ngdbuild: logical net 'rx_fifo1/af_clr_cmp_ci_a_S1' has no load WARNING - ngdbuild: logical net 'rx_fifo1/a5_COUT' has no load WARNING - ngdbuild: logical net 'rx_fifo1/a5_S1' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO10' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO11' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO12' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO13' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO14' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO15' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO16' has no load WARNING - ngdbuild: logical net 'rx_fifo1/pdp_ram_0_1_0_DO17' has no load WARNING - ngdbuild: logical net 'rd_count_cry_0_S0_0' has no load WARNING - ngdbuild: logical net 'rd_count_s_0_S1_7' has no load WARNING - ngdbuild: logical net 'rd_count_s_0_COUT_7' has no load WARNING - ngdbuild: logical net 'DAC_TS' has no load WARNING - ngdbuild: logical net 'OBN_0' has no load WARNING - ngdbuild: logical net 'OBN_1' has no load WARNING - ngdbuild: logical net 'OBN_2' has no load WARNING - ngdbuild: logical net 'OBN_3' has no load WARNING - ngdbuild: logical net 'OBN_4' has no load WARNING - ngdbuild: logical net 'OBN_5' has no load WARNING - ngdbuild: logical net 'OBN_6' has no load WARNING - ngdbuild: logical net 'OBN_7' has no load WARNING - ngdbuild: logical net 'OBN_8' has no load WARNING - ngdbuild: logical net 'OBN_9' has no load WARNING - ngdbuild: logical net 'OBN_10' has no load WARNING - ngdbuild: logical net 'OBN_11' has no load WARNING - ngdbuild: logical net 'OBN_12' has no load WARNING - ngdbuild: logical net 'OBN_13' has no load WARNING - ngdbuild: DRC complete with 96 warnings WARNING - map: Semantic Error: "I_brd_clk" matches no ports in the design. Occu rred at line 19 in "FREQUENCY PORT "I_brd_clk" 52.000000 MHz ; WARNING - map: Semantic Error: srio_subsys_top_u/refck2core matches no nets in t he design. Occurred at line 95 in "FREQUENCY NET "srio_subsys_top_u/refck2core" 125.000000 MHz ; WARNING - map: Semantic Error: srio_subsys_top_u/refck2core matches no nets in t he design. Occurred at line 96 in "USE SECONDARY NET "srio_subsys_top_u/refck2c ore" ; WARNING - map: Semantic Error: srio_subsys_top_u/rio_clk matches no nets in the design. Occurred at line 109 in "FREQUENCY NET "srio_subsys_top_u/rio_clk" 39.0 62500 MHz ; WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. Occurred at line 110 in "FREQUENCY NET "srio_subsys_top_u/tx_full _clk_c" 312.500000 MHz ; WARNING - map: Semantic Error: srio_subsys_top_u/pcs_if_clk matches no nets in t he design. Occurred at line 111 in "FREQUENCY NET "srio_subsys_top_u/pcs_if_clk " 156.250000 MHz ; WARNING - map: Semantic Error: srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. Occurred at line 112 in "FREQUENCY NET "srio_subsys_top_u/rx_ha lf_clk_ch0" 156.250000 MHz ; WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i
n the design. Occurred at line 118 in "USE SECONDARY NET "srio_subsys_top_u/tx_ full_clk_c" ; WARNING - map: Semantic Error: srio_subsys_top_u/pcs_if_clk matches no nets in t he design. srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. Occ urred at line 123 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/pcs_if_clk" TO C LKNET "srio_subsys_top_u/rx_half_clk_ch0" ; WARNING - map: Semantic Error: srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. srio_subsys_top_u/pcs_if_clk matches no nets in the design. Occ urred at line 124 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/rx_half_clk_ch0" TO CLKNET "srio_subsys_top_u/pcs_if_clk" ; WARNING - map: Semantic Error: srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. sys_clk matches no nets in the design. Occurred at line 125 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/rx_half_clk_ch0" TO CLKNET "sys_clk" ; WARNING - map: Semantic Error: sys_clk matches no nets in the design. srio_subsy s_top_u/refck2core matches no nets in the design. Occurred at line 126 in "BLOC K PATH FROM CLKNET "sys_clk" TO CLKNET "srio_subsys_top_u/refck2core" ; WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. srio_subsys_top_u/pcs_if_clk matches no nets in the design. Occur red at line 128 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/tx_full_clk_c" TO CLKNET "srio_subsys_top_u/pcs_if_clk" ; WARNING - map: Semantic Error: srio_subsys_top_u/pcs_if_clk matches no nets in t he design. srio_subsys_top_u/tx_full_clk_c matches no nets in the design. Occur red at line 129 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/pcs_if_clk" TO CLK NET "srio_subsys_top_u/tx_full_clk_c" ; WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. srio_subsys_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_ gen/full_clk_div8 matches no nets in the design. Occurred at line 130 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/tx_full_clk_c" TO CLKNET "srio_subsys_top_u /wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_gen/full_clk_div8" ; WARNING - map: Semantic Error: *rio_clk_reset_n matches no nets in the design. Occurred at line 132 in "BLOCK NET "*rio_clk_reset_n" ; WARNING - map: Semantic Error: *pcs_if_clk_reset_n matches no nets in the design . Occurred at line 133 in "BLOCK NET "*pcs_if_clk_reset_n" ; WARNING - map: Semantic Error: "srio_subsys_top_u/pcs_serdes/pcsd_inst" matches no asics in the design. Occurred at line 135 in "BLOCK PATH FROM ASIC "srio_sub sys_top_u/pcs_serdes/pcsd_inst" PIN "*FF_EBRD_CLK_?" ; WARNING - map: Semantic Error: *oplm2_mgt_1x_2x_nx_init_sm?init_state* matches n o cells in the design. Occurred at line 136 in "BLOCK PATH FROM CELL "*oplm2_mg t_1x_2x_nx_init_sm?init_state*" TO CELL "*oplm2_mgt_1x_2x_nx_tx_int*" ; WARNING - map: Semantic Error: "*wrapper*ollm_serial_tx_link_sched*local_reset_n " matches no cells in the design. Occurred at line 139 in "MAXDELAY FROM CELL " *wrapper*ollm_serial_tx_link_sched*local_reset_n" 16.000000 ns ; WARNING - map: Semantic Error: "*wrapper_srio_4x*rio_maintenance_module*bus_inte rface*mgt_a*" matches no cells in the design. Occurred at line 140 in "MULTICYC LE FROM CELL "*wrapper_srio_4x*rio_maintenance_module*bus_interface*mgt_a*" 2.00 0000 X ; WARNING - map: Semantic Error: iq_clk_c matches no nets in the design. Occurred at line 485 in "USE PRIMARY NET "iq_clk_c" ; WARNING - map: Semantic Error: FPGA_TO_DSP_OBN_CLKgen matches no nets in the des ign. Occurred at line 486 in "USE SECONDARY NET "FPGA_TO_DSP_OBN_CLKgen" ; WARNING - map: Port I_brd_clk does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (30): Error in IOBUF PORT "I_brd_clk" IO_TYPE=LVCMOS33 PCICLAMP=ON TERMINATEV TT=OFF DIFFRESISTOR=OFF ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (31): Error in LOCATE COMP "I_brd_clk" SITE "T3" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (71): Error in LOCATE COMP "I_Rst_n" SITE "T2" ; WARNING - map: Port I_Rst_n does not connect to any buffers
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (72): Error in IOBUF PORT "I_Rst_n" IO_TYPE=LVCMOS33 ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (94): Error in LOCATE COMP "srio_subsys_top_u/pcs_serdes/pcsd_inst" SITE "PCS A" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (120): Error in UGROUP "urio_clk_ff" WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (121): Error in LOCATE UGROUP "urio_clk_ff" SITE "R62C92D" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (122): Error in LOCATE UGROUP "RIO_CLK_GEN_GROUP" SITE "R64C90D" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (141): Error in LOCATE COMP "B_ARM_Data_0" SITE "T18" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (142): Error in LOCATE COMP "B_ARM_Data_1" SITE "T19" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (143): Error in LOCATE COMP "B_ARM_Data_2" SITE "T20" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (144): Error in LOCATE COMP "B_ARM_Data_3" SITE "T21" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (145): Error in LOCATE COMP "B_ARM_Data_4" SITE "T22" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (146): Error in LOCATE COMP "B_ARM_Data_5" SITE "U15" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (147): Error in LOCATE COMP "B_ARM_Data_6" SITE "U16" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (148): Error in LOCATE COMP "B_ARM_Data_7" SITE "U18" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (149): Error in LOCATE COMP "B_ARM_Data_8" SITE "U19" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (150): Error in LOCATE COMP "B_ARM_Data_9" SITE "U20" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (151): Error in LOCATE COMP "B_ARM_Data_10" SITE "U22" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (152): Error in LOCATE COMP "B_ARM_Data_11" SITE "V17" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (153): Error in LOCATE COMP "B_ARM_Data_12" SITE "V18" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (154): Error in LOCATE COMP "B_ARM_Data_13" SITE "V19" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (155): Error in LOCATE COMP "B_ARM_Data_14" SITE "V22" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (156): Error in LOCATE COMP "B_ARM_Data_15" SITE "W17" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (157): Error in LOCATE COMP "O_ARM_WAIT_n" SITE "E10" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (158): Error in LOCATE COMP "I_ARM_CS_n" SITE "R3" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (159): Error in LOCATE COMP "I_ARM_OE_n" SITE "R1" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (160): Error in LOCATE COMP "I_ARM_WE_n" SITE "R2" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (161): Error in LOCATE COMP "I_ARM_Addr_1" SITE "AA20" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (162): Error in LOCATE COMP "I_ARM_Addr_2" SITE "AA21" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (163): Error in LOCATE COMP "I_ARM_Addr_3" SITE "AA22" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (164): Error in LOCATE COMP "I_ARM_Addr_4" SITE "AB17" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l
pf (165): WARNING pf (166): WARNING pf (167): WARNING pf (168): WARNING pf (169): WARNING WARNING pf (170): WARNING WARNING pf (171): WARNING WARNING pf (172): WARNING WARNING pf (173): WARNING WARNING pf (174): WARNING WARNING pf (175): WARNING WARNING pf (176): WARNING WARNING pf (177): WARNING WARNING pf (178): WARNING WARNING pf (179): WARNING WARNING pf (180): WARNING WARNING pf (181): WARNING WARNING pf (182): WARNING WARNING pf (183): WARNING WARNING pf (184): WARNING WARNING pf (185): WARNING WARNING pf (186):
Error in LOCATE COMP "I_ARM_Addr_5" SITE "AB18" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "I_ARM_Addr_6" SITE "AB19" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "I_ARM_Addr_7" SITE "AB20" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "I_ARM_Addr_8" SITE "AB21" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "I_ARM_Addr_9" SITE "Y17" ; map: Port I_ARM_Addr_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_9" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_8" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_7" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_6" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_5" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_4" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_3" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_2" IO_TYPE=LVCMOS33 ; map: Port I_ARM_Addr_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_Addr_1" IO_TYPE=LVCMOS33 ; map: Port I_ARM_CS_n does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_CS_n" IO_TYPE=LVCMOS33 ; map: Port I_ARM_OE_n does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_OE_n" IO_TYPE=LVCMOS33 ; map: Port I_ARM_WE_n does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "I_ARM_WE_n" IO_TYPE=LVCMOS33 ; map: Port O_ARM_WAIT_n does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "O_ARM_WAIT_n" IO_TYPE=LVCMOS33 ; map: Port O_ARM_INT_n does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "O_ARM_INT_n" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_15 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_15" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_14 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_14" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_13 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_13" IO_TYPE=LVCMOS33 ;
WARNING WARNING pf (187): WARNING WARNING pf (188): WARNING WARNING pf (189): WARNING WARNING pf (190): WARNING WARNING pf (191): WARNING WARNING pf (192): WARNING WARNING pf (193): WARNING WARNING pf (194): WARNING WARNING pf (195): WARNING WARNING pf (196): WARNING WARNING pf (197): WARNING WARNING pf (198): WARNING WARNING pf (199): WARNING WARNING pf (200): WARNING WARNING pf (201): WARNING WARNING pf (202): WARNING WARNING pf (203): WARNING WARNING pf (204): WARNING WARNING pf (205): WARNING WARNING pf (206):
map: Port B_ARM_Data_12 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_12" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_11 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_11" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_10 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_10" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_9" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_8" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_7" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_6" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_5" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_4" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_3" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_2" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_1" IO_TYPE=LVCMOS33 ; map: Port B_ARM_Data_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "B_ARM_Data_0" IO_TYPE=LVCMOS33 ; map: Port spi_clk does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_clk" IO_TYPE=LVCMOS33 ; map: Port spi_do does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_do" IO_TYPE=LVCMOS33 ; map: Port spi_en_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en_3" IO_TYPE=LVCMOS33 ; map: Port spi_en_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en_2" IO_TYPE=LVCMOS33 ; map: Port spi_en_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en_1" IO_TYPE=LVCMOS33 ; map: Port spi_en_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en_0" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_0" IO_TYPE=LVCMOS33 ;
map: Port SEQ_DATA_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_1" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_2" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_3" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_4" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_5" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_6" IO_TYPE=LVCMOS33 ; map: Port SEQ_DATA_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SEQ_DATA_7" IO_TYPE=LVCMOS33 ; map: Port iq_wrt2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "iq_wrt2" IO_TYPE=LVCMOS33 ; map: Port iq_sel2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "iq_sel2" IO_TYPE=LVCMOS33 ; map: Port tx_data2_11 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_11" IO_TYPE=LVCMOS33 ; map: Port tx_data2_10 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_10" IO_TYPE=LVCMOS33 ; map: Port tx_data2_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_9" IO_TYPE=LVCMOS33 ; map: Port tx_data2_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_8" IO_TYPE=LVCMOS33 ; map: Port tx_data2_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_7" IO_TYPE=LVCMOS33 ; map: Port tx_data2_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_6" IO_TYPE=LVCMOS33 ; map: Port tx_data2_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_5" IO_TYPE=LVCMOS33 ; map: Port tx_data2_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_4" IO_TYPE=LVCMOS33 ; map: Port tx_data2_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_3" IO_TYPE=LVCMOS33 ; map: Port tx_data2_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_2" IO_TYPE=LVCMOS33 ; map: Port tx_data2_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_1" IO_TYPE=LVCMOS33 ;
map: Port tx_data2_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data2_0" IO_TYPE=LVCMOS33 ; map: Port txdac_reset2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "txdac_reset2" IO_TYPE=LVCMOS33 ; map: Port txc_sleep2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "txc_sleep2" IO_TYPE=LVCMOS33 ; map: Port SCL does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SCL" IO_TYPE=LVCMOS33 ; map: Port SDA does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "SDA" IO_TYPE=LVCMOS33 ; map: Port timing_fs does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "timing_fs" IO_TYPE=LVCMOS33 ; map: Port TX2_MOD_EN_A does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "TX2_MOD_EN_A" IO_TYPE=LVCMOS33 ; map: Port TX1_MOD_EN_A does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "TX1_MOD_EN_A" IO_TYPE=LVCMOS33 ; map: Port clk_out does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "clk_out" IO_TYPE=LVCMOS33 ; map: Port TX_DAC_EN does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "TX_DAC_EN" IO_TYPE=LVCMOS33 ; map: Port FPGA_TO_DSP_TS_INT does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FPGA_TO_DSP_TS_INT" IO_TYPE=LVCMOS33 ; map: Port FPGA_TO_DSP_OBN_CLK does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FPGA_TO_DSP_OBN_CLK" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_13 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_13" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_12 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_12" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_11 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_11" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_10 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_10" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_9" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_8" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_7" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_6" IO_TYPE=LVCMOS33 ;
WARNING WARNING pf (247): WARNING WARNING pf (248): WARNING WARNING pf (249): WARNING WARNING pf (250): WARNING WARNING pf (251): WARNING WARNING pf (252): WARNING pf (253): WARNING pf (254): WARNING WARNING pf (255): WARNING WARNING pf (256): WARNING WARNING pf (257): WARNING WARNING pf (258): WARNING WARNING pf (259): WARNING WARNING pf (260): WARNING WARNING pf (261): WARNING WARNING pf (262): WARNING WARNING pf (263): WARNING WARNING pf (264): WARNING WARNING pf (265): WARNING WARNING pf (266): WARNING WARNING -
map: Port adc_obn_int_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_5" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_4" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_3" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_2" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_1" IO_TYPE=LVCMOS33 ; map: Port adc_obn_int_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "adc_obn_int_0" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "timing_fs" SITE "H19" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "TX1_MOD_EN_A" SITE "D15" ; map: Port ADC_SYNC does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_SYNC" IO_TYPE=LVCMOS33 ; map: Port RX_ADC_EN does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "RX_ADC_EN" IO_TYPE=LVCMOS33 ; map: Port ADC_TS_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_TS_2" IO_TYPE=LVCMOS33 ; map: Port ADC_TS_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_TS_1" IO_TYPE=LVCMOS33 ; map: Port ADC_TS_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_TS_0" IO_TYPE=LVCMOS33 ; map: Port rxb_dtack_rdy does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_dtack_rdy" IO_TYPE=LVCMOS33 ; map: Port ADC_MC_ADDR_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_MC_ADDR_2" IO_TYPE=LVCMOS33 ; map: Port ADC_MC_ADDR_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_MC_ADDR_1" IO_TYPE=LVCMOS33 ; map: Port ADC_MC_ADDR_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "ADC_MC_ADDR_0" IO_TYPE=LVCMOS33 ; map: Port rxb_rdnwr does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_rdnwr" IO_TYPE=LVCMOS33 ; map: Port rxb_dsrd does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_dsrd" IO_TYPE=LVCMOS33 ; map: Port rxb_cs does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_cs" IO_TYPE=LVCMOS33 ; map: Port rxb_d_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l
pf (267): WARNING WARNING pf (268): WARNING WARNING pf (269): WARNING WARNING pf (270): WARNING WARNING pf (271): WARNING WARNING pf (272): WARNING WARNING pf (273): WARNING WARNING pf (274): WARNING pf (275): WARNING pf (276): WARNING pf (277): WARNING pf (278): WARNING WARNING pf (279): WARNING WARNING pf (280): WARNING pf (281): WARNING pf (282): WARNING pf (283): WARNING pf (284): WARNING WARNING pf (285): WARNING WARNING pf (286): WARNING WARNING pf (287): WARNING WARNING pf (288): WARNING WARNING pf (289): WARNING -
Error in IOBUF PORT "rxb_d_7" IO_TYPE=LVCMOS33 ; map: Port rxb_d_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_6" IO_TYPE=LVCMOS33 ; map: Port rxb_d_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_5" IO_TYPE=LVCMOS33 ; map: Port rxb_d_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_4" IO_TYPE=LVCMOS33 ; map: Port rxb_d_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_3" IO_TYPE=LVCMOS33 ; map: Port rxb_d_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_2" IO_TYPE=LVCMOS33 ; map: Port rxb_d_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_1" IO_TYPE=LVCMOS33 ; map: Port rxb_d_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rxb_d_0" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "SCL" SITE "G15" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "SDA" SITE "G14" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "spi_clk" SITE "G9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "spi_do" SITE "F13" ; map: Port FPGA_LED does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FPGA_LED" IO_TYPE=LVCMOS33 ; map: Port T2RXC1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "T2RXC1" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "spi_en_1" SITE "E6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "spi_en_0" SITE "D11" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FPGA_TO_DSP_OBN_CLK" SITE "V3" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FPGA_TO_DSP_TS_INT" SITE "W2" ; map: Port EN_DIS_DATA_PUMP does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "EN_DIS_DATA_PUMP" IO_TYPE=LVCMOS33 ; map: Port RESET_RADIO_IF does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "RESET_RADIO_IF" IO_TYPE=LVCMOS33 ; map: Port PA_MEAS does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "PA_MEAS" IO_TYPE=LVCMOS33 ; map: Port PERIO_ATTN_EN_DIS does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "PERIO_ATTN_EN_DIS" IO_TYPE=LVCMOS33 ; map: Port PA_ON_OFF does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "PA_ON_OFF" IO_TYPE=LVCMOS33 ; map: Port EN_DIS_DATA_PUMP2 does not connect to any buffers
WARNING pf (290): WARNING WARNING pf (291): WARNING WARNING pf (292): WARNING WARNING pf (293): WARNING WARNING pf (294): WARNING WARNING pf (295): WARNING WARNING pf (296): WARNING WARNING pf (297): WARNING WARNING pf (298): WARNING WARNING pf (299): WARNING WARNING pf (300): WARNING WARNING pf (301): WARNING WARNING pf (302): WARNING WARNING pf (303): WARNING WARNING pf (304): WARNING WARNING pf (305): WARNING WARNING pf (306): WARNING WARNING pf (307): WARNING WARNING pf (308): WARNING WARNING pf (309): WARNING -
map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "EN_DIS_DATA_PUMP2" IO_TYPE=LVCMOS33 ; map: Port RF_enable does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "RF_enable" IO_TYPE=LVCMOS33 ; map: Port RESET_RADIO_IF2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "RESET_RADIO_IF2" IO_TYPE=LVCMOS33 ; map: Port PA_MEAS2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "PA_MEAS2" IO_TYPE=LVCMOS33 ; map: Port PERIO_ATTN_EN_DIS2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "PERIO_ATTN_EN_DIS2" IO_TYPE=LVCMOS33 ; map: Port PA_ON_OFF2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "PA_ON_OFF2" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_13 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_13" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_12 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_12" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_11 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_11" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_10 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_10" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_9" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_8" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_7" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_6" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_5" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_4" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_3" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_2" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_1" IO_TYPE=LVCMOS33 ; map: Port FRAME_SYNC1_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "FRAME_SYNC1_0" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l
pf (310): WARNING pf (311): WARNING pf (312): WARNING pf (313): WARNING pf (314): WARNING pf (315): WARNING pf (316): WARNING pf (317): WARNING pf (318): WARNING pf (319): WARNING pf (320): WARNING pf (321): WARNING pf (322): WARNING pf (323): WARNING WARNING pf (324): WARNING WARNING pf (325): WARNING WARNING pf (326): WARNING WARNING pf (327): WARNING WARNING pf (328): WARNING WARNING pf (329): WARNING WARNING pf (330): WARNING WARNING pf (331): WARNING WARNING pf (332): WARNING WARNING pf (333): WARNING pf (334): WARNING -
Error in LOCATE COMP "FRAME_SYNC1_0" SITE "C5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_1" SITE "C6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_2" SITE "C7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_3" SITE "C8" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_4" SITE "C9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_5" SITE "C10" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_6" SITE "D5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_7" SITE "D6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_8" SITE "D7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_9" SITE "D8" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_10" SITE "D9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_11" SITE "D10" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_12" SITE "D11" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "FRAME_SYNC1_13" SITE "E6" ; map: Port TX1_Lock does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "TX1_Lock" IO_TYPE=LVCMOS33 ; map: Port TX2_Lock does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "TX2_Lock" IO_TYPE=LVCMOS33 ; map: Port RX1_Lock does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "RX1_Lock" IO_TYPE=LVCMOS33 ; map: Port RX2_Lock does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "RX2_Lock" IO_TYPE=LVCMOS33 ; map: Port spi_clk2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_clk2" IO_TYPE=LVCMOS33 ; map: Port spi_en2_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_3" IO_TYPE=LVCMOS33 ; map: Port spi_en2_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_2" IO_TYPE=LVCMOS33 ; map: Port spi_en2_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_1" IO_TYPE=LVCMOS33 ; map: Port spi_en2_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_0" IO_TYPE=LVCMOS33 ; map: Port spi_do2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_do2" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "ADC_SYNC" SITE "E13" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l
pf (335): WARNING pf (336): WARNING pf (337): WARNING pf (338): WARNING pf (339): WARNING pf (340): WARNING pf (341): WARNING pf (342): WARNING pf (343): WARNING pf (344): WARNING pf (345): WARNING pf (346): WARNING pf (347): WARNING pf (348): WARNING pf (349): WARNING pf (350): WARNING pf (351): WARNING pf (352): WARNING pf (353): WARNING pf (354): WARNING pf (355): WARNING pf (356): WARNING pf (357): WARNING pf (358): WARNING pf (359): WARNING pf (360): WARNING pf (361): WARNING pf (362): WARNING pf (363): WARNING pf (364): WARNING -
Error in LOCATE COMP "RF_enable" SITE "D14" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_0" SITE "A16" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_1" SITE "A17" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_2" SITE "A12" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_3" SITE "A13" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_4" SITE "A14" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_5" SITE "A15" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_6" SITE "A18" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_d_7" SITE "A19" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_dtack_rdy" SITE "G14" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "TX1_Lock" SITE "C16" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "TX2_Lock" SITE "C17" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "RX1_Lock" SITE "A6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "RX2_Lock" SITE "A7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "ADC_MC_ADDR_2" SITE "B18" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rxb_cs" SITE "N20" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "spi_clk2" SITE "D17" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "spi_do2" SITE "E12" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_0" SITE "C5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_1" SITE "C6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_2" SITE "C7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_3" SITE "C8" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_4" SITE "C9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_5" SITE "C10" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_6" SITE "D5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_7" SITE "D6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_8" SITE "D7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_9" SITE "D8" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_10" SITE "D9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data2_11" SITE "D10" ; map: Port DIR_CTRL does not connect to any buffers
WARNING pf (365): WARNING WARNING pf (366): WARNING WARNING pf (367): WARNING WARNING pf (368): WARNING WARNING pf (369): WARNING WARNING pf (370): WARNING WARNING pf (371): WARNING WARNING pf (372): WARNING WARNING pf (373): WARNING WARNING pf (374): WARNING WARNING pf (375): WARNING WARNING pf (376): WARNING WARNING pf (377): WARNING WARNING pf (378): WARNING WARNING pf (379): WARNING WARNING pf (380): WARNING WARNING pf (381): WARNING WARNING pf (382): WARNING pf (383): WARNING pf (384): WARNING pf (385): WARNING -
map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "DIR_CTRL" IO_TYPE=LVCMOS33 ; map: Port tx_reset does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_reset" IO_TYPE=LVCMOS33 ; map: Port iq_sel_a does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "iq_sel_a" IO_TYPE=LVCMOS33 ; map: Port iq_sel_b does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "iq_sel_b" IO_TYPE=LVCMOS33 ; map: Port dac_a_clk does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "dac_a_clk" IO_TYPE=LVCMOS33 ; map: Port dac_b_clk does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "dac_b_clk" IO_TYPE=LVCMOS33 ; map: Port tx_data_11 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_11" IO_TYPE=LVCMOS33 ; map: Port tx_data_10 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_10" IO_TYPE=LVCMOS33 ; map: Port tx_data_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_9" IO_TYPE=LVCMOS33 ; map: Port tx_data_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_8" IO_TYPE=LVCMOS33 ; map: Port tx_data_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_7" IO_TYPE=LVCMOS33 ; map: Port tx_data_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_6" IO_TYPE=LVCMOS33 ; map: Port tx_data_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_5" IO_TYPE=LVCMOS33 ; map: Port tx_data_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_4" IO_TYPE=LVCMOS33 ; map: Port tx_data_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_3" IO_TYPE=LVCMOS33 ; map: Port tx_data_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_2" IO_TYPE=LVCMOS33 ; map: Port tx_data_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_1" IO_TYPE=LVCMOS33 ; map: Port tx_data_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "tx_data_0" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_0" SITE "C5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_1" SITE "C6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_2" SITE "C7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l
pf (386): WARNING pf (387): WARNING pf (388): WARNING pf (389): WARNING pf (390): WARNING pf (391): WARNING pf (392): WARNING pf (393): WARNING pf (394): WARNING WARNING pf (400): WARNING WARNING pf (401): WARNING WARNING pf (402): WARNING WARNING pf (403): WARNING WARNING pf (404): WARNING pf (405): WARNING pf (406): WARNING pf (407): WARNING pf (408): WARNING pf (409): WARNING pf (410): WARNING pf (411): WARNING pf (412): WARNING pf (413): WARNING pf (414): WARNING pf (415): WARNING pf (416): WARNING pf (417): WARNING pf (418):
Error in LOCATE COMP "tx_data_3" SITE "C8" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_4" SITE "C9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_5" SITE "C10" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_6" SITE "D5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_7" SITE "D6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_8" SITE "D7" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_9" SITE "D8" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_10" SITE "D9" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "tx_data_11" SITE "D10" ; map: Port rx_clk does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rx_clk" IO_TYPE=LVCMOS33 ; map: Port rx_sync does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rx_sync" IO_TYPE=LVCMOS33 ; map: Port rx_data0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rx_data0" IO_TYPE=LVCMOS33 ; map: Port rx_data1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "rx_data1" IO_TYPE=LVCMOS33 ; map: Port dc_dc_sync does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "dc_dc_sync" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rx_sync" SITE "AB4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rx_clk" SITE "AA6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rx_data0" SITE "AB5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "rx_data1" SITE "AB6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "dc_dc_sync" SITE "P19" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HRDY_L" SITE "AA4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HAS" SITE "AA1" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HCS_L" SITE "AB5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HDS1_L" SITE "AB6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HDS2_L" SITE "T4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HHWIL" SITE "AA6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_R_WL" SITE "AA5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HCNTL_1" SITE "AB4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_HCNTL_0" SITE "AB3" ;
WARNING pf (419): WARNING pf (420): WARNING pf (421): WARNING pf (422): WARNING pf (423): WARNING pf (424): WARNING pf (425): WARNING pf (426): WARNING pf (427): WARNING pf (428): WARNING pf (429): WARNING pf (430): WARNING pf (431): WARNING pf (432): WARNING pf (433): WARNING pf (434): WARNING pf (435): WARNING pf (436): WARNING pf (437): WARNING pf (438): WARNING pf (439): WARNING pf (440): WARNING pf (441): WARNING pf (442): WARNING pf (443): WARNING pf (444): WARNING pf (445): WARNING pf (446): WARNING pf (447): WARNING pf (448):
map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_15" SITE "P4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_14" SITE "P3" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_13" SITE "P1" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_12" SITE "N6" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_11" SITE "N5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_10" SITE "N4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_9" SITE "N3" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_8" SITE "N2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_7" SITE "N1" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_6" SITE "M5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_5" SITE "M4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_4" SITE "M2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_3" SITE "M1" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_2" SITE "L4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_1" SITE "L3" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "HPI_DATA_0" SITE "L2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_CLK" SITE "K4" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_9" SITE "D2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_8" SITE "J2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_7" SITE "M18" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_6" SITE "L18" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_5" SITE "J22" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_4" SITE "H21" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_3" SITE "E3" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_2" SITE "H5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_1" SITE "E22" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BBIN_DATA_0" SITE "K1" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_SYNC" SITE "J17" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_CLK" SITE "K17" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_7" SITE "M21" ;
WARNING pf (449): WARNING pf (450): WARNING pf (451): WARNING pf (452): WARNING pf (453): WARNING pf (454): WARNING pf (455): WARNING WARNING pf (456): WARNING WARNING pf (457): WARNING WARNING pf (458): WARNING WARNING pf (459): WARNING WARNING pf (460): WARNING WARNING pf (461): WARNING WARNING pf (462): WARNING WARNING pf (463): WARNING WARNING pf (464): WARNING WARNING pf (465): WARNING WARNING pf (466): WARNING WARNING pf (467): WARNING WARNING pf (468): WARNING WARNING pf (469): WARNING WARNING pf (470): WARNING -
map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_6" SITE "K21" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_5" SITE "G21" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_4" SITE "K20" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_3" SITE "B1" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_2" SITE "B2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_1" SITE "H2" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "BB_DATA_0" SITE "H4" ; map: Port HPI_HRDY_L does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HRDY_L" IO_TYPE=LVCMOS33 ; map: Port HPI_HAS does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HAS" IO_TYPE=LVCMOS33 ; map: Port HPI_HCS_L does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HCS_L" IO_TYPE=LVCMOS33 ; map: Port HPI_HDS1_L does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HDS1_L" IO_TYPE=LVCMOS33 ; map: Port HPI_HDS2_L does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HDS2_L" IO_TYPE=LVCMOS33 ; map: Port HPI_HHWIL does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HHWIL" IO_TYPE=LVCMOS33 ; map: Port HPI_R_WL does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_R_WL" IO_TYPE=LVCMOS33 ; map: Port HPI_HCNTL_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HCNTL_1" IO_TYPE=LVCMOS33 ; map: Port HPI_HCNTL_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_HCNTL_0" IO_TYPE=LVCMOS33 ; map: Port spi_en2_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_7" IO_TYPE=LVCMOS33 ; map: Port spi_en2_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_6" IO_TYPE=LVCMOS33 ; map: Port spi_en2_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_5" IO_TYPE=LVCMOS33 ; map: Port spi_en2_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "spi_en2_4" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_15 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_15" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_14 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_14" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_13 does not connect to any buffers
WARNING pf (471): WARNING WARNING pf (472): WARNING WARNING pf (473): WARNING WARNING pf (474): WARNING WARNING pf (475): WARNING WARNING pf (476): WARNING WARNING pf (477): WARNING WARNING pf (478): WARNING WARNING pf (479): WARNING WARNING pf (480): WARNING WARNING pf (481): WARNING WARNING pf (482): WARNING WARNING pf (483): WARNING WARNING pf (484): WARNING pf (487): WARNING pf (488): WARNING WARNING pf (489): WARNING WARNING pf (490): WARNING pf (491): WARNING WARNING pf (492): WARNING pf (493): WARNING pf (494):
map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_13" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_12 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_12" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_11 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_11" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_10 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_10" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_9 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_9" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_8 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_8" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_7 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_7" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_6 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_6" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_5 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_5" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_4 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_4" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_3 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_3" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_2 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_2" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_1 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_1" IO_TYPE=LVCMOS33 ; map: Port HPI_DATA_0 does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "HPI_DATA_0" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "GC_SYNC_A" SITE "E5" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "GC_SYNC_B" SITE "G4" ; map: Port GC_SYNC_A does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "GC_SYNC_A" IO_TYPE=LVDS25 ; map: Port GC_SYNC_B does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "GC_SYNC_B" IO_TYPE=LVDS25 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "EMIFENA" SITE "R21" ; map: Port EMIFENA does not connect to any buffers map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in IOBUF PORT "EMIFENA" IO_TYPE=LVCMOS33 ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "DSP6748_SYNC_A" SITE "B15" ; map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l Error in LOCATE COMP "DSP6748_SYNC_B" SITE "B16" ;
WARNING - map: Port DSP6748_SYNC_A does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (495): Error in IOBUF PORT "DSP6748_SYNC_A" IO_TYPE=LVCMOS33 ; WARNING - map: Port DSP6748_SYNC_B does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (496): Error in IOBUF PORT "DSP6748_SYNC_B" IO_TYPE=LVCMOS33 ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (497): Error in LOCATE COMP "spi_en2_0" SITE "F7" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (498): Error in LOCATE COMP "spi_en2_1" SITE "F8" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (499): Error in LOCATE COMP "spi_en2_2" SITE "F9" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (500): Error in LOCATE COMP "spi_en2_3" SITE "F10" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (501): Error in LOCATE COMP "spi_en2_4" SITE "F11" ; WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (502): Error in LOCATE COMP "spi_en2_5" SITE "F12" ; WARNING - map: Preference parsing results: 386 semantic errors detected WARNING - map: There are errors in the preference file, "D:/MC-DMB-FPGA/MC_FPGA_ 17_10_2011_0345PM/fpga_first_release/top.lpf". WARNING - map: Using local reset signal 'fifo2_clear' to infer global GSR net. WARNING - map: IO buffer missing for top level port DAC_TS...logic will be disca rded. WARNING - map: IO buffer missing for top level port OBN[13:0](13)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](12)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](11)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](10)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](9)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](8)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](7)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](6)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](5)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](4)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](3)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](2)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](1)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](0)...logic will be discarded. WARNING - map: There are semantic errors in the preference file, "D:/MC-DMB-FPGA /MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.prf". WARNING - par: Due to difficulties in finding a legal I/O placement, it may be i mpossible to assign optimal locations for the PIO drivers of clock and/or PLL/DL L inputs in this design. Please check the PAR and PAD reports, see if the place ment fulfill the requirements; and use LOCATE preference to lock clock and/or PL L/DLL input pins if necessary.
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port
I_brd_clk does not connect to any buffers I_Rst_n does not connect to any buffers I_ARM_Addr_9 does not connect to any buffers I_ARM_Addr_8 does not connect to any buffers I_ARM_Addr_7 does not connect to any buffers I_ARM_Addr_6 does not connect to any buffers I_ARM_Addr_5 does not connect to any buffers I_ARM_Addr_4 does not connect to any buffers I_ARM_Addr_3 does not connect to any buffers I_ARM_Addr_2 does not connect to any buffers I_ARM_Addr_1 does not connect to any buffers I_ARM_CS_n does not connect to any buffers I_ARM_OE_n does not connect to any buffers I_ARM_WE_n does not connect to any buffers O_ARM_WAIT_n does not connect to any buffers O_ARM_INT_n does not connect to any buffers B_ARM_Data_15 does not connect to any buffers B_ARM_Data_14 does not connect to any buffers B_ARM_Data_13 does not connect to any buffers B_ARM_Data_12 does not connect to any buffers B_ARM_Data_11 does not connect to any buffers B_ARM_Data_10 does not connect to any buffers B_ARM_Data_9 does not connect to any buffers B_ARM_Data_8 does not connect to any buffers B_ARM_Data_7 does not connect to any buffers B_ARM_Data_6 does not connect to any buffers B_ARM_Data_5 does not connect to any buffers B_ARM_Data_4 does not connect to any buffers B_ARM_Data_3 does not connect to any buffers B_ARM_Data_2 does not connect to any buffers B_ARM_Data_1 does not connect to any buffers B_ARM_Data_0 does not connect to any buffers spi_clk does not connect to any buffers spi_do does not connect to any buffers spi_en_3 does not connect to any buffers spi_en_2 does not connect to any buffers spi_en_1 does not connect to any buffers spi_en_0 does not connect to any buffers SEQ_DATA_0 does not connect to any buffers SEQ_DATA_1 does not connect to any buffers SEQ_DATA_2 does not connect to any buffers SEQ_DATA_3 does not connect to any buffers SEQ_DATA_4 does not connect to any buffers SEQ_DATA_5 does not connect to any buffers SEQ_DATA_6 does not connect to any buffers SEQ_DATA_7 does not connect to any buffers iq_wrt2 does not connect to any buffers iq_sel2 does not connect to any buffers tx_data2_11 does not connect to any buffers tx_data2_10 does not connect to any buffers tx_data2_9 does not connect to any buffers tx_data2_8 does not connect to any buffers tx_data2_7 does not connect to any buffers tx_data2_6 does not connect to any buffers tx_data2_5 does not connect to any buffers tx_data2_4 does not connect to any buffers tx_data2_3 does not connect to any buffers tx_data2_2 does not connect to any buffers tx_data2_1 does not connect to any buffers tx_data2_0 does not connect to any buffers
txdac_reset2 does not connect to any buffers txc_sleep2 does not connect to any buffers SCL does not connect to any buffers SDA does not connect to any buffers timing_fs does not connect to any buffers TX2_MOD_EN_A does not connect to any buffers TX1_MOD_EN_A does not connect to any buffers clk_out does not connect to any buffers TX_DAC_EN does not connect to any buffers FPGA_TO_DSP_TS_INT does not connect to any buffers FPGA_TO_DSP_OBN_CLK does not connect to any buffers adc_obn_int_13 does not connect to any buffers adc_obn_int_12 does not connect to any buffers adc_obn_int_11 does not connect to any buffers adc_obn_int_10 does not connect to any buffers adc_obn_int_9 does not connect to any buffers adc_obn_int_8 does not connect to any buffers adc_obn_int_7 does not connect to any buffers adc_obn_int_6 does not connect to any buffers adc_obn_int_5 does not connect to any buffers adc_obn_int_4 does not connect to any buffers adc_obn_int_3 does not connect to any buffers adc_obn_int_2 does not connect to any buffers adc_obn_int_1 does not connect to any buffers adc_obn_int_0 does not connect to any buffers ADC_SYNC does not connect to any buffers RX_ADC_EN does not connect to any buffers ADC_TS_2 does not connect to any buffers ADC_TS_1 does not connect to any buffers ADC_TS_0 does not connect to any buffers rxb_dtack_rdy does not connect to any buffers ADC_MC_ADDR_2 does not connect to any buffers ADC_MC_ADDR_1 does not connect to any buffers ADC_MC_ADDR_0 does not connect to any buffers rxb_rdnwr does not connect to any buffers rxb_dsrd does not connect to any buffers rxb_cs does not connect to any buffers rxb_d_7 does not connect to any buffers rxb_d_6 does not connect to any buffers rxb_d_5 does not connect to any buffers rxb_d_4 does not connect to any buffers rxb_d_3 does not connect to any buffers rxb_d_2 does not connect to any buffers rxb_d_1 does not connect to any buffers rxb_d_0 does not connect to any buffers FPGA_LED does not connect to any buffers T2RXC1 does not connect to any buffers EN_DIS_DATA_PUMP does not connect to any buffers RESET_RADIO_IF does not connect to any buffers PA_MEAS does not connect to any buffers PERIO_ATTN_EN_DIS does not connect to any buffers PA_ON_OFF does not connect to any buffers EN_DIS_DATA_PUMP2 does not connect to any buffers RF_enable does not connect to any buffers RESET_RADIO_IF2 does not connect to any buffers PA_MEAS2 does not connect to any buffers PERIO_ATTN_EN_DIS2 does not connect to any buffers PA_ON_OFF2 does not connect to any buffers FRAME_SYNC1_13 does not connect to any buffers FRAME_SYNC1_12 does not connect to any buffers
FRAME_SYNC1_11 does not connect to any buffers FRAME_SYNC1_10 does not connect to any buffers FRAME_SYNC1_9 does not connect to any buffers FRAME_SYNC1_8 does not connect to any buffers FRAME_SYNC1_7 does not connect to any buffers FRAME_SYNC1_6 does not connect to any buffers FRAME_SYNC1_5 does not connect to any buffers FRAME_SYNC1_4 does not connect to any buffers FRAME_SYNC1_3 does not connect to any buffers FRAME_SYNC1_2 does not connect to any buffers FRAME_SYNC1_1 does not connect to any buffers FRAME_SYNC1_0 does not connect to any buffers TX1_Lock does not connect to any buffers TX2_Lock does not connect to any buffers RX1_Lock does not connect to any buffers RX2_Lock does not connect to any buffers spi_clk2 does not connect to any buffers spi_en2_3 does not connect to any buffers spi_en2_2 does not connect to any buffers spi_en2_1 does not connect to any buffers spi_en2_0 does not connect to any buffers spi_do2 does not connect to any buffers DIR_CTRL does not connect to any buffers tx_reset does not connect to any buffers iq_sel_a does not connect to any buffers iq_sel_b does not connect to any buffers dac_a_clk does not connect to any buffers dac_b_clk does not connect to any buffers tx_data_11 does not connect to any buffers tx_data_10 does not connect to any buffers tx_data_9 does not connect to any buffers tx_data_8 does not connect to any buffers tx_data_7 does not connect to any buffers tx_data_6 does not connect to any buffers tx_data_5 does not connect to any buffers tx_data_4 does not connect to any buffers tx_data_3 does not connect to any buffers tx_data_2 does not connect to any buffers tx_data_1 does not connect to any buffers tx_data_0 does not connect to any buffers rx_clk does not connect to any buffers rx_sync does not connect to any buffers rx_data0 does not connect to any buffers rx_data1 does not connect to any buffers dc_dc_sync does not connect to any buffers HPI_HRDY_L does not connect to any buffers HPI_HAS does not connect to any buffers HPI_HCS_L does not connect to any buffers HPI_HDS1_L does not connect to any buffers HPI_HDS2_L does not connect to any buffers HPI_HHWIL does not connect to any buffers HPI_R_WL does not connect to any buffers HPI_HCNTL_1 does not connect to any buffers HPI_HCNTL_0 does not connect to any buffers spi_en2_7 does not connect to any buffers spi_en2_6 does not connect to any buffers spi_en2_5 does not connect to any buffers spi_en2_4 does not connect to any buffers HPI_DATA_15 does not connect to any buffers HPI_DATA_14 does not connect to any buffers
Port HPI_DATA_13 does not connect to any buffers Port HPI_DATA_12 does not connect to any buffers Port HPI_DATA_11 does not connect to any buffers Port HPI_DATA_10 does not connect to any buffers Port HPI_DATA_9 does not connect to any buffers Port HPI_DATA_8 does not connect to any buffers Port HPI_DATA_7 does not connect to any buffers Port HPI_DATA_6 does not connect to any buffers Port HPI_DATA_5 does not connect to any buffers Port HPI_DATA_4 does not connect to any buffers Port HPI_DATA_3 does not connect to any buffers Port HPI_DATA_2 does not connect to any buffers Port HPI_DATA_1 does not connect to any buffers Port HPI_DATA_0 does not connect to any buffers Port GC_SYNC_A does not connect to any buffers Port GC_SYNC_B does not connect to any buffers Port EMIFENA does not connect to any buffers Port DSP6748_SYNC_A does not connect to any buffers Port DSP6748_SYNC_B does not connect to any buffers Invalid Signal [I_ARM_Addr_3] is not shown up. Invalid Signal [ADC_SYNC] is not shown up. Invalid Signal [HPI_HDS2_L] is not shown up. Invalid Signal [I_ARM_Addr_4] is not shown up. Invalid Signal [RESET_RADIO_IF2] is not shown up. Invalid Signal [I_ARM_Addr_5] is not shown up. Invalid Signal [PA_MEAS] is not shown up. Invalid Signal [I_ARM_Addr_6] is not shown up. Invalid Signal [I_ARM_Addr_7] is not shown up. Invalid Signal [I_ARM_Addr_8] is not shown up. Invalid Signal [SEQ_DATA_0] is not shown up. Invalid Signal [tx_data_10] is not shown up. Invalid Signal [I_ARM_Addr_9] is not shown up. Invalid Signal [SEQ_DATA_1] is not shown up. Invalid Signal [tx_data2_0] is not shown up. Invalid Signal [tx_data_11] is not shown up. Invalid Signal [O_ARM_WAIT_n] is not shown up. Invalid Signal [SEQ_DATA_2] is not shown up. Invalid Signal [tx_data2_1] is not shown up. Invalid Signal [rx_clk] is not shown up. Invalid Signal [SEQ_DATA_3] is not shown up. Invalid Signal [tx_data2_2] is not shown up. Invalid Signal [spi_clk] is not shown up. Invalid Signal [SEQ_DATA_4] is not shown up. Invalid Signal [tx_data2_3] is not shown up. Invalid Signal [clk_out] is not shown up. Invalid Signal [SEQ_DATA_5] is not shown up. Invalid Signal [tx_data2_4] is not shown up. Invalid Signal [HPI_HRDY_L] is not shown up. Invalid Signal [HPI_DATA_10] is not shown up. Invalid Signal [SEQ_DATA_6] is not shown up. Invalid Signal [tx_data2_5] is not shown up. Invalid Signal [HPI_DATA_11] is not shown up. Invalid Signal [SEQ_DATA_7] is not shown up. Invalid Signal [tx_data2_6] is not shown up. Invalid Signal [adc_obn_int_10] is not shown up. Invalid Signal [HPI_DATA_12] is not shown up. Invalid Signal [tx_data2_7] is not shown up. Invalid Signal [TX_DAC_EN] is not shown up. Invalid Signal [adc_obn_int_11] is not shown up. Invalid Signal [HPI_DATA_13] is not shown up.
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal
[tx_data2_8] is not shown up. [adc_obn_int_12] is not shown up. [rxb_d_0] is not shown up. [FPGA_LED] is not shown up. [dac_b_clk] is not shown up. [HPI_DATA_14] is not shown up. [tx_data2_9] is not shown up. [adc_obn_int_13] is not shown up. [rxb_d_1] is not shown up. [HPI_DATA_15] is not shown up. [rxb_rdnwr] is not shown up. [rxb_d_2] is not shown up. [rxb_d_3] is not shown up. [HPI_DATA_0] is not shown up. [I_Rst_n] is not shown up. [rxb_d_4] is not shown up. [EN_DIS_DATA_PUMP2] is not shown up. [TX2_Lock] is not shown up. [HPI_DATA_1] is not shown up. [FRAME_SYNC1_0] is not shown up. [rxb_d_5] is not shown up. [HPI_DATA_2] is not shown up. [FRAME_SYNC1_10] is not shown up. [rxb_d_6] is not shown up. [FRAME_SYNC1_1] is not shown up. [HPI_HAS] is not shown up. [HPI_R_WL] is not shown up. [HPI_DATA_3] is not shown up. [FRAME_SYNC1_11] is not shown up. [rxb_d_7] is not shown up. [FRAME_SYNC1_2] is not shown up. [HPI_DATA_4] is not shown up. [FRAME_SYNC1_12] is not shown up. [SCL] is not shown up. [FRAME_SYNC1_3] is not shown up. [HPI_DATA_5] is not shown up. [FRAME_SYNC1_13] is not shown up. [iq_sel2] is not shown up. [FRAME_SYNC1_4] is not shown up. [spi_en2_0] is not shown up. [HPI_DATA_6] is not shown up. [PERIO_ATTN_EN_DIS2] is not shown up. [FRAME_SYNC1_5] is not shown up. [spi_en2_1] is not shown up. [spi_do2] is not shown up. [HPI_DATA_7] is not shown up. [DSP6748_SYNC_A] is not shown up. [FRAME_SYNC1_6] is not shown up. [spi_en2_2] is not shown up. [HPI_DATA_8] is not shown up. [DSP6748_SYNC_B] is not shown up. [FRAME_SYNC1_7] is not shown up. [spi_en2_3] is not shown up. [HPI_DATA_9] is not shown up. [GC_SYNC_A] is not shown up. [FRAME_SYNC1_8] is not shown up. [spi_en2_4] is not shown up. [GC_SYNC_B] is not shown up. [I_ARM_WE_n] is not shown up. [FRAME_SYNC1_9] is not shown up.
[spi_en2_5] is not shown up. [TX1_Lock] is not shown up. [dac_a_clk] is not shown up. [dc_dc_sync] is not shown up. [spi_en2_6] is not shown up. [RF_enable] is not shown up. [I_ARM_Addr_1] is not shown up. [FPGA_TO_DSP_TS_INT] is not shown up. [spi_en2_7] is not shown up. [spi_clk2] is not shown up. [I_ARM_Addr_2] is not shown up. [RX_ADC_EN] is not shown up. [DIR_CTRL] is not shown up. [EN_DIS_DATA_PUMP] is not shown up. [I_brd_clk] is not shown up. [RESET_RADIO_IF] is not shown up. [RX1_Lock] is not shown up. [HPI_HCNTL_0] is not shown up. [B_ARM_Data_0] is not shown up. [txc_sleep2] is not shown up. [HPI_HCNTL_1] is not shown up. [B_ARM_Data_1] is not shown up. [B_ARM_Data_2] is not shown up. [HPI_HDS1_L] is not shown up. [B_ARM_Data_3] is not shown up. [rxb_dsrd] is not shown up. [O_ARM_INT_n] is not shown up. [B_ARM_Data_4] is not shown up. [ADC_TS_0] is not shown up. [EMIFENA] is not shown up. [B_ARM_Data_5] is not shown up. [ADC_TS_1] is not shown up. [rx_sync] is not shown up. [B_ARM_Data_6] is not shown up. [adc_obn_int_0] is not shown up. [ADC_TS_2] is not shown up. [B_ARM_Data_7] is not shown up. [timing_fs] is not shown up. [adc_obn_int_1] is not shown up. [B_ARM_Data_8] is not shown up. [spi_en_0] is not shown up. [adc_obn_int_2] is not shown up. [B_ARM_Data_10] is not shown up. [B_ARM_Data_9] is not shown up. [spi_do] is not shown up. [spi_en_1] is not shown up. [TX1_MOD_EN_A] is not shown up. [adc_obn_int_3] is not shown up. [PERIO_ATTN_EN_DIS] is not shown up. [B_ARM_Data_11] is not shown up. [spi_en_2] is not shown up. [adc_obn_int_4] is not shown up. [tx_data_0] is not shown up. [B_ARM_Data_12] is not shown up. [spi_en_3] is not shown up. [SDA] is not shown up. [adc_obn_int_5] is not shown up. [ADC_MC_ADDR_0] is not shown up. [B_ARM_Data_13] is not shown up. [FPGA_TO_DSP_OBN_CLK] is not shown up.
WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING OUTPUT: =======
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal
[adc_obn_int_6] is not shown up. [ADC_MC_ADDR_1] is not shown up. [tx_data_1] is not shown up. [B_ARM_Data_14] is not shown up. [adc_obn_int_7] is not shown up. [ADC_MC_ADDR_2] is not shown up. [tx_reset] is not shown up. [tx_data_2] is not shown up. [B_ARM_Data_15] is not shown up. [tx_data2_10] is not shown up. [TX2_MOD_EN_A] is not shown up. [adc_obn_int_8] is not shown up. [tx_data_3] is not shown up. [I_ARM_OE_n] is not shown up. [tx_data2_11] is not shown up. [adc_obn_int_9] is not shown up. [rxb_dtack_rdy] is not shown up. [tx_data_4] is not shown up. [rxb_cs] is not shown up. [iq_sel_a] is not shown up. [tx_data_5] is not shown up. [HPI_HCS_L] is not shown up. [I_ARM_CS_n] is not shown up. [iq_sel_b] is not shown up. [tx_data_6] is not shown up. [tx_data_7] is not shown up. [rx_data0] is not shown up. [iq_wrt2] is not shown up. [txdac_reset2] is not shown up. [T2RXC1] is not shown up. [RX2_Lock] is not shown up. [tx_data_8] is not shown up. [rx_data1] is not shown up. [PA_ON_OFF2] is not shown up. [tx_data_9] is not shown up. [PA_ON_OFF] is not shown up. [PA_MEAS2] is not shown up. [HPI_HHWIL] is not shown up.
Starting: "prj_run Export -impl top -task Bitgen" ************************************************************ ** Synplify Pro ** ************************************************************ synpwrap -prj "top_top_synplify.tcl" -log "top_top.srf" Copyright (C) 1992-2010 Lattice Semiconductor Corporation. All rights reserved. Lattice Diamond Version 1.1.00.50.42.10 ==contents of top_top.srf #Build: Synplify Pro for Lattice D-2010.03L-SP1, Build 142R, Aug 11 2010 #install: C:\lscc\diamond\1.1\synpbase #OS: Windows_NT #Hostname: VNL-1B3D3CD7DDA $ Start of Compile
#Thu Dec 01 13:46:37 2011 Synopsys HDL Compiler, version comp510rc, Build 126R, built Jul 22 2010 @N|Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Synopsys VHDL Compiler, version comp510rc, Build 126R, built Jul 22 2010 @N|Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N: CD720 :"C:\lscc\diamond\1.1\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\aif.vhd " @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\Clock_d ivider.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\logical _rx_path.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\logical _tx_path.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\obn_cou nter.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\RX_ARBI TER.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_64 _64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Arb _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Clk _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Cnt _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_INT _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Mai n_Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Mpu _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_SS_ Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Syn ch_Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32 _64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_51 2_64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\UHPI.vh d" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_15 6_64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_15 7_64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\DDR_INP UT.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\DDR_OUT PUT.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\spi_tra nsmitter.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Top .vhd"
@I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_COM M.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\rx_path .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\tx_path .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\top_AMC .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\ADC_SPI _RX.vhd" VHDL syntax check successful! File D:\MC\MC-DMB-FPGA\fpga_first_release\source\aif.vhd changed - recompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\Clock_divider.vhd changed - rec ompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\logical_rx_path.vhd changed - r ecompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\logical_tx_path.vhd changed - r ecompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\obn_counter.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\RX_ARBITER.vhd changed - recomp iling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\FIFO_64_64_64.vhd changed - rec ompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Arb_Blk.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Clk_Blk.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Cnt_Blk.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_INT_Blk.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Main_Blk.vhd changed - reco mpiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Mpu_Blk.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_SS_Blk.vhd changed - recomp iling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Synch_Blk.vhd changed - rec ompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\FIFO_32_64_64.vhd changed - rec ompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\FIFO_512_64_64.vhd changed - re compiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\UHPI.vhd changed - recompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\FIFO_156_64_64.vhd changed - re compiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\FIFO_157_64_64.vhd changed - re compiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\DDR_INPUT.vhd changed - recompi ling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\DDR_OUTPUT.vhd changed - recomp iling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\DDR_OUT_PLL.vhd changed - recom piling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\spi_transmitter.vhd changed - r ecompiling File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_Top.vhd changed - recompili ng File D:\MC\MC-DMB-FPGA\fpga_first_release\source\I2C_COMM.vhd changed - recompil
ing File D:\MC\MC-DMB-FPGA\fpga_first_release\source\rx_path.vhd changed - recompili ng File D:\MC\MC-DMB-FPGA\fpga_first_release\source\tx_path.vhd changed - recompili ng File D:\MC\MC-DMB-FPGA\fpga_first_release\source\top_AMC.vhd changed - recompili ng File C:\lscc\diamond\1.1\synpbase\lib\vhd\numeric.vhd changed - recompiling # Thu Dec 01 13:46:38 2011 ###########################################################] Synopsys Verilog Compiler, version comp510rc, Build 126R, built Jul 22 2010 @N|Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\lscc\diamond\1.1\synpbase\lib\lucent\ecp3.v" @I::"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\pcs_if.v " @I:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\pcs_if.v" :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\SRIO_demo_c fg.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\phy_demo _clock_gen.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\phy_demo _rio2_rx_policy.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\srio_def ines.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\srio_sub sys_top.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\wrapper_ srio_4x.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serdes_1x_3 G125\pcs_serdes_1x_3G125.v" @N: CG334 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":103:11:103:23|Read directive translate_off @N: CG333 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":112:11:112:22|Read directive translate_on @N: CG334 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":652:11:652:23|Read directive translate_off @N: CG333 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":2130:11:2130:22|Read directive translate_on @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\srio_1x_3G125\e val_support\itd_wrapper_bb.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\srio_1x_3G125\s rio_1x_3G125_bb.v" Verilog syntax check successful! # Thu Dec 01 13:46:38 2011 ###########################################################] @N: CD720 :"C:\lscc\diamond\1.1\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\aif.vhd " @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\Clock_d ivider.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\logical _rx_path.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\logical _tx_path.vhd"
@I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\obn_cou nter.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\RX_ARBI TER.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_64 _64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Arb _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Clk _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Cnt _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_INT _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Mai n_Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Mpu _Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_SS_ Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Syn ch_Blk.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32 _64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_51 2_64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\UHPI.vh d" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_15 6_64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_15 7_64_64.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\DDR_INP UT.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\DDR_OUT PUT.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\spi_tra nsmitter.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_Top .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\I2C_COM M.vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\rx_path .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\tx_path .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\top_AMC .vhd" @I:: "D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\ADC_SPI _RX.vhd" VHDL syntax check successful! Options changed - recompiling @N: CD630 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":5:7:5:16|Synthesizing work.adc_spi_rx.rtl @N: CD233 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":44:24:44:25|Using sequential encoding for type fifo_wr_state_type @N: CD233 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":46:24:46:25|Using sequential encoding for type fifo_rd_state_type @N: CD233 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":50:24:50:25|Using sequential encoding for type spi_rd_state_type
@N: CD233 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":53:24:53:25|Using sequential encoding for type spi_wr_state_type @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":276:18:276:28|Removed redundant assignment @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":277:18:277:26|Removed redundant assignment @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":294:18:294:28|Removed redundant assignment @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":295:18:295:26|Removed redundant assignment @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":310:14:310:27|OTHERS clause is not synthesized @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":362:18:362:25|Removed redundant assignment @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":363:18:363:27|Removed redundant assignment @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":380:18:380:25|Removed redundant assignment @N: CD364 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":381:18:381:27|Removed redundant assignment @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":396:14:396:27|OTHERS clause is not synthesized @W: CD326 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":409:2:409:9|Port almostempty of entity work.fifo_32_64_64 is unco nnected @W: CD326 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":426:4:426:11|Port almostempty of entity work.fifo_32_64_64 is unc onnected @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":518:5:518:18|OTHERS clause is not synthesized @W: CD604 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":597:14:597:27|OTHERS clause is not synthesized @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":31:30:31:39|Signal fifo_write is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":35:7:35:17|Signal wr_adc_data is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":37:7:37:13|Signal cs_read is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":37:16:37:23|Signal cs_write is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":42:7:42:22|Signal start_fifo1_read is undriven @W: CD638 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":42:24:42:39|Signal start_fifo2_read is undriven @N: CD630 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\F IFO_32_64_64.vhd":14:7:14:19|Synthesizing work.fifo_32_64_64.structure @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":280:14:280:17|Inconsistency in number of generics declared on componen t and2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":313:14:313:16|Inconsistency in number of generics declared on componen t inv (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":316:14:316:16|Inconsistency in number of generics declared on componen t or2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":330:14:330:17|Inconsistency in number of generics declared on componen t xor2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":297:14:297:20|Inconsistency in number of generics declared on componen
t fd1p3bx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":301:14:301:20|Inconsistency in number of generics declared on componen t fd1p3dx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":309:14:309:20|Inconsistency in number of generics declared on componen t fd1s3dx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":305:14:305:20|Inconsistency in number of generics declared on componen t fd1s3bx (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":287:14:287:19|Inconsistency in number of generics declared on componen t fadd2b (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":283:14:283:16|Inconsistency in number of generics declared on componen t cu2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":292:14:292:19|Inconsistency in number of generics declared on componen t fsub2b (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":276:14:276:18|Inconsistency in number of generics declared on componen t ageb2 (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":324:14:324:16|Inconsistency in number of generics declared on componen t vhi (0) @W:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":327:14:327:16|Inconsistency in number of generics declared on componen t vlo (0) Post processing for work.fifo_32_64_64.structure Post processing for work.adc_spi_rx.rtl @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|Pruning Register wr_fifo_not_empty @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":450:5:450:6|Pruning Register ADC_fifo_op(63 downto 0) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":324:8:324:9|Pruning Register data_written @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":240:8:240:9|Pruning Register data_received @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(63) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(62) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(61) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(60) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(59) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(58) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(57) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(56) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(55) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(54) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(53)
@W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(52) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(51) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(50) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(49) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(48) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(47) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(46) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(45) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(44) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(43) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(42) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(41) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(40) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(39) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(38) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(37) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(36) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(35) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(34) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(33) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(32) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(31) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(30) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(29) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(28) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(27) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(26) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(25) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(24) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(23)
@W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(22) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(21) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(20) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(19) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(18) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(17) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(16) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(15) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(14) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(13) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(12) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(11) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(10) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(9) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(8) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(7) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(6) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(5) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(4) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(3) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(2) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(1) @W: CL169 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":172:1:172:2|Pruning Register fifo_data_wr_cl(0) @A:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\ADC_SPI_R X.vhd":172:1:172:2|Feedback mux created for signal rd_en. Did you forget the set /reset assignment for this signal? Specifying a reset value will improve timing and area @A:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\ADC_SPI_R X.vhd":172:1:172:2|Feedback mux created for signal start_fifo_wr. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\ADC_SPI_R X.vhd":450:5:450:6|Feedback mux created for signal fifo_rd_state[1:0]. Did you f orget the set/reset assignment for this signal? Specifying a reset value will im prove timing and area @A:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\ADC_SPI_R X.vhd":450:5:450:6|Feedback mux created for signal RD_DATA[63:0]. Did you forget
the set/reset assignment for this signal? Specifying a reset value will improve timing and area @W: CL111 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|All reachable assignments to both_fifo_not_empty assi gn '0', register removed by optimization @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|Sharing sequential element fifo1_clear. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A
DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A
DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL177 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":506:13:506:25|Sharing sequential element fifo_data_wr_e. @N: CL201 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":324:8:324:9|Trying to extract state machine for register spi_wr_s tate Extracted state machine for register spi_wr_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":324:8:324:9|Initial value is not supported on state machine spi_w r_state @N: CL201 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":240:8:240:9|Trying to extract state machine for register spi_rd_s tate Extracted state machine for register spi_rd_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":240:8:240:9|Initial value is not supported on state machine spi_r d_state @N: CL201 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":450:5:450:6|Trying to extract state machine for register fifo_rd_ state Extracted state machine for register fifo_rd_state State machine has 3 reachable states with original encodings of: 00 01 10 @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":450:5:450:6|Initial value is not supported on state machine fifo_ rd_state @N: CL201 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|Trying to extract state machine for register fifo_wr_ state Extracted state machine for register fifo_wr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W: CL249 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":541:8:541:9|Initial value is not supported on state machine fifo_ wr_state @W: CL159 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A
DC_SPI_RX.vhd":11:0:11:5|Input DAC_TS is unused @W: CL159 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\A DC_SPI_RX.vhd":16:0:16:2|Input OBN is unused # Thu Dec 01 13:46:39 2011 ###########################################################] @I::"C:\lscc\diamond\1.1\synpbase\lib\lucent\ecp3.v" @I::"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\pcs_if.v " @I:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\pcs_if.v" :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\SRIO_demo_c fg.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\phy_demo _clock_gen.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\phy_demo _rio2_rx_policy.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\srio_def ines.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\srio_sub sys_top.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\wrapper_ srio_4x.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serdes_1x_3 G125\pcs_serdes_1x_3G125.v" @N: CG334 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":103:11:103:23|Read directive translate_off @N: CG333 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":112:11:112:22|Read directive translate_on @N: CG334 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":652:11:652:23|Read directive translate_off @N: CG333 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":2130:11:2130:22|Read directive translate_on @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\srio_1x_3G125\e val_support\itd_wrapper_bb.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\srio_1x_3G125\s rio_1x_3G125_bb.v" Verilog syntax check successful! @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":43:7:43:10 |Synthesizing module AND2 @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":457:7:457: 9|Synthesizing module INV @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":834:7:834: 9|Synthesizing module OR2 @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":1078:7:107 8:10|Synthesizing module XOR2 @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":186:7:186: 13|Synthesizing module FD1P3BX @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":197:7:197: 13|Synthesizing module FD1P3DX @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":258:7:258: 13|Synthesizing module FD1S3DX @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":248:7:248:
13|Synthesizing module FD1S3BX @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":148:7:148: 12|Synthesizing module FADD2B @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":129:7:129: 9|Synthesizing module CU2 @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":382:7:382: 12|Synthesizing module FSUB2B @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":25:7:25:11 |Synthesizing module AGEB2 @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":1025:7:102 5:9|Synthesizing module VHI @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":1029:7:102 9:9|Synthesizing module VLO # Thu Dec 01 13:46:39 2011 ###########################################################] @I::"C:\lscc\diamond\1.1\synpbase\lib\lucent\ecp3.v" @I::"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\pcs_if.v " @I:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\pcs_if.v" :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\SRIO_demo_c fg.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\phy_demo _clock_gen.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\phy_demo _rio2_rx_policy.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\srio_def ines.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\srio_sub sys_top.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\wrapper_ srio_4x.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serdes_1x_3 G125\pcs_serdes_1x_3G125.v" @N: CG334 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":103:11:103:23|Read directive translate_off @N: CG333 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":112:11:112:22|Read directive translate_on @N: CG334 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":652:11:652:23|Read directive translate_off @N: CG333 :"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\pcs_serd es_1x_3G125\pcs_serdes_1x_3G125.v":2130:11:2130:22|Read directive translate_on @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\srio_1x_3G125\e val_support\itd_wrapper_bb.v" @I::"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\srio_1x_3G125\s rio_1x_3G125_bb.v" Verilog syntax check successful! @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":1360:7:136 0:14|Synthesizing module PDPW16KC @N: CG364 :"C:\lscc\diamond\1.1\cae_library\synthesis\verilog\ecp3.v":956:7:956: 14|Synthesizing module ROM16X1A
# Thu Dec 01 13:46:39 2011 ###########################################################] Call Queue Stats: Suppressed 15 calls Synopsys Netlist Filter, version comp510rc, Build 126R, built Jul 22 2010 @N|Running in 32-bit mode @N:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":710:4:710:16|Number of passed parameters/generics from instance pdp_ra m_0_1_0 do not match cell PDPW16KC @N:"D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_release\source\FIFO_32_6 4_64.vhd":676:4:676:16|Number of passed parameters/generics from instance pdp_ra m_0_0_1 do not match cell PDPW16KC Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Dec 01 13:46:40 2011 ###########################################################] @END Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Thu Dec 01 13:46:40 2011 ###########################################################] Synopsys Generic Technology Mapper, Version map520lat, Build 110R, Built Sep 28 2010 10:52:10 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2010.03L-SP1 @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N|Running in logic synthesis mode without enhanced optimization Finished Timing Extraction Phase. (Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) Automatic dissolve at startup in view:work.ADC_SPI_RX(rtl) of rx_fifo2(FIFO_32_6 4_64) Automatic dissolve at startup in view:work.ADC_SPI_RX(rtl) of rx_fifo1(FIFO_32_6 4_64) @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":626:4:626:9|Removing instance rx_fifo2.LUT4_9 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":631:4:631:9|Removing instance rx_fifo2.LUT4_8 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":636:4:636:9|Removing instance rx_fifo2.LUT4_7 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":641:4:641:9|Removing instance rx_fifo2.LUT4_6 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":646:4:646:9|Removing instance rx_fifo2.LUT4_5 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":967:4:967:8|Removing sequential instance rx_fifo2.FF_39 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":970:4:970:8|Removing sequential instance rx_fifo2.FF_38 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":973:4:973:8|Removing sequential instance rx_fifo2.FF_37 of vie
w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":976:4:976:8|Removing sequential instance rx_fifo2.FF_36 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":979:4:979:8|Removing sequential instance rx_fifo2.FF_35 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":982:4:982:8|Removing sequential instance rx_fifo2.FF_34 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1009:4:1009:8|Removing sequential instance rx_fifo2.FF_25 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1013:4:1013:8|Removing sequential instance rx_fifo2.FF_24 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1017:4:1017:8|Removing sequential instance rx_fifo2.FF_23 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1021:4:1021:8|Removing sequential instance rx_fifo2.FF_22 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1025:4:1025:8|Removing sequential instance rx_fifo2.FF_21 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1029:4:1029:8|Removing sequential instance rx_fifo2.FF_20 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1033:4:1033:8|Removing sequential instance rx_fifo2.FF_19 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1037:4:1037:8|Removing sequential instance rx_fifo2.FF_18 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1041:4:1041:8|Removing sequential instance rx_fifo2.FF_17 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1045:4:1045:8|Removing sequential instance rx_fifo2.FF_16 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1049:4:1049:8|Removing sequential instance rx_fifo2.FF_15 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1053:4:1053:8|Removing sequential instance rx_fifo2.FF_14 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1057:4:1057:8|Removing sequential instance rx_fifo2.FF_13 of v iew:LUCENT.FD1S3BX(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1294:4:1294:15|Removing instance rx_fifo2.ae_clr_cmp_2 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1290:4:1290:15|Removing instance rx_fifo2.ae_clr_cmp_1 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1286:4:1286:15|Removing instance rx_fifo2.ae_clr_cmp_0 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp
uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1255:4:1255:15|Removing instance rx_fifo2.ae_set_cmp_2 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1251:4:1251:15|Removing instance rx_fifo2.ae_set_cmp_1 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1247:4:1247:15|Removing instance rx_fifo2.ae_set_cmp_0 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":626:4:626:9|Removing instance rx_fifo1.LUT4_9 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":631:4:631:9|Removing instance rx_fifo1.LUT4_8 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":636:4:636:9|Removing instance rx_fifo1.LUT4_7 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":641:4:641:9|Removing instance rx_fifo1.LUT4_6 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":646:4:646:9|Removing instance rx_fifo1.LUT4_5 of black_box vie w:LUCENT.ROM16X1A(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":967:4:967:8|Removing sequential instance rx_fifo1.FF_39 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":970:4:970:8|Removing sequential instance rx_fifo1.FF_38 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":973:4:973:8|Removing sequential instance rx_fifo1.FF_37 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":976:4:976:8|Removing sequential instance rx_fifo1.FF_36 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":979:4:979:8|Removing sequential instance rx_fifo1.FF_35 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":982:4:982:8|Removing sequential instance rx_fifo1.FF_34 of vie w:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1009:4:1009:8|Removing sequential instance rx_fifo1.FF_25 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1013:4:1013:8|Removing sequential instance rx_fifo1.FF_24 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1017:4:1017:8|Removing sequential instance rx_fifo1.FF_23 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1021:4:1021:8|Removing sequential instance rx_fifo1.FF_22 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1025:4:1025:8|Removing sequential instance rx_fifo1.FF_21 of v
iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1029:4:1029:8|Removing sequential instance rx_fifo1.FF_20 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1033:4:1033:8|Removing sequential instance rx_fifo1.FF_19 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1037:4:1037:8|Removing sequential instance rx_fifo1.FF_18 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1041:4:1041:8|Removing sequential instance rx_fifo1.FF_17 of v iew:LUCENT.FD1P3BX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1045:4:1045:8|Removing sequential instance rx_fifo1.FF_16 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1049:4:1049:8|Removing sequential instance rx_fifo1.FF_15 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1053:4:1053:8|Removing sequential instance rx_fifo1.FF_14 of v iew:LUCENT.FD1P3DX(PRIM) because there are no references to its outputs @N: BN116 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1057:4:1057:8|Removing sequential instance rx_fifo1.FF_13 of v iew:LUCENT.FD1S3BX(PRIM) because there are no references to its outputs @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1294:4:1294:15|Removing instance rx_fifo1.ae_clr_cmp_2 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1290:4:1290:15|Removing instance rx_fifo1.ae_clr_cmp_1 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1286:4:1286:15|Removing instance rx_fifo1.ae_clr_cmp_0 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1255:4:1255:15|Removing instance rx_fifo1.ae_set_cmp_2 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1251:4:1251:15|Removing instance rx_fifo1.ae_set_cmp_1 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts @N: BN114 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1247:4:1247:15|Removing instance rx_fifo1.ae_set_cmp_0 of blac k_box view:work.AGEB2(syn_black_box) because there are no references to its outp uts Available hyper_sources - for debug and ip models None Found @N: FA239 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":353:30:353:40|Rom DAC_SDI1_2 mapped in logic. @N: FA239 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":353:30:353:40|Rom DAC_SDI1_2 mapped in logic. @N: MO106 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":353:30:353:40|Found ROM, 'DAC_SDI1_2', 16 words by 1 bits Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 75MB p
eak: 77MB) Encoding state machine work.ADC_SPI_RX(rtl)-spi_wr_state[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine work.ADC_SPI_RX(rtl)-spi_rd_state[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine work.ADC_SPI_RX(rtl)-fifo_wr_state[0:2] original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine work.ADC_SPI_RX(rtl)-fifo_rd_state[0:2] original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\adc_spi_r x.vhd":324:8:324:9|Found counter in view:work.ADC_SPI_RX(rtl) inst bit_count1[3: 0] @N:"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\adc_spi_r x.vhd":240:8:240:9|Found counter in view:work.ADC_SPI_RX(rtl) inst bit_count[3:0 ] @N:"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\adc_spi_r x.vhd":213:8:213:9|Found counter in view:work.ADC_SPI_RX(rtl) inst clk_div[3:0] @N:"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\adc_spi_r x.vhd":172:1:172:2|Found counter in view:work.ADC_SPI_RX(rtl) inst rd_count[7:0] Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79M B)
#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ############## ######[ ================================================================================ ====== Instance:Pin Generated Clock Optimization Status ================================================================================ ====== fifo_data_wr_e:C Done fifo_data_wr[17]:C Done fifo_data_wr[16]:C Done fifo_data_wr[32]:C Done fifo_data_wr[31]:C Done fifo_data_wr[30]:C Done fifo_data_wr[29]:C Done fifo_data_wr[28]:C Done fifo_data_wr[27]:C Done fifo_data_wr[26]:C Done fifo_data_wr[25]:C Done fifo_data_wr[24]:C Done
fifo_data_wr[23]:C fifo_data_wr[22]:C fifo_data_wr[21]:C fifo_data_wr[20]:C fifo_data_wr[19]:C fifo_data_wr[18]:C fifo_data_wr[47]:C fifo_data_wr[46]:C fifo_data_wr[45]:C fifo_data_wr[44]:C fifo_data_wr[43]:C fifo_data_wr[42]:C fifo_data_wr[41]:C fifo_data_wr[40]:C fifo_data_wr[39]:C fifo_data_wr[38]:C fifo_data_wr[37]:C fifo_data_wr[36]:C fifo_data_wr[35]:C fifo_data_wr[34]:C fifo_data_wr[33]:C fifo_data_wr[62]:C fifo_data_wr[61]:C fifo_data_wr[60]:C fifo_data_wr[59]:C fifo_data_wr[58]:C fifo_data_wr[57]:C fifo_data_wr[56]:C fifo_data_wr[55]:C fifo_data_wr[54]:C fifo_data_wr[53]:C fifo_data_wr[52]:C fifo_data_wr[51]:C fifo_data_wr[50]:C fifo_data_wr[49]:C fifo_data_wr[48]:C fifo_data_wr[13]:C fifo_data_wr[12]:C fifo_data_wr[11]:C fifo_data_wr[10]:C fifo_data_wr[9]:C fifo_data_wr[8]:C fifo_data_wr[7]:C fifo_data_wr[6]:C fifo_data_wr[5]:C fifo_data_wr[4]:C fifo_data_wr[3]:C fifo_data_wr[2]:C fifo_data_wr[1]:C fifo_data_wr[0]:C fifo_data_wr[63]:C fifo_data_wr[15]:C fifo_data_wr[14]:C wr_count1[4]:C wr_count1[3]:C wr_count1[2]:C wr_count1[1]:C wr_count1[0]:C rd_count[7:0]:C rd_cmd:C
Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done Done
wr_cmd:C start_fifo_wr:C rd_en:C
Done Done Done
##################### END OF GENERATED CLOCK OPTIMIZATION REPORT ############### ######] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Me mory used current: 77MB peak: 79MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB) @N: BN114 :|Removing instance un7_wr_count1_pt_0 of black_box view:LUCENT.MULT18 X18C(PRIM) because there are no references to its outputs @N: BN114 :|Removing instance un7_wr_count1_pt of black_box view:LUCENT.MULT18X1 8C(PRIM) because there are no references to its outputs Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current : 77MB peak: 79MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current : 77MB peak: 79MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 77MB pe ak: 79MB) Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 82MB) Pass CPU time Worst Slack -----------------------------------------------------------Pass CPU time Worst Slack -----------------------------------------------------------1 0h:00m:01s -0.14ns 2 0h:00m:02s -0.14ns -----------------------------------------------------------Timing driven replication report Luts / Registers Luts / Registers 354 / 350 / 207 207
Pass CPU time Worst Slack -----------------------------------------------------------1 0h:00m:03s -0.14ns 2 0h:00m:03s -0.14ns 3 0h:00m:03s -0.14ns 4 0h:00m:03s -0.14ns ------------------------------------------------------------
Luts / Registers 351 / 351 / 351 / 351 / 207 207 207 207
Pass
CPU time
Worst Slack
Luts / Registers
-----------------------------------------------------------1 0h:00m:03s -0.14ns 2 0h:00m:03s -0.14ns 3 0h:00m:03s -0.14ns 4 0h:00m:03s -0.14ns ------------------------------------------------------------
351 / 351 / 351 / 351 /
207 207 207 207
Net buffering Report for view:work.ADC_SPI_RX(rtl): @N: FX103 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Instance "fifo_data_wr_e" with "128" loads has been replicated "1" time(s) due to a soft fanout limit of "100" Added 0 Buffers Added 1 Registers via replication Added 0 LUTs via replication Finished technology timing optimizations and critical path resynthesis (Time ela psed 0h:00m:03s; Memory used current: 80MB peak: 82MB) @N: FX164 |The option to pack flops in the IOB has not been specified @N: FX623 |Packing into LUT62 @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":450:5:450:6|Boundary register RD_REQ.fb has been packed into a co mplex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":142:1:142:2|Boundary register wr_cmd.fb has been packed into a co mplex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":142:1:142:2|Boundary register rd_cmd.fb has been packed into a co mplex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_14_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_15_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_63_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_0_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_1_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_2_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_3_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n
et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_4_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_5_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_6_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_7_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_8_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_9_.fb has been packe d into a complex cell. To disable this register packing, set syn_keep=1 on the n et between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_10_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_11_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_12_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_13_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_48_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_49_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_50_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_51_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_52_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the
net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_53_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_54_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_55_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_56_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_57_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_58_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_59_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_60_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_61_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_62_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_33_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_34_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_35_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_36_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_37_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the
net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_38_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_39_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_40_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_41_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_42_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_43_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_44_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_45_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_46_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_47_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_18_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_19_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_20_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_21_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_22_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the
net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_23_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_24_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_25_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_26_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_27_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_28_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_29_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_30_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_31_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_32_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_16_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":506:13:506:25|Boundary register fifo_data_wr_17_.fb has been pack ed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net
between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_9_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_8_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_7_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_6_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_5_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_4_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_3_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_2_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_1_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":240:8:240:9|Boundary register rd_adc_data_0_.fb has been packed i nto a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A: BN291 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\a dc_spi_rx.vhd":324:8:324:9|Boundary register DAC_SDI1.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net betwee n the register and the complex cell. @W: MT420 |Found inferred clock ADC_SPI_RX|CLOCK with period 5.00ns. A user-defi ned clock should be declared on object "p:CLOCK"
@W: MT420 |Found inferred clock ADC_SPI_RX|lnk_clk with period 5.00ns. A user-de fined clock should be declared on object "p:lnk_clk" @W: MT420 |Found inferred clock ADC_SPI_RX|DAC_SCLK_inferred_clock with period 5 .00ns. A user-defined clock should be declared on object "n:DAC_SCLK" @W: MT246 :"d:\mc-dmb-fpga\mc_fpga_17_10_2011_0345pm\fpga_first_release\source\f ifo_32_64_64.vhd":1187:4:1187:14|Blackbox AGEB2 is missing a user supplied timin g model. This may have a negative effect on timing analysis and optimizations (Q uality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Dec 01 13:46:46 2011 # Top view: ADC_SPI_RX Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.. Performance Summary ******************* Worst slack in design: 0.004 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------ADC_SPI_RX|CLOCK 200.0 MHz 259.2 MHz 5.000 3.857 1.143 inferred Inferred_clkgroup_1 ADC_SPI_RX|DAC_SCLK_inferred_clock 200.0 MHz 610.0 MHz 5.000 1.639 3.361 inferred Inferred_clkgroup_2 ADC_SPI_RX|lnk_clk 200.0 MHz 206.0 MHz 5.000 4.855 0.145 inferred Inferred_clkgroup_0 System 200.0 MHz 1074.8 MHz 5.000 0.930 4.070 system default_clkgroup ================================================================================ ==========================================================
Clock Relationships ******************* Clocks | ris e to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | const raint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------ADC_SPI_RX|lnk_clk ADC_SPI_RX|lnk_clk | 5.000 0.145 | No paths | No paths | No paths ADC_SPI_RX|lnk_clk ADC_SPI_RX|CLOCK | Diff grp | No paths | No paths | No paths ADC_SPI_RX|lnk_clk ADC_SPI_RX|DAC_SCLK_inferred_clock | Diff grp | No paths | No paths | No paths ADC_SPI_RX|CLOCK ADC_SPI_RX|lnk_clk | Diff grp | No paths | No paths | No paths ADC_SPI_RX|CLOCK ADC_SPI_RX|CLOCK | 5.000 1.143 | No paths | No paths | No paths ADC_SPI_RX|DAC_SCLK_inferred_clock ADC_SPI_RX|lnk_clk | Diff grp | No paths | No paths | No paths ADC_SPI_RX|DAC_SCLK_inferred_clock ADC_SPI_RX|CLOCK | Diff grp | No paths | No paths | No paths ADC_SPI_RX|DAC_SCLK_inferred_clock ADC_SPI_RX|DAC_SCLK_inferred_clock | 5.000 3.361 | No paths | No paths | No paths ================================================================================ ============================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of cl ock edges. 'Diff grp' indicates that paths exist but the starting clock and ending c lock are in different clock groups.
Interface Information *********************
Input Ports: Port Name Slack Starting Reference Clock ------------------------------------------------------------------------------------ADC_GNT System (rising) NA 0.000 1.250 CLOCK NA DAC_SDO DAC_TS NA OBN[0] NA OBN[1] NA OBN[2] NA OBN[3] NA NA System (rising) NA NA NA NA NA NA NA NA NA NA NA NA NA 0.000 NA NA NA NA NA NA 2.912 NA NA NA NA NA User Constraint Arrival Time Required Time
OBN[4] NA OBN[5] NA OBN[6] NA OBN[7] NA OBN[8] NA OBN[9] NA OBN[10] NA OBN[11] NA OBN[12] NA OBN[13] NA RESET SPI_EN lnk_clk NA start_new_packet
NA NA NA NA NA NA NA NA NA NA System (rising) System (rising) NA System (rising)
NA NA NA NA NA NA NA NA NA NA NA NA NA NA
NA NA NA NA NA NA NA NA NA NA 0.000 0.000 NA 0.000
NA NA NA NA NA NA NA NA NA NA 1.339 1.484 NA 1.072
================================================================================ ====== Output Ports: Port Arrival Name nt Time Starting Required Reference Time Slack Clock User Constrai
-------------------------------------------------------------------------------------------------------------------DAC_CS_L ADC_SPI_RX|CLOCK (rising) NA 4.996 5.000 DAC_SCLK ADC_SPI_RX|CLOCK (rising) NA 4.448 5.000 DAC_SDI ADC_SPI_RX|CLOCK (rising) NA 4.340 5.000 RD_DATA[0] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[1] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[2] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[3] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[4] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[5] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000
RD_DATA[6] 4.340 RD_DATA[7] 4.340 RD_DATA[8] 4.340 RD_DATA[9] 4.340 RD_DATA[10] 4.340 RD_DATA[11] 4.340 RD_DATA[12] 4.340 RD_DATA[13] 4.340 RD_DATA[14] 4.340 RD_DATA[15] 4.340 RD_DATA[16] 4.340 RD_DATA[17] 4.340 RD_DATA[18] 4.340 RD_DATA[19] 4.340 RD_DATA[20] 4.340 RD_DATA[21] 4.340 RD_DATA[22] 4.340 RD_DATA[23] 4.340 RD_DATA[24] 4.340 RD_DATA[25] 4.340 RD_DATA[26] 4.340 RD_DATA[27] 4.340 RD_DATA[28] 4.340 RD_DATA[29] 4.340 RD_DATA[30] 4.340 RD_DATA[31] 4.340 RD_DATA[32] 4.340 RD_DATA[33] 4.340 RD_DATA[34] 4.340 RD_DATA[35] 4.340
ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
RD_DATA[36] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[37] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[38] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[39] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[40] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[41] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[42] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[43] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[44] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[45] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[46] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[47] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[48] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[49] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[50] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[51] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[52] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[53] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[54] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[55] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[56] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[57] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[58] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[59] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[60] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[61] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[62] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_DATA[63] ADC_SPI_RX|lnk_clk 4.340 5.000 RD_REQ ADC_SPI_RX|lnk_clk 4.340 5.000 RX_ADC7923_ERROR[0] NA NA NA NA
(rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising) (rising)
RX_ADC7923_ERROR[1] ADC_SPI_RX|DAC_SCLK_inferred_clock (rising) NA 4.367 5.000 RX_ADC7923_ERROR[2] ADC_SPI_RX|DAC_SCLK_inferred_clock (rising) NA 4.367 5.000 RX_ADC7923_ERROR[3] NA NA NA NA NA rd_cnt[0] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[1] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[2] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[3] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[4] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[5] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 ================================================================================ ===================================== ##### END OF TIMING REPORT #####] --------------------------------------Resource Usage Report Part: lfe3_70ea-7 Register bits: 370 of 62640 (1%) PIC Latch: 0 I/O cells: 85 Block Rams : 4 of 240 (1%) Details: AND2: CCU2C: CU2: FADD2B: FD1P3AX: FD1P3BX: FD1P3DX: FD1P3IX: FD1P3JX: FD1S3AX: FD1S3BX: FD1S3DX: FD1S3IX: FSUB2B: GSR: IB: IFS1P3DX: IFS1P3IX: INV: OB: OBZ: OFS1P3DX: OFS1P3JX: OR2: ORCALUT4:
4 5 24 24 4 14 174 17 6 4 3 72 8 8 1 7 1 1 13 72 6 65 1 2 343
PDPW16KC: 4 PFUMX: 1 PUR: 1 ROM16X1A: 38 VHI: 1 VLO: 1 XOR2: 22 Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 82MB) Writing Analyst data base D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fpga_first_re lease\top\top_top.srm @N: MF203 |Set autoconstraint_io Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current : 80MB peak: 82MB) Writing EDIF Netlist and constraint files D-2010.03L-SP1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:04s; Mem ory used current: 84MB peak: 85MB) Writing Verilog Simulation files Finished Writing Verilog Simulation files (Time elapsed 0h:00m:04s; Memory used current: 84MB peak: 85MB) Writing VHDL Simulation files Finished Writing VHDL Simulation files (Time elapsed 0h:00m:05s; Memory used cur rent: 85MB peak: 85MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 84MB peak: 85MB) @N: MF276 |Gated clock conversion enabled, but no gated clocks found in design Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 84MB peak: 85MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Mem ory used current: 84MB peak: 85MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Mem ory used current: 84MB peak: 85MB)
##### START OF TIMING REPORT #####[ # Timing Report written on Thu Dec 01 13:46:47 2011 # Top view: ADC_SPI_RX Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary ******************* Worst slack in design: 0.004 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------ADC_SPI_RX|CLOCK 200.0 MHz 259.2 MHz 5.000 3.857 1.143 inferred Inferred_clkgroup_1 ADC_SPI_RX|DAC_SCLK_inferred_clock 200.0 MHz 610.0 MHz 5.000 1.639 3.361 inferred Inferred_clkgroup_2 ADC_SPI_RX|lnk_clk 200.0 MHz 206.0 MHz 5.000 4.855 0.145 inferred Inferred_clkgroup_0 System 200.0 MHz 1074.8 MHz 5.000 0.930 4.070 system default_clkgroup ================================================================================ ==========================================================
Clock Relationships ******************* Clocks | ris e to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------Starting Ending | const raint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------ADC_SPI_RX|lnk_clk ADC_SPI_RX|lnk_clk | 5.000 0.145 | No paths | No paths | No paths ADC_SPI_RX|lnk_clk ADC_SPI_RX|CLOCK | Diff grp | No paths | No paths | No paths ADC_SPI_RX|lnk_clk ADC_SPI_RX|DAC_SCLK_inferred_clock | Diff grp | No paths | No paths | No paths ADC_SPI_RX|CLOCK ADC_SPI_RX|lnk_clk | Diff grp | No paths | No paths | No paths ADC_SPI_RX|CLOCK ADC_SPI_RX|CLOCK | 5.000 1.143 | No paths | No paths | No paths ADC_SPI_RX|DAC_SCLK_inferred_clock ADC_SPI_RX|lnk_clk | Diff grp | No paths | No paths | No paths ADC_SPI_RX|DAC_SCLK_inferred_clock ADC_SPI_RX|CLOCK | Diff grp | No paths | No paths | No paths ADC_SPI_RX|DAC_SCLK_inferred_clock ADC_SPI_RX|DAC_SCLK_inferred_clock | 5.000 3.361 | No paths | No paths | No paths ================================================================================ ============================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of cl ock edges. 'Diff grp' indicates that paths exist but the starting clock and ending c lock are in different clock groups.
Interface Information *********************
Input Ports: Port Name Slack Starting Reference Clock ------------------------------------------------------------------------------------ADC_GNT System (rising) NA 0.000 1.250 CLOCK NA DAC_SDO DAC_TS NA OBN[0] NA OBN[1] NA OBN[2] NA OBN[3] NA OBN[4] NA OBN[5] NA OBN[6] NA OBN[7] NA OBN[8] NA OBN[9] NA OBN[10] NA OBN[11] NA OBN[12] NA OBN[13] NA RESET SPI_EN lnk_clk NA NA System (rising) NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA System (rising) System (rising) NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0.000 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0.000 0.000 NA NA 2.912 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 1.339 1.484 NA User Constraint Arrival Time Required Time
start_new_packet
System (rising)
NA
0.000
1.072
================================================================================ ====== Output Ports: Port Arrival Name nt Time Starting Required Reference Time Slack Clock User Constrai
-------------------------------------------------------------------------------------------------------------------DAC_CS_L ADC_SPI_RX|CLOCK (rising) NA 4.996 5.000 DAC_SCLK ADC_SPI_RX|CLOCK (rising) NA 4.448 5.000 DAC_SDI ADC_SPI_RX|CLOCK (rising) NA 4.340 5.000 RD_DATA[0] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[1] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[2] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[3] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[4] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[5] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[6] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[7] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[8] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[9] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[10] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[11] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[12] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[13] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[14] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[15] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[16] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[17] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[18] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000
RD_DATA[19] 4.340 RD_DATA[20] 4.340 RD_DATA[21] 4.340 RD_DATA[22] 4.340 RD_DATA[23] 4.340 RD_DATA[24] 4.340 RD_DATA[25] 4.340 RD_DATA[26] 4.340 RD_DATA[27] 4.340 RD_DATA[28] 4.340 RD_DATA[29] 4.340 RD_DATA[30] 4.340 RD_DATA[31] 4.340 RD_DATA[32] 4.340 RD_DATA[33] 4.340 RD_DATA[34] 4.340 RD_DATA[35] 4.340 RD_DATA[36] 4.340 RD_DATA[37] 4.340 RD_DATA[38] 4.340 RD_DATA[39] 4.340 RD_DATA[40] 4.340 RD_DATA[41] 4.340 RD_DATA[42] 4.340 RD_DATA[43] 4.340 RD_DATA[44] 4.340 RD_DATA[45] 4.340 RD_DATA[46] 4.340 RD_DATA[47] 4.340 RD_DATA[48] 4.340
ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000 ADC_SPI_RX|lnk_clk (rising) 5.000
RD_DATA[49] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[50] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[51] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[52] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[53] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[54] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[55] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[56] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[57] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[58] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[59] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[60] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[61] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[62] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_DATA[63] ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RD_REQ ADC_SPI_RX|lnk_clk (rising) NA 4.340 5.000 RX_ADC7923_ERROR[0] NA NA NA NA NA RX_ADC7923_ERROR[1] ADC_SPI_RX|DAC_SCLK_inferred_clock (rising) NA 4.367 5.000 RX_ADC7923_ERROR[2] ADC_SPI_RX|DAC_SCLK_inferred_clock (rising) NA 4.367 5.000 RX_ADC7923_ERROR[3] NA NA NA NA NA rd_cnt[0] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[1] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[2] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[3] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[4] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 rd_cnt[5] ADC_SPI_RX|lnk_clk (rising) NA 4.864 5.000 ================================================================================ ===================================== ##### END OF TIMING REPORT #####] Mapper successful! Process took 0h:00m:05s realtime, 0h:00m:05s cputime
# Thu Dec 01 13:46:47 2011 ###########################################################] Synthesis exit by 0. Done: completed successfully ************************************************************ ** Translate Design ** ************************************************************ edif2ngd -l LatticeECP3 -d LFE3-70EA -path "D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_03 45PM/fpga_first_release/top" -path "D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpg a_first_release" "D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/t op/top_top.edi" "top_top.ngo" edif2ngd: version Diamond_1.1_Production (517) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights rese rved. WARNING - edif2ngd: Property mem_init_file has no value - ignoring... On or above line 1031 in file D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fp ga_first_release\top\top_top.edi WARNING - edif2ngd: Property mem_init_file has no value - ignoring... On or above line 1042 in file D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fp ga_first_release\top\top_top.edi WARNING - edif2ngd: Property mem_init_file has no value - ignoring... On or above line 3440 in file D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fp ga_first_release\top\top_top.edi WARNING - edif2ngd: Property mem_init_file has no value - ignoring... On or above line 3451 in file D:\MC-DMB-FPGA\MC_FPGA_17_10_2011_0345PM\fp ga_first_release\top\top_top.edi Writing the design to top_top.ngo... ngdbuild -a LatticeECP3 -d LFE3-70EA -p "C:/lscc/diamond/1.1/ispfpga/ep5c00/da ta" -p "D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top" -p "D: /MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release" -p "D:/MC-DMB-FPGA/MC _FPGA_17_10_2011_0345PM/fpga_first_release/srio_1x_3G125" "top_top.ngo" "top_to p.ngd" ngdbuild: version Diamond_1.1_Production (517) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights rese rved. Reading 'top_top.ngo' ... Loading NGL library 'C:/lscc/diamond/1.1/ispfpga/ep5c00a/data/ec5alib.ngl'... Loading NGL library 'C:/lscc/diamond/1.1/ispfpga/ep5c00/data/ep5clib.ngl'... Loading NGL library 'C:/lscc/diamond/1.1/ispfpga/ep5a00/data/ep5alib.ngl'... Loading NGL library 'C:/lscc/diamond/1.1/ispfpga/ep5g00/data/ep5glib.ngl'... Loading NGL library 'C:/lscc/diamond/1.1/ispfpga/or5g00/data/orc5glib.ngl'... Running WARNING WARNING WARNING DRC... - ngdbuild: logical net 'rx_fifo2/w_gctr_cia_S0_0' has no load - ngdbuild: logical net 'rx_fifo2/w_gctr_cia_S1_0' has no load - ngdbuild: logical net 'rx_fifo2/co2' has no load
ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild:
logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical logical
net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net
'rx_fifo2/r_gctr_cia_S0_0' has no load 'rx_fifo2/r_gctr_cia_S1_0' has no load 'rx_fifo2/co2_1' has no load 'rx_fifo2/rfill_0_S0_0' has no load 'rx_fifo2/rfill_3_BOUT_0' has no load 'rx_fifo2/rfill_3_S1_0' has no load 'rx_fifo2/empty_cmp_ci_a_S0_0' has no load 'rx_fifo2/empty_cmp_ci_a_S1_0' has no load 'rx_fifo2/a0_COUT_0' has no load 'rx_fifo2/a0_S1_0' has no load 'rx_fifo2/full_cmp_ci_a_S0_0' has no load 'rx_fifo2/full_cmp_ci_a_S1_0' has no load 'rx_fifo2/a1_COUT_0' has no load 'rx_fifo2/a1_S1_0' has no load 'rx_fifo2/af_set_ctr_cia_S0_0' has no load 'rx_fifo2/af_set_ctr_cia_S1_0' has no load 'rx_fifo2/co2_6' has no load 'rx_fifo2/af_set_cmp_ci_a_S0_0' has no load 'rx_fifo2/af_set_cmp_ci_a_S1_0' has no load 'rx_fifo2/a4_COUT_0' has no load 'rx_fifo2/a4_S1_0' has no load 'rx_fifo2/af_clr_ctr_cia_S0_0' has no load 'rx_fifo2/af_clr_ctr_cia_S1_0' has no load 'rx_fifo2/co2_7' has no load 'rx_fifo2/af_clr_cmp_ci_a_S0_0' has no load 'rx_fifo2/af_clr_cmp_ci_a_S1_0' has no load 'rx_fifo2/a5_COUT_0' has no load 'rx_fifo2/a5_S1_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO10_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO11_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO12_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO13_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO14_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO15_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO16_0' has no load 'rx_fifo2/pdp_ram_0_1_0_DO17_0' has no load 'rx_fifo1/w_gctr_cia_S0' has no load 'rx_fifo1/w_gctr_cia_S1' has no load 'rx_fifo1/co2' has no load 'rx_fifo1/r_gctr_cia_S0' has no load 'rx_fifo1/r_gctr_cia_S1' has no load 'rx_fifo1/co2_1' has no load 'rx_fifo1/rfill_0_S0' has no load 'rx_fifo1/rfill_3_BOUT' has no load 'rx_fifo1/rfill_3_S1' has no load 'rx_fifo1/empty_cmp_ci_a_S0' has no load 'rx_fifo1/empty_cmp_ci_a_S1' has no load 'rx_fifo1/a0_COUT' has no load 'rx_fifo1/a0_S1' has no load 'rx_fifo1/full_cmp_ci_a_S0' has no load 'rx_fifo1/full_cmp_ci_a_S1' has no load 'rx_fifo1/a1_COUT' has no load 'rx_fifo1/a1_S1' has no load 'rx_fifo1/af_set_ctr_cia_S0' has no load 'rx_fifo1/af_set_ctr_cia_S1' has no load 'rx_fifo1/co2_6' has no load 'rx_fifo1/af_set_cmp_ci_a_S0' has no load 'rx_fifo1/af_set_cmp_ci_a_S1' has no load 'rx_fifo1/a4_COUT' has no load 'rx_fifo1/a4_S1' has no load
WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild: ngdbuild:
logical net 'rx_fifo1/af_clr_ctr_cia_S0' has no load logical net 'rx_fifo1/af_clr_ctr_cia_S1' has no load logical net 'rx_fifo1/co2_7' has no load logical net 'rx_fifo1/af_clr_cmp_ci_a_S0' has no load logical net 'rx_fifo1/af_clr_cmp_ci_a_S1' has no load logical net 'rx_fifo1/a5_COUT' has no load logical net 'rx_fifo1/a5_S1' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO10' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO11' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO12' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO13' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO14' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO15' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO16' has no load logical net 'rx_fifo1/pdp_ram_0_1_0_DO17' has no load logical net 'rd_count_cry_0_S0_0' has no load logical net 'rd_count_s_0_S1_7' has no load logical net 'rd_count_s_0_COUT_7' has no load logical net 'DAC_TS' has no load logical net 'OBN_0' has no load logical net 'OBN_1' has no load logical net 'OBN_2' has no load logical net 'OBN_3' has no load logical net 'OBN_4' has no load logical net 'OBN_5' has no load logical net 'OBN_6' has no load logical net 'OBN_7' has no load logical net 'OBN_8' has no load logical net 'OBN_9' has no load logical net 'OBN_10' has no load logical net 'OBN_11' has no load logical net 'OBN_12' has no load logical net 'OBN_13' has no load DRC complete with 96 warnings
Design Results: 970 blocks expanded complete the first expansion Writing 'top_top.ngd' ... Done: completed successfully ************************************************************ ** Map Design ** ************************************************************ map -a LatticeECP3 -p LFE3-70EA -t FPBGA484 -s 7 -oc Commercial "top_top.ngd" o "top_top_map.ncd" -pr "top_top.prf" -mp "top_top.mrp" "D:/MC-DMB-FPGA/MC_FPGA_ 17_10_2011_0345PM/fpga_first_release/top.lpf" map: version Diamond_1.1_Production (517) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2010 Lattice Semiconductor Corporation, All rights rese rved. Process the file: top_top.ngd Picdevice="LFE3-70EA" Pictype="FPBGA484" Picspeed=7 Remove unused logic
Do not produce over sized NCDs. Part used: LFE3-70EAFPBGA484, Speed used: 7. WARNING - map: Semantic Error: "I_brd_clk" matches no ports in the design. Occu rred at line 19 in "FREQUENCY PORT "I_brd_clk" 52.000000 MHz ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/refck2core matches no nets in t he design. Occurred at line 95 in "FREQUENCY NET "srio_subsys_top_u/refck2core" 125.000000 MHz ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/refck2core matches no nets in t he design. Occurred at line 96 in "USE SECONDARY NET "srio_subsys_top_u/refck2c ore" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/rio_clk matches no nets in the design. Occurred at line 109 in "FREQUENCY NET "srio_subsys_top_u/rio_clk" 39.0 62500 MHz ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. Occurred at line 110 in "FREQUENCY NET "srio_subsys_top_u/tx_full _clk_c" 312.500000 MHz ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/pcs_if_clk matches no nets in t he design. Occurred at line 111 in "FREQUENCY NET "srio_subsys_top_u/pcs_if_clk " 156.250000 MHz ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. Occurred at line 112 in "FREQUENCY NET "srio_subsys_top_u/rx_ha lf_clk_ch0" 156.250000 MHz ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. Occurred at line 118 in "USE SECONDARY NET "srio_subsys_top_u/tx_ full_clk_c" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/pcs_if_clk matches no nets in t he design. srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. Occ urred at line 123 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/pcs_if_clk" TO C LKNET "srio_subsys_top_u/rx_half_clk_ch0" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. srio_subsys_top_u/pcs_if_clk matches no nets in the design. Occ urred at line 124 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/rx_half_clk_ch0" TO CLKNET "srio_subsys_top_u/pcs_if_clk" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. sys_clk matches no nets in the design. Occurred at line 125 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/rx_half_clk_ch0" TO CLKNET "sys_clk" ; ". Disabled this preference. WARNING - map: Semantic Error: sys_clk matches no nets in the design. srio_subsy s_top_u/refck2core matches no nets in the design. Occurred at line 126 in "BLOC K PATH FROM CLKNET "sys_clk" TO CLKNET "srio_subsys_top_u/refck2core" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. srio_subsys_top_u/pcs_if_clk matches no nets in the design. Occur red at line 128 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/tx_full_clk_c" TO CLKNET "srio_subsys_top_u/pcs_if_clk" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/pcs_if_clk matches no nets in t he design. srio_subsys_top_u/tx_full_clk_c matches no nets in the design. Occur red at line 129 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/pcs_if_clk" TO CLK
NET "srio_subsys_top_u/tx_full_clk_c" ; ". Disabled this preference. WARNING - map: Semantic Error: srio_subsys_top_u/tx_full_clk_c matches no nets i n the design. srio_subsys_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_ gen/full_clk_div8 matches no nets in the design. Occurred at line 130 in "BLOCK PATH FROM CLKNET "srio_subsys_top_u/tx_full_clk_c" TO CLKNET "srio_subsys_top_u /wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_gen/full_clk_div8" ; ". Disabled this preference. WARNING - map: Semantic Error: *rio_clk_reset_n matches no nets in the design. Occurred at line 132 in "BLOCK NET "*rio_clk_reset_n" ; ". Disabled this preference. WARNING - map: Semantic Error: *pcs_if_clk_reset_n matches no nets in the design . Occurred at line 133 in "BLOCK NET "*pcs_if_clk_reset_n" ; ". Disabled this preference. WARNING - map: Semantic Error: "srio_subsys_top_u/pcs_serdes/pcsd_inst" matches no asics in the design. Occurred at line 135 in "BLOCK PATH FROM ASIC "srio_sub sys_top_u/pcs_serdes/pcsd_inst" PIN "*FF_EBRD_CLK_?" ; ". Disabled this preference. WARNING - map: Semantic Error: *oplm2_mgt_1x_2x_nx_init_sm?init_state* matches n o cells in the design. Occurred at line 136 in "BLOCK PATH FROM CELL "*oplm2_mg t_1x_2x_nx_init_sm?init_state*" TO CELL "*oplm2_mgt_1x_2x_nx_tx_int*" ; ". Disabled this preference. WARNING - map: Semantic Error: "*wrapper*ollm_serial_tx_link_sched*local_reset_n " matches no cells in the design. Occurred at line 139 in "MAXDELAY FROM CELL " *wrapper*ollm_serial_tx_link_sched*local_reset_n" 16.000000 ns ; ". Disabled this preference. WARNING - map: Semantic Error: "*wrapper_srio_4x*rio_maintenance_module*bus_inte rface*mgt_a*" matches no cells in the design. Occurred at line 140 in "MULTICYC LE FROM CELL "*wrapper_srio_4x*rio_maintenance_module*bus_interface*mgt_a*" 2.00 0000 X ; ". Disabled this preference. WARNING - map: Semantic Error: iq_clk_c matches no nets in the design. Occurred at line 485 in "USE PRIMARY NET "iq_clk_c" ; ". Disabled this preference. WARNING - map: Semantic Error: FPGA_TO_DSP_OBN_CLKgen matches no nets in the des ign. Occurred at line 486 in "USE SECONDARY NET "FPGA_TO_DSP_OBN_CLKgen" ; ". Disabled this preference. WARNING - map: Port I_brd_clk does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (30): Error in IOBUF PORT "I_brd_clk" IO_TYPE=LVCMOS33 PCICLAMP=ON TERMINATEV TT=OFF DIFFRESISTOR=OFF ; : Port "I_brd_clk" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (31): Error in LOCATE COMP "I_brd_clk" SITE "T3" ; : COMP "I_brd_clk" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (71): Error in LOCATE COMP "I_Rst_n" SITE "T2" ; : COMP "I_Rst_n" not found in design. Disabled this preference. WARNING - map: Port I_Rst_n does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (72): Error in IOBUF PORT "I_Rst_n" IO_TYPE=LVCMOS33 ; : Port "I_Rst_n" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (94): Error in LOCATE COMP "srio_subsys_top_u/pcs_serdes/pcsd_inst" SITE "PCS A" ; : COMP "srio_subsys_top_u/pcs_serdes/pcsd_inst" not found in design. Disabl ed this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (120): Error in UGROUP "urio_clk_ff" BLKNAME srio_subsys_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_cl
k_gen/RIO_CLK_FF; : Block "srio_subsys_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_ gen/RIO_CLK_FF" of UGROUP "urio_clk_ff" not found in design. Disabled this prefe rence. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (121): Error in LOCATE UGROUP "urio_clk_ff" SITE "R62C92D" ; : UGROUP "urio_clk_ff" not found for LOCATE UGROUP. Disabled this preferenc e. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (122): Error in LOCATE UGROUP "RIO_CLK_GEN_GROUP" SITE "R64C90D" ; : UGROUP "RIO_CLK_GEN_GROUP" not found for LOCATE UGROUP. Disabled this pre ference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (141): Error in LOCATE COMP "B_ARM_Data_0" SITE "T18" ; : COMP "B_ARM_Data_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (142): Error in LOCATE COMP "B_ARM_Data_1" SITE "T19" ; : COMP "B_ARM_Data_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (143): Error in LOCATE COMP "B_ARM_Data_2" SITE "T20" ; : COMP "B_ARM_Data_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (144): Error in LOCATE COMP "B_ARM_Data_3" SITE "T21" ; : COMP "B_ARM_Data_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (145): Error in LOCATE COMP "B_ARM_Data_4" SITE "T22" ; : COMP "B_ARM_Data_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (146): Error in LOCATE COMP "B_ARM_Data_5" SITE "U15" ; : COMP "B_ARM_Data_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (147): Error in LOCATE COMP "B_ARM_Data_6" SITE "U16" ; : COMP "B_ARM_Data_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (148): Error in LOCATE COMP "B_ARM_Data_7" SITE "U18" ; : COMP "B_ARM_Data_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (149): Error in LOCATE COMP "B_ARM_Data_8" SITE "U19" ; : COMP "B_ARM_Data_8" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (150): Error in LOCATE COMP "B_ARM_Data_9" SITE "U20" ; : COMP "B_ARM_Data_9" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (151): Error in LOCATE COMP "B_ARM_Data_10" SITE "U22" ; : COMP "B_ARM_Data_10" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (152): Error in LOCATE COMP "B_ARM_Data_11" SITE "V17" ; : COMP "B_ARM_Data_11" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (153): Error in LOCATE COMP "B_ARM_Data_12" SITE "V18" ; : COMP "B_ARM_Data_12" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (154): Error in LOCATE COMP "B_ARM_Data_13" SITE "V19" ; : COMP "B_ARM_Data_13" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (155): Error in LOCATE COMP "B_ARM_Data_14" SITE "V22" ; : COMP "B_ARM_Data_14" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (156): Error in LOCATE COMP "B_ARM_Data_15" SITE "W17" ; : COMP "B_ARM_Data_15" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (157): Error in LOCATE COMP "O_ARM_WAIT_n" SITE "E10" ; : COMP "O_ARM_WAIT_n" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (158): Error in LOCATE COMP "I_ARM_CS_n" SITE "R3" ; : COMP "I_ARM_CS_n" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (159): Error in LOCATE COMP "I_ARM_OE_n" SITE "R1" ; : COMP "I_ARM_OE_n" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (160): Error in LOCATE COMP "I_ARM_WE_n" SITE "R2" ; : COMP "I_ARM_WE_n" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (161): Error in LOCATE COMP "I_ARM_Addr_1" SITE "AA20" ; : COMP "I_ARM_Addr_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (162): Error in LOCATE COMP "I_ARM_Addr_2" SITE "AA21" ; : COMP "I_ARM_Addr_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (163): Error in LOCATE COMP "I_ARM_Addr_3" SITE "AA22" ; : COMP "I_ARM_Addr_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (164): Error in LOCATE COMP "I_ARM_Addr_4" SITE "AB17" ; : COMP "I_ARM_Addr_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (165): Error in LOCATE COMP "I_ARM_Addr_5" SITE "AB18" ; : COMP "I_ARM_Addr_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (166): Error in LOCATE COMP "I_ARM_Addr_6" SITE "AB19" ; : COMP "I_ARM_Addr_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (167): Error in LOCATE COMP "I_ARM_Addr_7" SITE "AB20" ; : COMP "I_ARM_Addr_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (168): Error in LOCATE COMP "I_ARM_Addr_8" SITE "AB21" ; : COMP "I_ARM_Addr_8" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (169): Error in LOCATE COMP "I_ARM_Addr_9" SITE "Y17" ; : COMP "I_ARM_Addr_9" not found in design. Disabled this preference. WARNING - map: Port I_ARM_Addr_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (170): Error in IOBUF PORT "I_ARM_Addr_9" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_9" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (171): Error in IOBUF PORT "I_ARM_Addr_8" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_8" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (172): Error in IOBUF PORT "I_ARM_Addr_7" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_7" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (173): Error in IOBUF PORT "I_ARM_Addr_6" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_6" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_5 does not connect to any buffers
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (174): Error in IOBUF PORT "I_ARM_Addr_5" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_5" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (175): Error in IOBUF PORT "I_ARM_Addr_4" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_4" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (176): Error in IOBUF PORT "I_ARM_Addr_3" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_3" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (177): Error in IOBUF PORT "I_ARM_Addr_2" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_2" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_Addr_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (178): Error in IOBUF PORT "I_ARM_Addr_1" IO_TYPE=LVCMOS33 ; : Port "I_ARM_Addr_1" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port I_ARM_CS_n does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (179): Error in IOBUF PORT "I_ARM_CS_n" IO_TYPE=LVCMOS33 ; : Port "I_ARM_CS_n" does not exist in the design.. Disabled this preference . WARNING - map: Port I_ARM_OE_n does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (180): Error in IOBUF PORT "I_ARM_OE_n" IO_TYPE=LVCMOS33 ; : Port "I_ARM_OE_n" does not exist in the design.. Disabled this preference . WARNING - map: Port I_ARM_WE_n does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (181): Error in IOBUF PORT "I_ARM_WE_n" IO_TYPE=LVCMOS33 ; : Port "I_ARM_WE_n" does not exist in the design.. Disabled this preference . WARNING - map: Port O_ARM_WAIT_n does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (182): Error in IOBUF PORT "O_ARM_WAIT_n" IO_TYPE=LVCMOS33 ; : Port "O_ARM_WAIT_n" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port O_ARM_INT_n does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (183): Error in IOBUF PORT "O_ARM_INT_n" IO_TYPE=LVCMOS33 ; : Port "O_ARM_INT_n" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port B_ARM_Data_15 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (184): Error in IOBUF PORT "B_ARM_Data_15" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_15" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port B_ARM_Data_14 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (185): Error in IOBUF PORT "B_ARM_Data_14" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_14" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port B_ARM_Data_13 does not connect to any buffers
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (186): Error in IOBUF PORT "B_ARM_Data_13" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_13" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port B_ARM_Data_12 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (187): Error in IOBUF PORT "B_ARM_Data_12" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_12" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port B_ARM_Data_11 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (188): Error in IOBUF PORT "B_ARM_Data_11" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_11" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port B_ARM_Data_10 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (189): Error in IOBUF PORT "B_ARM_Data_10" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_10" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port B_ARM_Data_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (190): Error in IOBUF PORT "B_ARM_Data_9" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_9" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (191): Error in IOBUF PORT "B_ARM_Data_8" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_8" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (192): Error in IOBUF PORT "B_ARM_Data_7" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_7" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (193): Error in IOBUF PORT "B_ARM_Data_6" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_6" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (194): Error in IOBUF PORT "B_ARM_Data_5" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_5" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (195): Error in IOBUF PORT "B_ARM_Data_4" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_4" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (196): Error in IOBUF PORT "B_ARM_Data_3" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_3" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (197): Error in IOBUF PORT "B_ARM_Data_2" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_2" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_1 does not connect to any buffers
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (198): Error in IOBUF PORT "B_ARM_Data_1" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_1" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port B_ARM_Data_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (199): Error in IOBUF PORT "B_ARM_Data_0" IO_TYPE=LVCMOS33 ; : Port "B_ARM_Data_0" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port spi_clk does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (200): Error in IOBUF PORT "spi_clk" IO_TYPE=LVCMOS33 ; : Port "spi_clk" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_do does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (201): Error in IOBUF PORT "spi_do" IO_TYPE=LVCMOS33 ; : Port "spi_do" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (202): Error in IOBUF PORT "spi_en_3" IO_TYPE=LVCMOS33 ; : Port "spi_en_3" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (203): Error in IOBUF PORT "spi_en_2" IO_TYPE=LVCMOS33 ; : Port "spi_en_2" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (204): Error in IOBUF PORT "spi_en_1" IO_TYPE=LVCMOS33 ; : Port "spi_en_1" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (205): Error in IOBUF PORT "spi_en_0" IO_TYPE=LVCMOS33 ; : Port "spi_en_0" does not exist in the design.. Disabled this preference. WARNING - map: Port SEQ_DATA_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (206): Error in IOBUF PORT "SEQ_DATA_0" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_0" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (207): Error in IOBUF PORT "SEQ_DATA_1" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_1" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (208): Error in IOBUF PORT "SEQ_DATA_2" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_2" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (209): Error in IOBUF PORT "SEQ_DATA_3" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_3" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (210): Error in IOBUF PORT "SEQ_DATA_4" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_4" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l
pf (211): Error in IOBUF PORT "SEQ_DATA_5" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_5" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (212): Error in IOBUF PORT "SEQ_DATA_6" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_6" does not exist in the design.. Disabled this preference . WARNING - map: Port SEQ_DATA_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (213): Error in IOBUF PORT "SEQ_DATA_7" IO_TYPE=LVCMOS33 ; : Port "SEQ_DATA_7" does not exist in the design.. Disabled this preference . WARNING - map: Port iq_wrt2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (214): Error in IOBUF PORT "iq_wrt2" IO_TYPE=LVCMOS33 ; : Port "iq_wrt2" does not exist in the design.. Disabled this preference. WARNING - map: Port iq_sel2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (215): Error in IOBUF PORT "iq_sel2" IO_TYPE=LVCMOS33 ; : Port "iq_sel2" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data2_11 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (216): Error in IOBUF PORT "tx_data2_11" IO_TYPE=LVCMOS33 ; : Port "tx_data2_11" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port tx_data2_10 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (217): Error in IOBUF PORT "tx_data2_10" IO_TYPE=LVCMOS33 ; : Port "tx_data2_10" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port tx_data2_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (218): Error in IOBUF PORT "tx_data2_9" IO_TYPE=LVCMOS33 ; : Port "tx_data2_9" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (219): Error in IOBUF PORT "tx_data2_8" IO_TYPE=LVCMOS33 ; : Port "tx_data2_8" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (220): Error in IOBUF PORT "tx_data2_7" IO_TYPE=LVCMOS33 ; : Port "tx_data2_7" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (221): Error in IOBUF PORT "tx_data2_6" IO_TYPE=LVCMOS33 ; : Port "tx_data2_6" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (222): Error in IOBUF PORT "tx_data2_5" IO_TYPE=LVCMOS33 ; : Port "tx_data2_5" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (223): Error in IOBUF PORT "tx_data2_4" IO_TYPE=LVCMOS33 ; : Port "tx_data2_4" does not exist in the design.. Disabled this preference
. WARNING - map: Port tx_data2_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (224): Error in IOBUF PORT "tx_data2_3" IO_TYPE=LVCMOS33 ; : Port "tx_data2_3" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (225): Error in IOBUF PORT "tx_data2_2" IO_TYPE=LVCMOS33 ; : Port "tx_data2_2" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (226): Error in IOBUF PORT "tx_data2_1" IO_TYPE=LVCMOS33 ; : Port "tx_data2_1" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data2_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (227): Error in IOBUF PORT "tx_data2_0" IO_TYPE=LVCMOS33 ; : Port "tx_data2_0" does not exist in the design.. Disabled this preference . WARNING - map: Port txdac_reset2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (228): Error in IOBUF PORT "txdac_reset2" IO_TYPE=LVCMOS33 ; : Port "txdac_reset2" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port txc_sleep2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (229): Error in IOBUF PORT "txc_sleep2" IO_TYPE=LVCMOS33 ; : Port "txc_sleep2" does not exist in the design.. Disabled this preference . WARNING - map: Port SCL does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (230): Error in IOBUF PORT "SCL" IO_TYPE=LVCMOS33 ; : Port "SCL" does not exist in the design.. Disabled this preference. WARNING - map: Port SDA does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (231): Error in IOBUF PORT "SDA" IO_TYPE=LVCMOS33 ; : Port "SDA" does not exist in the design.. Disabled this preference. WARNING - map: Port timing_fs does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (232): Error in IOBUF PORT "timing_fs" IO_TYPE=LVCMOS33 ; : Port "timing_fs" does not exist in the design.. Disabled this preference. WARNING - map: Port TX2_MOD_EN_A does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (233): Error in IOBUF PORT "TX2_MOD_EN_A" IO_TYPE=LVCMOS33 ; : Port "TX2_MOD_EN_A" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port TX1_MOD_EN_A does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (234): Error in IOBUF PORT "TX1_MOD_EN_A" IO_TYPE=LVCMOS33 ; : Port "TX1_MOD_EN_A" does not exist in the design.. Disabled this preferen ce. WARNING - map: Port clk_out does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (235): Error in IOBUF PORT "clk_out" IO_TYPE=LVCMOS33 ; : Port "clk_out" does not exist in the design.. Disabled this preference. WARNING - map: Port TX_DAC_EN does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (236): Error in IOBUF PORT "TX_DAC_EN" IO_TYPE=LVCMOS33 ;
: Port "TX_DAC_EN" does not exist in the design.. Disabled this preference. WARNING - map: Port FPGA_TO_DSP_TS_INT does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (237): Error in IOBUF PORT "FPGA_TO_DSP_TS_INT" IO_TYPE=LVCMOS33 ; : Port "FPGA_TO_DSP_TS_INT" does not exist in the design.. Disabled this pr eference. WARNING - map: Port FPGA_TO_DSP_OBN_CLK does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (238): Error in IOBUF PORT "FPGA_TO_DSP_OBN_CLK" IO_TYPE=LVCMOS33 ; : Port "FPGA_TO_DSP_OBN_CLK" does not exist in the design.. Disabled this p reference. WARNING - map: Port adc_obn_int_13 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (239): Error in IOBUF PORT "adc_obn_int_13" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_13" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port adc_obn_int_12 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (240): Error in IOBUF PORT "adc_obn_int_12" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_12" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port adc_obn_int_11 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (241): Error in IOBUF PORT "adc_obn_int_11" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_11" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port adc_obn_int_10 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (242): Error in IOBUF PORT "adc_obn_int_10" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_10" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port adc_obn_int_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (243): Error in IOBUF PORT "adc_obn_int_9" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_9" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (244): Error in IOBUF PORT "adc_obn_int_8" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_8" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (245): Error in IOBUF PORT "adc_obn_int_7" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_7" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (246): Error in IOBUF PORT "adc_obn_int_6" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_6" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (247): Error in IOBUF PORT "adc_obn_int_5" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_5" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (248): Error in IOBUF PORT "adc_obn_int_4" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_4" does not exist in the design.. Disabled this prefere
nce. WARNING - map: Port adc_obn_int_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (249): Error in IOBUF PORT "adc_obn_int_3" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_3" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (250): Error in IOBUF PORT "adc_obn_int_2" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_2" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (251): Error in IOBUF PORT "adc_obn_int_1" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_1" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port adc_obn_int_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (252): Error in IOBUF PORT "adc_obn_int_0" IO_TYPE=LVCMOS33 ; : Port "adc_obn_int_0" does not exist in the design.. Disabled this prefere nce. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (253): Error in LOCATE COMP "timing_fs" SITE "H19" ; : COMP "timing_fs" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (254): Error in LOCATE COMP "TX1_MOD_EN_A" SITE "D15" ; : COMP "TX1_MOD_EN_A" not found in design. Disabled this preference. WARNING - map: Port ADC_SYNC does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (255): Error in IOBUF PORT "ADC_SYNC" IO_TYPE=LVCMOS33 ; : Port "ADC_SYNC" does not exist in the design.. Disabled this preference. WARNING - map: Port RX_ADC_EN does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (256): Error in IOBUF PORT "RX_ADC_EN" IO_TYPE=LVCMOS33 ; : Port "RX_ADC_EN" does not exist in the design.. Disabled this preference. WARNING - map: Port ADC_TS_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (257): Error in IOBUF PORT "ADC_TS_2" IO_TYPE=LVCMOS33 ; : Port "ADC_TS_2" does not exist in the design.. Disabled this preference. WARNING - map: Port ADC_TS_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (258): Error in IOBUF PORT "ADC_TS_1" IO_TYPE=LVCMOS33 ; : Port "ADC_TS_1" does not exist in the design.. Disabled this preference. WARNING - map: Port ADC_TS_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (259): Error in IOBUF PORT "ADC_TS_0" IO_TYPE=LVCMOS33 ; : Port "ADC_TS_0" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_dtack_rdy does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (260): Error in IOBUF PORT "rxb_dtack_rdy" IO_TYPE=LVCMOS33 ; : Port "rxb_dtack_rdy" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port ADC_MC_ADDR_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (261): Error in IOBUF PORT "ADC_MC_ADDR_2" IO_TYPE=LVCMOS33 ; : Port "ADC_MC_ADDR_2" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port ADC_MC_ADDR_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (262): Error in IOBUF PORT "ADC_MC_ADDR_1" IO_TYPE=LVCMOS33 ;
: Port "ADC_MC_ADDR_1" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port ADC_MC_ADDR_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (263): Error in IOBUF PORT "ADC_MC_ADDR_0" IO_TYPE=LVCMOS33 ; : Port "ADC_MC_ADDR_0" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port rxb_rdnwr does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (264): Error in IOBUF PORT "rxb_rdnwr" IO_TYPE=LVCMOS33 ; : Port "rxb_rdnwr" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_dsrd does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (265): Error in IOBUF PORT "rxb_dsrd" IO_TYPE=LVCMOS33 ; : Port "rxb_dsrd" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_cs does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (266): Error in IOBUF PORT "rxb_cs" IO_TYPE=LVCMOS33 ; : Port "rxb_cs" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (267): Error in IOBUF PORT "rxb_d_7" IO_TYPE=LVCMOS33 ; : Port "rxb_d_7" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (268): Error in IOBUF PORT "rxb_d_6" IO_TYPE=LVCMOS33 ; : Port "rxb_d_6" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (269): Error in IOBUF PORT "rxb_d_5" IO_TYPE=LVCMOS33 ; : Port "rxb_d_5" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (270): Error in IOBUF PORT "rxb_d_4" IO_TYPE=LVCMOS33 ; : Port "rxb_d_4" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (271): Error in IOBUF PORT "rxb_d_3" IO_TYPE=LVCMOS33 ; : Port "rxb_d_3" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (272): Error in IOBUF PORT "rxb_d_2" IO_TYPE=LVCMOS33 ; : Port "rxb_d_2" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (273): Error in IOBUF PORT "rxb_d_1" IO_TYPE=LVCMOS33 ; : Port "rxb_d_1" does not exist in the design.. Disabled this preference. WARNING - map: Port rxb_d_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (274): Error in IOBUF PORT "rxb_d_0" IO_TYPE=LVCMOS33 ; : Port "rxb_d_0" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (275): Error in LOCATE COMP "SCL" SITE "G15" ; : COMP "SCL" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (276): Error in LOCATE COMP "SDA" SITE "G14" ; : COMP "SDA" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (277): Error in LOCATE COMP "spi_clk" SITE "G9" ; : COMP "spi_clk" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (278): Error in LOCATE COMP "spi_do" SITE "F13" ; : COMP "spi_do" not found in design. Disabled this preference. WARNING - map: Port FPGA_LED does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (279): Error in IOBUF PORT "FPGA_LED" IO_TYPE=LVCMOS33 ; : Port "FPGA_LED" does not exist in the design.. Disabled this preference. WARNING - map: Port T2RXC1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (280): Error in IOBUF PORT "T2RXC1" IO_TYPE=LVCMOS33 ; : Port "T2RXC1" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (281): Error in LOCATE COMP "spi_en_1" SITE "E6" ; : COMP "spi_en_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (282): Error in LOCATE COMP "spi_en_0" SITE "D11" ; : COMP "spi_en_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (283): Error in LOCATE COMP "FPGA_TO_DSP_OBN_CLK" SITE "V3" ; : COMP "FPGA_TO_DSP_OBN_CLK" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (284): Error in LOCATE COMP "FPGA_TO_DSP_TS_INT" SITE "W2" ; : COMP "FPGA_TO_DSP_TS_INT" not found in design. Disabled this preference. WARNING - map: Port EN_DIS_DATA_PUMP does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (285): Error in IOBUF PORT "EN_DIS_DATA_PUMP" IO_TYPE=LVCMOS33 ; : Port "EN_DIS_DATA_PUMP" does not exist in the design.. Disabled this pref erence. WARNING - map: Port RESET_RADIO_IF does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (286): Error in IOBUF PORT "RESET_RADIO_IF" IO_TYPE=LVCMOS33 ; : Port "RESET_RADIO_IF" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port PA_MEAS does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (287): Error in IOBUF PORT "PA_MEAS" IO_TYPE=LVCMOS33 ; : Port "PA_MEAS" does not exist in the design.. Disabled this preference. WARNING - map: Port PERIO_ATTN_EN_DIS does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (288): Error in IOBUF PORT "PERIO_ATTN_EN_DIS" IO_TYPE=LVCMOS33 ; : Port "PERIO_ATTN_EN_DIS" does not exist in the design.. Disabled this pre ference. WARNING - map: Port PA_ON_OFF does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (289): Error in IOBUF PORT "PA_ON_OFF" IO_TYPE=LVCMOS33 ; : Port "PA_ON_OFF" does not exist in the design.. Disabled this preference. WARNING - map: Port EN_DIS_DATA_PUMP2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (290): Error in IOBUF PORT "EN_DIS_DATA_PUMP2" IO_TYPE=LVCMOS33 ; : Port "EN_DIS_DATA_PUMP2" does not exist in the design.. Disabled this pre ference. WARNING - map: Port RF_enable does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (291): Error in IOBUF PORT "RF_enable" IO_TYPE=LVCMOS33 ; : Port "RF_enable" does not exist in the design.. Disabled this preference. WARNING - map: Port RESET_RADIO_IF2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (292): Error in IOBUF PORT "RESET_RADIO_IF2" IO_TYPE=LVCMOS33 ; : Port "RESET_RADIO_IF2" does not exist in the design.. Disabled this prefe rence.
WARNING - map: Port PA_MEAS2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (293): Error in IOBUF PORT "PA_MEAS2" IO_TYPE=LVCMOS33 ; : Port "PA_MEAS2" does not exist in the design.. Disabled this preference. WARNING - map: Port PERIO_ATTN_EN_DIS2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (294): Error in IOBUF PORT "PERIO_ATTN_EN_DIS2" IO_TYPE=LVCMOS33 ; : Port "PERIO_ATTN_EN_DIS2" does not exist in the design.. Disabled this pr eference. WARNING - map: Port PA_ON_OFF2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (295): Error in IOBUF PORT "PA_ON_OFF2" IO_TYPE=LVCMOS33 ; : Port "PA_ON_OFF2" does not exist in the design.. Disabled this preference . WARNING - map: Port FRAME_SYNC1_13 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (296): Error in IOBUF PORT "FRAME_SYNC1_13" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_13" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port FRAME_SYNC1_12 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (297): Error in IOBUF PORT "FRAME_SYNC1_12" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_12" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port FRAME_SYNC1_11 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (298): Error in IOBUF PORT "FRAME_SYNC1_11" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_11" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port FRAME_SYNC1_10 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (299): Error in IOBUF PORT "FRAME_SYNC1_10" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_10" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port FRAME_SYNC1_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (300): Error in IOBUF PORT "FRAME_SYNC1_9" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_9" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (301): Error in IOBUF PORT "FRAME_SYNC1_8" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_8" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (302): Error in IOBUF PORT "FRAME_SYNC1_7" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_7" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (303): Error in IOBUF PORT "FRAME_SYNC1_6" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_6" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (304): Error in IOBUF PORT "FRAME_SYNC1_5" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_5" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_4 does not connect to any buffers
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (305): Error in IOBUF PORT "FRAME_SYNC1_4" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_4" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (306): Error in IOBUF PORT "FRAME_SYNC1_3" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_3" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (307): Error in IOBUF PORT "FRAME_SYNC1_2" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_2" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (308): Error in IOBUF PORT "FRAME_SYNC1_1" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_1" does not exist in the design.. Disabled this prefere nce. WARNING - map: Port FRAME_SYNC1_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (309): Error in IOBUF PORT "FRAME_SYNC1_0" IO_TYPE=LVCMOS33 ; : Port "FRAME_SYNC1_0" does not exist in the design.. Disabled this prefere nce. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (310): Error in LOCATE COMP "FRAME_SYNC1_0" SITE "C5" ; : COMP "FRAME_SYNC1_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (311): Error in LOCATE COMP "FRAME_SYNC1_1" SITE "C6" ; : COMP "FRAME_SYNC1_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (312): Error in LOCATE COMP "FRAME_SYNC1_2" SITE "C7" ; : COMP "FRAME_SYNC1_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (313): Error in LOCATE COMP "FRAME_SYNC1_3" SITE "C8" ; : COMP "FRAME_SYNC1_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (314): Error in LOCATE COMP "FRAME_SYNC1_4" SITE "C9" ; : COMP "FRAME_SYNC1_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (315): Error in LOCATE COMP "FRAME_SYNC1_5" SITE "C10" ; : COMP "FRAME_SYNC1_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (316): Error in LOCATE COMP "FRAME_SYNC1_6" SITE "D5" ; : COMP "FRAME_SYNC1_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (317): Error in LOCATE COMP "FRAME_SYNC1_7" SITE "D6" ; : COMP "FRAME_SYNC1_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (318): Error in LOCATE COMP "FRAME_SYNC1_8" SITE "D7" ; : COMP "FRAME_SYNC1_8" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (319): Error in LOCATE COMP "FRAME_SYNC1_9" SITE "D8" ; : COMP "FRAME_SYNC1_9" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (320): Error in LOCATE COMP "FRAME_SYNC1_10" SITE "D9" ; : COMP "FRAME_SYNC1_10" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (321): Error in LOCATE COMP "FRAME_SYNC1_11" SITE "D10" ; : COMP "FRAME_SYNC1_11" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (322): Error in LOCATE COMP "FRAME_SYNC1_12" SITE "D11" ; : COMP "FRAME_SYNC1_12" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (323): Error in LOCATE COMP "FRAME_SYNC1_13" SITE "E6" ; : COMP "FRAME_SYNC1_13" not found in design. Disabled this preference. WARNING - map: Port TX1_Lock does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (324): Error in IOBUF PORT "TX1_Lock" IO_TYPE=LVCMOS33 ; : Port "TX1_Lock" does not exist in the design.. Disabled this preference. WARNING - map: Port TX2_Lock does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (325): Error in IOBUF PORT "TX2_Lock" IO_TYPE=LVCMOS33 ; : Port "TX2_Lock" does not exist in the design.. Disabled this preference. WARNING - map: Port RX1_Lock does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (326): Error in IOBUF PORT "RX1_Lock" IO_TYPE=LVCMOS33 ; : Port "RX1_Lock" does not exist in the design.. Disabled this preference. WARNING - map: Port RX2_Lock does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (327): Error in IOBUF PORT "RX2_Lock" IO_TYPE=LVCMOS33 ; : Port "RX2_Lock" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_clk2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (328): Error in IOBUF PORT "spi_clk2" IO_TYPE=LVCMOS33 ; : Port "spi_clk2" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (329): Error in IOBUF PORT "spi_en2_3" IO_TYPE=LVCMOS33 ; : Port "spi_en2_3" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (330): Error in IOBUF PORT "spi_en2_2" IO_TYPE=LVCMOS33 ; : Port "spi_en2_2" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (331): Error in IOBUF PORT "spi_en2_1" IO_TYPE=LVCMOS33 ; : Port "spi_en2_1" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (332): Error in IOBUF PORT "spi_en2_0" IO_TYPE=LVCMOS33 ; : Port "spi_en2_0" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_do2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (333): Error in IOBUF PORT "spi_do2" IO_TYPE=LVCMOS33 ; : Port "spi_do2" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (334): Error in LOCATE COMP "ADC_SYNC" SITE "E13" ; : COMP "ADC_SYNC" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (335): Error in LOCATE COMP "RF_enable" SITE "D14" ; : COMP "RF_enable" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (336): Error in LOCATE COMP "rxb_d_0" SITE "A16" ; : COMP "rxb_d_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (337): Error in LOCATE COMP "rxb_d_1" SITE "A17" ; : COMP "rxb_d_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (338): Error in LOCATE COMP "rxb_d_2" SITE "A12" ;
: COMP "rxb_d_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (339): Error in LOCATE COMP "rxb_d_3" SITE "A13" ; : COMP "rxb_d_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (340): Error in LOCATE COMP "rxb_d_4" SITE "A14" ; : COMP "rxb_d_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (341): Error in LOCATE COMP "rxb_d_5" SITE "A15" ; : COMP "rxb_d_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (342): Error in LOCATE COMP "rxb_d_6" SITE "A18" ; : COMP "rxb_d_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (343): Error in LOCATE COMP "rxb_d_7" SITE "A19" ; : COMP "rxb_d_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (344): Error in LOCATE COMP "rxb_dtack_rdy" SITE "G14" ; : COMP "rxb_dtack_rdy" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (345): Error in LOCATE COMP "TX1_Lock" SITE "C16" ; : COMP "TX1_Lock" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (346): Error in LOCATE COMP "TX2_Lock" SITE "C17" ; : COMP "TX2_Lock" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (347): Error in LOCATE COMP "RX1_Lock" SITE "A6" ; : COMP "RX1_Lock" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (348): Error in LOCATE COMP "RX2_Lock" SITE "A7" ; : COMP "RX2_Lock" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (349): Error in LOCATE COMP "ADC_MC_ADDR_2" SITE "B18" ; : COMP "ADC_MC_ADDR_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (350): Error in LOCATE COMP "rxb_cs" SITE "N20" ; : COMP "rxb_cs" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (351): Error in LOCATE COMP "spi_clk2" SITE "D17" ; : COMP "spi_clk2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (352): Error in LOCATE COMP "spi_do2" SITE "E12" ; : COMP "spi_do2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (353): Error in LOCATE COMP "tx_data2_0" SITE "C5" ; : COMP "tx_data2_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (354): Error in LOCATE COMP "tx_data2_1" SITE "C6" ; : COMP "tx_data2_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (355): Error in LOCATE COMP "tx_data2_2" SITE "C7" ; : COMP "tx_data2_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (356): Error in LOCATE COMP "tx_data2_3" SITE "C8" ; : COMP "tx_data2_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (357): Error in LOCATE COMP "tx_data2_4" SITE "C9" ; : COMP "tx_data2_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (358): Error in LOCATE COMP "tx_data2_5" SITE "C10" ;
: COMP "tx_data2_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (359): Error in LOCATE COMP "tx_data2_6" SITE "D5" ; : COMP "tx_data2_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (360): Error in LOCATE COMP "tx_data2_7" SITE "D6" ; : COMP "tx_data2_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (361): Error in LOCATE COMP "tx_data2_8" SITE "D7" ; : COMP "tx_data2_8" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (362): Error in LOCATE COMP "tx_data2_9" SITE "D8" ; : COMP "tx_data2_9" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (363): Error in LOCATE COMP "tx_data2_10" SITE "D9" ; : COMP "tx_data2_10" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (364): Error in LOCATE COMP "tx_data2_11" SITE "D10" ; : COMP "tx_data2_11" not found in design. Disabled this preference. WARNING - map: Port DIR_CTRL does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (365): Error in IOBUF PORT "DIR_CTRL" IO_TYPE=LVCMOS33 ; : Port "DIR_CTRL" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_reset does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (366): Error in IOBUF PORT "tx_reset" IO_TYPE=LVCMOS33 ; : Port "tx_reset" does not exist in the design.. Disabled this preference. WARNING - map: Port iq_sel_a does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (367): Error in IOBUF PORT "iq_sel_a" IO_TYPE=LVCMOS33 ; : Port "iq_sel_a" does not exist in the design.. Disabled this preference. WARNING - map: Port iq_sel_b does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (368): Error in IOBUF PORT "iq_sel_b" IO_TYPE=LVCMOS33 ; : Port "iq_sel_b" does not exist in the design.. Disabled this preference. WARNING - map: Port dac_a_clk does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (369): Error in IOBUF PORT "dac_a_clk" IO_TYPE=LVCMOS33 ; : Port "dac_a_clk" does not exist in the design.. Disabled this preference. WARNING - map: Port dac_b_clk does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (370): Error in IOBUF PORT "dac_b_clk" IO_TYPE=LVCMOS33 ; : Port "dac_b_clk" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_11 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (371): Error in IOBUF PORT "tx_data_11" IO_TYPE=LVCMOS33 ; : Port "tx_data_11" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data_10 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (372): Error in IOBUF PORT "tx_data_10" IO_TYPE=LVCMOS33 ; : Port "tx_data_10" does not exist in the design.. Disabled this preference . WARNING - map: Port tx_data_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (373): Error in IOBUF PORT "tx_data_9" IO_TYPE=LVCMOS33 ; : Port "tx_data_9" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (374): Error in IOBUF PORT "tx_data_8" IO_TYPE=LVCMOS33 ;
: Port "tx_data_8" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (375): Error in IOBUF PORT "tx_data_7" IO_TYPE=LVCMOS33 ; : Port "tx_data_7" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (376): Error in IOBUF PORT "tx_data_6" IO_TYPE=LVCMOS33 ; : Port "tx_data_6" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (377): Error in IOBUF PORT "tx_data_5" IO_TYPE=LVCMOS33 ; : Port "tx_data_5" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (378): Error in IOBUF PORT "tx_data_4" IO_TYPE=LVCMOS33 ; : Port "tx_data_4" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (379): Error in IOBUF PORT "tx_data_3" IO_TYPE=LVCMOS33 ; : Port "tx_data_3" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (380): Error in IOBUF PORT "tx_data_2" IO_TYPE=LVCMOS33 ; : Port "tx_data_2" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (381): Error in IOBUF PORT "tx_data_1" IO_TYPE=LVCMOS33 ; : Port "tx_data_1" does not exist in the design.. Disabled this preference. WARNING - map: Port tx_data_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (382): Error in IOBUF PORT "tx_data_0" IO_TYPE=LVCMOS33 ; : Port "tx_data_0" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (383): Error in LOCATE COMP "tx_data_0" SITE "C5" ; : COMP "tx_data_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (384): Error in LOCATE COMP "tx_data_1" SITE "C6" ; : COMP "tx_data_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (385): Error in LOCATE COMP "tx_data_2" SITE "C7" ; : COMP "tx_data_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (386): Error in LOCATE COMP "tx_data_3" SITE "C8" ; : COMP "tx_data_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (387): Error in LOCATE COMP "tx_data_4" SITE "C9" ; : COMP "tx_data_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (388): Error in LOCATE COMP "tx_data_5" SITE "C10" ; : COMP "tx_data_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (389): Error in LOCATE COMP "tx_data_6" SITE "D5" ; : COMP "tx_data_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (390): Error in LOCATE COMP "tx_data_7" SITE "D6" ; : COMP "tx_data_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (391): Error in LOCATE COMP "tx_data_8" SITE "D7" ; : COMP "tx_data_8" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (392): Error in LOCATE COMP "tx_data_9" SITE "D8" ; : COMP "tx_data_9" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (393): Error in LOCATE COMP "tx_data_10" SITE "D9" ; : COMP "tx_data_10" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (394): Error in LOCATE COMP "tx_data_11" SITE "D10" ; : COMP "tx_data_11" not found in design. Disabled this preference. WARNING - map: Port rx_clk does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (400): Error in IOBUF PORT "rx_clk" IO_TYPE=LVCMOS33 ; : Port "rx_clk" does not exist in the design.. Disabled this preference. WARNING - map: Port rx_sync does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (401): Error in IOBUF PORT "rx_sync" IO_TYPE=LVCMOS33 ; : Port "rx_sync" does not exist in the design.. Disabled this preference. WARNING - map: Port rx_data0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (402): Error in IOBUF PORT "rx_data0" IO_TYPE=LVCMOS33 ; : Port "rx_data0" does not exist in the design.. Disabled this preference. WARNING - map: Port rx_data1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (403): Error in IOBUF PORT "rx_data1" IO_TYPE=LVCMOS33 ; : Port "rx_data1" does not exist in the design.. Disabled this preference. WARNING - map: Port dc_dc_sync does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (404): Error in IOBUF PORT "dc_dc_sync" IO_TYPE=LVCMOS33 ; : Port "dc_dc_sync" does not exist in the design.. Disabled this preference . WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (405): Error in LOCATE COMP "rx_sync" SITE "AB4" ; : COMP "rx_sync" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (406): Error in LOCATE COMP "rx_clk" SITE "AA6" ; : COMP "rx_clk" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (407): Error in LOCATE COMP "rx_data0" SITE "AB5" ; : COMP "rx_data0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (408): Error in LOCATE COMP "rx_data1" SITE "AB6" ; : COMP "rx_data1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (409): Error in LOCATE COMP "dc_dc_sync" SITE "P19" ; : COMP "dc_dc_sync" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (410): Error in LOCATE COMP "HPI_HRDY_L" SITE "AA4" ; : COMP "HPI_HRDY_L" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (411): Error in LOCATE COMP "HPI_HAS" SITE "AA1" ; : COMP "HPI_HAS" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (412): Error in LOCATE COMP "HPI_HCS_L" SITE "AB5" ; : COMP "HPI_HCS_L" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (413): Error in LOCATE COMP "HPI_HDS1_L" SITE "AB6" ; : COMP "HPI_HDS1_L" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (414): Error in LOCATE COMP "HPI_HDS2_L" SITE "T4" ; : COMP "HPI_HDS2_L" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (415): Error in LOCATE COMP "HPI_HHWIL" SITE "AA6" ; : COMP "HPI_HHWIL" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (416): Error in LOCATE COMP "HPI_R_WL" SITE "AA5" ; : COMP "HPI_R_WL" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (417): Error in LOCATE COMP "HPI_HCNTL_1" SITE "AB4" ; : COMP "HPI_HCNTL_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (418): Error in LOCATE COMP "HPI_HCNTL_0" SITE "AB3" ; : COMP "HPI_HCNTL_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (419): Error in LOCATE COMP "HPI_DATA_15" SITE "P4" ; : COMP "HPI_DATA_15" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (420): Error in LOCATE COMP "HPI_DATA_14" SITE "P3" ; : COMP "HPI_DATA_14" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (421): Error in LOCATE COMP "HPI_DATA_13" SITE "P1" ; : COMP "HPI_DATA_13" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (422): Error in LOCATE COMP "HPI_DATA_12" SITE "N6" ; : COMP "HPI_DATA_12" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (423): Error in LOCATE COMP "HPI_DATA_11" SITE "N5" ; : COMP "HPI_DATA_11" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (424): Error in LOCATE COMP "HPI_DATA_10" SITE "N4" ; : COMP "HPI_DATA_10" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (425): Error in LOCATE COMP "HPI_DATA_9" SITE "N3" ; : COMP "HPI_DATA_9" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (426): Error in LOCATE COMP "HPI_DATA_8" SITE "N2" ; : COMP "HPI_DATA_8" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (427): Error in LOCATE COMP "HPI_DATA_7" SITE "N1" ; : COMP "HPI_DATA_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (428): Error in LOCATE COMP "HPI_DATA_6" SITE "M5" ; : COMP "HPI_DATA_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (429): Error in LOCATE COMP "HPI_DATA_5" SITE "M4" ; : COMP "HPI_DATA_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (430): Error in LOCATE COMP "HPI_DATA_4" SITE "M2" ; : COMP "HPI_DATA_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (431): Error in LOCATE COMP "HPI_DATA_3" SITE "M1" ; : COMP "HPI_DATA_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (432): Error in LOCATE COMP "HPI_DATA_2" SITE "L4" ; : COMP "HPI_DATA_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (433): Error in LOCATE COMP "HPI_DATA_1" SITE "L3" ; : COMP "HPI_DATA_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (434): Error in LOCATE COMP "HPI_DATA_0" SITE "L2" ; : COMP "HPI_DATA_0" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (435): Error in LOCATE COMP "BBIN_CLK" SITE "K4" ; : COMP "BBIN_CLK" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (436): Error in LOCATE COMP "BBIN_DATA_9" SITE "D2" ; : COMP "BBIN_DATA_9" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (437): Error in LOCATE COMP "BBIN_DATA_8" SITE "J2" ; : COMP "BBIN_DATA_8" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (438): Error in LOCATE COMP "BBIN_DATA_7" SITE "M18" ; : COMP "BBIN_DATA_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (439): Error in LOCATE COMP "BBIN_DATA_6" SITE "L18" ; : COMP "BBIN_DATA_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (440): Error in LOCATE COMP "BBIN_DATA_5" SITE "J22" ; : COMP "BBIN_DATA_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (441): Error in LOCATE COMP "BBIN_DATA_4" SITE "H21" ; : COMP "BBIN_DATA_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (442): Error in LOCATE COMP "BBIN_DATA_3" SITE "E3" ; : COMP "BBIN_DATA_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (443): Error in LOCATE COMP "BBIN_DATA_2" SITE "H5" ; : COMP "BBIN_DATA_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (444): Error in LOCATE COMP "BBIN_DATA_1" SITE "E22" ; : COMP "BBIN_DATA_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (445): Error in LOCATE COMP "BBIN_DATA_0" SITE "K1" ; : COMP "BBIN_DATA_0" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (446): Error in LOCATE COMP "BB_SYNC" SITE "J17" ; : COMP "BB_SYNC" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (447): Error in LOCATE COMP "BB_CLK" SITE "K17" ; : COMP "BB_CLK" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (448): Error in LOCATE COMP "BB_DATA_7" SITE "M21" ; : COMP "BB_DATA_7" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (449): Error in LOCATE COMP "BB_DATA_6" SITE "K21" ; : COMP "BB_DATA_6" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (450): Error in LOCATE COMP "BB_DATA_5" SITE "G21" ; : COMP "BB_DATA_5" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (451): Error in LOCATE COMP "BB_DATA_4" SITE "K20" ; : COMP "BB_DATA_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (452): Error in LOCATE COMP "BB_DATA_3" SITE "B1" ; : COMP "BB_DATA_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (453): Error in LOCATE COMP "BB_DATA_2" SITE "B2" ; : COMP "BB_DATA_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (454): Error in LOCATE COMP "BB_DATA_1" SITE "H2" ; : COMP "BB_DATA_1" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (455): Error in LOCATE COMP "BB_DATA_0" SITE "H4" ; : COMP "BB_DATA_0" not found in design. Disabled this preference. WARNING - map: Port HPI_HRDY_L does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (456): Error in IOBUF PORT "HPI_HRDY_L" IO_TYPE=LVCMOS33 ; : Port "HPI_HRDY_L" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_HAS does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (457): Error in IOBUF PORT "HPI_HAS" IO_TYPE=LVCMOS33 ; : Port "HPI_HAS" does not exist in the design.. Disabled this preference. WARNING - map: Port HPI_HCS_L does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (458): Error in IOBUF PORT "HPI_HCS_L" IO_TYPE=LVCMOS33 ; : Port "HPI_HCS_L" does not exist in the design.. Disabled this preference. WARNING - map: Port HPI_HDS1_L does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (459): Error in IOBUF PORT "HPI_HDS1_L" IO_TYPE=LVCMOS33 ; : Port "HPI_HDS1_L" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_HDS2_L does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (460): Error in IOBUF PORT "HPI_HDS2_L" IO_TYPE=LVCMOS33 ; : Port "HPI_HDS2_L" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_HHWIL does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (461): Error in IOBUF PORT "HPI_HHWIL" IO_TYPE=LVCMOS33 ; : Port "HPI_HHWIL" does not exist in the design.. Disabled this preference. WARNING - map: Port HPI_R_WL does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (462): Error in IOBUF PORT "HPI_R_WL" IO_TYPE=LVCMOS33 ; : Port "HPI_R_WL" does not exist in the design.. Disabled this preference. WARNING - map: Port HPI_HCNTL_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (463): Error in IOBUF PORT "HPI_HCNTL_1" IO_TYPE=LVCMOS33 ; : Port "HPI_HCNTL_1" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_HCNTL_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (464): Error in IOBUF PORT "HPI_HCNTL_0" IO_TYPE=LVCMOS33 ; : Port "HPI_HCNTL_0" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port spi_en2_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (465): Error in IOBUF PORT "spi_en2_7" IO_TYPE=LVCMOS33 ; : Port "spi_en2_7" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (466): Error in IOBUF PORT "spi_en2_6" IO_TYPE=LVCMOS33 ; : Port "spi_en2_6" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (467): Error in IOBUF PORT "spi_en2_5" IO_TYPE=LVCMOS33 ; : Port "spi_en2_5" does not exist in the design.. Disabled this preference. WARNING - map: Port spi_en2_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (468): Error in IOBUF PORT "spi_en2_4" IO_TYPE=LVCMOS33 ; : Port "spi_en2_4" does not exist in the design.. Disabled this preference.
WARNING - map: Port HPI_DATA_15 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (469): Error in IOBUF PORT "HPI_DATA_15" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_15" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_DATA_14 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (470): Error in IOBUF PORT "HPI_DATA_14" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_14" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_DATA_13 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (471): Error in IOBUF PORT "HPI_DATA_13" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_13" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_DATA_12 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (472): Error in IOBUF PORT "HPI_DATA_12" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_12" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_DATA_11 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (473): Error in IOBUF PORT "HPI_DATA_11" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_11" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_DATA_10 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (474): Error in IOBUF PORT "HPI_DATA_10" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_10" does not exist in the design.. Disabled this preferenc e. WARNING - map: Port HPI_DATA_9 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (475): Error in IOBUF PORT "HPI_DATA_9" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_9" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_8 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (476): Error in IOBUF PORT "HPI_DATA_8" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_8" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_7 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (477): Error in IOBUF PORT "HPI_DATA_7" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_7" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_6 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (478): Error in IOBUF PORT "HPI_DATA_6" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_6" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_5 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (479): Error in IOBUF PORT "HPI_DATA_5" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_5" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_4 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (480): Error in IOBUF PORT "HPI_DATA_4" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_4" does not exist in the design.. Disabled this preference .
WARNING - map: Port HPI_DATA_3 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (481): Error in IOBUF PORT "HPI_DATA_3" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_3" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_2 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (482): Error in IOBUF PORT "HPI_DATA_2" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_2" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_1 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (483): Error in IOBUF PORT "HPI_DATA_1" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_1" does not exist in the design.. Disabled this preference . WARNING - map: Port HPI_DATA_0 does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (484): Error in IOBUF PORT "HPI_DATA_0" IO_TYPE=LVCMOS33 ; : Port "HPI_DATA_0" does not exist in the design.. Disabled this preference . WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (487): Error in LOCATE COMP "GC_SYNC_A" SITE "E5" ; : COMP "GC_SYNC_A" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (488): Error in LOCATE COMP "GC_SYNC_B" SITE "G4" ; : COMP "GC_SYNC_B" not found in design. Disabled this preference. WARNING - map: Port GC_SYNC_A does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (489): Error in IOBUF PORT "GC_SYNC_A" IO_TYPE=LVDS25 ; : Port "GC_SYNC_A" does not exist in the design.. Disabled this preference. WARNING - map: Port GC_SYNC_B does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (490): Error in IOBUF PORT "GC_SYNC_B" IO_TYPE=LVDS25 ; : Port "GC_SYNC_B" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (491): Error in LOCATE COMP "EMIFENA" SITE "R21" ; : COMP "EMIFENA" not found in design. Disabled this preference. WARNING - map: Port EMIFENA does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (492): Error in IOBUF PORT "EMIFENA" IO_TYPE=LVCMOS33 ; : Port "EMIFENA" does not exist in the design.. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (493): Error in LOCATE COMP "DSP6748_SYNC_A" SITE "B15" ; : COMP "DSP6748_SYNC_A" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (494): Error in LOCATE COMP "DSP6748_SYNC_B" SITE "B16" ; : COMP "DSP6748_SYNC_B" not found in design. Disabled this preference. WARNING - map: Port DSP6748_SYNC_A does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (495): Error in IOBUF PORT "DSP6748_SYNC_A" IO_TYPE=LVCMOS33 ; : Port "DSP6748_SYNC_A" does not exist in the design.. Disabled this prefer ence. WARNING - map: Port DSP6748_SYNC_B does not connect to any buffers WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (496): Error in IOBUF PORT "DSP6748_SYNC_B" IO_TYPE=LVCMOS33 ; : Port "DSP6748_SYNC_B" does not exist in the design.. Disabled this prefer ence. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (497): Error in LOCATE COMP "spi_en2_0" SITE "F7" ; : COMP "spi_en2_0" not found in design. Disabled this preference.
WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (498): Error in LOCATE COMP "spi_en2_1" SITE "F8" ; : COMP "spi_en2_1" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (499): Error in LOCATE COMP "spi_en2_2" SITE "F9" ; : COMP "spi_en2_2" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (500): Error in LOCATE COMP "spi_en2_3" SITE "F10" ; : COMP "spi_en2_3" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (501): Error in LOCATE COMP "spi_en2_4" SITE "F11" ; : COMP "spi_en2_4" not found in design. Disabled this preference. WARNING - map: D:/MC-DMB-FPGA/MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.l pf (502): Error in LOCATE COMP "spi_en2_5" SITE "F12" ; : COMP "spi_en2_5" not found in design. Disabled this preference. WARNING - map: Preference parsing results: 386 semantic errors detected WARNING - map: There are errors in the preference file, "D:/MC-DMB-FPGA/MC_FPGA_ 17_10_2011_0345PM/fpga_first_release/top.lpf". Loading device for application map from file 'ec5a97x146.nph' in environment: C: /lscc/diamond/1.1/ispfpga. Package Status: Final Version 1.2 Running general design DRC... Removing unused logic... Optimizing... 23 CCU2 constant inputs absorbed. WARNING - map: Using local reset signal 'fifo2_clear' to infer global GSR net. WARNING - map: IO buffer missing for top level port DAC_TS...logic will be disca rded. WARNING - map: IO buffer missing for top level port OBN[13:0](13)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](12)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](11)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](10)...logic will b e discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](9)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](8)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](7)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](6)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](5)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](4)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](3)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](2)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](1)...logic will be discarded. WARNING - map: IO buffer missing for top level port OBN[13:0](0)...logic will be discarded.
Design Summary:
Number of registers: 370 PFU registers: 302 PIO registers: 68 Number of SLICEs: 411 out of 33264 (1%) SLICEs(logic/ROM): 411 out of 26460 (2%) SLICEs(logic/ROM/RAM): 0 out of 6804 (0%) As RAM: 0 out of 6804 (0%) As Logic/ROM: 0 out of 6804 (0%) Number of logic LUT4s: 412 Number of distributed RAM: 0 (0 LUT4s) Number of ripple logic: 85 (170 LUT4s) Number of shift registers: 0 Total number of LUT4s: 582 Number of PIO sites used: 85 out of 295 (29%) Number of PIO FIXEDDELAY: 0 Number of PCS (SerDes): 0 out of 1 (0%) with bonded PIO sites Number of DQSDLLs: 0 out of 2 (0%) Number of PLLs: 0 out of 10 (0%) Number of DLLs: 0 out of 2 (0%) Number of block RAMs: 4 out of 240 (2%) Number of CLKDIVs: 0 out of 2 (0%) Number of GSRs: 1 out of 1 (100%) JTAG used : No Readback used : No Oscillator used : No Startup used : No Notes:1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distribu ted RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and rip ple logic. Number Of Mapped DSP Components: -------------------------------MULT18X18C 0 MULT9X9C 0 ALU54A 0 ALU24A 0 -------------------------------Number of Used DSP MULT Sites: 0 out of 256 (0 %) Number of Used DSP ALU Sites: 0 out of 128 (0 %) Number of clocks: 3 Net DAC_SCLK_inferred_clockgen: 76 loads, 76 rising, 0 falling (Driver: PIO CLOCK ) Net DAC_SCLK_inferred_clock: 49 loads, 49 rising, 0 falling (Driver: DAC_SC LK1 ) Net lnk_clk_c: 120 loads, 120 rising, 0 falling (Driver: PIO lnk_clk ) Number of Clock Enables: 21 Net DAC_SCLK1or_0: 4 loads, 4 LSLICEs Net un1_DAC_SDI1_0_sqmuxa_1_0_i_s_0_a2_RNI28NE: 3 loads, 3 LSLICEs Net un1_DAC_SDI1_0_sqmuxa_1_0_i_s_0: 1 loads, 0 LSLICEs Net un1_rd_adc_data_0_sqmuxa_0_a3_0_a3_0_a2: 7 loads, 7 LSLICEs Net rd_adc_data_0io_RNO_12: 1 loads, 0 LSLICEs Net DAC_SCLK1mux_RNIJQUA: 35 loads, 35 LSLICEs Net N_52_i: 64 loads, 0 LSLICEs Net un2_wr_count1_0_a2_RNIOR5G: 2 loads, 1 LSLICEs Net un1_rd_adc_data_0_sqmuxa_0_a3_0_a3_0_a2_RNIGSAI: 3 loads, 3 LSLICEs Net rx_fifo2/wren_i: 17 loads, 15 LSLICEs Net rx_fifo2/rden_i: 11 loads, 9 LSLICEs Net rx_fifo1/wren_i: 17 loads, 15 LSLICEs
Net rx_fifo1/rden_i: 11 loads, 9 LSLICEs Net rd_adc_data_RNO_4: 1 loads, 1 LSLICEs Net rd_adc_data_RNO_0: 1 loads, 1 LSLICEs Net fifo_rd_state_RNI13321_1: 1 loads, 1 LSLICEs Net RESET_c: 1 loads, 1 LSLICEs Net N_402_i: 1 loads, 1 LSLICEs Net un1_fifo_rd0_1_sqmuxa_2_0_i_s: 1 loads, 0 LSLICEs Net N_66: 9 loads, 9 LSLICEs Net rd_adc_datace_8: 1 loads, 1 LSLICEs Number of local set/reset loads for net fifo2_clear merged into GSR: 162 Number of LSRs: 3 Net fifo2_clear: 4 loads, 0 LSLICEs Net RESET_pad_RNIS2RA: 12 loads, 11 LSLICEs Net RESET_c: 69 loads, 66 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net RESET_c: 82 loads Net fifo_rd_state_0: 73 loads Net fifo_data_wr_e: 65 loads Net fifo_data_wr_e_1: 65 loads Net N_52_i: 64 loads Net DAC_SCLK1mux_RNIJQUA: 37 loads Net N_389: 24 loads Net rx_fifo1/wren_i: 23 loads Net rx_fifo2/wren_i: 23 loads Net rd_cmd: 19 loads Number of warnings: 17 Number of errors: 0 Total CPU Time: 4 secs Total REAL Time: 7 secs Peak Memory Usage: 244 MB WARNING - map: There are semantic errors in the preference file, "D:/MC-DMB-FPGA /MC_FPGA_17_10_2011_0345PM/fpga_first_release/top.prf". Dumping design to file top_top_map.ncd. Done: completed successfully ************************************************************ ** Place & Route Design ** ************************************************************ mpartrce -p "top_top.p2t" -f "top_top.p3t" -tf "top_top.pt" "top_top_map.ncd" "t op_top.ncd" ---- MParTrce Tool ---Removing old design directory at request of -rem command line option to this pro gram. Running par. Please wait . . . Lattice Place and Route Report for Design "top_top_map.ncd" Thu Dec 01 13:47:02 2011 PAR: Place And Route Diamond_1.1_Production (517). Command line: C:/lscc/diamond/1.1/ispfpga\bin\nt\par -f top_top.p2t top_top_map. ncd top_top.dir top_top.prf Preference file: top_top.prf.
Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file top_top_map.ncd. Design name: ADC_SPI_RX NCD version: 3.2 Vendor: LATTICE Device: LFE3-70EA Package: FPBGA484 Speed: 7 Loading device for application par from file 'ec5a97x146.nph' in environment: C: /lscc/diamond/1.1/ispfpga. Package Status: Final Version 1.2 Speed Hardware Data Status: Final Version 27.22 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) IOLOGIC SLICE GSR EBR 85/524 85/295 68/520 411/33264 1/1 4/240 16% used 28% bonded 13% used 1% used 100% used 1% used
Number of Signals: 1058 Number of Connections: 2713 Pin Constraint Summary: 1 out of 85 pins locked (1% locked). The following 3 signals are selected to use the primary clock routing resources: lnk_clk_c (driver: lnk_clk, clk load #: 124) DAC_SCLK_inferred_clockgen (driver: CLOCK, clk load #: 76) DAC_SCLK_inferred_clock (driver: SLICE_86, clk load #: 53) The following 3 signals are selected to use the secondary clock routing resource s: RESET_c (driver: RESET, clk load #: 0, sr load #: 69, ce load #: 1) N_52_i (driver: SLICE_248, clk load #: 0, sr load #: 0, ce load #: 64) DAC_SCLK1mux_RNIJQUA (driver: SLICE_160, clk load #: 0, sr load #: 0, ce loa d #: 35) Signal fifo2_clear is selected as Global Set/Reset. .................... ........................................................................ ........................................................................ ........................................................ WARNING - par: Due to difficulties in finding a legal I/O placement, it may be i mpossible to assign optimal locations for the PIO drivers of clock and/or PLL/DL L inputs in this design. Please check the PAR and PAD reports, see if the place ment fulfill the requirements; and use LOCATE preference to lock clock and/or PL L/DLL input pins if necessary. ....................
........................................................................ ........................................................................ ........................................................ .................... ........................................................................ ........................................................................ ........................................................ .................... ........................................................................ ........................................................................ ........................................................ .................... ........................................................................ ........................................................................ ........................................................ ERROR - par: I/O initial placement is unsuccessful. Please check the I/O placem ent constraints / user preferences (such as pin locking) carefully. ***** I/O Placement and Bank Assignment ***** *** Overview of I/O Grouping *** +---+------------+------+-----+-----------+-------+---------+------------+ | # | Vccio | Vref | Vtt | Dir/IOL | # IOs | # Sites | Attributes | +---+------------+------+-----+-----------+-------+---------+------------+ | 0 | 2.5V | OFF | OFF | OUT | 10 | 10 | | | 1 | 3.3V | OFF | OFF | OUT | 2 | 2 | | | 2 | 2.5V 3.3V | OFF | OFF | IN | 5 | 5 | | | 3 | 2.5V | OFF | OFF | OUT/XSIOL | 65 | 65 | | | 4 | 3.3V | OFF | OFF | OUT/XSIOL | 1 | 1 | | | 5 | 2.5V 3.3V | OFF | OFF | IN/XSIOL | 1 | 1 | | +---+------------+------+-----+-----------+-------+---------+------------+ IOs *LOCKED* - # of IOs: 1, required # of sites: 1 *** Primary/Secondary Clock Overview (PIO drivers only) *** Primary clock signal DAC_SCLK_inferred_clockgen (driver CLOCK, Vccio: 2.5V, Vref : OFF) uses PIO pad D5 (PT4B) in bank 0. Primary clock signal lnk_clk_c (driver lnk_clk, Vccio: 2.5V, Vref: OFF) uses PIO pad B6 (PT5B) in bank 0. Secondary clock signal RESET_c (driver RESET, Vccio: 2.5V, Vref: OFF) uses PIO p ad B3 (PT8A) in bank 0. *** I/O Bank Assignment Overview *** +------+-------+----------+-----+----------+------------+------------+----------+ | Bank | Vccio | Vref 1/2 | Vtt | Capacity | Input_Term | Diff_Drive | True_LVDS | +------+-------+----------+-----+----------+------------+------------+----------+ | 0 | 3.3V | OFF/OFF | OFF | 42 | OFF | OFF | NONE | | 1 | 3.3V | OFF/OFF | OFF | 36 | OFF | OFF | NONE | | 2 | 2.5V | OFF/OFF | OFF | 28 | OFF | OFF | NONE | | 3 | 3.3V | OFF/OFF | OFF | 58 | OFF | OFF | NONE | | 6 | 3.3V | OFF/OFF | OFF | 67 | OFF | OFF | NONE
| | 7 | 2.5V | OFF/OFF | OFF | 40 | OFF | OFF | NONE | | 8 | 3.3V | OFF/OFF | OFF | 24 | OFF | OFF | NONE | +------+-------+----------+-----+----------+------------+------------+----------+ *** Detailed Bank Assignment *** --- I/Os placed in Bank 0 --Bank Vccio=3.3V, Vref1/2=OFF/OFF, Vtt=OFF +-----+-------+--------------+-----+------+------+-------+------------------+---------+------------+------+-----+-----------+-------+-----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vccio | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +-----+-------+--------------+-----+------+------+-------+------------------+---------+------------+------+-----+-----------+-------+-----+------+-----------+ | C5 | PT2A | BIDI/SIOL | T | | | | DAC_SCLK | LV CMOS33 | 3.3V | OFF | OFF | OUT | ON | OFF | | | | B4 | PT2B | BIDI/SIOL | C | | | | DAC_CS_L | LV CMOS33 | 3.3V | OFF | OFF | OUT | ON | OFF | | | | E6 | PT4A | BIDI/SIOL | T | | 1 | | DAC_SDI | LV CMOS33 | 3.3V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | D5 | PT4B | BIDI/SIOL | C | | 2 | | CLOCK | LV CMOS25 | 2.5V 3.3V | OFF | OFF | IN | ON | OFF | | | | C6 | PT5A | BIDI/SIOL | T | | | | start_new_packet | LV CMOS25 | 2.5V 3.3V | OFF | OFF | IN | ON | OFF | | | | B6 | PT5B | BIDI/SIOL | C | | | | lnk_clk | LV CMOS25 | 2.5V 3.3V | OFF | OFF | IN | ON | OFF | | | | F8 | PT7A | BIDI/SDQSIOL | T | | | | ADC_GNT | LV CMOS25 | 2.5V 3.3V | OFF | OFF | IN | ON | OFF | | | | G9 | PT7B | BIDI/XSIOL | C | | | | SPI_EN | LV CMOS25 | 2.5V 3.3V | OFF | OFF | IN/XSIOL | ON | OFF | | | | B3 | PT8A | BIDI/SIOL | T | | | | RESET | LV CMOS25 | 2.5V 3.3V | OFF | OFF | IN | ON | OFF | | | | A2 | PT8B | BIDI/SIOL | C | | | | | | | | | | | | | | | D6 | PT10A | BIDI/SIOL | T | | | | | | | | | | | | | | | D7 | PT10B | BIDI/SIOL | C | | | | | | | | | | | | | | | A3 | PT11A | BIDI/SIOL | T | | | | | | | | | | | | | | | A4 | PT11B | BIDI/SIOL | C | | | | | | | | | | | | | | | F7 | PT13A | BIDI/SIOL | T | | | | | | | | | | | | | | | G8 | PT13B | BIDI/SIOL | C | | | | | | | | | | | | | | | A5 | PT14A | BIDI/SIOL | T | | | | | | | | | | | | | | | A6 | PT14B | BIDI/SIOL | C | | | | | | | | | | | | | | | C8 | PT56A | BIDI/SIOL | T | | | | | | | | | | | | | | | C7 | PT56B | BIDI/SIOL | C | | | | | | | | | | | | | | | F9 | PT58A | BIDI/SIOL | T | | | | | | | | | | | | | |
| E9 | PT58B | BIDI/SIOL | C | | | | | | | | | | | | | | | C9 | PT59A | BIDI/SIOL | T | | | | | | | | | | | | | | | C10 | PT59B | BIDI/SIOL | C | | | | | | | | | | | | | | | D9 | PT61A | BIDI/SDQSIOL | T | | | | | | | | | | | | | | | D10 | PT61B | BIDI/XSIOL | C | | | | | | | | | | | | | | | B7 | PT62A | BIDI/SIOL | T | | | | | | | | | | | | | | | A7 | PT62B | BIDI/SIOL | C | | | | | | | | | | | | | | | D8 | PT64A | BIDI/SIOL | T | | | | | | | | | | | | | | | E7 | PT64B | BIDI/SIOL | C | | | | | | | | | | | | | | | B8 | PT65A | BIDI/SIOL | T | | | | | | | | | | | | | | | A8 | PT65B | BIDI/SIOL | C | | | | | | | | | | | | | | | F10 | PT67A | BIDI/SIOL | T | | | | | | | | | | | | | | | E10 | PT67B | BIDI/SIOL | C | | | | | | | | | | | | | | | A9 | PT68A | BIDI/SIOL | T | | | | | | | | | | | | | | | B10 | PT68B | BIDI/SIOL | C | | | | | | | | | | | | | | | E11 | PT70A | BIDI/SDQSIOL | T | | | | | | | | | | | | | | | D11 | PT70B | BIDI/XSIOL | C | | | | | | | | | | | | | | | A10 | PT71A | BIDI/SIOL | T | | | | | | | | | | | | | | | A11 | PT71B | BIDI/SIOL | C | | | | | | | | | | | | | | | F11 | PT73A | BIDI/SIOL | T | | | | | | | | | | | | | | | F12 | PT73B | BIDI/SIOL | C | | | | | | | | | | | | | | +-----+-------+--------------+-----+------+------+-------+------------------+---------+------------+------+-----+-----------+-------+-----+------+-----------+ *** Bank 0 - # of PIO sites: 42, occupied: 9; # of Vref inputs used: 0 --- I/Os placed in Bank 1 --Bank Vccio=3.3V, Vref1/2=OFF/OFF, Vtt=OFF +-----+--------+--------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vcci o | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +-----+--------+--------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ | B11 | PT74A | BIDI/SIOL | T | | | | | | | | | | | | | | | B12 | PT74B | BIDI/SIOL | C | | | | | |
| | C12 | | D12 | | A12 | | A13 | | E12 | | E13 | | C13 | | C14 | | D13 | | D14 | | A14 | | B14 | | F13 | | F14 | | A15 | | B15 | | E16 | | E15 | | C15 | | D15 | | G15 | | G14 | | A16 | | B16 | | F15 | | F16 | | A17 | | B18 | | C17 | | C16
| | PT76A | | PT76B | | PT77A | | PT77B | | PT79A | | PT79B | | PT80A | | PT80B | | PT82A | | PT82B | | PT83A | | PT83B | | PT85A | | PT85B | | PT86A | | PT86B | | PT88A | | PT88B | | PT89A | | PT89B | | PT91A | | PT91B | | PT128A | | PT128B | | PT130A | | PT130B | | PT131A | | PT131B | | PT133A | | PT133B
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| BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SDQSIOL | BIDI/XSIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SDQSIOL | BIDI/XSIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SIOL | BIDI/SDQSIOL | BIDI/XSIOL
| | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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| | | | | | | | | A18 | PT134A | BIDI/SIOL | T | | | | | | | | | | | | | | | A19 | PT134B | BIDI/SIOL | C | | | | | | | | | | | | | | | D16 | PT136A | BIDI/SIOL | T | | 1 | | | | | | | | | | | | | D17 | PT136B | BIDI/SIOL | C | | 2 | | | | | | | | | | | | +-----+--------+--------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ *** Bank 1 - # of PIO sites: 36, occupied: 0; # of Vref inputs used: 0 --- I/Os placed in Bank 2 --Bank Vccio=2.5V, Vref1/2=OFF/OFF, Vtt=OFF +-----+---------+-------------+-----+------+------+-------+--------------------+ ----------+-------+------+-----+-----------+-------+-----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vccio | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +-----+---------+-------------+-----+------+------+-------+--------------------+ ----------+-------+------+-----+-----------+-------+-----+------+-----------+ | N17 | PR43E_D | IN/IOL | C | | | | | | | | | | | | | | | M18 | PR43E_C | IN/IOL | T | | | | | | | | | | | | | | | N22 | PR43E_B | IN/IOL | C | | | | | | | | | | | | | | | P21 | PR43E_A | IN/IOL | T | | | | | | | | | | | | | | | M20 | PR43B | BIDI/IOL | L- | | | | RD_DATA_50 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | M21 | PR43A | BIDI/IOL | L+ | | | | RD_DATA_51 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | M22 | PR41B | BIDI/IOL | C | | | | RD_DATA_52 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | L22 | PR41A | BIDI/IOL | T | | | | RD_DATA_53 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | L19 | PR40B | BIDI/XSIOL | C | | | | RD_DATA_54 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | L18 | PR40A | BIDI/DQSIOL | T | | | | RD_DATA_55 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | L21 | PR38B | BIDI/IOL | L- | | | | RD_DATA_56 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K21 | PR38A | BIDI/IOL | L+ | | | | RD_DATA_57 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K19 | PR37B | BIDI/IOL | L- | | | | RD_DATA_58 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K20 | PR37A | BIDI/IOL | L+ | | | | RD_DATA_59 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K22 | PR35B | BIDI/IOL | C | | | | RD_DATA_60 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J22 | PR35A | BIDI/IOL | T | | | | RD_DATA_61 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K18 | PR34B | BIDI/IOL | L- | | 2 | | RD_DATA_62 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K17 | PR34A | BIDI/IOL | L+ | | 1 | | RD_DATA_63 | LVCMOS25 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | |
| H22 | PR32B | BIDI/IOL | C | | | | rd_cnt_1 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | H21 | PR32A | BIDI/IOL | T | | | | rd_cnt_2 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | J20 | PR31B | BIDI/XSIOL | C | | | | rd_cnt_3 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | J19 | PR31A | BIDI/DQSIOL | T | | | | rd_cnt_4 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | G22 | PR29B | BIDI/IOL | L- | | | | rd_cnt_5 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | G21 | PR29A | BIDI/IOL | L+ | | | | RX_ADC7923_ERROR_0 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | J18 | PR28B | BIDI/IOL | L- | | | | RX_ADC7923_ERROR_1 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | J17 | PR28A | BIDI/IOL | L+ | | | | RX_ADC7923_ERROR_2 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | F22 | PR26B | BIDI/IOL | C | | | | RX_ADC7923_ERROR_3 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | | E22 | PR26A | BIDI/IOL | T | | | | rd_cnt_0 | LVCMOS25 | 2.5V | OFF | OFF | OUT | ON | OFF | | | +-----+---------+-------------+-----+------+------+-------+--------------------+ ----------+-------+------+-----+-----------+-------+-----+------+-----------+ *** Bank 2 - # of PIO sites: 28, occupied: 24; # of Vref inputs used: 0 --- I/Os placed in Bank 3 --Bank Vccio=3.3V, Vref1/2=OFF/OFF, Vtt=OFF +------+---------+-------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vcc io | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +------+---------+-------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ | U16 | PB133A | BIDI/XSIOL | T | | | | | | | | | | | | | | | U15 | PB133B | BIDI/XSIOL | C | | | | | | | | | | | | | | | AB17 | PB134A | BIDI/XSIOL | T | | | | | | | | | | | | | | | AA17 | PB134B | BIDI/XSIOL | C | | | | | | | | | | | | | | | T14 | PB136A | BIDI/XSIOL | T | | | | | | | | | | | | | | | R14 | PB136B | BIDI/XSIOL | C | | | | | | | | | | | | | | | AB18 | PB137A | BIDI/XSIOL | T | | | | | | | | | | | | | | | AB19 | PB137B | BIDI/XSIOL | C | | | | | | | | | | | | | | | W18 | PB139A | BIDI/XSIOL | T | | | | | | | | | | | | | | | W17 | PB139B | BIDI/XSIOL | C | | | | | | | | | | | | | | | Y17 | PB140A | BIDI/XSIOL | T | | | | | | | | | | | | | | | Y18 | PB140B | BIDI/XSIOL | C | | | | | | | | | | | | | | | V18 | PB142A | BIDI/XSIOL | T | | | | | |
| | V17 | | AA19 | | Y19 | | T15 | | T16 | | AB20 | | AA20 | | V19 | | W19 | | Y20 | | AA21 | | U18 | | U19 | | T18 | | T19 | | AB21 | | AA22 | | T17 | | R17 | | V20 | | V21 | | R18 | | R19 | | W21 | | Y21 | | U20 | | T21 | | W22 | | Y22 | | P17
| | | PB142B | | | | PB143A | | | | PB143B | | | | PB145A | | | | PB145B | | | | PR97B | | | | PR97A | | | | PR95B | | | | PR95A | | | | PR94B | | | | PR94A | | | | PR92B | | | | PR92A | | | | PR91B | | | | PR91A | | | | PR89B | | | | PR89A | | | | PR61E_D | | | | PR61E_C | | | | PR61E_B | | | | PR61E_A | | | | PR61B | | | | PR61A | | | | PR59B | | | | PR59A | | | | PR58B | | | | PR58A | | | | PR56B | | | | PR56A | | | | PR55B |
| BIDI/XSIOL | BIDI/XSIOL | BIDI/XSIOL | BIDI/XSIOL | BIDI/XSIOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/XSIOL | BIDI/DQSIOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | IN/IOL | IN/IOL | IN/IOL | IN/IOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/IOL | BIDI/XSIOL | BIDI/DQSIOL | BIDI/IOL | BIDI/IOL | BIDI/IOL
| | C | | T | | C | | T | | C | | | | | | | | | | | | | | | | | | | | | | | | | | L| L+ | C | T | C | T | L| L+ | L| L+ | C | T | C | T | C | T | L| L+ | C | T | C | T | L| L+ | L| | | | | |
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| | | | | | | | | R16 | PR55A | BIDI/IOL | L+ | | | | | | | | | | | | | | | V22 | PR53B | BIDI/IOL | C | | | | | | | | | | | | | | | U22 | PR53A | BIDI/IOL | T | | | | | | | | | | | | | | | N20 | PR52B | BIDI/IOL | L- | | 2 | | | | | | | | | | | | | P20 | PR52A | BIDI/IOL | L+ | | 1 | | | | | | | | | | | | | R20 | PR50B | BIDI/IOL | C | | | | | | | | | | | | | | | T20 | PR50A | BIDI/IOL | T | | | | | | | | | | | | | | | P19 | PR49B | BIDI/XSIOL | C | | | | | | | | | | | | | | | N18 | PR49A | BIDI/DQSIOL | T | | | | | | | | | | | | | | | T22 | PR47B | BIDI/IOL | L- | | | | | | | | | | | | | | | R22 | PR47A | BIDI/IOL | L+ | | | | | | | | | | | | | | | M19 | PR46B | BIDI/IOL | L- | | | | | | | | | | | | | | | N19 | PR46A | BIDI/IOL | L+ | | | | | | | | | | | | | | | R21 | PR44B | BIDI/IOL | C | | | | | | | | | | | | | | | P22 | PR44A | BIDI/IOL | T | | | | | | | | | | | | | | +------+---------+-------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ *** Bank 3 - # of PIO sites: 58, occupied: 0; # of Vref inputs used: 0 --- I/Os placed in Bank 6 --Bank Vccio=3.3V, Vref1/2=OFF/OFF, Vtt=OFF +-----+---------+-------------+-----+------+------+-------+---------+----------+ -------+------+-----+----------+-------+-----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vccio | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +-----+---------+-------------+-----+------+------+-------+---------+----------+ -------+------+-----+----------+-------+-----+------+-----------+ | V5 | PL97B | BIDI/IOL | L- | | | | | | | | | | | | | | | V4 | PL97A | BIDI/IOL | L+ | | | | | | | | | | | | | | | AA2 | PL95B | BIDI/IOL | C | | | | DAC_SDO | LVCMOS33 | 3.3V | OFF | OFF | IN/XSIOL | ON | OFF | Y | | | Y3 | PL95A | BIDI/IOL | T | | | | | | | | | | | | | | | U5 | PL94B | BIDI/XSIOL | C | | | | | | | | | | | | | | | T6 | PL94A | BIDI/DQSIOL | T | | | | | | | | | | | | | | | Y2 | PL92B | BIDI/IOL | L- | | | | | | | | | | | | | |
| AA1 | PL92A | | | U4 | PL91B | | | T4 | PL91A | | | Y1 | PL89B | | | W2 | PL89A | | | T5 | PL88B | | | R4 | PL88A | | | W3 | PL86B | | | V3 | PL86A | | | T7 | PL85B | | | R7 | PL85A | | | W1 | PL83B | | | V1 | PL83A | | | P7 | PL82B | | | U3 | PL61E_D | | | T3 | PL61E_C | | | T1 | PL61E_B | | | T2 | PL61E_A | | | U2 | PL61B | | | U1 | PL61A | | | R2 | PL59B | | | R3 | PL59A | | | R6 | PL58B | | | P5 | PL58A | | | R1 | PL56B | | | P1 | PL56A | | | P6 | PL55B | | | N5 | PL55A | | | P3 | PL53B | | | N3 | PL53A | |
| BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/XSIOL | | BIDI/DQSIOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | IN/IOL | | IN/IOL | | IN/IOL | | IN/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/XSIOL | | BIDI/DQSIOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL |
| L+ | | L| | L+ | | C | | T | | L| | L+ | | C | | T | | C | | T | | L| | L+ | | C | | C | | T | | C | | T | | L| | L+ | | C | | T | | C | | T | | L| | L+ | | L| | L+ | | C | | T |
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| P4 | PL52B | | N4 | PL52A | | N1 | PL50B | | N2 | PL50A | | N6 | PL49B | | M5 | PL49A | | M1 | PL47B | | M2 | PL47A | | M4 | PL46B | | L4 | PL46A | | L2 | PL44B | | L3 | PL44A | | AB3 | PB2A | | AB4 | PB2B | | W4 | PB4A | | Y5 | PB4B | | AA4 | PB5A | | AA5 | PB5B | | W5 | PB7A | | W6 | PB7B | | AB5 | PB8A | | AB6 | PB8B | | V6 | PB10A | | U7 | PB10B | | Y6 | PB11A | | AA6 | PB11B | | U8 | PB13A | | T8 | PB13B | | R9 | PB16A | | T9 | PB16B |
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| BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/XSIOL | | BIDI/DQSIOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/IOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL | | BIDI/XSIOL |
| L| | L+ | | C | | T | | C | | T | | L| | L+ | | L| | L+ | | C | | T | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C | | T | | C |
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+-----+---------+-------------+-----+------+------+-------+---------+----------+ -------+------+-----+----------+-------+-----+------+-----------+ *** Bank 6 - # of PIO sites: 67, occupied: 1; # of Vref inputs used: 0 --- I/Os placed in Bank 7 --Bank Vccio=2.5V, Vref1/2=OFF/OFF, Vtt=OFF +-----+---------+-------------+-----+------+------+-------+------------+---------+-------+------+-----+-----------+-------+-----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vccio | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +-----+---------+-------------+-----+------+------+-------+------------+---------+-------+------+-----+-----------+-------+-----+------+-----------+ | K6 | PL43E_D | IN/IOL | C | | | | | | | | | | | | | | | L5 | PL43E_C | IN/IOL | T | | | | | | | | | | | | | | | L1 | PL43E_B | IN/IOL | C | | | | | | | | | | | | | | | K1 | PL43E_A | IN/IOL | T | | | | | | | | | | | | | | | K5 | PL43B | BIDI/IOL | L- | | | | RD_DATA_49 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K4 | PL43A | BIDI/IOL | L+ | | | | RD_DATA_48 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J1 | PL41B | BIDI/IOL | C | | | | RD_DATA_47 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J2 | PL41A | BIDI/IOL | T | | | | RD_DATA_46 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | K3 | PL40B | BIDI/XSIOL | C | | | | RD_DATA_45 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J3 | PL40A | BIDI/DQSIOL | T | | | | RD_DATA_44 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | H3 | PL38B | BIDI/IOL | L- | | | | RD_DATA_43 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | H2 | PL38A | BIDI/IOL | L+ | | | | RD_DATA_42 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J6 | PL37B | BIDI/IOL | L- | | | | RD_DATA_41 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J7 | PL37A | BIDI/IOL | L+ | | | | RD_DATA_40 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | H1 | PL35B | BIDI/IOL | C | | | | RD_DATA_39 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | G1 | PL35A | BIDI/IOL | T | | | | RD_DATA_38 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | F1 | PL34B | BIDI/IOL | L- | | 2 | | RD_DATA_37 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | E1 | PL34A | BIDI/IOL | L+ | | 1 | | RD_DATA_36 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | G2 | PL32B | BIDI/IOL | C | | | | RD_DATA_35 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | G3 | PL32A | BIDI/IOL | T | | | | RD_DATA_34 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | H6 | PL31B | BIDI/XSIOL | C | | | | RD_DATA_33 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | H5 | PL31A | BIDI/DQSIOL | T | | | | RD_DATA_32 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | C1 | PL29B | BIDI/IOL | L- | | | | RD_DATA_31 | LVCMOS2
5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | B1 | PL29A | BIDI/IOL | L+ | | | | RD_DATA_30 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | J4 | PL28B | BIDI/IOL | L- | | | | RD_DATA_29 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | H4 | PL28A | BIDI/IOL | L+ | | | | RD_DATA_28 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | F3 | PL26B | BIDI/IOL | C | | | | RD_DATA_27 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | E2 | PL26A | BIDI/IOL | T | | | | RD_DATA_26 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | G5 | PL16B | BIDI/IOL | L- | | | | RD_DATA_25 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | G4 | PL16A | BIDI/IOL | L+ | | | | RD_DATA_24 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | D1 | PL14B | BIDI/IOL | C | | | | RD_DATA_23 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | D2 | PL14A | BIDI/IOL | T | | | | RD_DATA_22 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | F4 | PL13B | BIDI/XSIOL | C | | | | RD_DATA_21 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | F5 | PL13A | BIDI/DQSIOL | T | | | | RD_DATA_20 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | C2 | PL11B | BIDI/IOL | L- | | | | RD_DATA_19 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | B2 | PL11A | BIDI/IOL | L+ | | | | RD_DATA_18 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | E4 | PL10B | BIDI/IOL | L- | | | | RD_DATA_17 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | E5 | PL10A | BIDI/IOL | L+ | | | | RD_DATA_16 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | D4 | PL8B | BIDI/IOL | C | | | | RD_DATA_15 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | | E3 | PL8A | BIDI/IOL | T | | | | RD_DATA_14 | LVCMOS2 5 | 2.5V | OFF | OFF | OUT/XSIOL | ON | OFF | | | +-----+---------+-------------+-----+------+------+-------+------------+---------+-------+------+-----+-----------+-------+-----+------+-----------+ *** Bank 7 - # of PIO sites: 40, occupied: 36; # of Vref inputs used: 0 --- I/Os placed in Bank 8 --Bank Vccio=3.3V, Vref1/2=OFF/OFF, Vtt=OFF +-----+--------+------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ | Pin | Site | Dir/IOL | T/C | Proh | Vref | Other | PIO | IO Type | Vccio | Vref | Vtt | Dir/IOL | Clamp | OD | Lock | Attrbites | +-----+--------+------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ | C18 | PT140A | BIDI/XSIOL | T | | | | | | | | | | | | | | | B19 | PT140B | BIDI/XSIOL | C | | | | | | | | | | | | | | | E18 | PT142A | BIDI/XSIOL | T | | | | | | | | | | | | | | | E17 | PT142B | BIDI/XSIOL | C | | | | | | | | | | | | | | | A20 | PT143A | BIDI/XSIOL | T | | | | | | | | | | | | | |
| B20 | PT143B | BIDI/XSIOL | C | | | | | | | | | | | | | | | D18 | PT145A | BIDI/XSIOL | T | | | | | | | | | | | | | | | D19 | PT145B | BIDI/XSIOL | C | | | | | | | | | | | | | | | H20 | PR16B | BIDI/XSIOL | C | | | | | | | | | | | | | | | H19 | PR16A | BIDI/XSIOL | T | | | | | | | | | | | | | | | G20 | PR14B | BIDI/XSIOL | C | | | | | | | | | | | | | | | G19 | PR14A | BIDI/XSIOL | T | | | | | | | | | | | | | | | G18 | PR13B | BIDI/XSIOL | C | | | | | | | | | | | | | | | G17 | PR13A | BIDI/XSIOL | T | | | | | | | | | | | | | | | D22 | PR11B | BIDI/XSIOL | C | | | | | | | | | | | | | | | C22 | PR11A | BIDI/XSIOL | T | | | | | | | | | | | | | | | H17 | PR10B | BIDI/XSIOL | C | | | | | | | | | | | | | | | J16 | PR10A | BIDI/XSIOL | T | | | | | | | | | | | | | | | B22 | PR8B | BIDI/XSIOL | C | | | | | | | | | | | | | | | A21 | PR8A | BIDI/XSIOL | T | Y | | CONF | | | | | | | | | | | | F18 | PR7B | BIDI/XSIOL | C | | | | | | | | | | | | | | | F19 | PR7A | BIDI/XSIOL | T | | | | | | | | | | | | | | | D21 | PR5B | BIDI/XSIOL | C | Y | | CONF | | | | | | | | | | | | C21 | PR5A | BIDI/XSIOL | T | | | | | | | | | | | | | | +-----+--------+------------+-----+------+------+-------+-----+---------+------+------+-----+---------+-------+----+------+-----------+ *** Bank 8 - # of PIO sites: 24, occupied: 0; # of Vref inputs used: 0 *** I/Os not placed *** PIO "RD_DATA_13": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_12": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_11": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_10": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_9": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_8": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_7": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_6": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL,
PCICLAMP=ON) was not placed. PIO "RD_DATA_5": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_4": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_3": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_2": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_1": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_DATA_0": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCICLAMP=ON) was not placed. PIO "RD_REQ": (IO_TYPE=LVCMOS25_OUT, Vccio/Vref/Vtt=2.5V/OFF/OFF, OUT/XSIOL, PCI CLAMP=ON) was not placed. *** # of PIO comps per direction/IOLOGIC type *** +------+--------+--------+--------+--------+--------+--------+--------+--------+ | | NO_IOL | XSIOL |IDDRIOL | SIOL | IOL |SDQSIOL | DQSIOL | Total | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | IN | 5 | 2 | 0 | 0 | 0 | 0 | 0 | 7 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | OUT | 12 | 66 | 0 | 0 | 0 | 0 | 0 | 78 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | BIDI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | Total| 17 | 68 | 0 | 0 | 0 | 0 | 0 | 85 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ *** # of PIO sites per direction/IOLOGIC type *** +------+--------+--------+--------+--------+--------+--------+--------+--------+ | | NO_IOL | XSIOL |IDDRIOL | SIOL | IOL |SDQSIOL | DQSIOL | Total | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | IN | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 16 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | OUT | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | BIDI | 0 | 78 | 0 | 66 | 117 | 6 | 12 | 279 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ | Total| 0 | 78 | 0 | 66 | 133 | 6 | 12 | 295 | +------+--------+--------+--------+--------+--------+--------+--------+--------+ Exiting par with exit code 1 Exiting mpartrce with exit code 1 Done: error code 1 Loading logical preference information Finish loading logical preference file Loading logical design information Finish loading logical design information Loading device for application GENERIC from file 'ec5a97x146.nph' in environment : C:/lscc/diamond/1.1/ispfpga. WARNING - Port I_brd_clk does not connect to any buffers WARNING - Port I_Rst_n does not connect to any buffers WARNING - Port I_ARM_Addr_9 does not connect to any buffers WARNING - Port I_ARM_Addr_8 does not connect to any buffers WARNING - Port I_ARM_Addr_7 does not connect to any buffers
I_ARM_Addr_6 does not connect to any buffers I_ARM_Addr_5 does not connect to any buffers I_ARM_Addr_4 does not connect to any buffers I_ARM_Addr_3 does not connect to any buffers I_ARM_Addr_2 does not connect to any buffers I_ARM_Addr_1 does not connect to any buffers I_ARM_CS_n does not connect to any buffers I_ARM_OE_n does not connect to any buffers I_ARM_WE_n does not connect to any buffers O_ARM_WAIT_n does not connect to any buffers O_ARM_INT_n does not connect to any buffers B_ARM_Data_15 does not connect to any buffers B_ARM_Data_14 does not connect to any buffers B_ARM_Data_13 does not connect to any buffers B_ARM_Data_12 does not connect to any buffers B_ARM_Data_11 does not connect to any buffers B_ARM_Data_10 does not connect to any buffers B_ARM_Data_9 does not connect to any buffers B_ARM_Data_8 does not connect to any buffers B_ARM_Data_7 does not connect to any buffers B_ARM_Data_6 does not connect to any buffers B_ARM_Data_5 does not connect to any buffers B_ARM_Data_4 does not connect to any buffers B_ARM_Data_3 does not connect to any buffers B_ARM_Data_2 does not connect to any buffers B_ARM_Data_1 does not connect to any buffers B_ARM_Data_0 does not connect to any buffers spi_clk does not connect to any buffers spi_do does not connect to any buffers spi_en_3 does not connect to any buffers spi_en_2 does not connect to any buffers spi_en_1 does not connect to any buffers spi_en_0 does not connect to any buffers SEQ_DATA_0 does not connect to any buffers SEQ_DATA_1 does not connect to any buffers SEQ_DATA_2 does not connect to any buffers SEQ_DATA_3 does not connect to any buffers SEQ_DATA_4 does not connect to any buffers SEQ_DATA_5 does not connect to any buffers SEQ_DATA_6 does not connect to any buffers SEQ_DATA_7 does not connect to any buffers iq_wrt2 does not connect to any buffers iq_sel2 does not connect to any buffers tx_data2_11 does not connect to any buffers tx_data2_10 does not connect to any buffers tx_data2_9 does not connect to any buffers tx_data2_8 does not connect to any buffers tx_data2_7 does not connect to any buffers tx_data2_6 does not connect to any buffers tx_data2_5 does not connect to any buffers tx_data2_4 does not connect to any buffers tx_data2_3 does not connect to any buffers tx_data2_2 does not connect to any buffers tx_data2_1 does not connect to any buffers tx_data2_0 does not connect to any buffers txdac_reset2 does not connect to any buffers txc_sleep2 does not connect to any buffers SCL does not connect to any buffers SDA does not connect to any buffers timing_fs does not connect to any buffers
TX2_MOD_EN_A does not connect to any buffers TX1_MOD_EN_A does not connect to any buffers clk_out does not connect to any buffers TX_DAC_EN does not connect to any buffers FPGA_TO_DSP_TS_INT does not connect to any buffers FPGA_TO_DSP_OBN_CLK does not connect to any buffers adc_obn_int_13 does not connect to any buffers adc_obn_int_12 does not connect to any buffers adc_obn_int_11 does not connect to any buffers adc_obn_int_10 does not connect to any buffers adc_obn_int_9 does not connect to any buffers adc_obn_int_8 does not connect to any buffers adc_obn_int_7 does not connect to any buffers adc_obn_int_6 does not connect to any buffers adc_obn_int_5 does not connect to any buffers adc_obn_int_4 does not connect to any buffers adc_obn_int_3 does not connect to any buffers adc_obn_int_2 does not connect to any buffers adc_obn_int_1 does not connect to any buffers adc_obn_int_0 does not connect to any buffers ADC_SYNC does not connect to any buffers RX_ADC_EN does not connect to any buffers ADC_TS_2 does not connect to any buffers ADC_TS_1 does not connect to any buffers ADC_TS_0 does not connect to any buffers rxb_dtack_rdy does not connect to any buffers ADC_MC_ADDR_2 does not connect to any buffers ADC_MC_ADDR_1 does not connect to any buffers ADC_MC_ADDR_0 does not connect to any buffers rxb_rdnwr does not connect to any buffers rxb_dsrd does not connect to any buffers rxb_cs does not connect to any buffers rxb_d_7 does not connect to any buffers rxb_d_6 does not connect to any buffers rxb_d_5 does not connect to any buffers rxb_d_4 does not connect to any buffers rxb_d_3 does not connect to any buffers rxb_d_2 does not connect to any buffers rxb_d_1 does not connect to any buffers rxb_d_0 does not connect to any buffers FPGA_LED does not connect to any buffers T2RXC1 does not connect to any buffers EN_DIS_DATA_PUMP does not connect to any buffers RESET_RADIO_IF does not connect to any buffers PA_MEAS does not connect to any buffers PERIO_ATTN_EN_DIS does not connect to any buffers PA_ON_OFF does not connect to any buffers EN_DIS_DATA_PUMP2 does not connect to any buffers RF_enable does not connect to any buffers RESET_RADIO_IF2 does not connect to any buffers PA_MEAS2 does not connect to any buffers PERIO_ATTN_EN_DIS2 does not connect to any buffers PA_ON_OFF2 does not connect to any buffers FRAME_SYNC1_13 does not connect to any buffers FRAME_SYNC1_12 does not connect to any buffers FRAME_SYNC1_11 does not connect to any buffers FRAME_SYNC1_10 does not connect to any buffers FRAME_SYNC1_9 does not connect to any buffers FRAME_SYNC1_8 does not connect to any buffers FRAME_SYNC1_7 does not connect to any buffers
FRAME_SYNC1_6 does not connect to any buffers FRAME_SYNC1_5 does not connect to any buffers FRAME_SYNC1_4 does not connect to any buffers FRAME_SYNC1_3 does not connect to any buffers FRAME_SYNC1_2 does not connect to any buffers FRAME_SYNC1_1 does not connect to any buffers FRAME_SYNC1_0 does not connect to any buffers TX1_Lock does not connect to any buffers TX2_Lock does not connect to any buffers RX1_Lock does not connect to any buffers RX2_Lock does not connect to any buffers spi_clk2 does not connect to any buffers spi_en2_3 does not connect to any buffers spi_en2_2 does not connect to any buffers spi_en2_1 does not connect to any buffers spi_en2_0 does not connect to any buffers spi_do2 does not connect to any buffers DIR_CTRL does not connect to any buffers tx_reset does not connect to any buffers iq_sel_a does not connect to any buffers iq_sel_b does not connect to any buffers dac_a_clk does not connect to any buffers dac_b_clk does not connect to any buffers tx_data_11 does not connect to any buffers tx_data_10 does not connect to any buffers tx_data_9 does not connect to any buffers tx_data_8 does not connect to any buffers tx_data_7 does not connect to any buffers tx_data_6 does not connect to any buffers tx_data_5 does not connect to any buffers tx_data_4 does not connect to any buffers tx_data_3 does not connect to any buffers tx_data_2 does not connect to any buffers tx_data_1 does not connect to any buffers tx_data_0 does not connect to any buffers rx_clk does not connect to any buffers rx_sync does not connect to any buffers rx_data0 does not connect to any buffers rx_data1 does not connect to any buffers dc_dc_sync does not connect to any buffers HPI_HRDY_L does not connect to any buffers HPI_HAS does not connect to any buffers HPI_HCS_L does not connect to any buffers HPI_HDS1_L does not connect to any buffers HPI_HDS2_L does not connect to any buffers HPI_HHWIL does not connect to any buffers HPI_R_WL does not connect to any buffers HPI_HCNTL_1 does not connect to any buffers HPI_HCNTL_0 does not connect to any buffers spi_en2_7 does not connect to any buffers spi_en2_6 does not connect to any buffers spi_en2_5 does not connect to any buffers spi_en2_4 does not connect to any buffers HPI_DATA_15 does not connect to any buffers HPI_DATA_14 does not connect to any buffers HPI_DATA_13 does not connect to any buffers HPI_DATA_12 does not connect to any buffers HPI_DATA_11 does not connect to any buffers HPI_DATA_10 does not connect to any buffers HPI_DATA_9 does not connect to any buffers
WARNING - Port HPI_DATA_8 does not connect to any buffers WARNING - Port HPI_DATA_7 does not connect to any buffers WARNING - Port HPI_DATA_6 does not connect to any buffers WARNING - Port HPI_DATA_5 does not connect to any buffers WARNING - Port HPI_DATA_4 does not connect to any buffers WARNING - Port HPI_DATA_3 does not connect to any buffers WARNING - Port HPI_DATA_2 does not connect to any buffers WARNING - Port HPI_DATA_1 does not connect to any buffers WARNING - Port HPI_DATA_0 does not connect to any buffers WARNING - Port GC_SYNC_A does not connect to any buffers WARNING - Port GC_SYNC_B does not connect to any buffers WARNING - Port EMIFENA does not connect to any buffers WARNING - Port DSP6748_SYNC_A does not connect to any buffers WARNING - Port DSP6748_SYNC_B does not connect to any buffers ERROR - srio_subsys_top_u/rio_clk matches no nets in the design. ERROR - srio_subsys_top_u/refck2core matches no nets in the design. ERROR - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. ERROR - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. ERROR - srio_subsys_top_u/pcs_if_clk matches no nets in the design. ERROR - sys_clk matches no nets in the design. srio_subsys_top_u/refck2core matc hes no nets in the design. ERROR - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. srio_subs ys_top_u/pcs_if_clk matches no nets in the design. ERROR - srio_subsys_top_u/pcs_if_clk matches no nets in the design. srio_subsys_ top_u/tx_full_clk_c matches no nets in the design. ERROR - "srio_subsys_top_u/pcs_serdes/pcsd_inst" matches no asics in the design. ERROR - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. srio_subs ys_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_gen/full_clk_div8 match es no nets in the design. ERROR - srio_subsys_top_u/pcs_if_clk matches no nets in the design. srio_subsys_ top_u/rx_half_clk_ch0 matches no nets in the design. ERROR - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. srio_su bsys_top_u/pcs_if_clk matches no nets in the design. ERROR - *oplm2_mgt_1x_2x_nx_init_sm?init_state* matches no cells in the design. ERROR - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. sys_clk matches no nets in the design. ERROR - "*wrapper_srio_4x*rio_maintenance_module*bus_interface*mgt_a*" matches n o cells in the design. ERROR - <E0003> Port 'I_brd_clk' is not found. INFO - srio_subsys_top_u/rio_clk matches no nets in the design. INFO - srio_subsys_top_u/refck2core matches no nets in the design. INFO - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. INFO - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. INFO - srio_subsys_top_u/pcs_if_clk matches no nets in the design. ERROR - <E0002> Net '*pcs_if_clk_reset_n' is not found. ERROR - <E0002> Net '*rio_clk_reset_n' is not found. INFO - sys_clk matches no nets in the design. srio_subsys_top_u/refck2core match es no nets in the design. INFO - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. srio_subsy s_top_u/pcs_if_clk matches no nets in the design. INFO - srio_subsys_top_u/pcs_if_clk matches no nets in the design. srio_subsys_t op_u/tx_full_clk_c matches no nets in the design. INFO - "srio_subsys_top_u/pcs_serdes/pcsd_inst" matches no asics in the design. INFO - srio_subsys_top_u/tx_full_clk_c matches no nets in the design. srio_subsy s_top_u/wrapper_srio_4x/phy_demo_clock_gen_inst/rio_clk_gen/full_clk_div8 matche s no nets in the design. INFO - srio_subsys_top_u/pcs_if_clk matches no nets in the design. srio_subsys_t op_u/rx_half_clk_ch0 matches no nets in the design. INFO - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. srio_sub
sys_top_u/pcs_if_clk matches no nets in the design. INFO - *oplm2_mgt_1x_2x_nx_init_sm?init_state* matches no cells in the design. INFO - srio_subsys_top_u/rx_half_clk_ch0 matches no nets in the design. sys_clk matches no nets in the design. INFO - "*wrapper_srio_4x*rio_maintenance_module*bus_interface*mgt_a*" matches no cells in the design. ERROR - <E0005> Unknown Object 'CELL' '*wrapper*ollm_serial_tx_link_sched*local_ reset_n'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_3'. ERROR - <E0005> Unknown Object 'PORT' 'ADC_SYNC'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_HDS2_L'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_4'. ERROR - <E0005> Unknown Object 'PORT' 'RESET_RADIO_IF2'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_5'. ERROR - <E0005> Unknown Object 'PORT' 'PA_MEAS'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_6'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_7'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_8'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_0'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data_10'. ERROR - <E0005> Unknown Object 'PORT' 'I_ARM_Addr_9'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_1'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_0'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data_11'. ERROR - <E0005> Unknown Object 'PORT' 'O_ARM_WAIT_n'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_2'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_1'. ERROR - <E0005> Unknown Object 'PORT' 'rx_clk'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_3'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_2'. ERROR - <E0005> Unknown Object 'PORT' 'spi_clk'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_4'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_3'. ERROR - <E0005> Unknown Object 'PORT' 'clk_out'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_5'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_4'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_HRDY_L'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_DATA_10'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_6'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_5'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_DATA_11'. ERROR - <E0005> Unknown Object 'PORT' 'SEQ_DATA_7'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_6'. ERROR - <E0005> Unknown Object 'PORT' 'adc_obn_int_10'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_DATA_12'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_7'. ERROR - <E0005> Unknown Object 'PORT' 'TX_DAC_EN'. ERROR - <E0005> Unknown Object 'PORT' 'adc_obn_int_11'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_DATA_13'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_8'. ERROR - <E0005> Unknown Object 'PORT' 'adc_obn_int_12'. ERROR - <E0005> Unknown Object 'PORT' 'rxb_d_0'. ERROR - <E0005> Unknown Object 'PORT' 'FPGA_LED'. ERROR - <E0005> Unknown Object 'PORT' 'dac_b_clk'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_DATA_14'. ERROR - <E0005> Unknown Object 'PORT' 'tx_data2_9'. ERROR - <E0005> Unknown Object 'PORT' 'adc_obn_int_13'. ERROR - <E0005> Unknown Object 'PORT' 'rxb_d_1'. ERROR - <E0005> Unknown Object 'PORT' 'HPI_DATA_15'. ERROR - <E0005> Unknown Object 'PORT' 'rxb_rdnwr'.
'rxb_d_2'. 'rxb_d_3'. 'HPI_DATA_0'. 'I_Rst_n'. 'rxb_d_4'. 'EN_DIS_DATA_PUMP2'. 'TX2_Lock'. 'HPI_DATA_1'. 'FRAME_SYNC1_0'. 'rxb_d_5'. 'HPI_DATA_2'. 'FRAME_SYNC1_10'. 'rxb_d_6'. 'FRAME_SYNC1_1'. 'HPI_HAS'. 'HPI_R_WL'. 'HPI_DATA_3'. 'FRAME_SYNC1_11'. 'rxb_d_7'. 'FRAME_SYNC1_2'. 'HPI_DATA_4'. 'FRAME_SYNC1_12'. 'SCL'. 'FRAME_SYNC1_3'. 'HPI_DATA_5'. 'FRAME_SYNC1_13'. 'iq_sel2'. 'FRAME_SYNC1_4'. 'spi_en2_0'. 'HPI_DATA_6'. 'PERIO_ATTN_EN_DIS2'. 'FRAME_SYNC1_5'. 'spi_en2_1'. 'spi_do2'. 'HPI_DATA_7'. 'DSP6748_SYNC_A'. 'FRAME_SYNC1_6'. 'spi_en2_2'. 'HPI_DATA_8'. 'DSP6748_SYNC_B'. 'FRAME_SYNC1_7'. 'spi_en2_3'. 'HPI_DATA_9'. 'GC_SYNC_A'. 'FRAME_SYNC1_8'. 'spi_en2_4'. 'GC_SYNC_B'. 'I_ARM_WE_n'. 'FRAME_SYNC1_9'. 'spi_en2_5'. 'TX1_Lock'. 'dac_a_clk'. 'dc_dc_sync'. 'spi_en2_6'. 'RF_enable'. 'I_ARM_Addr_1'. 'FPGA_TO_DSP_TS_INT'. 'spi_en2_7'. 'spi_clk2'. 'I_ARM_Addr_2'.
'RX_ADC_EN'. 'DIR_CTRL'. 'EN_DIS_DATA_PUMP'. 'I_brd_clk'. 'RESET_RADIO_IF'. 'RX1_Lock'. 'HPI_HCNTL_0'. 'B_ARM_Data_0'. 'txc_sleep2'. 'HPI_HCNTL_1'. 'B_ARM_Data_1'. 'B_ARM_Data_2'. 'HPI_HDS1_L'. 'B_ARM_Data_3'. 'rxb_dsrd'. 'O_ARM_INT_n'. 'B_ARM_Data_4'. 'ADC_TS_0'. 'EMIFENA'. 'B_ARM_Data_5'. 'ADC_TS_1'. 'rx_sync'. 'B_ARM_Data_6'. 'adc_obn_int_0'. 'ADC_TS_2'. 'B_ARM_Data_7'. 'timing_fs'. 'adc_obn_int_1'. 'B_ARM_Data_8'. 'spi_en_0'. 'adc_obn_int_2'. 'B_ARM_Data_10'. 'B_ARM_Data_9'. 'spi_do'. 'spi_en_1'. 'TX1_MOD_EN_A'. 'adc_obn_int_3'. 'PERIO_ATTN_EN_DIS'. 'B_ARM_Data_11'. 'spi_en_2'. 'adc_obn_int_4'. 'tx_data_0'. 'B_ARM_Data_12'. 'spi_en_3'. 'SDA'. 'adc_obn_int_5'. 'ADC_MC_ADDR_0'. 'B_ARM_Data_13'. 'FPGA_TO_DSP_OBN_CLK'. 'adc_obn_int_6'. 'ADC_MC_ADDR_1'. 'tx_data_1'. 'B_ARM_Data_14'. 'adc_obn_int_7'. 'ADC_MC_ADDR_2'. 'tx_reset'. 'tx_data_2'. 'B_ARM_Data_15'. 'tx_data2_10'. 'TX2_MOD_EN_A'.
ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR c'. ERROR WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
<E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005> <E0005>
Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object Object
'PORT' 'adc_obn_int_8'. 'PORT' 'tx_data_3'. 'PORT' 'I_ARM_OE_n'. 'PORT' 'tx_data2_11'. 'PORT' 'adc_obn_int_9'. 'PORT' 'rxb_dtack_rdy'. 'PORT' 'tx_data_4'. 'PORT' 'rxb_cs'. 'PORT' 'iq_sel_a'. 'PORT' 'tx_data_5'. 'PORT' 'HPI_HCS_L'. 'PORT' 'I_ARM_CS_n'. 'PORT' 'iq_sel_b'. 'PORT' 'tx_data_6'. 'PORT' 'tx_data_7'. 'PORT' 'rx_data0'. 'PORT' 'iq_wrt2'. 'PORT' 'txdac_reset2'. 'PORT' 'T2RXC1'. 'PORT' 'RX2_Lock'. 'PORT' 'tx_data_8'. 'PORT' 'rx_data1'. 'PORT' 'PA_ON_OFF2'. 'PORT' 'tx_data_9'. 'PORT' 'PA_ON_OFF'. 'PORT' 'PA_MEAS2'. 'PORT' 'HPI_HHWIL'. 'CLOCK/CE/LSR NET' 'iq_clk_c'. 'CLKNET/CeLsrNET' 'FPGA_TO_DSP_OBN_CLKgen'. 'CLKNET/CeLsrNET' 'srio_subsys_top_u/tx_full_clk_
<E0005> Unknown Object 'CLKNET/CeLsrNET' 'srio_subsys_top_u/refck2core'. - Invalid Signal [I_ARM_Addr_3] is not shown up. - Invalid Signal [ADC_SYNC] is not shown up. - Invalid Signal [HPI_HDS2_L] is not shown up. - Invalid Signal [I_ARM_Addr_4] is not shown up. - Invalid Signal [RESET_RADIO_IF2] is not shown up. - Invalid Signal [I_ARM_Addr_5] is not shown up. - Invalid Signal [PA_MEAS] is not shown up. - Invalid Signal [I_ARM_Addr_6] is not shown up. - Invalid Signal [I_ARM_Addr_7] is not shown up. - Invalid Signal [I_ARM_Addr_8] is not shown up. - Invalid Signal [SEQ_DATA_0] is not shown up. - Invalid Signal [tx_data_10] is not shown up. - Invalid Signal [I_ARM_Addr_9] is not shown up. - Invalid Signal [SEQ_DATA_1] is not shown up. - Invalid Signal [tx_data2_0] is not shown up. - Invalid Signal [tx_data_11] is not shown up. - Invalid Signal [O_ARM_WAIT_n] is not shown up. - Invalid Signal [SEQ_DATA_2] is not shown up. - Invalid Signal [tx_data2_1] is not shown up. - Invalid Signal [rx_clk] is not shown up. - Invalid Signal [SEQ_DATA_3] is not shown up. - Invalid Signal [tx_data2_2] is not shown up. - Invalid Signal [spi_clk] is not shown up. - Invalid Signal [SEQ_DATA_4] is not shown up. - Invalid Signal [tx_data2_3] is not shown up. - Invalid Signal [clk_out] is not shown up. - Invalid Signal [SEQ_DATA_5] is not shown up. - Invalid Signal [tx_data2_4] is not shown up.
[HPI_HRDY_L] is not shown up. [HPI_DATA_10] is not shown up. [SEQ_DATA_6] is not shown up. [tx_data2_5] is not shown up. [HPI_DATA_11] is not shown up. [SEQ_DATA_7] is not shown up. [tx_data2_6] is not shown up. [adc_obn_int_10] is not shown up. [HPI_DATA_12] is not shown up. [tx_data2_7] is not shown up. [TX_DAC_EN] is not shown up. [adc_obn_int_11] is not shown up. [HPI_DATA_13] is not shown up. [tx_data2_8] is not shown up. [adc_obn_int_12] is not shown up. [rxb_d_0] is not shown up. [FPGA_LED] is not shown up. [dac_b_clk] is not shown up. [HPI_DATA_14] is not shown up. [tx_data2_9] is not shown up. [adc_obn_int_13] is not shown up. [rxb_d_1] is not shown up. [HPI_DATA_15] is not shown up. [rxb_rdnwr] is not shown up. [rxb_d_2] is not shown up. [rxb_d_3] is not shown up. [HPI_DATA_0] is not shown up. [I_Rst_n] is not shown up. [rxb_d_4] is not shown up. [EN_DIS_DATA_PUMP2] is not shown up. [TX2_Lock] is not shown up. [HPI_DATA_1] is not shown up. [FRAME_SYNC1_0] is not shown up. [rxb_d_5] is not shown up. [HPI_DATA_2] is not shown up. [FRAME_SYNC1_10] is not shown up. [rxb_d_6] is not shown up. [FRAME_SYNC1_1] is not shown up. [HPI_HAS] is not shown up. [HPI_R_WL] is not shown up. [HPI_DATA_3] is not shown up. [FRAME_SYNC1_11] is not shown up. [rxb_d_7] is not shown up. [FRAME_SYNC1_2] is not shown up. [HPI_DATA_4] is not shown up. [FRAME_SYNC1_12] is not shown up. [SCL] is not shown up. [FRAME_SYNC1_3] is not shown up. [HPI_DATA_5] is not shown up. [FRAME_SYNC1_13] is not shown up. [iq_sel2] is not shown up. [FRAME_SYNC1_4] is not shown up. [spi_en2_0] is not shown up. [HPI_DATA_6] is not shown up. [PERIO_ATTN_EN_DIS2] is not shown up. [FRAME_SYNC1_5] is not shown up. [spi_en2_1] is not shown up. [spi_do2] is not shown up. [HPI_DATA_7] is not shown up. [DSP6748_SYNC_A] is not shown up.
[FRAME_SYNC1_6] is not shown up. [spi_en2_2] is not shown up. [HPI_DATA_8] is not shown up. [DSP6748_SYNC_B] is not shown up. [FRAME_SYNC1_7] is not shown up. [spi_en2_3] is not shown up. [HPI_DATA_9] is not shown up. [GC_SYNC_A] is not shown up. [FRAME_SYNC1_8] is not shown up. [spi_en2_4] is not shown up. [GC_SYNC_B] is not shown up. [I_ARM_WE_n] is not shown up. [FRAME_SYNC1_9] is not shown up. [spi_en2_5] is not shown up. [TX1_Lock] is not shown up. [dac_a_clk] is not shown up. [dc_dc_sync] is not shown up. [spi_en2_6] is not shown up. [RF_enable] is not shown up. [I_ARM_Addr_1] is not shown up. [FPGA_TO_DSP_TS_INT] is not shown up. [spi_en2_7] is not shown up. [spi_clk2] is not shown up. [I_ARM_Addr_2] is not shown up. [RX_ADC_EN] is not shown up. [DIR_CTRL] is not shown up. [EN_DIS_DATA_PUMP] is not shown up. [I_brd_clk] is not shown up. [RESET_RADIO_IF] is not shown up. [RX1_Lock] is not shown up. [HPI_HCNTL_0] is not shown up. [B_ARM_Data_0] is not shown up. [txc_sleep2] is not shown up. [HPI_HCNTL_1] is not shown up. [B_ARM_Data_1] is not shown up. [B_ARM_Data_2] is not shown up. [HPI_HDS1_L] is not shown up. [B_ARM_Data_3] is not shown up. [rxb_dsrd] is not shown up. [O_ARM_INT_n] is not shown up. [B_ARM_Data_4] is not shown up. [ADC_TS_0] is not shown up. [EMIFENA] is not shown up. [B_ARM_Data_5] is not shown up. [ADC_TS_1] is not shown up. [rx_sync] is not shown up. [B_ARM_Data_6] is not shown up. [adc_obn_int_0] is not shown up. [ADC_TS_2] is not shown up. [B_ARM_Data_7] is not shown up. [timing_fs] is not shown up. [adc_obn_int_1] is not shown up. [B_ARM_Data_8] is not shown up. [spi_en_0] is not shown up. [adc_obn_int_2] is not shown up. [B_ARM_Data_10] is not shown up. [B_ARM_Data_9] is not shown up. [spi_do] is not shown up. [spi_en_1] is not shown up. [TX1_MOD_EN_A] is not shown up.
WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal
[adc_obn_int_3] is not shown up. [PERIO_ATTN_EN_DIS] is not shown up. [B_ARM_Data_11] is not shown up. [spi_en_2] is not shown up. [adc_obn_int_4] is not shown up. [tx_data_0] is not shown up. [B_ARM_Data_12] is not shown up. [spi_en_3] is not shown up. [SDA] is not shown up. [adc_obn_int_5] is not shown up. [ADC_MC_ADDR_0] is not shown up. [B_ARM_Data_13] is not shown up. [FPGA_TO_DSP_OBN_CLK] is not shown up. [adc_obn_int_6] is not shown up. [ADC_MC_ADDR_1] is not shown up. [tx_data_1] is not shown up. [B_ARM_Data_14] is not shown up. [adc_obn_int_7] is not shown up. [ADC_MC_ADDR_2] is not shown up. [tx_reset] is not shown up. [tx_data_2] is not shown up. [B_ARM_Data_15] is not shown up. [tx_data2_10] is not shown up. [TX2_MOD_EN_A] is not shown up. [adc_obn_int_8] is not shown up. [tx_data_3] is not shown up. [I_ARM_OE_n] is not shown up. [tx_data2_11] is not shown up. [adc_obn_int_9] is not shown up. [rxb_dtack_rdy] is not shown up. [tx_data_4] is not shown up. [rxb_cs] is not shown up. [iq_sel_a] is not shown up. [tx_data_5] is not shown up. [HPI_HCS_L] is not shown up. [I_ARM_CS_n] is not shown up. [iq_sel_b] is not shown up. [tx_data_6] is not shown up. [tx_data_7] is not shown up. [rx_data0] is not shown up. [iq_wrt2] is not shown up. [txdac_reset2] is not shown up. [T2RXC1] is not shown up. [RX2_Lock] is not shown up. [tx_data_8] is not shown up. [rx_data1] is not shown up. [PA_ON_OFF2] is not shown up. [tx_data_9] is not shown up. [PA_ON_OFF] is not shown up. [PA_MEAS2] is not shown up. [HPI_HHWIL] is not shown up.

PAR 17oct11

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PAR 17oct11

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ERRORS: ======== ERROR - par: I/O initial placement is unsuccessful.

- <E0005> Unknown Object 'CLKNET/CeLsrNET' 'srio_subsys_top_u/refck2core'.

wr_cmd:C start_fifo_wr:C rd_en:C

Done Done Done

351 / 351 / 351 / 351 /

207 207 207 207

Interface Information *********************

NA NA NA NA NA NA NA NA NA NA System (rising) System (rising) NA System (rising)

NA NA NA NA NA NA NA NA NA NA 0.000 0.000 NA 0.000

NA NA NA NA NA NA NA NA NA NA 1.339 1.484 NA 1.072

Interface Information *********************

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