Design of adder circuits

Half adder Full adder Half subtractor Full subtractor BCD adder IC 7483 for implementing Binary Adder Binary Subtractor BCD adder Look ahead carry adder
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Multplexer Demultiplexer Decoder Encoder Various decoders BCD to decimal binary to excess 3 code binary to gray code gray to binary BCD to 7 segment Digital comparators Multipliers
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Combinational logic circuits

N inputs

Combinational circuits

M outputs

Outputs, at any time, are determined by the input

combination When input changed, output changed immediately Real circuits is imperfect and have propagation delay A combinational circuit Performs logic operations that can be specified by a set of Boolean expressions Can be built hierarchically
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Adder circuits
Half adder
A 0 B 0 S 0 Ca 0

S=AB+AB Ca=AB
A

0 1
1

1 0
1

1 1
0

0 0
1

S B

Ca
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Full adder
S=ABC+ABC+ABC+ABC = A(BC+BC)+A(BC+BC) = A(B(exor)C) + A(B(exnor)C) = A(exor)B(exor)C
B

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Ca 0 0 0 1 0 1 1 1

C A

Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

Full adder
Ca=ABC+ABC+ABC+ABC = A(BC+BC)+BC(A+A) = A(B(exor)C) +BC
B

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Ca 0 0 0 1 0 1 1 1

C A Ca
Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR 6

Subtractor circuits
Half Subtractor
A 0 B 0 D 0 Bo 0

D=AB+AB Bo=AB
A

0 1
1

1 0
1

1 1
0

1 0
0

D B

Bo
Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR 7

Full subtractor
D=ABC+ABC+ABC+ABC =A(BC+BC)+A(BC+BC) =A(B(exor)C)+A(B(exnor)C)
B

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

D 0 1 1 0 1 0 0 1

Bo 0 1 1 1 0 0 0 1

C D A

Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

Full subtractor
Bo=ABC+ABC+ABC+ABC =A(BC+BC)+BC(A+A) =A(BC+BC)+BC =A(B(exor)C)+BC

Bo

0
0 0 1 1

0
1 1 0 0

1
0 1 0 1

1
1 0 1 0

1
1 1 0 0

1
1

1
1

0
1

0
1

0
1

Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

Full subtractor
Bo=A(B(exor)C)+BC
Bo=((BC) . Z) = ((BC) . (B(exor)C . (B(exor)C . A)) =BC+ (B(exor)C . (B(exor)C . A)) =BC+ B(exor)C . ((B(exor)C) + A) = BC+ B(exor)C . A

Y=(X.A) Z=(X.Y)

Bo B (BC)

X=B(exor)C
Y

Z D

C A

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Multiplexers (MUXs)
(also called a data selector) Input lines consist of data lines: 2n lines select lines: n lines there may or may not be an enable line Output line: output line: 1 line

Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

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Multiplexer Function
Truth table of a 4:1 multiplexer (without enable) Select inputs Output S1 S0 Y 0 0 A0 0 1 A1 1 0 A2 1 1 A3

F S1S0A0 S1S0A1 S1S0A2 S1S0A3

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Multiplexer Function
Truth table of a 4:1 multiplexer (with enable)
Enable Select inputs Output

E
0 1 1

S1
X 0 0

S0
X 0 1

Y
0 A0 A1

1
1

1
1

0
1

A2
A3

Y E.(S1.S0 .A0 S1.S0 .A1 S1.S0 .A2 S1.S0 .A3 )

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Multiplexers (Mux)
Functionality: Selection of a particular input
A0 A1 A2 A3 En

Route 1 of N inputs (A) to the output Y

Y

4-to-1 Mux
S1 S0

En(able) bit can disable

the route and set y to 0 N Require log 2 selection bits (S)

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Logic Diagram of a 4-to-1 Mux

S1 S0 A0 Y

A1

A2

A3

F S1S0A0 S1S0A1 S1S0A2 S1S0A3

15 Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

B 0 0 1 1 0 0

C 0 1 0 1 0 1

Y 0 1 1 0 0 0

8 to 1 Mux
Example

0 0 0 0 1 1

0
1 1 0 0 0 1 1

A0 A1 A2 A3 A4 A5 A6 A7

1
1

1
1

0
1

1
1

8-to-1 Mux

S2 S1 S0

A B C

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Demultiplexers
Performs the reverse operation of a multiplexer Input lines are: 1 data line n select lines

maybe 1 enable
Output lines are 2n output lines
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Demultiplexers (DeMux)
A0 A1 A2 A3
Y0

4-to-1 Mux
S1 S0

1-to-4 DeMux
S1 S0

Y1 Y2 Y3

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Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

DeMux Operations
S1 0 0
Y0 Y1 Y2 Y3

S0 0 1 0 1

Y3 0 0 0 D

Y2 0 0 D 0

Y1 0 D 0 0

Y0 D 0 0 0

1 1

1-to-4 DeMux
S1 S0

Y 0 S 0 S 1D
Y 1 S 0 S 1D

Y 2 S 0 S 1D
Y 3 S 0S1D

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Logic Diagram of a 1-to-4 De-mux

S1 S0 D Y1

Y0

Y 0 S 0 S 1D
Y 1 S 0 S 1D

Y2

Y 2 S 0 S 1D
Y 3 S 0S1D

Y3

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Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

DeMux Operations w/ Enable

S1 Y0

S0
Y1 En 0 Y2 1 1 Y3 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 Y3 0 0 0 0 D Y2 0 0 0 D 0 Y1 0 0 D 0 0 Y0 0 D 0 0 0

En

D
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Application Example
A multiplexer/demultiplexer arrangement for information transmission
1-to-4 DEMUX

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Decoders
A n-to-2n-line decoder is a circuit in which only one of the output line responds to the n select lines(input) Number of input:output is n:2n (Note: a demultiplexer is a decoder with an enable input acting as a data input line)

Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

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Logic Diagram of a 2-to-4 line Decoder

S1 S0 Y0

Y1

Y2

Y3

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3-to-8-line Decoder

Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

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Prepared by Jasmine K S, HOS(E&C),GPTC,PBVR

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3-to-8-line Decoder

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Encoders
Number of input:output is 2n:n

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inputs
X0 X1

Z0
0 0

Z1
0 0

Z2
0 1

X2
X3 X4 X5 X6 X7

0
0 1 1 1 1

1
1 0 0 1 1

0
1 0 1 0 1

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