CPE/EE 427, CPE 527 VLSI Design I Complementary CMOS Logic Gates

Department of Electrical and Computer Engineering University of Alabama in Huntsville

Aleksandar Milenkovic ( www.ece.uah.edu/~milenka )

Static CMOS Logic

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CMOS Circuit Styles

Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path
high noise margins
full rail to rail swing VOH and VOL are at VDD and GND, respectively

low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions)

Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes
simpler, faster gates increased sensitivity to noise
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Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)
VDD PMOS transistors only In1 In2 InN In1 In2 InN PDN PUN pull-up: make a connection from VDD to F when F(In1,In2,InN) = 1 F(In1,In2,InN) pull-down: make a connection from F to GND when F(In1,In2,InN) = 0 NMOS transistors only

PUN and PDN are dual logic networks

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Threshold Drops
PUN VDD VDD 0 CL 0 CL VDD

PDN VDD

VDD CL

VDD CL

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Threshold Drops
PUN VDD
S

VDD
D

VDD
D

0 VDD CL

VGS

0 VDD - VTn CL

PDN
D

VDD 0 CL

VGS

VDD |VTp|
S

VDD
S

CL

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Construction of PDN
NMOS devices in series implement a NAND function
AB A B

NMOS devices in parallel implement a NOR function

A+B A B

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Dual PUN and PDN

PUN and PDN are dual networks
DeMorgans theorems
A+B=AB AB=A+B [!(A + B) = !A !B or !(A | B) = !A & !B] [!(A B) = !A + !B or !(A & B) = !A | !B]

a parallel connection of transistors in the PUN corresponds to a series connection of the PDN

Complementary gate is naturally inverting (NAND, NOR, AOI, OAI) Number of transistors for an N-input logic gate is 2N

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CMOS NAND
A 0 0 1 1 B 0 1 0 1 F 1 1 1 0

AB A B A B

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CMOS NAND
Vdd

NAND B F = NAND(A,B) A
B F

GND

Vdd

Vdd

Vdd

Vdd

B=0

F=1 B=0

F=1

B=1

F=1

B=1

F=0

A=0

A=1

A=0

A=1

GND

GND

GND

GND

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CMOS NOR

B A A+B A B

A 0 0 1 1

B 0 1 0 1

F 1 0 0 0

A B

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CMOS NOR
Vdd A

NOR B F = NOR(A,B) A

B F

GND Vdd A=0 A=0 Vdd A=1 Vdd A=1 Vdd

B=0 F=1

B=1 F=0

B=0 F=0

B=1 F=0

GND

GND

GND

GND

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Complex CMOS Gate

OUT = !(D + A (B + C)) A D B C

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Complex CMOS Gate

B A C D OUT = !(D + A (B + C)) A D B C

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XNOR/XOR Implementation
XNOR A B AB A B AB XOR

A B AB

A B AB

How many transistors in each? Can you create the stick transistor layout for the lower left circuit?
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Combinational Logic Cells CMOS logic cells

AND-OR-INVERT (AOI) OR-AND-INVERT(OAI)
2 A B C Z

AOI221
And Or Inverter

2 Example: AOI221 D E 1 Z = (A*B + C*D + E) Z = AOI221(A, B, C, D, E) Exercise: Construct this logic cell? Example: OAI321 Z = [(A+B+C)*(D+E)*F] Z = OAI321(A, B, C, D, E, F) Exercise: Construct this logic cell?

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AOI221
Vdd A B

Z A C E B D

GND
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Standard Cell Layout Methodology

Routing channel VDD

signals

GND

What logic function is this?

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OAI21 Logic Graph

A j B X = !(C (A + B)) C A i B A B C X B i C

X C

PUN

VDD j A PDN

GND

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Two Stick Layouts of !(C (A + B))

A VDD

C VDD

GND

GND

uninterrupted diffusion strip

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Consistent Euler Path

An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each edge is visited once and only once.

C X B i A VDD j GND

For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
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Consistent Euler Path

An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each edge is visited once and only once.

C X B i A A B C VDD j GND

For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)
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OAI22 Logic Graph

A B

C D X = !((A+B)(C+D)) X B A B C D D

X C

PUN

VDD A PDN

C A

D B

GND

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OAI22 Layout
A VDD B D C

GND

Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)
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Combinational Logic Cells (contd) The AOI family of cells with 3 index numbers or less
X = {AOI, OAI, AO, OA}; a,b,c={2,3}
Cell Type Xa1 Xa11 Xab Xab1 Xabc Total
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Cells X21, X31 X211, X311 X22, X33, X32 X221, X321, X331 X222, X333, X332, X322

Number of Unique Cells 2 2 3 3 4 14

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VTC is Data-Dependent
3

M3 B

M4

0.5/0.25 NMOS 0.75 /0.25 PMOS

F= A B
D

2
weaker PUN

A,B: 0 -> 1 B=1, A:0 -> 1 A=1, B:0->1

A
VGS2 = VA VDS1

M2 M1
S

S D

1
Cint

B
VGS1 = VB

0 0 1 2

The threshold voltage of M2 is higher than M1 due to the body effect ()

VTn1 = VTn0 VTn2 = VTn0 + ((|2F| + Vint) - |2F|) since VSB of M2 is not zero (when VB = 0) due to the presence of Cint
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Static CMOS Full Adder Circuit

B A B B A Cin A A B B A B Cin A B Cin A Cin !Sum Cin A B

!Cout

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Static CMOS Full Adder Circuit

!Cout = !Cin & (!A | !B) | (!A & !B) !Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin) B A B B A Cin A A B B A B Cin A B Cin A Cin !Sum Cin A B

!Cout

Cout = Cin & (A | B) | (A & B)

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Sum = !Cout & (A | B | Cin) | (A & B & Cin)

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