CAD LAB (EEC-653)

EXPERIMENT NO. 1

OBJECT:- Transient analysis of BJT Inverter using step input. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:A BJT inverter is a simple CE switch as shown in Figure 1 (a). When the input voltage Vi is LOW, the output voltage is VO is HIGH and vice-versa. Its voltage transfer characteristics are such as shown in Figure 1 (b). The noise margins NM can be determined from the transfer characteristics as follows: NMH=VOH VIH ,(Volts) NML=VIL VOL ,(Volts) The higher noise margins, the higher are the immunity of the logic gate to unwanted signals(noise).

CIRCUIT DIAGRAM:VCC 5V VCC R1 1k XMM1

2 Q1 4 R2 1 BC107BP 3 R3 1k 0 V1 1k 0.5 V 0 0

Figure 1 : The BJT inverter and its transfer characteristics

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CAD LAB (EEC-653)

OBSERVATIONS:Vin (Input Voltage in Volts) 0V 0.5 V 1.0 V 1.5 V 2.0 V 2.5 V 3.0 V 3.5 V 4.0 V 4.5 V 5.0 V Vout (Output Voltage in Volts) 5V 4.996 V 4.616 V 4.141 V 3.656 V 3.168 V 2.679 V 2.616 V 2.770 V 2.931 V 3.094 V

RESULT:- Study of transient analysis of BJT Inverter using step input

has been done.

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CAD LAB (EEC-653)

EXPERIMENT NO.02

OBJECT:- Transient analysis of BJT Inverter using NPN Transistor. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it useful in analog electronics as a class A amplifier (e.g., as the output stage of an operational amplifier . Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

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CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC VCC 5V R3 130 R1 4k 2 9 Q1 BC107BP V1 0V 0 D2 1N4007 8 R5 1k 10 0 BC107BP 1 BC107BP 5 Q4 R2 1.8k 3 Q2 BC107BP 6 D1 1N4007 R4 100 7 0 LED1 4 Q3

OBSERVATIONS:Input (A) L H Output (Y) H L

RESULT:- Study of transient analysis of BJT Inverter using NPN

Transistor has been done.

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CAD LAB (EEC-653)

EXPERIMENT NO.03

OBJECT:- Transient Analysis of NMOS inverter using step input. APPARATUS REQUIRED:- Multisim v.10.0 THEORY:For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.Once the operation and characterization of an inverter circuit sare thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. N-type metal-oxide-semiconductor logic uses n-type metal-oxidesemiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

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CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VDD 10V VDD R1 10k 0 1 Q1 2 V1 3.3 V 0 MTD4N20E 0 0 C1 20pF XMM1

OBSERVATIONS:Sr.no. 1. 2. 3. 4. 5. 6. Input(V1) in volts 0V 1V 2V 3V 4V 5V Output(Vo) in volts 9.99 V 9.991 V 9.992 V 9.993 V 1.876mV 936.64uV

RESULT:- Study of transient Analysis of NMOS inverter using step

input has been done.

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CAD LAB (EEC-653)

EXPERIMENT NO.04

OBJECT:-

Transient Analysis of NMOS inverter using pulse input.

APPARATUS REQUIRED:- Multisim v.10.0. THEORY:For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuit thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. N-type metal-oxide-semiconductor logic uses n-type metal-oxidesemiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

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CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VDD 10V VDD XFG1

Agilent

XSC1
Ext Trig + _ A + _ + B _

R1 10k 1 0 Q1 2 MTD4N20E 0 0 C1 20pF

OBSERVATIONS:-

Result:- Study of Transient Analysis of NMOS inverter using pulse

input has been done.
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CAD LAB (EEC-653)

EXPERIMENT NO.05

OBJECT:- Transient Analysis of CMOS inverter using step input. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistor-transistor logic (RTL) or a transistor-transistor logic (TTL) configuration. Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

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CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC 10V VCC R1 1k 2 Q2 XMM1

2N6804 0 1 Q1

V1 5 V 0

MTD4N20E 0

OBSERVATIONS:Input (V1) in volts 0V 1V 2V 3V 4V 5V Output (Vo) in volts 9.99 V 9.991 V 9.992 V 9.993 V 1.876mV 936.64uV

RESULT:-

Study of transient Analysis of CMOS inverter using step input has been done.

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CAD LAB (EEC-653)

EXPERIMENT NO.06

OBJECT:- Transient Analysis of CMOS inverter using pulse input. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistor-transistor logic (RTL) or a transistor-transistor logic (TTL) configuration. Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

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CIRCUIT DIAGRAM:VCC 10V VCC R1 1k 2 Q2 XFG1

Agilent

XSC1
Ext T rig +

3 0

2N6804 1
+

_ A _ + B _

0 Q1

MTD4N20E 0

OBSERVATIONS:-

RESULT:- Study of Transient Analysis of CMOS inverter using pulse

input has been done.
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CAD LAB (EEC-653)

EXPERIMENT NO.07

OBJECT:- Transient & D.C. Analysis of NOR gate using n-p-n transistor. APPARATUS REQUIRED:- Multisim V.10.0. THEORY:The NOR gate is a digital logic gate that implements logical NOR it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa. In most, but not all, circuit implementations, the negation comes for freeincluding CMOS and TTL. In such logic families, OR is the more complicated operation; it may use a NOR followed by a NOT. A significant exception is some forms of the domino logic family. The original Apollo Guidance Computer used 4,100 ICs, each one containing only a single 3-input NOR gate.

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CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC 5V VCC R2 100 1 3 R3 4.7k R1 V1 5V 0 0 4 4.7k V2 5V BC107BP R5 100k 0 Q1 5 R4 100 2

LED1 0

OBSERVATIONS:INPUT (A) L L H H INPUT (B) L H L H OUTPUT (Y) H L L L

RESULT:- Study of transient & D.C. Analysis of NOR gate using n-p-n
transistor has been done.
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CAD LAB (EEC-653)

EXPERIMENT NO.08

OBJECT:- Transient &D.C. analysis of NAND Gate using NPN transistor. APPARATUS REQUIRED:- Multisim V.10.0. THEORY:The Negated AND, NOT AND or NAND gate is the opposite of the digital AND gate, and behaves in a manner that corresponds to the opposite of AND gate, as shown in the truth table on the right. A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results. The NAND gate is significant because any boolean function can be implemented by using a combination of NAND gates. This property is called functional completeness. Digital systems employing certain logic circuits take advantage of NAND's functional completeness. In complicated logical expressions, normally written in terms of other logic functions such as AND, OR, and NOT, writing these in terms of NAND saves on cost, because implementing such circuits using NAND gate yields a more compact result than the alternatives[1] . NAND gates can also be made with more than two inputs, yielding an output of LOW if all of the inputs are HIGH, and an output of HIGH if any of the inputs is LOW. These kinds of gates therefore operate as nary operators instead of a simple binary operator. Algebraically, these can be expressed as the function NAND(a, b, ..., n), which is logically equivalent to NOT(a AND b AND ... AND n).

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CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC 5V VCC R3 4.7 R4 4 Q1 6 V1 5V 0 R1 10k BC107BP 1 Q2 7 V2 0V 0 R2 10k BC107BP 0 3 2 600 5 0

LED1

OBSERVATIONS:Input (A) L L H H Input (B) L H L H Output (Y) H H H L

RESULT:- Study of Transient &D.C. analysis of NAND Gate using n-pn transistor has been done.

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CAD LAB (EEC-653)

EXPERIMENT NO.09

OBJECT:- To implement FULL ADDER using VHDL. APPARATUS REQUIRED:BLOCK DIAGRAM:VHDL Software.

TRUTH TABLE:a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1

rd

S(sum) 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1
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VHDL CODE:LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY full_adder IS PORT(x: IN std_logic ; y: IN std_logic ; cin: IN std_logic ; cout: OUT std_logic ; sum: OUT std_logic ); END full_adder ; ARCHITECTURE equations OF full_adder IS BEGIN sum <= x XOR y XOR cin ; cout <= (x AND y) OR (x AND cin) OR (y AND cin) ; END ;

RTL SCHEMATIC:-

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SIMULATION WAVEFORMS:-

RESULT:- Implementation of

FULL ADDER using VHDL has been done.

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CAD LAB (EEC-653)

EXPERIMENT NO.10
OBJECT:- To implement FULL SUBTRACTOR using VHDL. APPARATUS REQUIRED:- VHDL Software. BLOCK DIAGRAM:-

TRUTH TABLE:-

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

diff 0 1 1 0 1 0 0 1

bout 0 1 1 1 0 0 0 1

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VHDL CODE:library IEEE; library IEEE.STD_LOGIC_1164.ALL; entity FULL SUBTRACTOR is port ( a: in STD_LOGIC, b: in STD_LOGIC, bin: in STD_LOGIC; bout: out STD_LOGIC, diff: out STD_LOGIC); end FULL SUBTRACTOR; architecture behavior of FULL SUBTRACTOR is begin P9: process (a, b, bin) variable temp1, temp2, temp3, temp4, temp5: STD_LOGIC; begin temp1 := not a; temp2 := a xor b; temp3 := temp1 and b; temp4 := temp1 and bin; temp5 := b and bin; bout <= temp3 or temp4 or temp5; diff <= temp2 xor bin; end process P9; end behaviour;

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RTL SCHEMATIC:-

SIMULATION WAVEFORMS:-

RESULT:- Implementation of
been done.

FULL SUBTRACTOR using VHDL has

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CAD LAB (EEC-653)

EXPERIMENT NO.11

OBJECT:- To implement 8*1 MULTIPLEXER using VHDL. APPARATUS REQUIRED:- VHDL Software. BLOCK DIAGRAM:-

TRUTH TABLE:S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Z 7 6 5 4 3 2 1 0

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VHDL CODE:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8x1 is Port ( i : in std_logic_vector(7 downto 0); s : in std_logic_vector (2 downto 0); y : out std_logic ); end mux8x1; architecture Behavioral of mux8x1 is begin process (i,s) begin if (s = "000") then y <= i(0); elsif (s = "001") then y <= i(1); elsif (s = "010") then y <= i(2); elsif (s = "011") then y <= i(3); elsif (s = "100") then y <= i(4); elsif (s = "101") then y <= i(5); elsif (s = "110") then y <= i(6); else y <= i(7); end if; end process; end Behavioral;

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RTL SCHEMATIC:-

SIMULATION WAVEFORMS:-

RESULT:- Implementation of 8*1 MULTIPLEXER using VHDL has been

done.
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CAD LAB (EEC-653)

EXPERIMENT NO.12

OBJECT:- To implement 2*4 DECODER using VHDL. APPARATUS REQUIRED:- VHDL Software. BLOCK DIAGRAM:-

TRUTH TABLE:A(1) 0 0 1 1 A(0) 0 1 0 1 D(3) 0 0 0 1 D(2) 0 0 1 0 D(1) 0 1 0 0 D(0) 1 0 0 0

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VHDL CODE:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2x4 is port (sel: in std_logic_vector (1 downto 0); e: in std_logic; y: out std_logic_vector (3 downto 0)); end decoder2x4; architecture Behavioral of decoder2x4 is begin process(e,sel) begin if(e='0') then if(sel = "00") then y <= "0111" ; elsif(sel = "01") then y <= "1011" ; elsif(sel = "10") then y <= "1101" ; else y <= "1110" ; end if; else y <= "1111"; end if; end process; end Behavioral;

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CAD LAB (EEC-653)

RTL SCHEMATIC:-

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SIMULATION WAVEFORMS:-

RESULT:- Implementation of 2*4 DECODER using VHDL has been

done.

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