Dell Mini 10 - Compal La-5091p Kiu20 - Rev 1.0sec

A
MODEL )AME : KIU20

PCB )O : LA-5091P (DA60000BR10)
BOM P/) : 43169831L02
1
Compal Confidential
Bear Schematics Document
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
2009-3-31
REV: 1.0
3
@ : Nopop Component
1@ : For N280 only
2@ : For N270 only
Date:
LA-5091P
Wednesday, April 22, 2009
Sheet
E
ho
f@
Cover Page
Size
Document Number
Custom
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Classification
tm
ai
l.c
om
of
39
Compal Confidential
Thermal Sensor
Diamondville SC
Model )ame : KIU20

File )ame : LA-5091P
EMC1402
FCBGA8
437Pins
22x22mm
Clock Generator
CK505
page 12
page 4,5
FSB
H_A#(3..31)
CRT Conn
page 4
H_D#(0..63)
400/533MHz
Memory BUS(DDRII)
Calistoga GSE
FCBGA998
page 14
page 19
DDRII-SO-DIMM
page 11
1.8V DDRII 400/533
LVDS
LCD Conn.
WWA
Port 4
RGB
Port 6
WLA
27x27mm
page 13
page 19
page 6,7,8,9,10
DMI
X2 mode
Port 0
USB Port X1
PWR page 27
USB
PCI-Express
ICH7M
BGA652
SATA
31x31mm
HDA
USB daughter board

Port 3
page 15,16,17,18
page 27
Port 7
page 22
RTL8103EL
WLA
USB Port X1
2.5" HDD
10/100 Ethernet
MII Card
USB Port X1
page 27
page 19
page 24
LPC BUS
Audio Codec
page 20
RJ45
Through BT cable
AMP & Speaker
ALC272-VB-GR
page 21
Port 5
BlueTooth
page 24
Power O/OFF
DC/DC Interface
DC I
3VALW/5VALW
page 26
EE KBC
KB926page
page 30
page 19
HeadPhone &
MIC Jack
SPI
page 21
Through LVDS cable
25
Port 1
page 30
BATT CO/OTP
page 36
CHARGER
4
page 31
LED CO
page 22
CMOS CAM
page 32
page 13
Int.KBD
1.5VS/0.9VS/
2.5VS
page 25
Touch Pad
page 26
SPI ROM
page 26
Card Reader
RTS5159
SD/MMC/MS
Port 2
page 34
page 23
1.8V/VCCP
page 33
CPU CORE
2008/11/10
Issued Date
Compal Secret Data
page 35
2009/11/10
Deciphered Date
A
Title
Block Diagrams
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
E
of
39
ZZZ
PCB
DA60000BR10
1
Voltage Rails
S3
External PCI Devices
Power Plane
Description
S1
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
+VCCP
VCCP switched power rail
ON
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+2.5VS
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VS
VS always on power rail
ON
ON
ON*
+RTCBATT
RTC power
ON
ON
ON
S5
DEVICE
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
REQ/GNT #
PIRQ
No PCI Device
EC SM Bus1 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
IDSEL #
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011X b
EMC1402
1001 100X b
EEPROM(24C16/02)
1010 000X b
Clock
Full ON
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
S3 (Suspend to RAM)
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
ICH7M SM Bus address

BOARD ID Table(Page 25)
ID
0
1
2
3
BRD ID
R01 (SSI)
R02 (ST)
R10 (X build)
R10A (MP)
Ra
NC
100K
100K
100K
Rb
0
8.2K
18K
NC
Vab
0V
0.25V
0.50V
3.3V
Device
Address
Clock Generator
(SLG8SP556VTR)
1101 001Xb
DDR DIMMA
1010 000Xb
ho
f@
Notes List
Size
Document Number
Custom
Date:
LA-5091P
in
Title
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
Sheet
E
of
39
T7 PAD
<16>
<16>
<16>
<16>
<16>
<16>
<16>
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D6
G6
H6
K4
K5
M15
L16
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
BR1#
PROCHOT#
THRMDA
THRMDC
THERMTRIP#
T21
T19
Y18
H_DEFER#
H_DRDY#
H_DBSY#
H_DEFER# <6>
H_DRDY# <6>
H_DBSY# <6>
T20
H_BR0#
F16
V16
H_IERR#
H_INIT#_R
W20
H_LOCK#
H_LOCK#
D15
W18
Y17
U20
W19
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_RESET#
AA17
V20
H_HIT#
H_HITM#
H_HIT#
H_HITM#
K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
BR1#
G17
E4
E5
H_PROCHOT#_R
H_THERMDA
H_THERMDC
R201
56_0402_5%
2
H_BR0#
R27
330_0402_5%
2 1K_0402_5%
<6>
H_INIT#
<16>
Close to CPU
<6>
H_RS#[0..2]
<6>
<6>
<6>
<6>
<6>
<6>
H17
H_THERMTRIP#
V11
V12
CLK_CPU_BCLK
CLK_CPU_BCLK#
1
R202
H_PROCHOT#
<35>
<6>
<6>
<6>
Close to CPU
H_THERMTRIP#
H_DSTBN#1
H_DSTBP#1
H_DINV#1
T13 PAD
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DP#0
Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_DP#1
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
<6,16>
+CPU_GTLREF
BCLK[0]
BCLK[1]
H_DSTBN#0
H_DSTBP#0
H_DINV#0
T10 PAD
H_D#[16..31]
<6>
<6>
2
22_0402_5%
CLK_CPU_BCLK <12>
CLK_CPU_BCLK# <12>
R240 1
R239 1
@
@
2 1K_0402_5%
2 1K_0402_5%
ACLKPH
DCLKPH
+CPU_EXTBGREF
C21
C1
A3
RSVD3
RSVD2
RSVD1
H_D#[32..47]
U5B
<6>
R33 1
H_TRDY#
H_D#[0..15]
+VCCP
<6>
<6>
<6>
H_ADS#
H_BNR#
H_BPRI#
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
<12> CPU_BSEL0
<12> CPU_BSEL1
<12> CPU_BSEL2
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
GTLREF
ACLKPH
DCLKPH
BINIT#
MISC
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
+VCCP
+VCCP
H_A20M#
H_IGNNE#
H_DPRSTP#
H_DPSLP#
H_PWRGOOD
H_SMI#
H_NMI
H_INTR
+VCCP
JITP3
BR1#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
H_RESET# 1
@ R103
PREQ#
H_RESET_R#
2
124_0402_1%~D ITP_TCK
<12> CPU_ITP
<12> CPU_ITP#
ITP_TDO
1
2
@ R105
22.6_0402_1%
ITP_TCK
ITP_TRST#
ITP_TMS
ITP_TDI
T1
T2
F20
F21
COMP0
COMP1
COMP2
COMP3
R18
R17
U4
V17
N18
A13
B7
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DINV#2 <6>
PAD T15
H_D#[48..63]
<6>
H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DINV#3 <6>
PAD T12
1
1
2
2
R57
R58
R208
R209
2
2
1
1
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
H_DPRSTP# <16,35>
H_DPSLP# <16>
H_DPWR# <6>
H_PWRGOOD <16>
H_CPUSLP# <6>
+CPU_CMREF
1
R49
2K_0402_1%
1
C65
0.1U_0402_16V4Z
Close to CPU pin

within 500mils.
Zo=55ohm
Close to CPU pin

within 500mils.
Zo=55ohm
H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil
+VCCP
+3VS
CPU THERMAL SENSOR
@
R158
1K_0402_1%
H_DPWR#
@
R136
2K_0402_1%
C351
1
2
1
C352
U17
2
1
H_THERMDA
H_THERMDC
2200P_0402_50V7K
3
4
VDD
SMCLK
DP
SMDATA
DN
ALERT#
THERM#
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2
<25>
EC_SMB_DA2
<25>
R304 1
10K_0402_5%
+3VS
GND
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
MOLEX_52435-2891_28P~D
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
4
Zo=27.4ohm +/-15%, make

than 0.5"
Zo=55ohm +/-15%, make
than0.5"
1
2
Close to CPU pin

within 500mils.
Zo=55ohm
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
@
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
H_DP#3
ITP_TCK
ITP_TRST#
2 56_0402_5%
2 56_0402_5%
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R238
2K_0402_1%
0.1U_0402_16V4Z
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z~D
1
1
1
1
1
1
1
1
C342
R48
2K_0402_1%
R28
R32
R113
R124
R135
R286
R287
R288
1
C62
0.1U_0402_16V4Z
@
@
@
@
@
@
ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
56_0402_5%
56_0402_5%
56_0402_5%
56_0402_5%
2
R213 1
R218 1
2
2
2
2
29
1
1
1
1
GND6
+VCCP
R200
R198
R206
R199
R51
1K_0402_1%
+CPU_CMREF
GND7
H_A#32
H_A#33
H_A#34
H_A#35
30
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
R234
1K_0402_1%
+CPU_EXTBGREF
This shall place near CPU

2
2
2
2
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
CORE_DET
CMREF[1]
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4
<6>
R47
1K_0402_1%
+CPU_GTLREF
+VCCP
1
1
1
1
COMP[0]
COMP[1]
COMP[2]
COMP[3]
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_DP#2
Layout note:
COMP0,2 connect with
trace length shorter
COMP1,3 connect with
trace length shorter
+VCCP
CPU N270 P/N: SA00002O31L

CPU N280 P/N: SA000031F1L
R34
R30
R31
R29
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3
R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4
AU80586GE025D_FCBGA437
+VCCP
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2
DATA GRP 2
CONTROL
U18
T16
J4
R16
T15
R15
U17
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
THERM
XDP/ITP SIGNALS
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
IERR#
INIT#
H_ADS#
H_BNR#
H_BPRI#
DATA GRP 1
H_ADSTB#1
C19
F19
E21
A16
D19
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18
BR0#
ADDR GROUP 1
<6>
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1
DEFER#
DRDY#
DBSY#
+VCCP
V19
Y19
U21
H CLK
<6> H_A#[17..31]
ADS#
BNR#
BPRI#
NC
T5 PAD
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
AP0
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
DATA GRP 0
<6> H_ADSTB#0
<6> H_REQ#[0..4]
P21
H20
N20
R20
J19
N19
G20
M19
H21
L20
M20
K19
J20
L21
K20
D17
N21
J21
G19
P20
R19
ADDR
GROUP
0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_AP0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
DATA GRP 3
<6>
U5A
H_A#[3..16]
<6>
Title
Diamondville(1/2)
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
of
39
1
+
C57
PLACE IN CAVITY
F14
F13
E14
E13
VCCPC64
VCCPC63
VCCPC62
VCCPC61
+1.5VS
130mA
D7
VCCA
VCCSENSE
VSSSENSE
F15
D16
E18
G15
G16
E17
G18
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
C13
VCCSENSE
D13
VSSSENSE
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
<35>
<35>
<35>
<35>
<35>
<35>
<35>
C338
0.1U_0402_10V7K~D
+CPU_CORE
1
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
R221
100_0402_1%
2
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
C341
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
220U_B2_2.5VM_R35
+CPU_CORE
C337
VCCQ1
VCCQ2
1U_0402_6.3V6K
VCCF
C307
A9
B9
1U_0402_6.3V6K
+VCCP
V10
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
C295
VCCSENSE
<35>
VSSSENSE
<35>
Length match within 25 mils

The trace space 7 mils,
Zo=27.4ohm
R220
100_0402_1%
2
N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
0.1U_0402_10V7K~D
+VCCP
U5C
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
0.1U_0402_10V7K~D
VSS1
VSS2
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS41
VSS42
VSS45
VSS46
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
U5D
A2
A4
A8
A15
A18
A19
A20
B1
B2
B5
B8
B13
B20
B21
C8
C17
D1
D5
D8
D14
D18
D21
E3
E6
E7
E8
E15
E16
E19
F4
F5
F6
F7
F17
F18
G1
G4
G7
G9
G13
G21
H3
H4
H7
H9
H13
H16
H18
H19
J5
J7
J9
J13
J17
K1
K6
K7
K9
K13
K15
K21
L3
L4
L5
L6
L7
L9
L13
L15
L18
L19
M1
M5
M7
M9
M13
M21
N4
+CPU_CORE
+CPU_CORE
PLACE IN CAVITY
1U_0402_6.3V6K
C308
C309
C310
1U_0402_6.3V6K
1
C311
C312
2 x 330uF(9mohm/2)
1U_0402_6.3V6K
1
C313
C314
1U_0402_6.3V6K
1
C320
C321
1U_0402_6.3V6K
1
C322
C323
1U_0402_6.3V6K
1
C324
C326
1U_0402_6.3V6K
1
C327
1U_0402_6.3V6K
C325
C315
+ C51
330U 2.5V Y
2
2
1U_0402_6.3V6K
2
1U_0402_6.3V6K
10U_0805_10V4Z~D
C298
C299
2
10U_0805_10V4Z~D
C300
2
1U_0402_6.3V6K
10U_0805_10V4Z~D
1
C301
2
10U_0805_10V4Z~D
C302
2
1U_0402_6.3V6K
10U_0805_10V4Z~D
1
C46
2
10U_0805_10V4Z~D
C304
2
1U_0402_6.3V6K
10U_0805_10V4Z~D
1
C303
C335
10U_0805_10V4Z~D
2
1U_0402_6.3V6K
10U_0805_10V4Z~D
1
C47
10U_0805_10V4Z~D
C328
2
1U_0402_6.3V6K
+ C331
2
330U 2.5V Y
1U_0402_6.3V6K
10U_0805_10V4Z~D
1
C334
10U_0805_10V4Z~D
PLACE IN CORRIDOR AND CLOSE TO CPU

A
ho
f@
Diamondville(2/2)
Size
Document Number
Custom
Date:
in
Title
LA-5091P
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
Sheet
1
of
39
H_XRCOMP
H_XSCOMP
+H_SWNG0
H_YRCOMP
H_YSCOMP
+H_SWNG1
R182
24.9_0402_1%
2
1
A10
A6
C15
J1
K1
H1
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
F10
C12
H16
E2
B9
C7
G8
B10
E1
H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#
<4>
U1B
<17>
<17>
<17>
<17>
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
<11> M_CLK_DDR0
<11> M_CLK_DDR1
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
M_CLK_DDR0
M_CLK_DDR1
Y29
Y32
Y28
Y31
V28
V31
V29
V32
AF33
AG1
AJ1
AM30
<11> M_CLK_DDR#0
<11> M_CLK_DDR#1
M_CLK_DDR#0
M_CLK_DDR#1
AG33
AF1
AK1
AN30
<11> DDR_CKE0
<11> DDR_CKE1
H_ADS#
<4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
<11> DDR_CS0#
<11> DDR_CS1#
DDR_CKE0
DDR_CKE1
AN21
AN22
AF26
AF25
DDR_CS0#
DDR_CS1#
AG14
AF12
AK14
AH12
H_BNR#
<4>
H_BPRI# <4>
H_BR0#
<4>
H_RESET# <4>
AJ21
AF11
CLK_MCH_BCLK# <12>
CLK_MCH_BCLK <12>
H_DBSY# <4>
H_DEFER# <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
H_DPWR# <4>
H_DRDY# <4>
<11>
<11>
+1.8V
R232 1
1
R228
+DIMM_VREF
H_DSTBN#[0..3]
<4>
H_DSTBP#[0..3]
<4>
H_HIT#
H_HITM#
H_LOCK#
M_ODT0
M_ODT1
2 80.6_0402_1%
2
80.6_0402_1%
M_ODT0
M_ODT1
AE12
AF14
AJ14
AJ12
SMRCOMPN
SMRCOMPP
AN12
AN14
AA33
AE1
10uA
1
<4>
<4>
<4>
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
C18
E18
G20
G18
J20
J18
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
SM_CK_0
SM_CK_1
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
Layout Note:
+DIMM_VREF trace
width and spacing
is 20/20.
1
R181
E31
G21
F26
H26
J15
AB29
W27
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
PM_EXTTS#1
H_THERMTRIP#
ICH_POK_EC
PLTRST_R#
2.2K_0402_5%
2
R203
1
0_0402_5%
1
R211
2
100_0402_5%
MCH_ICH_SYNC#
<15>
PM_BMBUSY# <17>
PM_EXTTS#0 <11>
PM_DPRSLPVR <17,35>
H_THERMTRIP# <4,16>
ICH_POK_EC <17,25>
PLTRST# <15,17,19,24,25>
CLK_MCH_DREFCLK#
<12>
CLK_MCH_DREFCLK
<12>
MCH_SSCDREFCLK#
<12>
MCH_SSCDREFCLK
<12>
MCH_CLKREQ# <12>
Calistoga-GSE_FCBGA998
+1.8V
Strap Pin Table

Low
CFG5
R41
<4>
A27
A26
J33
H33
J22
D_REFCLKN
D_REFCLKP
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
= DMI x 2
High = DMI x 4
1K_0402_1%
H_REQ#[0..4]
<12>
<12>
<12>
SM_OCDCOMP_0
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
CFG5
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
K32
K31
C17
F18
A3
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
SM_CK_2
SM_CK_3
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG/RSVD
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI
<17>
<17>
<17>
<17>
PM
HCLKN
HCLKP
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
CLK
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
DDR2 MUXING
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
+DIMM_VREF
1
R6
54.9_0402_1%
2
1
+VCCP
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
C53
H_RS#[0..2]
<4>
H_CPUSLP# <4>
H_TRDY# <4>
R43
1K_0402_1%
2
R7
24.9_0402_1%
2
1
H_A#[3..31]
U1A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R175
54.9_0402_1%
2
1
H_D#[0..63]
HOST
<4>
0.1U_0402_16V4Z
Share +DIMM_VREF for

1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1
+3VS
PM_EXTTS#0
PM_EXTTS#1
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
+VCCP
1
R187
1
@ R188
2
10K_0402_5%
2
10K_0402_5%
+VCCP
1
R180
2
221_0402_1%~D
1
2
221_0402_1%~D
R167
100_0402_1%
+H_SWNG1
C251
0.1U_0402_16V4Z
1
R178
2
100_0402_1%
C240
0.1U_0402_16V4Z
1
2
C50 be placed <100mils

from GMCH pin
R166
C243
0.1U_0402_16V4Z
100_0402_1%
2
1
2
+H_SWNG0
+H_VREF
200_0402_1%
R174
R176
+VCCP
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
5
Title
Calistoga(1/5)-GTL/DMI/DDR
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
of
39
U1C
<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2
<11> DDR_A_DM[0..7]
<11> DDR_A_DQS[0..7]
<11> DDR_A_DQS#[0..7]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AK12
AH11
AG17
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AB30
AL31
AF30
AK26
AL9
AG7
AK5
AH3
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AC28
AJ30
AK33
AL25
AN9
AH8
AM2
AE3
DDR_A_DQS#0 AC29
DDR_A_DQS#1 AK30
DDR_A_DQS#2 AJ33
DDR_A_DQS#3 AM25
DDR_A_DQS#4 AN8
DDR_A_DQS#5
AJ8
DDR_A_DQS#6 AM3
DDR_A_DQS#7 AE2
<11> DDR_A_MA[0..13]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
<11> DDR_A_CAS#
<11> DDR_A_RAS#
T9 PAD
T8 PAD
<11> DDR_A_WE#
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
AJ17
AK18
AN28
AM28
AH17
AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
DDR2 SYSTEM MEMORY
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
SB_WE#
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
<11>
AG19
AG21
AG20
ho
f@
Calistoga(2/5)-DDR2
Size
Document Number
Custom
Date:
in
Title
LA-5091P
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
Sheet
1
of
39
U1F
GMCH_CRT_B
<14> GMCH_CRT_CLK
<14> GMCH_CRT_DATA
<14> GMCH_CRT_B
<14> GMCH_CRT_G
<14> GMCH_CRT_R
Close to U1.H25
R183 2
1 255_0402_1%
<14> GMCH_CRT_VSYNC
<14> GMCH_CRT_HSYNC
R171 2
2
R184
<13> EDID_CLK_LCD
<13> EDID_DAT_LCD
<13> GMCH_LVDDEN
1
1.5K_0402_1%
<13> LVDSAC<13> LVDSAC+
<13> LVDSA0<13> LVDSA1<13> LVDSA2<13> LVDSA0+

<13> LVDSA1+
<13> LVDSA2+
+3VS
1
R192
1
R191
GMCH_CRT_G
GMCH_CRT_R
CRT_IREF
1 100K_0402_5%
<25> GMCH_ENBKL
GMCH_CRT_B
LCTLA_CLK
LCTLB_DATA
EDID_CLK_LCD
EDID_DAT_LCD
L_IBG
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
LVDSACLVDSAC+
D30
C30
A30
A29
LVDSA0LVDSA1LVDSA2-
G31
F32
D31
LVDSA0+
LVDSA1+
LVDSA2+
H31
G32
C31
F33
D33
F30
LCTLA_CLK
2
10K_0402_5%
LCTLB_DATA
2
10K_0402_5%
E33
D32
F29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
VGA
R9
<12> CLK_MCH_3GPLL#
<12> CLK_MCH_3GPLL
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
R28
M28
PEGCOMP
+1.5VS_PCIE
R190
24.9_0402_1%
2
N30
R30
T29
M30
P30
T30
P28
N32
P32
T32
N28
M32
P33
R32
+1.5VS
TV
GMCH_CRT_G
1
150_0402_1%
1
150_0402_1%
2
1
150_0402_1%
MISC
GMCH_CRT_R
EXP_A_COMPI
EXP_A_ICOMPO
SDVO
R8
SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLKN
G_CLKP
LVDS
R10
H27
J27
Y26
AA26
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_DCONSEL0
TV_DCONSEL1
A21
C20
E20
G23
B21
C21
D21
Disable TV
G26
J26
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
5
Title
Calistoga(3/5)-VGA/LVDS
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
of
39
+1.5VS
U1E
+VCCP
T10
R10
P10
N10
L10
D1
M10
A18
AB10
AA10
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
AH33
Y33
V33
R33
G33
AK32
AG32
AE32
AC32
AA32
U32
H32
E32
C32
AM31
AJ31
AA31
U31
T31
R31
P31
N31
M31
J31
F31
AL30
AG30
AE30
AC30
AA30
Y30
V30
U30
G30
E30
B30
AA29
U29
R29
P29
N29
M29
H29
E29
B29
AK28
AH28
AE28
AA28
U28
T28
J28
D28
AM27
AF27
AB27
AA27
Y27
U27
T27
R27
P27
N27
M27
G27
E27
C27
B27
AL26
AH26
W26
U26
AN25
AK25
AG25
AE25
J25
G25
A25
H23
F23
B23
AM22
AJ22
AF22
G22
E22
J21
H21
F21
AM20
AK20
AH20
AF20
D20
W19
R19
AM18
AH18
AF18
U18
H18
D18
AK17
V17
T17
F17
B17
AH16
U16
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
U1G
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
W33
AM33
AL33
C33
B33
AN32
A32
AN31
W28
V27
W29
J24
H24
W32
G24
F24
E24
D24
K33
A31
E21
C23
AN19
AM19
AL19
AK19
AJ19
AH19
AN3
Y9
J19
H19
G19
F19
E19
D19
C19
B19
A19
Y8
G16
F16
E16
D16
C16
B16
AN2
A16
Y7
AM4
AF4
AD4
AL4
AK4
W31
AJ4
AH4
AG4
AE4
AM1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
om
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VSS
U1H
T25
R25
P25
N25
M25
P24
N24
M24
Y22
W22
V22
U22
T22
R22
P22
N22
M22
Y21
W21
V21
U21
T21
R21
P21
N21
M21
Y20
W20
V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14
W14
V14
U14
T14
R14
P14
N14
M14
NC
+VCCP
ho
f@
Calistoga(4/5)-PWR/GND
Size
Document Number
Custom
Date:
in
Title
LA-5091P
Sheet
1
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
of
39
C287
0.1U_0402_16V4Z
C278
10U_0805_10V4Z
C277
0.1U_0402_16V4Z
C43
0.1U_0402_16V4Z
C44
C52
10U_0805_10V4Z
10U_0805_10V4Z
C23
10U_0805_10V4Z
C239
0.1U_0402_16V4Z
C24
10U_0805_10V4Z
C235
0.1U_0402_16V4Z
C48
0.1U_0402_16V4Z
C293
4.7U_0603_6.3V6M~D
C319
1U_0402_6.3V4Z~D
C
40mA Max.
+1.5VS_DPLLB
10mil
1
1
+
2
Route +2.5VS from GMCH pinN33 to

decoupling cap <200mil to the edge.
C267
0.1U_0402_16V4Z
+VCCP
+
2
+1.5VS_PCIE
R177
2
1
0_0805_5%
+1.5VS_3GPLL
+2.5VS
+2.5VS
+2.5VS
400mA
+2.5VS_CRTDAC
2
+1.5VS
L2
FBMA-L10-160808-301LMT_2P
+1.5VS_MPLL 45mA
+1.5VS_HPLL 45mA
+1.5VS_DPLLA 50mA
+1.5VS_DPLLB 50mA
+1.5VS 150mA
+2.5VS 60mA
2
+1.5VS
L20
FBMA-L10-160808-301LMT_2P
C236
0.1U_0402_16V4Z
10mil
40mA Max.
+1.5VS_DPLLA
+2.5VS
70mA
70mA
1
R172 1
2
10_0603_5%
1
+2.5VS
CRTDAC: Route FB
within 3" of Calistoga
+1.5VS
1
+
2
+2.5VS
C248
0.47U_0402_10V4Z~D
Route VSSACRTDAC gnd from GMCH to

decoupling cap ground lead and then
connect to the gnd plane.
+2.5VS
close pin C29/D29
2008/11/10
Issued Date
2009/11/10
Deciphered Date
4
2
A
close pin B31
Compal Secret Data
+1.5VS
C246
0.1U_0402_16V4Z
10mil
2
C283
0.47U_0603_16V4Z
P1
L1
G1
U1
Y1
0.01U_0402_25V7K
C237
10mil
VTT41
VTT42
VTT43
VTT44
VTT45
R38
0_0603_5%
2
1
+1.5VS
C247
0.1U_0402_16V4Z
45mA Max.
C260
4.7U_0603_6.3V6M~D
C259
220U_B2_2.5VM_R35
C253
10U_0805_10V4Z
10mil
C254
10U_0805_10V4Z
C281
4.7U_0603_6.3V6M~D
C276
4.7U_0603_6.3V6M~D
C40
220U_B2_2.5VM_R35
0.47U_0603_16V4Z
533 MTS=1720mA
+1.5VS_HPLL
R45
0_0603_5%
2
1
+1.8V
10U_0805_10V4Z
C245
210mil
45mA Max.
+1.5VS_MPLL
C256
C22
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
C257
0.47U_0603_16V4Z
C27
A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
AA1
F1
0_0603_5%
1
330U_D2E_2.5VM
10mil
C249
330U_D2E_2.5VM
0.1U_0402_16V4Z
+VCCP
780mA
C25
10mil
10mil
0.1U_0402_16V4Z
Check power sequence

if OK then @
Vccp->1.5V->3.3V
+3VS
C330
4.7U_0603_6.3V6M~D
40mA
C288
1U_0603_10V6K~D
10_0402_5%
+1.5VS
10U_0805_10V4Z
C244
+2.5VS
R168
C250
1 1
0.1U_0402_16V4Z
1250mA
20mA
C242
0.1U_0402_16V4Z
D15
RB751V-40_SOD323-2
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
+1.5VS
R210
2
C286
1U_0603_10V6K~D
+1.5VS
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
J14
J10
H10
AE9
AD9
U9
AD8
AD7
AD6
+1.5VS_3GPLL
C241
0.022U_0402_16V7K
PCI-E/MEM/PSB PLL decoupling

Disable TV
C329
1U_0603_10V6K~D
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26400mA
N33 2mA
M33
J23
C24
B24
B25
B31 10mA
B32
C318
1U_0603_10V6K~D
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCADPLLB
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCC3G0
VCC3G1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCSYNC
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VCCALVDS
VSSALVDS
C54
1U_0603_10V6K~D
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
POWER
C266
0.1U_0402_16V4Z
C265
0.1U_0402_16V4Z
C261
0.1U_0402_16V4Z
T26
R26
P26
N26
M26
V19
U19
T19
W18
V18
T18
R18
W17
U17
R17
W16
V16
T16
R16
V15
U15
T15
+VCCP
144mA
U1D
C39
10U_0805_10V4Z
C41
10U_0805_10V4Z
C37
220U_B2_2.5VM_R35
2940mA
+1.5VS
+VCCP
Title
Calistoga(5/5)-PWR/GND
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
10
of
39
+1.8V
+1.8V
JDIM1
<7> DDR_A_DQS#[0..7]
+DIMM_VREF
DDR_A_D0
DDR_A_D1
<7> DDR_A_D[0..63]
<7> DDR_A_DM[0..7]
DDR_A_DQS#0
DDR_A_DQS0
Layout Note:
Place near JDIM1
<7> DDR_A_DQS[0..7]
<7> DDR_A_MA[0..13]
DDR_A_D2
DDR_A_D3
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
+1.8V
C87
0.1U_0402_16V4Z
C88
0.1U_0402_16V4Z
C68
0.1U_0402_16V4Z
C69
0.1U_0402_16V4Z
C61
220U_B2_2.5VM_R35
20mils
DDR_A_D16
DDR_A_D17
1
C86
DDR_A_DQS#2
DDR_A_DQS2
C92
2.2U_0603_6.3V6K
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
2
DDR_A_D26
DDR_A_D27
<6>
<7>
DDR_CKE0
DDR_A_BS2
DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
<7>
DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
<6>
DDR_CS1#
<6>
M_ODT1
+0.9VS
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1#
M_ODT1
DDR_A_D32
DDR_A_D33
C100
0.1U_0402_16V4Z
C80
0.1U_0402_16V4Z
C78
0.1U_0402_16V4Z
C99
0.1U_0402_16V4Z
C101
0.1U_0402_16V4Z
C82
0.1U_0402_16V4Z
C83
0.1U_0402_16V4Z
C102
0.1U_0402_16V4Z
C103
0.1U_0402_16V4Z
C81
0.1U_0402_16V4Z
C104
0.1U_0402_16V4Z
DDR_A_D34
DDR_A_D35
1
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
+0.9VS
DDR_A_D50
DDR_A_D51
RP5
8
7
6
5
8
7
6
5
1
2
3
4
DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
DDR_A_BS0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
56_0804_8P4R_5%
RP2
1
8
2
7
3
6
4
5
56_0804_8P4R_5%
RP6
8
1 DDR_A_MA6
7
2 DDR_A_MA7
6
3 DDR_A_MA11
5
4 DDR_CKE1
56_0804_8P4R_5%
RP3
M_ODT1
1
8
DDR_CS1#
2
7
DDR_A_CAS# 3
6
DDR_A_WE#
4
5
56_0804_8P4R_5%
RP4
8
1 DDR_A_MA5
7
2 DDR_A_MA8
6
3 DDR_A_MA9
5
4 DDR_A_MA12
56_0804_8P4R_5%
DDR_A_D56
DDR_A_D57
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
DDR_A_DM7
DDR_A_D58
DDR_A_D59
+3VS
<12> CLK_SMBDATA
<12> CLK_SMBCLK
CLK_SMBDATA
CLK_SMBCLK
+3VS
56_0804_8P4R_5%
C361
0.1U_0402_16V4Z
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>
DDR_A_D14
DDR_A_D15
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_A_D20
DDR_A_D21
R54
DDR_A_DM2
0_0402_5%
2
PM_EXTTS#0 <6>
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1
DDR_CKE1
<6>
C
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0#
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0# <6>
M_ODT0
DDR_A_MA13
M_ODT0
<6>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
B
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R53
R52
1
1
2 10K_0402_5%
2 10K_0402_5%
TYCO_292526-4
DIMMA
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
3
ho
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
1 R159
2
56_0402_5%
1 R160
2
56_0402_5%
Title
f@
DDR_CKE0
DDRII-SODIMM A
Size
Document Number
Custom
Date:
in
DDR_A_BS2
tm
ai
l.c
2/10:Change from 5.2mm to 4mm height CPN:SP07000CK00
LA-5091P
Sheet
1
Rev
1.0
xa
1
2
3
4
@C360
@
C360
2.2U_0603_6.3V6K
RP1
DDR_A_MA13
M_ODT0
DDR_CS0#
DDR_A_RAS#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
he
C84
0.1U_0402_16V4Z
C79
0.1U_0402_16V4Z
DDR_A_DQS#4
DDR_A_DQS4
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
+DIMM_VREF
0.1U_0402_16V4Z
2
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
om
C71
2.2U_0603_6.3V6K
C70
2.2U_0603_6.3V6K
C89
2.2U_0603_6.3V6K
C90
2.2U_0603_6.3V6K
C91
2.2U_0603_6.3V6K
DDR_A_D10
DDR_A_D11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
of
39
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
DOT_96 USB
MHz
MHz
1
R78
+3VS
266
100
33.3
14.318
96.0
48.0
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
166
100
33.3
14.318
96.0
48.0
333
100
33.3
14.318
96.0
48.0
100
100
33.3
14.318
96.0
48.0
400
100
33.3
14.318
96.0
2
0_0805_5%
+3VS
1
C151
10U_0805_10V4Z
C181
47P_0402_50V8J
C175
0.1U_0402_16V4Z
C197
0.1U_0402_16V4Z
C199
0.1U_0402_16V4Z
1
R131
+VCCP
2
0_0805_5%
C163
10U_0805_10V4Z
C198
47P_0402_50V8J
C152
0.1U_0402_16V4Z
C153
0.1U_0402_16V4Z
C167
0.1U_0402_16V4Z
CLK_SMBDATA
CLK_SMBCLK
71
CLK_CPU_BCLK
70
CLK_CPU_BCLK#
68
CLK_MCH_BCLK
CPU_1#
67
CLK_MCH_BCLK#
24
CLK_MCH_DREFCLK
25
CLK_MCH_DREFCLK#
CPU_0
VDD_CPU
CPU_0#
VDD_PCI
VDD_48
66
VDD_CPU_IO
SRC_0/DOT_96
VDD_PLL3_IO
SRC_0#/DOT_96#
62
@ R141
52
1K_0402_5%
23
1
4.7P_0402_50VNPO
2
@ C124
2
5P_0402_50V8C
2
22_0402_5%
1
4.7P_0402_50VNPO
MCH_CLKSEL1 <6>
R86
1K_0402_5%
R137
1
@ C832
<17> CLK_ICH_14M
1K_0402_5%
R295
2
22_0402_5%
<17> CLK_ICH_48M
1@ R81
VDD_SRC_IO
LCDCLK/27M
VDD_SRC_IO
LCDCLK#/27M_SS
2
R101 33_0402_5%
VDD_SRC_IO
FSA
20
FSB
FSC
2
@ C392
USB_0/FS_A
SRC_3
FS_B/TEST_MODE
SRC_3#
2.2K_0402_5%
CLK_SMBDATA
C200
+3VS
0.1U_0402_16V4Z
3
CLK_SMBCLK
REF_1
SRC_4
SRC_4#
NC
SRC_6
SRC_6#
<17> H_STP_CPU#
<17> H_STP_PCI#
H_STP_CPU#
53
H_STP_PCI#
54
CLK_XTAL_IN
CLK_XTAL_OUT
CPU_STOP#
SRC_7
PCI_STOP#
SRC_7#
+VCCP
2
4.7P_0402_50VNPO
@ C120 1
28
MCH_SSCDREFCLK
29
MCH_SSCDREFCLK#
32
CLK_PCIE_SATA
33
CLK_PCIE_SATA#
35
CLK_MCH_3GPLL
36
CLK_MCH_3GPLL#
SRC PORT LIST
CLK_SMBCLK <11>
CLK_CPU_BCLK
<4>
CLK_CPU_BCLK#
<4>
CLK_MCH_BCLK
<6>
CLK_MCH_BCLK#
PORT
<6>
CLK_MCH_DREFCLK
<6>
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
<6>
<6>
MCH_SSCDREFCLK#
CLK_PCIE_SATA
<6>
<16>
CLK_PCIE_SATA# <16>
CLK_MCH_3GPLL
<8>
CLK_MCH_3GPLL#
<8>
DEVICE
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
MCH_DREFCLK
PCIE_SATA
MCH_3GPLL
PCIE_WLAN
PCIE_LAN
PCIE_ICH
39
40
CKPWRGD/PD#
11
0_0402_5%
CLK_SMBDATA <11>
REF_0/FS_C/TEST_
8
VGATE
<17,25,35> VGATE
SRC_2
SRC_2#
2@ R82
VDD_IO
38
1
<23> RTS5159_48M
CPU_BSEL1
VDD_PLL3
31
+VCCP
<4>
CPU_1
27
1
+1.05VM_CK505
MCH_CLKSEL0 <6>
R142
1K_0402_5%
0.1U_0402_16V4Z
VDD_REF
56_0402_5%
C189
10
SCL
R140
FSB
SDA
VDD_SRC
19
1
2
R91
@ 0_0402_5%
R108
2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
Q10A
U11
72
R112
0.1U_0402_16V4Z
SA000020K00 (Silego : SLG8SP556VTR )

SA000020H10 (ICS : ICS9LPRS387AKLFT)
12
C154
48.0
+VCCP
1
2
@ R147
0_0402_5%
Q10B
2N7002DW-T/R7_SOT363-6
CPU_BSEL0
0.1U_0402_16V4Z
<17> ICH_SMBCLK
55
<4>
C155
<17> ICH_SMBDATA
1
+3VM_CK505
+1.05VM_CK505
Reserved
R138
2.2K_0402_5%
FSA 2
1
+3VM_CK505
FSB
FSC
XTAL_IN
SRC_8/CPU_ITP
XTAL_OUT
SRC_8#/CPU_ITP#
57
CLK_PCIE_WLAN
56
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
<19>
CLK_PCIE_WLAN#
<19>
61
60
64
CPU_ITP
63
CPU_ITP#
44
CLK_PCIE_LAN
45
CLK_PCIE_LAN#
CLK_PCIE_LAN#
50
CLK_PCIE_ICH
CLK_PCIE_ICH
51
CLK_PCIE_ICH#
CPU_ITP <4>
CPU_ITP# <4>
+3VS
@ R97
<4>
CPU_BSEL2
1
2
@ R95
0_0402_5%
<25> CLK_PCI_LPC
1K_0402_5%
1
MCH_CLKSEL2 <6>
R99
1K_0402_5%
@ C123 1
PCI_LPC
13
PCI2_TME
14
15
2
R121
1
<15> CLK_PCI_ICH
R98
2
R289
33_0402_5%
4.7P_0402_50VNPO
FSC
R100
10K_0402_5%
2
1
PCI4_SEL
16
ITP_EN
17
PCI_1
SRC_9
PCI_2
SRC_9#
PCI_3
SRC_10
PCI_4/SEL_LCDCL
SRC_10#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For PCI4_SEL, 0 = Pin24/25

Pin28/29
1 = Pin24/25
Pin28/29
:
:
:
:
SRC_11
18
DOT96 / DOT96#
LCDCLK / LCDCLK#
SRC_0 / SRC_0#
27M/27M_SS
For PCI2_TME:0=Overclocking of CPU and SRC allowed

(ICS only)
1=Overclocking of CPU and SRC NOT allowed
VSS_PCI
26
69
30
R132
@
10K_0402_5%
1
CLK_XTAL_OUT
22P_0402_50V8J
Routing the trace at least 10mil
R139 2
R111 2
R84 2
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
<17>
<17>
SRC_11#
REQ PORT LIST
48
47
PORT
VSS_48
CLKREQ_3#
VSS_IO
CLKREQ_4#
VSS_CPU
CLKREQ_6#
VSS_PLL3
CLKREQ_7#
VSS_SRC
CLKREQ_9#
VSS_SRC
SLKREQ_10#
VSS_SRC
73
VSS
CLKREQ_11#
USB_1/CLKREQ_A#
37
MCH_CLKREQ#
MCH_CLKREQ#
<6>
41
58
WLAN_CLKREQ#
WLAN_CLKREQ#
<19>
65
43
CLKREQ_LAN#
CLKREQ_LAN#
DEVICE
REQ_3#
MCH_DREFCLK
REQ_4#
REQ_6# PCIE_WLAN
REQ_7#
REQ_9# PCIE_LAN
REQ_10#
REQ_11#
REQ_A#
<24>
49
46
21
10K_0402_5%
PCI4_SEL
SLG8SP556VTR_QFN72_10X10
PCI2_TME
R117
Issued Date
Compal Secret Data
R110
@
10K_0402_5%
10K_0402_5%
1
C162
ITP_EN
R109
MCH_CLKREQ#
CLKREQ_LAN#
WLAN_CLKREQ#
Y2
14.31818MHZ_16PF_DSX840GA
10K_0402_5%
1
22P_0402_50V8J
C169
42
2
R119
@
10K_0402_5%
1
R129
CLK_XTAL_IN
59
+3VS
+3VS
<24>
VSS_REF
22
34
+3VS
CLK_PCIE_ICH#
<24>
PCIF_5/ITP_EN
33_0402_5%
0_0402_5%
CLK_PCIE_LAN
2008/11/10
Deciphered Date
2009/11/10
3
Title
Clock Generator CK505

Size
Document Number
Rev
1.0
LA-5091P
Date:
Sheet
1
12
of
39
+LCDVDD
LCD POWER CIRCUIT
+5VALW
R70
470_0805_5%
R63
1M_0402_5%
D
+3VS
Q29A
R73
W=60mils
Q3
1
2
100K_0402_5%
Q29B
C395
R72
100K_0402_5%
W=20mils
2
1
0_0603_5%
4.7U_0805_10V4Z
C397
0.1U_0402_16V4Z
+3VS_LCD
L22
1
+3VS
FBMA-L11-201209-221LMA30T_0805
C45
0.1U_0402_16V4Z
+VMIC
L37
1
FBMA-L11-201209-221LMA30T_0805
C399
0.1U_0402_16V4Z
C647
0.1U_0402_16V4Z
@ C396
1
1000P_0402_50V7K
C398
W=60mils
<8> GMCH_LVDDEN
R35
2
+LCDVDD
1
+3VS
FBMA-L11-201209-221LMA30T_0805
+CAM_VDD
+LCDVDD_R
L21
1
AO3413_SOT23
D
2
2N7002DW-T/R7_SOT363-6
+5VALW
+LCDVDD
6 2
4.7U_0805_10V4Z
C394
0.1U_0402_16V4Z
2N7002DW-T/R7_SOT363-6
+3VS
2
<8>
<8>
LVDSA0+
LVDSA0-
<8>
<8>
LVDSA2+
LVDSA2R1006 1
R1007 1
MIC_DATA
MIC_CLK
2 0_0402_5%
2 0_0402_5%
BKOFF#
<25> BKOFF#
C229
100P_0402_50V8J~D
@
C230
2 100P_0402_50V8J~D
+3VS_LCD
+VMIC
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GMD
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
INVPWR_B+
JP24
R65
10K_0402_5%
R60
4.7K_0402_5%
<20>
<20>
+LCDVDD_R
+CAM_VDD
+3VS
1/9: Reversed LVDS cannector

pinout, but LVDS cable did
not need to change.
R69
10K_0402_5%
1
2
LCD/PANEL BD. Conn.
EDID_CLK_LCD
EDID_DAT_LCD
<8>
<8>
R44
1
LVDSA1+ <8>
LVDSA1- <8>
LVDC+
LVDC-
R1027
R1026
1
2
2 0_0402_5%
1 0_0402_5%
0_0402_5%
LVDSAC+ <8>
LVDSAC- <8>
USBP1
USBN1
INVT_PWM
<25>
@
WCM2012F2S-900T04_0805
4
3
4
3
USB20_P1 <17>
USB20_N1
1
L64
<17>
R46
1
ACES_87242-4001-09
2
0_0402_5%
Change to SP02000MD00
B+
INVPWR_B+
@ L18
FBMA-L11-201209-221LMA30T_0805
2
1
C85
68P_0402_50V8J
C393
0.1U_0603_25V7K
Q80
SI3457BDV-T1-E3_TSOP6~D
6
5
2
1
40mil
40mil
C829
R1158
1000P_0402_50V7K
100K_0402_5%~D
C830
0.1U_0603_50V4Z~D
@
PWR_SRC_ON
Q81
RHU002N06_SOT323-3~D
om
2
1
332K_0402_1%
5
LVDS/INVERTER
Size
Document Number
LA-5091P
ho
f@
Title
in
2009/11/10
Deciphered Date
Rev
1.0
xa
2008/11/10
Issued Date
Compal Secret Data
he
BKOFF#
tm
ai
2
G
1
R1159
l.c
Date:
Sheet
1
13
of
39
@
D4
Place closed to chipset

L1
1
2
BLM18BB470SN1D_2P~D
L3
1
2
BLM18BB470SN1D_2P~D
L4
1
2
BLM18BB470SN1D_2P~D
<8> GMCH_CRT_G
R13
R19
150_0402_1%
2
1
150_0402_1%
2
1
R5
150_0402_1%
2
1
<8> GMCH_CRT_B
@ C26
@ C30
2
39_0402_5%
@ C20
10P_0402_50V8J
2
@C29
@
C29
10P_0402_50V8J
1
L19
2
BLM18AG121SN1D_0603~D
JVGA_HS
1
L5
2
BLM18AG121SN1D_0603~D
JVGA_VS
2
U15
CRT_HSYNC_1
@ C232
10P_0402_50V8J
1
R282
<8> GMCH_CRT_HSYNC
5
P
OE#
C38
BLUE
@ C1
10P_0402_50V8J
2
2
2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
2
0.1U_0402_16V4Z
RED
GREEN
+CRT_VCC
1
@ C35
PSOT24C_SOT23-3
<8> GMCH_CRT_R
PSOT24C_SOT23-3
@
D3
Close to CRT CONN for ESD.
SN74AHCT1G125DCKR_SC70-5
@C31
@
C31
10P_0402_50V8J
2
0.1U_0402_16V4Z
OE#
1
@ C234
+CRT_VCC
Place closed to chipset
2
39_0402_5%
U4
Y
CRT_VSYNC_1
1
R296
SN74AHCT1G125DCKR_SC70-5
<8> GMCH_CRT_VSYNC
CRT PORT
+3VS
R163
D6
+3VS
2.2K_0402_5%
2
2.2K_0402_5%
2
+CRT_VCC
+5VS
R165
+CRT_VCC
R16
W=40mils
1
F1
5A_125V_R451005.MRL~D
1
2
@
R164
<8> GMCH_CRT_CLK
JP68
VGA_DDC_DAT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RED
VGA_DDC_DAT
GREEN
Q14B
2N7002DW-T/R7_SOT363-6
<8> GMCH_CRT_DATA
0_0805_5%
2.2K_0402_5%
2
5
4
2
1U_0402_6.3V4Z~D
R303
2.2K_0402_5%
1
C36
CH491DPT_SOT-23
VGA_DDC_CLK
JVGA_HS
BLUE
Q14A
2N7002DW-T/R7_SOT363-6
JVGA_VS
@
C228
100P_0402_50V8J~D
VGA_DDC_CLK
C33
2
2 68P_0402_50V8K
16
17
FOX_DZ11A91-SB264-7F~D
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
A
Title
CRT PORT
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
E
14
of
39
+3VS
U6B
R262 1
2 8.2K_0402_5%
PCI_TRDY#
R264 1
2 8.2K_0402_5%
PCI_FRAME#
R259 1
2 8.2K_0402_5%
PCI_PLOCK#
R256 1
2 8.2K_0402_5%
PCI_IRDY#
R258 1
2 8.2K_0402_5%
PCI_SERR#
R257 1
2 8.2K_0402_5%
PCI_PERR#
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
+3VS
R254 1
2 8.2K_0402_5%
PCI_PIRQA#
R255 1
2 8.2K_0402_5%
PCI_PIRQB#
R271 1
2 8.2K_0402_5%
PCI_PIRQC#
R270 1
2 8.2K_0402_5%
PCI_PIRQD#
R276 1
2 8.2K_0402_5%
PCI_PIRQE#
R272 1
2 8.2K_0402_5%
PCI_PIRQF#
R275 1
2 8.2K_0402_5%
PCI_PIRQG#
R273 1
2 8.2K_0402_5%
PCI_PIRQH#
R274 1
2 8.2K_0402_5%
PCI_REQ#0
R265 1
2 8.2K_0402_5%
PCI_REQ#1
R266 1
2 8.2K_0402_5%
PCI_REQ#2
R261 1
2 8.2K_0402_5%
PCI_REQ#3
R277 1
2 8.2K_0402_5%
PCI_REQ#4
R278 1
2 8.2K_0402_5%
PCI_REQ#5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#
PCI
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
For EMI, close to ICH7
PCI_REQ#3
PCI_REQ#4
PCI_RST#
PCI_REQ#5
PLTRST#_ICH
B15
C12
D12
C15
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
PCI_IRDY#
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
C26
A9
B19
PLTRST#_ICH
CLK_PCI_ICH
G8
F7
F8
G7
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_RST#
1
C358
0.1U_0402_16V4Z
PCI_STOP#
<25>
C
2
R244
100K_0402_5%
For EC request.
CLK_PCI_ICH
Place closely pin A9
<12>
CLK_PCI_ICH
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9
Interrupt
PIRQA#
PIRQB#
PIRQC#
PIRQD#
I/F
GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#
MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
PCI_DEVSEL#
2 8.2K_0402_5%
@
R246
10_0402_5%
1
2 8.2K_0402_5%
R263 1
C357
0.1U_0402_16V4Z
R260 1
AE9
AG8
AH8
F21
AH20
@
C359
8.2P_0402_50V8D
MCH_ICH_SYNC#
<6>
ICH7_BGA652
+3VS
TC7SH08FUF_SSOP5
@ U16
Y
PLTRST# <6,17,19,24,25>
PLTRST#_ICH
2
0.1U_0402_16V4Z
1
@ C297
R227
100K_0402_5%
1
R226
0_0402_5%
ho
f@
ICH7M(1/4)-HUB/PCI/HOST
Size
in
Title
Document Number
LA-5091P
Date:
Sheet
1
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
15
of
39
C49
15P_0402_50V8J
2
1
2
V3
1U_0603_10V4Z
U3
U5
V4
T5
<20> HDA_SYNC_AUDIO
R235
HDA_BITCLK_AUDIO_R
1
R230
1
<20> HDA_RST_AUDIO#
<20> HDA_SDOUT_AUDIO
R233
HDA_SYNC_ICH
HDA_SDOUT_ICH
C389
39P_0402_50V8J
@
HDA_BITCLK_ICH
HDA_SYNC_ICH
U1
R6
HDA_RST_ICH#
R5
T2
T3
T1
<20> HDA_SDIN0
1
HDA_SDOUT_ICH
T4
AF18
SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
LAN_CLK
LAN_RSTSYNC
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
C409 2
C411 2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
<12> CLK_PCIE_SATA#
<12> CLK_PCIE_SATA
R11
2 24.9_0402_1%
AH10
AG10
CPUSLP#
TP1 / DPRSTP#
TP2 / DPSLP#
LAN_RXD0
LAN_RXD1
LAN_RXD2
FERR#
GPIO49 / CPUPWRGD
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
IGNNE#
INIT3_3V#
INIT#
INTR
SMI#
NMI
STPCLK#
DA0
DA1
DA2
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
DCS1#
DCS3#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
+3VS
R77
R23
B
+RTCBATT
1
1
2 4.7K_0402_5%
2
8.2K_0402_5%
AG16
AH16
AF16
AH15
AF15
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
<25>
<25>
<25>
<25>
AC3
AA5
R900
AB3
LPC_FRAME#_R
AE22
AH28
GATEA20
H_A20M#
33_0402_5%
2
1 R204
GATEA20
H_A20M#
LPC_FRAME#
10K_0402_5%
<25>
+3VS
<25>
<4>
AG27
AF24
AH25
H_DPRSTP#
H_DPSLP#
AG26
H_FERR#
AG24
H_PWRGOOD
AG22
AG21
AF22
AF25
H_IGNNE#
H_IGNNE#
H_INIT#
H_INTR
H_INIT#
H_INTR
<4>
<4>
AG23
KB_RST#
KB_RST#
<25>
AF23
AH24
H_SMI#
H_NMI
H_SMI#
H_NMI
<4>
<4>
AH22
H_STPCLK#
H_STPCLK#
AF26
THRMTRIP_ICH#
H_DPRSTP# <4,35>
H_DPSLP# <4>
+VCCP
1 56_0402_5%
H_FERR# <4> R20
H_PWRGOOD
<4>
<4>
+VCCP
RCIN#
THERMTRIP#
ACZ_SDOUT
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
2
A20GATE
A20M#
SATA
<22>
<22>
<22>
<22>
LFRAME#
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
HDA_RST_ICH#
C280
39P_0402_50V8J
@
U7
V6
V7
LDRQ0#
LDRQ1# / GPIO23
AC-97/AZALIA
R236
2
39_0402_5%
2
39_0402_5%
2
39_0402_5%
2
39_0402_5%
INTVRMEN
INTRUDER#
LAN
W1
Y1
Y2
W3
C317
1
W4
Y5
2
3MM
RTCRST#
AA6
AB5
AC4
Y6
IDE
DDREQ
ICH_INTVRMEN
SM_INTRUDER#
@ J5
1
AA3
LAD0
LAD1
LAD2
LAD3
R194
C
56_0402_5%
<4>
2
ICH_RTCRST#
RTXC1
RTCX2
LPC
R217 1
20K_0402_5%
RTC
+RTCBATT
U6A
AB1
AB2
ICH_RTCX2
CPU
OUT
C50
15P_0402_50V8J
2
1
R37
10M_0402_5%
2
1
NC
ICH_RTCX1
Y3
32.768K_1TJS125BJ4A421P
2
1
NC
IN
3
H_THERMTRIP#
R196
24.9_0402_1%
AH17
AE17
AF17
<4,6>
Layout note: R194 needs to placed

within 2" of ICH7, R193 must be placed
within 2" of R194 w/o stub.
AE16
AD16
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AE15
ICH7_BGA652
1M_0402_5%
2 SM_INTRUDER#
R216
1
332K_0402_1%
2 ICH_INTVRMEN
+3VS
+3VS
R214
1
R309
4.7K_0402_5%
@
U8
2
+RTCBATT
HDA_BITCLK_AUDIO_R
1
2
3
4
FS
VDD
SSEXTR
DLY_CTRL
GND
ModOUT
8
7
6
1
@ C815
1
R150
@
PCS3P73Z11BXG-08-CR_TDFN8_2X2
SA00002G800
@
R311
4.7K_0402_5%
@
0.1U_0402_16V4Z
PD#/OE
2
0.1U_0402_16V4Z
2
1M_0402_5%
HDA_BITCLK_AUDIO
<20>
R307
22_0402_5%
@
C294
CLKIN
R312
A
2
0_0402_5%
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
5
Title
ICH7M(2/4)-LAN/ATA/LPC/RTC
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
16
of
39
Place closely pin B2
Place closely pin AC1
+3VS
2 SPI_MISO
10K_0402_5%
1
@ R223
2 SB_SPI_CS#
10K_0402_5%
2 ICH_PCIE_WAKE#
1K_0402_5%
2
R250
1 ICH_LOW_BAT#
8.2K_0402_5%
A28
SB_SPKR
SUS_STAT#
ITP_DBRESET#
A19
A27
A22
+3VALW
R59
1
2
8.2K_0402_5%
<20>
SB_SPKR
T4 PAD
<6> PM_BMBUSY#
PM_BMBUSY#
OCP#
<12> H_STP_PCI#
<12> H_STP_CPU#
RI#
SPKR
SUS_STAT#
SYS_RST#
AB18
GPIO0 / BM_BUSY#
B23
H_STP_PCI#
H_STP_CPU#
2 SPI_MOSI
10K_0402_5%
AC20
AF21
GPIO18 / STPPCI#
GPIO20 / STPCPU#
<19> ICH_PCIE_WAKE#
<25>
SERIRQ
<25> EC_THERM#
<12,25,35>
VGATE
ICH_PCIE_WAKE#
SERIRQ
EC_THERM#
AG18
GPIO32 / CLKRUN#
AD22
<25>
2 H_STP_PCI#
10K_0402_5%
EC_SMI#
EC_SMI#
AC21
AC18
E21
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
GPIO16 / DPRSLPVR
TP0 / BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
AF19
AH18
AH19
AE19
WAKE#
SERIRQ
THRM#
VRMPWRGD
GPIO
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39
1
R212
@ 10_0402_5%
@ 10_0402_5%
R245
@ 4.7P_0402_50V8C
CLK_ICH_14M
CLK_ICH_48M
C20
ICH_SUSCLK
B24
D23
F22
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_S3# <25>
PM_SLP_S4# <25>
PM_SLP_S5# <25>
AA4
ICH_POK_EC
AC22
PM_DPRSLPVR
R24
ICH_POK_EC <6,25>
1
2 10K_0402_5%
PM_DPRSLPVR <6,35>
CLK_ICH_14M
CLK_ICH_48M
C355
AC1
B2
C275
@ 4.7P_0402_50V8C
<12>
<12>
T16 PAD
C21
ICH_LOW_BAT#
C23
PBTN_OUT#
PBTN_OUT#
C19
PLTRST#
PLTRST# <6,15,19,24,25>
Y4
EC_RSMRST#
R26
10K_0402_5%
1
2
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
EC_SCI#
ACIN
GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#
F20
AH21
AF20
VGATE
+3VALW
1
@ R284
GPIO27
GPIO28
AC19
U2
1/9: De-pop R284

for +3VS back
drive issue.
GPIO26
B21
E23
PM_CLKRUN#
GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP
GPIO11 / SMBALERT#
A21
1
@ R222
ICH_RI#
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
GPIO
1
R241
C22
B22
A26
B25
A25
SATA
GPIO
1
@ R224
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
Clocks
2 OCP#
10K_0402_5%
1
R268
<12> ICH_SMBCLK
<12> ICH_SMBDATA
SYS
2 ITP_DBRESET#
10K_0402_5%
10K_0402_5%
SMB
1
R267
10K_0402_5%
2 LINKALERT#
10K_0402_5%
R207
8.2K_0402_5%
U6C
2.2K_0402_5%
2
2.2K_0402_5%
1
R56
R252
POWER MGT
+3VALW
R55
CLK_ICH_14M
+3VS
R251
1
R269
CLK_ICH_48M
+3VALW
1
2 SERIRQ
10K_0402_5%
2 PM_CLKRUN#
8.2K_0402_5%
1
R21
1
R22
+3VALW
EC_RSMRST#
EC_SCI#
ACIN
EC_LID_OUT#
<25>
<25>
<25>
<25,30>
EC_LID_OUT#
<25>
ICH7_BGA652
some intel ICH7M

H_STP_PCI# has the
below glitch
that let Silego clk.
gen enter iAMT mode
when power on, but
ICS clk. gen has no
this issue now.
WLAN
PCIE_PTX_IRX_N2
PCIE_PTX_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
C66
C67
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
H26
H25
G28
G27
<24>
<24>
<24>
<24>
PCIE_PTX_IRX_N3
PCIE_PTX_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
C60
C64
1
1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3
K26
K25
J28
J27
PERn2
PERp2
PETn2
PETp2
PERn3
PERp3
PETn3
PETp3
M26
M25
L28
L27
PERn4
PERp4
PETn4
PETp4
P26
P25
N28
N27
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
USB_OC#0
USB_OC#3
USB_OC#7
R247 2
1
10K_0402_5%
<27>
USB_OC#0
<27>
USB_OC#3
R249 2
1
10K_0402_5%
<27>
R248 2
1
10K_0402_5%
USB_OC#7
SPI_MOSI
SPI_MISO
P5
P2
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
PERn6
PERp6
PETn6
PETp6
SPI_CLK
SPI_CS#
SPI_ARB
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
SPI
+3VALW
USB_OC#1
USB_OC#2
USB_OC#4
USB_OC#5
USB_OC#6
SB_SPI_CS#
R2
P6
P1
PCI-EXPRESS
LAN
<19>
<19>
<19>
<19>
PERn1
PERp1
PETn1
PETp1
DIRECT MEDIA INTERFACE
U6D
F26
F25
E28
E27
USB
USBRBIAS#
USBRBIAS
V26
V25
U28
U27
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
Y26
Y25
W28
W27
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
DMI_MTX_IRX_N0 <6>
DMI_MTX_IRX_P0 <6>
DMI_ITX_MRX_N0 <6>
DMI_ITX_MRX_P0 <6>
DMI_MTX_IRX_N1 <6>
DMI_MTX_IRX_P1 <6>
DMI_ITX_MRX_N1 <6>
DMI_ITX_MRX_P1 <6>
AB26
AB25
AA28
AA27
AD25
AD24
AC28
AC27
AE28
AE27
CLK_PCIE_ICH#
CLK_PCIE_ICH
C25
D25
DMI_IRCOMP
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
D2
D1
USBRBIAS
CLK_PCIE_ICH# <12>
CLK_PCIE_ICH <12>
R243
1
24.9_0402_1%
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
Within 500 mils

+1.5VS
<27>
<27>
<13>
<13>
<19,23>
<19,23>
<27>
<27>
<19>
<19>
<19>
<19>
<19,23>
<19,23>
<27>
<27>
USB1(Right)
CMOS
CARD READER
USB2(Left)
WWAN
BT
USB3(Left)
R242 22.6_0402_1%
1
2
A
Within 500 mils
ho
f@
ICH7M(3/4)-USB/GPIO/PCIE
Size
Document Number
Custom
Date:
in
Title
LA-5091P
Sheet
1
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
ICH7_BGA652
17
of
39
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
1
+
C93
220U_B2_2.5VM_R35
C279
2
+5VS
C305
C349
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R237
D21
RB751V-40_SOD323-2
Place closely pin

D28,T28,AD28.
100_0402_5%
ICH_V5REF_RUN
1
C343
1U_0603_10V4Z
+5VALW +3VALW
R64
D11
RB751V-40_SOD323-2
10_0402_5%
Check power sequence

if OK then @
Vccp->1.5V->3.3V
ICH_V5REF_SUS
C346
+3VS
0.1U_0402_16V4Z
C356
0.1U_0402_16V4Z
Place closely pin AG28 within 100mlis.

+1.5VS_DMIPLLR
+1.5VS_DMIPLL
R189
B27
R186
2
0.5_0805_1%
+1.5VS_DMIPLL
2
0_0805_5%
0.01U_0402_25V7K
C271
10U_0805_10V4Z
C272
+1.5VS
50mA
+1.5VS
AG28
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
0.64A
C282
0.1U_0402_16V4Z
Place closely pin AG5.
+3VALW
C340
0.1U_0402_16V4Z
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
+1.5VS
C269
1U_0603_10V4Z
Place closely pin AG9.

10mA
1
+1.5VS
2
AD2
AH11
+3VS
C263
0.1U_0402_16V4Z
C264
0.1U_0402_16V4Z
+1.5VS
C350
0.1U_0402_16V4Z
1
T2
T6
PAD
PAD
E3
C1
ICH_AA2
ICH_Y7
AA2
Y7
V5
V1
W2
W7
+3VS
1
V5REF_Sus
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA
Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
C336
C316
2
1U_0603_10V4Z
+ C252
220U_B2_2.5VM_R35
+3VS56mA
U6
R7
+3VALW
AE23
AE26
AH26
10mA
+VCCP
2
14mA
+3VS0.27A
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
C285
0.1U_0402_16V4Z
C296
0.1U_0402_16V4Z
+3VS
W5
+RTCBATT
45mA
P7
1
A24
C24
D19
D22
G19
C332
0.1U_0402_16V4Z
2
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
C333
0.1U_0402_16V4Z
2
AB17
AC17
+3VALW
C347
0.1U_0402_16V4Z
C292
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V5REF[2]
4.7U_0805_10V4Z
C262
F6
C274
0.1U_0402_16V4Z
10mA ICH_V5REF_SUS
U6E
0.94A
C289
0.1U_0402_16V4Z
+1.5VS
0.77A
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
C273
0.1U_0402_16V4Z
AD17
V5REF[1]
0.1U_0402_16V4Z
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C345
0.1U_0402_16V4Z
G10
C353
0.1U_0402_16V4Z
ICH_V5REF_RUN
+VCCP
U6F
6mA
C354
0.1U_0402_16V4Z
+3VALW
C339
0.1U_0402_16V4Z
+1.5VS
T7
F17
G17
AB8
AC8
K7
C284 0.1U_0402_16V4Z
ICH_K7
PAD T11
C28
G20
ICH_C28
ICH_G20
A1
H6
H7
J6
J7
17mA
PAD T3
PAD T14
+1.5VS
1
C344
0.1U_0402_16V4Z
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
ICH7_BGA652
ICH7_BGA652
C291
0.1U_0402_16V4Z
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
5
Title
ICH7-M(4/4)-POWER/GND
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
18
of
39
+3VS_WLAN
1
C904
47P_0402_50V8J
C113
C118
0.01U_0402_25V7K
0.1U_0402_16V4Z
C121
C903
47P_0402_50V8J
0.1U_0402_16V4Z
C98
C195
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+1.5VS
Mini-Express Card for WLAN
JP54
2
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
0_0402_5%
0_0402_5%
<12> CLK_PCIE_WLAN#
<12> CLK_PCIE_WLAN
<17> PCIE_PTX_IRX_N2
<17> PCIE_PTX_IRX_P2
<17> PCIE_ITX_C_PRX_N2
<17> PCIE_ITX_C_PRX_P2
+3VS_WLAN
0.1U_0402_16V4Z
<25>
<25>
R85
R87
1
1
2
2
C222
0_0402_5%
0_0402_5%
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_WLAN
R62
2 0_0805_5%
+3VS
+1.5VS
WL_OFF#
WL_OFF# <25>
PLTRST#
PLTRST# <6,15,17,24,25>
1
2
+3VS
0_0402_5%
R83
1
2
+3VALW
0_0402_5%
@ R348
USB20_WLAN_N
USB20_WLAN_P
R1166
R1167
1
1
2 0_0402_5%
2 0_0402_5%
BlueTooth Interface
USB20_N6 <17,23>
USB20_P6 <17,23>
+5VS
+3VS
@ R1168 1
@ R1169 1
2 0_0402_5%
2 0_0402_5%
Q20
AO3413_SOT23
R94
100K_0402_5%
47P_0402_50V8J
1
C905
0.1U_0402_16V4Z
1
C106
4.7U_0805_10V4Z
C196
SB770020010
4.7U_0805_10V4Z
+BT_VCC
C186
0.1U_0402_16V4Z
C171
2N7002LT1G_SOT23-3
+3VS_WWAN
C185
Q11
2
G
<25> BT_OFF#
BELLW_80003-1021
SP07000IE00
1
3
54
GND2
GND1
C172
0.1U_0402_16V4Z
53
+BT_VCC
R93
1M_0402_5%
USB20_N2 <17,23>
USB20_P2 <17,23>
1
EC_TX
EC_RX
EC_TX
EC_RX
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
@
@
<12> WLAN_CLKREQ#
R118 1
R116 1
ICH_PCIE_WAKE#
BT_ACTIVE#
WLAN_ACTIVE
WLAN_CLKREQ#
<17> ICH_PCIE_WAKE#
1000P_0402_50V7K
(MAX=200mA)
Mini-Express Card for WWAN
+3VS
+BT_VCC
@ R130
0_0603_5%
2
+3VS_WWAN
+3VS_WWAN
0.1U_0402_16V4Z
EC_TX
EC_RX
@ R114 1
@ R115 1
2
2
2
@ C223
0_0402_5%
0_0402_5%
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
J3
W=120mils
@ JP56
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_WWAN
USB20_P5
USB20_N5
BT_ACTIVE#
WLAN_ACTIVE
<17> USB20_P5
<17> USB20_N5
2
+3VS
JUMP_43X39
JP22
8
7
6
5
4
3
2
1
10
8 GND
7
6
5
4
3
2
1 GND
ACES_87213-0800G
@ R14 1
WXMIT_OFF#
PLTRST#
0_0402_5%
<25>
Tiger FW update for S3 issue.
USB20_N4 <17>
USB20_P4 <17>
54
BELLW_80003-1021
SP07000IE00
4
Document Number
LA-5091P
Date:
ho
f@
Mini-Card/BT CONN
Size
in
Title
Sheet
E
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
19
of
39
+VDDA
+VDDA
<17> SB_SPKR
2
C
2
B
LINE_OUTL
680P_0402_50V7K
LINE_OUTR
+5VS
MONO_IN
L15
1
Q13
1U_0603_10V4Z
R156
560_0402_5%
1 1
2
1U_0603_10V4Z
1
2
1
C405
10U_0805_10V4Z
(output = 150 mA)

+VDDA
@ U20
60mil
FBMA-L11-201209-221LMA30T_0805
20K_0402_5%
R151
2SC2411KT146_SOT23-3
R293
0_0603_5%
2
1
+5VAMP
@ R1161
10K_0402_5%
2
2
1
2
680P_0402_50V7K
C833
1
3
OUT
GND
SHDN
BYP
APL5151-475BC-TRL_SOT23-5
4.75V for LDO pop
40mil
IN
C408
1U_0603_10V6K~D
C219
2MONO_IN1
20K_0402_5%
1
R153
C213
C406
1U_0603_10V6K~D
C220
@ C226
0.1U_0402_16V4Z
R152
10K_0402_5%
1U_0603_10V4Z
1 1
1U_0603_10V4Z
@C407
0.01U_0402_25V7K
BEEP#
R155
560_0402_5%
2
C218
<25>
@ R1160
10K_0402_5%
C216
2
R149
10K_0402_5%
1
1
@ D1
2
2
@ R1170
10K_0402_5%
CH751H-40PT_SOD323-2
+3VS
D13
CH751H-40PT_SOD323-2
2
@ R154
10K_0402_5%
Need to create symbol and footprint for Codec VA2
HD Audio Codec
FBMA-L11-160808-800LMT_0603
+AVDD_AC97
L23
C404
4.7U_0805_10V4Z
25
38
DVDD
AVDD2
LINE2_L
LOUT1_L
LINE2_R
LOUT_R
MIC2_L
LOUT2_L
MIC2_R
LOUT2_R
LINE1_L
SPDIFO2
LINE1_R
DMIC_CLK1/2
2
1000P_0402_50V7K
2
1000P_0402_50V7K
@ C174
1
@ C385
35
C_LINE_OUTL
36
C_LINE_OUTR
C187
C173
LINE_OUTL
1U_0603_10V4Z
LINE_OUTR
1U_0603_10V4Z
LINE_OUTL
<21>
LINE_OUTR
<21>
39
41
45
18
20
19
<21>
MIC1_L
R290 1
<21>
MIC1_R
R331 1
2 1K_0402_5%
2 1K_0402_5%
1 C373
2.2U_0603_6.3V6K
1 C387
2.2U_0603_6.3V6K
21
22
MONO_IN
11
<16> HDA_SYNC_AUDIO
10
5
<16> HDA_SDOUT_AUDIO
R215
R310
1
1
2 20K_0402_1%
2 5.1K_0402_1%
2
3
13
34
R96
2 0_0402_5%
47
<13> MIC_DATA
<21> JACK_PLUG_MIC
<21> JACK_PLUG_HP
<25>
EAPD
EAPD
12
<16> HDA_RST_AUDIO#
48
4
7
LINE1_VREFO
NC
LINE2_VREFO
DMIC_CLK3/4
MIC2_VREFO
BITCLK
46
SDATA_IN
PCBEEP_IN
MONO_OUT
CBP
RESET#
CPVEE
SYNC
MIC1_VREFO
SDATA_OUT
HPOUT_R
GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B
EAPD
CBN
VREF
JDREF
SPDIFO1
HPOUT_L
DVSS1
DVSS2
AVSS1
AVSS2
<13>
44
HDA_BITCLK_AUDIO
6
@
MIC1_L
MIC1_R
MIC_CLK
43
1
R405
2
10_0402_5%
1
R133
2
39_0402_5%
1
@C400
@
C400
<16>
2
10P_0402_50V8J
HDA_SDIN0
<16>
37
29
31
28
C376
1
+MIC1_VREFO
C374
2.2U_0603_6.3V6K
2
1
2.2U_0603_6.3V6K
10mil
+MIC1_VREFO
32
HP_R
HP_R
<21>
2
R15
75_0402_1%
30
27
ACZ_VREF
40
ACZ_JDREF
33
HP_L
HP_L
<21>
R25
75_0402_1%
26
42
C183
0.1U_0402_16V4Z
ACZ_VREF
ACZ_JDREF
ALC272-GR_LQFP48
2
0_0603_5%
10mil
C188
10U_0805_10V4Z
X5R for audio

performance considering
R533
4.7K_0402_5%
R92
20K_0402_1%
AGND
@ C192
0.1U_0402_16V4Z
Close to codec
DGND
2
0_0603_5%
+3VS
24
R535
4.7K_0402_5%
1
R313
FBMA-L11-160808-800LMT_0603
1
DVDD_IO
14
23
2
0_0603_5%
1
C403
0.1U_0402_16V4Z
U23
17
1
R281
1
C210
2
16
R79
1
L24
15
20mil 0.1U_0402_16V4Z
AVDD1
C170
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C258
4.7U_0805_10V4Z
+MIC1_VREFO
+VDDC
40mil
2
C402
+VDDA
DGND
AGND
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
A
Title
ALC272-VB-GR Codec
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
E
20
of
39
APA2031A SPK Amplifier

6dB
10dB
15.6dB
21.6dB
+5VAMP
GAIN1
D17
PJDLC05_SOT23-3
D18
PJDLC05_SOT23-3
R292
47K_0402_5%
U19
GAIN0
GAIN1
<20> LINE_OUTL
R306 1
2 0_0402_5%
INL_A
<20> LINE_OUTR
R308 1
2 0_0402_5%
INR_A
17
9
LIN+
RIN+
SPKL+
18
SPKR+
JP55
1
11
13
20
21
10
SPKL+
SPKLSPKR+
SPKR-
20mil
C34
0.47U_0603_16V4Z
1
1
1
1
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SPK_L1+
SPK_L1SPK_R1+
SPK_R1-
1
2
3
4
Speaker Conn.
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
R197
0_0402_5%
@
JP60
2
6
5
<20> JACK_PLUG_HP
5
6
ACES_87213-0400G
HeadPhone JACK
1
2
3 GND
4 GND
@ C268
C813
0.1U_0603_25V7K
R225
R219
R205
R195
22P_0402_50V8J
GND
GND
GND
GND
GND
BYPASS
SPKR-
EC_MUTE# <25>
@ C270
RIN-
14
APA2031RI-TRL_TSSOP20
ROUT+
SPKL-
@ C290
C814
0.1U_0603_25V7K
LIN-
EC_MUTE#
@ C306
R712
10K_0402_5%
10K_0402_5%
R711
VDD
NC
PVDD SHUTDOWN#
PVDD
LOUTGAIN0
ROUTGAIN1
LOUT+
12
19
16
6
15
R716
100K_0402_1%
@
+3VALW
Close to Speaker CONN for ESD.
GAIN0
R715
100K_0402_1%
C383
R714
100K_0402_1%
2 1
R713
100K_0402_1%
2 1
C375
@
W=40mil
+5VAMP
+5VAMP
4.7U_0805_10V4Z
GAIN1
0
1
0
1
0.1U_0402_16V4Z
GAIN0
0
0
1
1
4
1
2
BLM15AG121SN1D_0402
HPR
2
BLM15AG121SN1D_0402
HPL
2
1
L50
HP_L
L51
<20>
HP_R
<20>
@ J7
JUMP_43X39
PJDLC05_SOT23-3
D45
Ext.MIC JACK
JACK-AGND
1
2
@ J8
JUMP_43X39
10P_0402_50V8J
@ C769
10P_0402_50V8J
SUYIN_010030FR006G109ZL
@ C768
JP61
6
5
<20> JACK_PLUG_MIC
1
L53
2
BLM15AG121SN1D_0402
2
BLM15AG121SN1D_0402
MIC1_R_1
MIC1_L_1
2
1
<20> MIC1_L
1
L52
<20> MIC1_R
SUYIN_010030FR006G109ZL
@ C770
@ C771
JACK-AGND
D46
PJDLC05_SOT23-3
220P_0402_50V8J
1
220P_0402_50V8J
A
ho

AMP/VR/Audio Jack/MIC
f@
Title
Size
Document Number
Custom
Date:
in
2009/11/10
Deciphered Date
Rev
1.0
xa
2008/11/10
LA-5091P
he
Compal Secret Data
Issued Date
tm
ai
l.c
om
Sheet
E
21
of
39
For HDD
OCTEK_SAT-22DD1G_NR
<16> SATA_ITX_C_DRX_P0
<16> SATA_ITX_C_DRX_N0
1
2
3
4
5
6
7
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
<16> SATA_IRX_DTX_N0
<16> SATA_IRX_DTX_P0
C414 2
C415 2
1 0.01U_0402_16V7K
1 0.01U_0402_16V7K
SATA_IRX_C_DTX_N0
SATA_IRX_C_DTX_P0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3VS
+5VS
C410
0.1U_0402_16V4Z
C419
1000P_0402_50V7K
GND
RX+
RXGND
TXTX+
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
24
GND
23
GND
JP48
Pleace near HDD CONN

2
POWER LED
BATT CHARGE LED
2 DC1
820_0402_5%
1
100K_0402_5%
100K_0402_5%
100K_0402_5%
5
4
2N7002DW-T/R7_SOT363-6
Q31A
2N7002DW-T/R7_SOT363-6
Q75A
2N7002DW-T/R7_SOT363-6
2
1
<25> CHARGE_LED#
Q75B
2N7002DW-T/R7_SOT363-6
Q31B
100K_0402_5%
<25> PWR_LED#
2 DC2
300_0402_5%
1
R315
R886
R883
R1104
R1103
1
R314
+5VALW
+5VALW
2
@ R90
1
0_0402_5%
2
@ R104
1
0_0402_5%
JP62
+5VALW
DC1
DC2
1
2
3
4
1
2
3 GND
4 GND
5
6
ACES_87213-0400G
Issued Date
Compal Secret Data
2008/11/10
2009/11/10
Deciphered Date
A
Title
HDD/LED
Size
Document Number
Custom
G
Rev
1.0
LA-5091P
Date:
Sheet
22
H
of
39
4 in 1 Card Reader
JP4
SDWP#
SD_DATA1
SD_MS_DATA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MSBS
SDCLK
MS_DATA1
SD_MS_DATA0
+VCC_4IN1
MS_DATA2_SD_DATA7
2 @ R495
0_0603_5% 1
+3VALW
2 R496
2
0.1U_0402_16V4Z
R1164
<17,19> USB20_N2
R1165
<17,19> USB20_P2
R437
1
C532
+3VS_CARD
RST#_R
MODE SEL
XTLO
XTLI
USB20_CARD_N
USB20_CARD_P
2 0_0402_5%
2 0_0402_5%
1
1
8
44
45
47
48
4
5
14
100K_0402_5%
VREG
MS_D4
NC
3V3_IN
RST#
MODE_SEL
XTLO
XTLI
XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
MS_INS#_SP9
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI
DM
DP
GPIO0
RST#_R
1
0_0402_5%
C514
1U_0402_6.3V4Z~D
<17,19> USB20_N6
<17,19> USB20_P6
@ R1162
@ R1163
2
2
1 0_0402_5%
1 0_0402_5%
2
12
32
6
46
XTAL_CTR
MS_D5
DGND
DGND
EEDO
EECS
EESK
SD_CMD
AGND
AGND
13
24
10_0402_5%
@ C540
1U_0402_6.3V4Z~D
10P_0402_50V8J
@C539
@C539
10P_0402_50V8J
SD_DATA2
SD_DATA3
R460
1
R446
1
SD_MS_CLK
@ R1032 1
2 10_0402_5%
R299 1
SDCLK
2
33_0402_5%
2
33_0402_5%
2 0_0402_5%
MSCLK
MS_DATA3_SD_DATA6
MSCD#
MS_DATA2_SD_DATA7
SD_MS_DATA0
MS_DATA1
MSBS
SD_DATA1
SDCD#
SDWP#
1
2
@ C731
10P_0402_50V8J
+3VS
15
16
17
36
The XTAL_CTR can immediacy to +3VS
SDCMD
RTS5159-GR_LQFP48_7X7
R433
0_0402_5%
R447
6.19K_0402_1%
RREF
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
C523
R439
RST#
@ R461
10_0402_5%
10
22
30
22
23
TAITW_R009-025-LR_NR
SP07000JC00
1
@ R458
AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3
+SDPWR_MSPWR
Trace width 40 mil

0_0603_5% 1
+3VS
SD_DATA2
SDCD#
U30
1
3
7
9
11
33
+D3V3
C
SD_DATA3
2
@ C511
MODE SEL
2
0_0402_5%
RTS5159_48M <12>
@ Y4
@ R436
12MHZ_16P_6X12000012
0_0402_5%
2
2
0.1U_0402_16V4Z
1
R440
@ C513
XTLI
1
22P_0402_50V8J
R454
0_0603_5%
2
MSCD#
MS_DATA3_SD_DATA6
SDCMD
MSCLK
C534
C525
+VCC_4IN1
0.1U_0402_16V4Z
Trace width 40 mil
1
1U_0402_6.3V4Z~D
1
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C526
2
@ C178
C580
1
2
C182
C531
1U_0402_6.3V4Z~D
4.7U_0603_6.3V6K
R438
0_0603_5%
1
2
SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
SD-DAT2 GND1
SD-CD
GND2
2
@ C515
1
22P_0402_50V8J
XTLO
A
Date:
LA-5091P
ho
f@
Carder RTS5159
Size
Document Number
Custom
in
Title
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
Sheet
1
23
of
39
R285 1
+3V_LAN
3.6K_0402_5%
U22
U9
<17> PCIE_PTX_IRX_P3
<17> PCIE_PTX_IRX_N3
C132
C138
1 0.1U_0402_16V7K
PCIE_PTX_C_IRX_P3
20
1 0.1U_0402_16V7K
PCIE_PTX_C_IRX_N3
21
PCIE_ITX_C_PRX_P3
<17> PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
<17> PCIE_ITX_C_PRX_N3
25
<12> CLKREQ_LAN#
<6,15,17,19,25>
27
PLTRST#
R42
1K_0402_1%
R193 1
2
30P_0402_50V8J
1
C127
2
30P_0402_50V8J
1
C139
2 2.49K_0402_1%
46
LOM_WAKE#
ISOLATEB
26
28
LAN_X1
LAN_X2
41
42
Y1
HSON
HSIP
LED0
HSIN
RTL8103EL-GR
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
REFCLK_P
REFCLK_M
CLKREQB
PERSTB
RSET
7
14
31
47
19
30
36
13
10
GND
GND
GND
GND
0.1U_0402_16V4Z
10U_0805_10V4Z
+EVDD12
@
1
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 10U_0805_10V4Z
2 0.1U_0402_16V4Z
C136
1U_0402_6.3V4Z~D
C141
1U_0402_6.3V4Z~D
+3V_LAN
3
C168
C137
C128
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RTL8103EL-GR_LQFP48_7X7
RJ45 symbol need update
+3V_LAN
R148
1
C732
2
JP71
0_0603_5%
470P_0402_50V7K~D
13
12
LAN_ACTIVITY#
1
2
R283
@ C193
1
300_0402_5%
7
RJ45_MIDI1-
U21
LAN_MDI0+
LAN_MDI0C143 1
R161 1
2 0_0402_5% LAN_MDI0+_R
R231 1
2 0_0402_5% LAN_MDI0-_R
LAN_CT0
2 0.01U_0402_25V7K
C129 1
LAN_MDI1+
LAN_MDI1-
LAN_CT1
2 0.01U_0402_25V7K
R253 1
2 0_0402_5% LAN_MDI1+_R
R145 1
2 0_0402_5% LAN_MDI1-_R
1
2
3
4
5
6
7
8
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
LEF8423A-R
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0RJ45_CT0
RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-
14
8
68P_0402_50V8J
2
2
6
5
1
R229
2
75_0402_1%
1
R162
2
75_0402_1%
+3V_LAN
Close to Pin45
1
40
43
@ C126
0.1U_0402_16V4Z
+LAN_VDD12
29
37
AVDD33
NC
NC
1K_0402_1%
2
C149 2
C134 2
C180 2
C190
@ C191 1
C133 1
44
45
VDD33
VDD33
GNDTX
Close to Pin10,13,30,36
39
NC
VCTRL12D
5
6
7
8
GND
NC
NC
VCC
R173
VCTRL12
0.1U_0402_16V4Z
22
NC
NC
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
DO
DI
SK
CS
@ AT93C46-10SI-2.7_SO8
C131
NC
23
24
2
3
5
6
8
9
11
12
4
3
2
1
C140
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
25MHz_20pF_6X25000017
LAN_ACTIVITY#
48
VCTRL12A
CKXTAL1
CKXTAL2
38
NC
LANWAKEB
ISOLATEB
EEDO
LAN_10M#_EEDI
LAN_100M#_EESK
EECS
33
34
35
32
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
<25> LAN_WAKE#
R170
15K_0402_5%
16
17
18
<12> CLK_PCIE_LAN
<12> CLK_PCIE_LAN#
+3VS
15
HSOP
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
C184
1000P_1206_2KV7K
Unused
Yellow LED+
Yellow LEDPR4PR4+
2
PR2PR3PR3+
PR2+
PR1GND
PR1+
GND
LAN_100M#_EESK
1
2
R144
@ C125
1
300_0402_5%
11
+3V_LAN
10
68P_0402_50V8J
15
16
Orange LEDGreen LED+

Green LEDFOX_JM3611A-R5A53-7F-X4
LAN_10M#_EEDI
1
2
R157
1
300_0402_5%
@ C130
68P_0402_50V8J
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
A
Title
RTL8103EL
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
E
24
of
39
+EC_AVCC
+3VALW
+3VALW
FBMA-L11-160808-601LMT_2P
L26
2
R120 1
R89 1
<17> PM_SLP_S3#
<17> PM_SLP_S5#
<17> EC_SMI#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
2 0_0402_5%
2 0_0402_5%
EC_SMI#
EC_TX
EC_RX
<19>
EC_TX
<19>
EC_RX
<26>
ON/OFF#
<22> PWR_LED#
<6,15,17,19,24> PLTRST#
PLTRST#
PLTRST#_R
2
0_0402_5%
1
@ R319
XCLKI
XCLKO
67
2
1
1
TP_CLK
<26>
TP_DATA <26>
WL_OFF#
WL_OFF#
LID_SW#
LID_SW#
SM Bus
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
GPO
GPI
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
XCLK1
XCLK0
V18R
119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
<19>
<26>
For EMI
FRD#SPI_SO <26>
FWR#SPI_SI <26>
SPI_CLK <26>
FSEL#SPICS# <26>
100P_1206_8P4C_50V8
KSO14
KSO11
KSO10
KSO15
FSTCHG <31>
CHARGE_LED#
CHARGE_LED#
SYSON
SYSON
VR_ON
ACIN
<28,33>
<35>
<17,30>
1
2
C831
100P_0402_50V8J
R123 1
2 0_0402_5%
EC_LID_OUT#
EC_ON <26>
EC_ON
EC_RSMRST#
KSO6
KSO3
KSO12
KSO13
<17>
BKOFF# <13>
1
BT_OFF# <19>
R106
WXMIT_OFF# <19>
2
0_0402_5%
VGATE
100P_1206_8P4C_50V8
RB751V-40_SOD323-2
ICH_POK_EC
1
@ R107
124
SUSP#
PBTN_OUT#
ICH_POK_EC
<6,17>
4
3
2
1
5
6
7
8
CP2
100P_1206_8P4C_50V8
KSI3
KSO5
KSO1
KSI0
4
3
2
1
R1153
5
6
7
8
CP3
100K_0402_5%
LAN_WAKE#
KSO2
KSO4
KSO7
KSO8
2
+3VS
10K_0402_5%
100P_1206_8P4C_50V8
KSI4
KSI5
KSO0
KSI2
<24>
V18R
5
6
7
8
CP4
@ D14 RB751V-40_SOD323-2
1
2
PM_SLP_S4# <17>
GMCH_ENBKL <8>
EAPD
<20>
EC_THERM# <17>
SUSP# <28,33,34>
PBTN_OUT# <17>
5
6
7
8
4
3
2
1
D24
R76
2
1
10K_0402_5%
<17>
+3VALW
110
112
114
115
116
117
118
4
3
2
1
CP1
100P_1206_8P4C_50V8
<22>
4
3
2
1
5
6
7
8
CP5
100P_1206_8P4C_50V8
C144
C160
27P_0402_50V8J
TP_CLK
TP_DATA
C146
32.768KHZ_12.5P_1TJE125DP1A000M
1
1
GPIO
KB926QFD3_LQFP128_14X14
X4
1
SPI Flash ROM
GND
GND
GND
GND
GND
XCLKO
@
97
98
99
109
ACES_85201-24051
SP01000FD00
EC_MUTE# <21>
USB_EN# <27>
SPI Device Interface
11
24
35
94
113
20M_0603_5%
122
123
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
83
84
85
86
87
88
4.7U_0603_6.3V6K
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
PS2 Interface
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
0.1U_0402_16V4Z
R327
XCLKI
77
78
79
80
R143
4.7K_0402_5%
KSI1
KSI7
KSI6
KSO9
4
3
2
1
5
6
7
8
CP6
C161
27P_0402_50V8J
om
<36>
<36>
<4>
<4>
@
@
R146
4.7K_0402_5%
l.c
<12,17,35> VGATE
<33> PM_1.8V_PWRGD
R301 1
R300 1
Rb
IREF
<31>
CHGVADJ <31>
Issued Date
Compal Secret Data
2008/11/10
Deciphered Date
ai
VGATE
PM_1.8V_PWRGD
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
R127
18K_0402_5%
68
70
71
72
2009/11/10
tm
for KB926C/D chip
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
+5VS
Title
ho
KSO2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
0_0402_5%
2
2 0_0402_5%
BRD_ID
KB926
Size
Document Number
Custom
Date:
f@
KSO1
2
47K_0402_1%
2
47K_0402_1%
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
BATT_TEMP <36>
BATT_OVP <31>
ADP_I
<31>
LA-5091P
Sheet
Rev
1.0
in
EC_SMB_CK2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
+3VALW
1
R71
1
R80
AD
63
64
65
66
75
76
xa
+3VS
R320 1
MISC
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
Ra
R122
100K_0402_5%
PWM Output
C159
0.1U_0402_16V4Z
+3VALW
INVT_PWM <13>
BEEP#
<20>
EN_WOL# <28>
ACOFF
<31>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
he
INVT_PWM
BEEP#
EN_WOL#
ACOFF
21
23
26
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
EC_RST#
EC_SCI#
<17> EC_SCI#
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
12
13
37
20
38
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
R323 1
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
AGND
R324
EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<12> CLK_PCI_LPC
<15> PCI_RST#
R321
47K_0402_5%
R322
JP13
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
1 10_0402_5%
<17>
<16>
<16>
<16>
<16>
<16>
69
@ R291
2
1
+3VALW
1
0_0402_5%
<16> GATEA20
2
0_0402_5%
1
22P_0402_50V8J
+5VALW
R330 2
2 10K_0402_5%
For ESD.
2
@ C107
KEYBOARD
CONN.
4.7U_0603_6.3V6K
ECAGND
1
R66
C166
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
R67
+3VS
0.1U_0402_16V4Z
ECAGND
U27
<16> KB_RST#
C176
9
22
33
96
111
125
1
C145
4.7U_0603_6.3V6K
1
C150
C148
C147
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
25
of
39
Need to create symbol and footprint for MX SPI ROM
Touch/B Connector
System SPI Flash ROM (8Mb)
+5VS
U28
JP20
1
2
3
4
5
6
1
2
3
4
G1
G2
<25> SPI_CLK
2 0_0402_5%
R1069
2 33_0402_5%
2 0_0402_5%
R1070
<25> FSEL#SPICS#
+3VALW
ACES_85201-0405N
SP01000H300
C179
8
0.1U_0402_16V4Z
R1068
FRD#SPI_SO
<25>
0_0402_5%
C
S
HOLD
W
VCC
VSS
SST25LF080A_SO8-200mil
1
2
C177
C750
1U_0402_6.3V4Z~D
1
C749
D48
PJDLC05_SOT23-3
100P_0402_50V8J
100P_0402_50V8J
TP_CLK
TP_DATA
R1067
R305
10_0402_5%
@
2
@ C122
22P_0402_50V8J
@ C119
4.7P_0402_50VNPO
LID Switch
MB_Power On/Off SW
+3VALW
1
+3VALW
+3VALW
R125
PUT ON TOP SIDE
100K_0402_5%
R102
47K_0402_5%
@
1
SW2
TJG-533-V-T/R_6P
D22
2
3
ON/OFFBTN#
VOUT
LID_SW#
<25>
<25>
51_ON# <30>
4
CHN202UPT SC-70
6
5
VDD
GND
ON/OFF#
U18
APX9132ATI-TRL_SOT23-3
R126
1
2
3
4
ON/OFFBTN#
2N7002LT1G_SOT23-3
10K_0402_5%
C900
ACES_87213-0200
0.1U_0402_16V4Z
1
C158
2008/11/10
D19
RLZ20A_LL34
SB770020010
D50
PJDLC05_SOT23-3
Compal Secret Data
Issued Date
1
2
G1
G2
Q18
3
JP42
2
G
EC_ON
2
<25>
1000P_0402_50V7K
C156
10P_0402_50V8J
C157
2 0.1U_0402_16V4Z
<25>
<25>
<25> FWR#SPI_SI
Deciphered Date
2009/11/10
Title
LID SW/BIOS/TP
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
26
of
39
D20
+USB_RIGHT
R17
2A
+5VALW
On Board USB Connector
+USB_RIGHT
C111
0.1U_0402_16V4Z
GND
IN
EN1#
EN2#
OC1#
OUT1
OUT2
OC2#
USB_OC#0
<17> USB20_N0
<17> USB20_P0
<17>
TPS2062ADR_SO8~D
8
7
6
5
4
3
2
1
PJDLC05_SOT23-3
@
WCM2012F2S-900T04_0805
8
7
6
5
JP16
0_0402_5%
U14
1
2
3
4
2
2
USBN0
USBP0
1
4
GND
GND
GND
GND
VCC
USB_N
USB_P
GND
SUYIN_020173MR004S52KZL
L62
R36
1
1
2
C363
USB_EN#
150U_B2_6.3V-M~D
C21
0_0402_5%
470P_0402_50V7K~D
@ D23
R39
1
2
2
1
3
0_0402_5%
PJDLC05_SOT23-3
@ L63
1.5A
<17> USB20_N3
<17> USB20_P3
USBN3
USBP3
JP72
+USB_LEFT
+5VALW
12
11
+USB_LEFT
WCM2012F2S-900T04_0805
GND2
GND1
3
U7
1
C95
0.1U_0402_16V4Z
1
2
3
4
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
R40
1
RT9711PS_SO8
USB_OC#3
<17>
USB_OC#7
<17>
2
0_0402_5%
@ D25
R74
1
10
9
8
7
6
5
4
3
2
1
2
2
@ C77
3
0_0402_5%
1000P_0402_50V7K
PJDLC05_SOT23-3
10
9
8
7
6
5
4
3
2
1
ACES_87213-1000G
@ L65
<25>
USB_EN#
USB_EN#
<17> USB20_N7
<17> USB20_P7
USBN7
USBP7
1
WCM2012F2S-900T04_0805
@ C233
R88
1
150U_B2_6.3V-M~D
2
C16
470P_0402_50V7K~D
0_0402_5%
Date:
LA-5091P
Sheet
E
ho
f@
USB PORTS
Size
Document Number
Custom
in
Title
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
27
of
39
+5VALW TO +5VS
C215
10U_0805_10V4Z
C202
C214
2
1U_0603_10V4Z
10U_0805_10V4Z
2 SUSP
G
Q9
2N7002_SOT23
@
C108
S
1
2
R185
100K_0402_5%
B+
R179
470_0603_5%
@
C201
SUSP
2
Q8 G
2N7002_SOT23
1
2
3
10U_0805_10V4Z
1 1
C76
1U_0603_10V4Z
2
2
R50
470_0603_5%
@
S
1
R68
20K_0402_5%
C74
10U_0805_10V4Z
5VS_GATE
B+
Q12
C96
2 10U_0805_10V4Z
10U_0805_10V4Z
1
2
3
+3VS
SI4800BDY-T1-E3_SO8
8
7
6
5
C97
Q6
+3VALW
SI4800BDY-T1-E3_SO8
8
7
6
5
+3VALW TO +3VS
+5VS
2 SUSP
G
Q16
2N7002_SOT23
@
C255
SUSP
0.01U_0402_25V7K
2
Q17
G
2N7002_SOT23
+5VALW
0.1U_0402_25V7K~D
If the +1.8V discharge

circuit is pop, R302,
Q28 need pop.
+5VALW
+3VALW to +3V_LA'
+3VALW
+3V_LAN
@ R302
100K_0402_5%
J4
1
JUMP_43X39
SYSON#
@ Q19
SI3445ADV-T1-E3_TSOP6
D
1U_0402_6.3V4Z~D
1
2
@ C164
0.1U_0402_16V4Z
SYSON
<25,33> SYSON
IN
@ R128
2
@ Q28
DTC124EKAT146_SC59-3
OUT
1
2
@ C165
3
GND
6
5
2
1
4
@ R134
47K_0402_5%
1
<25> EN_WOL#
2.2K_0402_5%
2
G
@ Q4
2N7002_SOT23
+RTCVREF
+5VALW
1
2
D
2 SUSP
G
Q7
2N7002_SOT23
@
IN
Q27
DTC124EKAT146_SC59-3
<25,33,34> SUSP#
1
S
R279
470_0603_5%
@
D
2 SUSP
G
Q24
2N7002_SOT23
@
D
2 SUSP
G
Q15
2N7002_SOT23
@
R61
470_0603_5%
@
1
1
1
S
R280
470_0603_5%
@
D
2 SUSP
G
Q2
2N7002_SOT23
@
R169
470_0603_5%
@
R18
470_0603_5%
@
SUSP
SUSP
+1.8V
OUT
+0.9VS
GND
+VCCP
<34>
+2.5VS
R297
100K_0402_5%
1
@ R298
100K_0402_5%
+1.5VS
2 SYSON#
G
Q23
2N7002_SOT23
@
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
A
Title
DC INTERFACE
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
E
28
of
39
CLIP1
EMI_CLIP
GND
CLIP2
EMI_CLIP
H34
H
H35
H
@
H36
H
@
H_2P8
H33
H
H32
H
@
H31
H
H30
H
H29
H
@
AGND
H7
H
H37
H
H38
H
H39
H
H_3P2
H4
H
H_2P8X3P8
FM1
@
FIDUCIAL_C40M80
om
ai
l.c
tm
Title
ho
2009/11/10
Screw
Size
Document Number
Custom
Date:
f@
Deciphered Date
Rev
1.0
in
2008/11/10
LA-5091P
Sheet
xa
Issued Date
Compal Secret Data
he
FM2
@
FM4
@
FM3
H24
H
H15
H
H23
H
GND
29
of
39
Vin Detector
1
VIN
17.624
16.998
PR1
PC4
@ 10K_0402_1% @ 0.01U_0402_25V7K
1
2
1
2
1
2
PC2
100P_0402_50V8J
PC3
100P_0402_50V8J
PC1
1000P_0402_50V7K
E&T_3802-E04N-01R
SP02000BZ00
17.841
17.210
APDIN
1
2
3
4
5
6
1
2
3
4
G1
G1
PL1
SMB3025500YA_2P
1
JP53
High 18.059
Low 17.418
PC5
1000P_0402_50V7K
PR2
1M_0402_1%
1
2
VIN
VS
N1
1
PR4
10K_0805_5%
2
PC6
0.01U_0402_25V7K
2
8
1
PR8
10K_0402_1%
2
PD1
RLZ4.3B_LL34
P
G
4
1
2
3.3V
PJ1
2
1
2
+3VALWP
2
1
2
+RTCVREF
VS
PC10
0.1U_0603_25V7K
PJ2
+3VALW
+1.5VSP
JUMP_43X118
OUT
+1.5VS
PJ4
+5VALW
+0.9VSP
JUMP_43X118
+0.9VS
JUMP_43X79
N2
PJ5
2
+CPU_COREP
PC12
1U_0805_25V4Z
PJ6
1
+CPU_CORE
+1.8VP
JUMP_43X118
+1.8V
JUMP_43X118
IN
GND
PC11
10U_0805_10V4Z
1
3
3.3V
2
PR15
200_0603_5%
PU2
BIT3021
+CHGRTC
PR16
0_0402_5%
1
JUMP_43X118
PJ3
2
+5VALWP
+RTCVREF
<17,25>
PACIN
PU1A
LM393DG_SO8
PR9
10K_0402_1%
2
1
ACIN
PR11
68_1206_5%
PC9
0.22U_0603_25V7K
1
PR13
100K_0402_1%
<26> 51_ON#
PR10
68_1206_5%
2
PR12
200_0603_5%
1
2
PR14
22K_0402_1%
1
2
PR5
10K_0402_1%
1
2
PQ1
TP0610K-T1-E3_SOT23-3
CHGRTCP
PD3
LL4148_LL34-2
2
1
+BATT
PC8
0.1U_0402_16V7K
1
2
2
PD2
LL4148_LL34-2
PR6
22K_0603_1%
1
2
2
1
PR7
19.6K_0603_0.1%
PC7
0.068U_0603_25V7M
2
1
VIN
PR3
82.5K_0603_0.1%
VIN
PJ7
+VCCPP
+VCCP
JUMP_43X118
PD16
+CHGRTC
PJ8
JP79
1
PD4
RB751V-40TE17_SOD323-2
+RTCBATT
PR17
1K_0402_5%
2
1
4
3
2
1
G2
G1
2
1
ACES_ 85204-0200N
+2.5VSP
SP02000IA00
+2.5VS
JUMP_43X118
RB751V-40TE17_SOD323-2
Issued Date
Compal Secret Data
2008/11/10
Deciphered Date
2009/11/10
A
Title
DCIN/DECTOR
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P

D
Sheet
30
of
39
PQ3
FDS4435BZ_SO8
B+
+RTCVREF
PR34
100K_0402_1%
2
1
VDAC
SRN
24751_VREF
VADJ
TP
/BATDRV
14
SRSET
PR36
2
1
107K_0402_1%
16
BATDRV
1
1
PR38
10_0603_5%
PC39
@ 0.01U_0402_25V7K
1
2
3
PR20
100K_0402_1%
5
6
7
8
1
2
3 Cell
1.9A
6 Cell
<25>
PR42
100K_0402_1%
4.35V
0V
4V
CHGEN#
1
Pre Cell
3.3V
CHGVADJ
VADJ
PC59
1000P_0402_50V7K
2
2
<25> CHGVADJ
2
G
<25> FSTCHG
PQ14
2N7002W-T/R7_SOT323-3
"CHGVADJ" connect to EC DA pin
om
Deciphered Date
B
ho
2009/11/10
f@
2008/11/10
Title
CHARGER
in
Issued Date
Compal Secret Data
tm
ai
PU4B
LM358DR_SO8
xa
G
4
l.c
Size
Document Number
Custom
Date:
Rev
1.0
he
1
2
LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.1112*BATT+
PC62
0.01U_0402_25V7K
PR62
105K_0402_1%
PU4A
LM358DR_SO8
PC13
0.01U_0402_25V7K
1
2
1.54A
2.58V
24751_VREF
ADP_I
PR41
@ 0_0402_5%
PR43
210K_0402_1%
1
2
PR64
499K_0402_1%
2
1
PR63
PR66
499K_0402_1% 340K_0402_1%
1
2
1
2
PC61
0.01U_0402_25V7K
1
2
G
4
Current
2.1V
8
P
PR39
102K_0402_1%
15
PC60
100P_0402_50V8J
IREF
IREF <25>
BQ24751ARHDR_QFN28_5X5
PQ23
2N7002W-T/R7_SOT323-3
PC18
820P_0402_25V7
ICHG setting
ACGOOD
IADAPT
PQ13
2N7002W-T/R7_SOT323-3
VS
A/D
PC37
0.1U_0603_25V7K
29
REGN
S
18
17
2
1
PC35
@ 0.1U_0603_25V7K
1
12
13
2
G
PR65
10K_0402_1%
2
1
PC34
0.1U_0603_25V7K
19
VADJ
2
PC38
VMB
<25> BATT_OVP
CELLS
<25>
1
3
20
ACOFF
@ PR32
0_0402_5%
1
2
ACOFF
21
PR156
0_0402_5%
1
2
0.1U_0603_25V7K
D
PC32
680P_0603_50V8J
PC33
0.1U_0402_16V7K
1
2
VREF
BAT
PC63
0.1U_0402_16V7K
PR40
340K_0402_1%
22
PR35
200K_0402_1%
+BATT
LEARN
SRP
11
ACSET
AGND
2
G
PR29
4.7_1206_5%
1
PGND
CELLS
24751_VREF
SIS412
23
PC36
1U_0603_10V6K
Fsw : 300KHz
PC28
10U_1206_25V6M
PC30
1U_0603_10V6K
OVPSET
PR33
100K_0402_1%
1
2
PQ7
SI2301BDS-T1-E3_SOT23-3
PC24
470P_0402_50V8J
1
2
2
9
CP Point=(Vacset/Vvdac)*(0.1/PR19)=1.328A
PR37
100K_0402_1%
PQ6
24
10
ACOFF
PC26
0.1U_0603_25V7K
LODRV
24751_VREF
24751_VREF
PR25
0.02_1206_1%
PL5
10UH_MPL73-100_3A_20%
1
2
1
PD13
LL4148_LL34-2
1
PR30
51K_0402_1%
2
7
ACOP
PC31
0.47U_0603_16V7K
30W adapter
Vacset=3.3*(51K/(205K+51K))=0.657V
ACIN detect : 17.26V
PQ4
FDS4435BZ_SO8
25
2
ACSET
3
2
1
PH
/BATDRV
26
CP point=Iadapter*85%
Input OVP : 22.3V
PR23
0_0402_5%
1
2
CP Point Setting
ACDRV
ACDET
REGN
CP setting
HIDRV
27
PQ5
SIS412
OVPSET
PR31
54.9K_0402_1%
ACN
ACP
28
REGN
ACSET
PC29
@ 0.01U_0402_25V7K
BTST
2
3
4
5
PR28
205K_0402_1%
24751_VREF 1
2
PR27
54.9K_0402_1%
PR26
340K_0402_1%
PVCC
1
2
1
PR150
0_0805_5%
ACDET
CHGEN
3
2
1
PR24
340K_0402_1%
PC21
0.1U_0603_25V6-K~D
1
2
PU3
1
PC23
@ 0.1U_0603_25V7K
PC22
0.1U_0603_25V7K
2
1
PR21
100K_0402_1%
2
1
PC19
0.01U_0402_25V7K
2
1
1
2
PD9
RLZ24B_LL34
PC20
0.1U_0402_16V7K
1
2
PC25
2.2U_0805_25V6K
@
2
1 1
PR22
3.3_1210_5%
2 1
PC14
0.01U_0402_25V7K
PR19
3.3_1210_5%
CHG_B+
1
2
PL2
FBMA-L11-201209-121LMA50T_0805
CHGEN#
PC27
10U_1206_25V6M
PC17
4.7U_1206_25V6K
1
2
PC16
4.7U_1206_25V6K
1
2
PR18
0.015_1206_1%
8
7
6
5
PC15
4.7U_1206_25V6K
1
2
3
2
1
3
2
1
PQ2
FDS4435BZ_SO8
8
7
6
5
VIN
LA-5091P

D
Sheet
31
of
39
ISL6237_B+
DL3
23
FB3
30
32
VL
PHASE1
LGATE2
LGATE1
PGND
2VREF_TPS51427
OUT1
LX5
18
DL5
PR61
100K_0402_1%
2
4
2
BYP
PC68
0.22U_0603_25V7K
14
NC
POK2
EN_LDO
POK1
EN1
ILIM1
GND
TON
EN2
NC
27
ILIM2
11
PC50
2200P_0402_50V7K
2
1
+
2
9
PR58 @ 0_0402_5%
2
1
29
21
VL
+5VALWP
Imax=4.3A
Ipeak=5.7A
Iocp(minimum)=6.4A
0_0402_5%
2VREF_TPS51427
2
28
PR60 @ 0_0402_5%
1
2
13
12
ILM1
31
ILIM2
2
1
PR70
274K_0402_1%
2
PU6
TPS51427_QFN32_5X5
PR71
316K_0402_1%
PR69
0_0402_5%
2VREF_TPS51427
1
2
3
PQ25
@
TP0610K-T1-E3_SOT23-3
PC49
4.7U_1206_25V6K
2
1
FB5
PR143
0_0402_5%
PC66
1U_0603_10V6K
2
1
2VREF_TPS51427 1
0_0402_5%
PC69
@ 0.047U_0402_16V7K
2
1
PR67
PR68
@ 47K_0402_5%
PC65
0.047U_0402_16V7K
2
PR144
806K_0603_1%
VL
PD14
RB751V-40TE17_SOD323-2
1
2
<36> MAINPWON
PR72
200K_0402_5%
1
2
PC64
680P_0603_50V8J
10
PD8
RLZ5.1B_LL34
1
2
PR51
4.7_1206_5%
22
PR59
1
VS
PC58
0.1U_0603_25V7K
LDOREFIN
SKIP
20
PQ12
SIS412
3
2
1
16
REF
PC70
0.22U_0603_25V7K
PD7
RB751V-40TE17_SOD323-2
1
2
BST5A2
PR53
2.2_0603_5%
REFIN2
FB1
DH5
17
OUT2
2VREF_TPS51427
+3VALWP
Imax=5.5A
Ipeak=7.2A
Iocp(minimum)=9A
15
PC53
2
1
PHASE2
4.7U_0805_6.3V6K
7
LDO
3
VCC
BOOT1
PC67
150U_B2_6.3VM_R35M
25
UGATE1
BOOT2
PR55
@ 61.9K_0402_1%
1
2
LX3
UGATE2
PL11
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1
PR57
0_0402_5%
1
2
24
PC54
1U_0603_10V6K
1
2
19
3
2
1
26
+5VALWP
DH3
BST3A
PVCC
2
1
PR52
2.2_0603_5%
PC56
0.1U_0603_25V7K
TP
VIN
6
4
1
SI7716ADN-T1-GE3_PAK1212-8
PQ24
1
2
3
5
2
1
PR56
10K_0402_1%
PC57
680P_0603_50V8J
PR50
4.7_1206_5%
PR54
0_0402_5%
33
1U_0603_10V6K
1
2
3
PL12
3.3UH_PCMC063T-3R3MN_6A_20%
1
2
PC52
1
2
SIS412
PQ11
PC51
0.1U_0603_25V7K
4
+3VALWP
VL
PQ26
SI7716ADN-T1-GE3_1212-8
2
1
2
1
PC47
2200P_0402_50V7K
2
1
PC48
4.7U_1206_25V6K
2
1
PR49
0_0402_5%
1
2
2
PC45
4.7U_1206_25V6K
2
1
PC55
150U_B2_6.3VM_R35M
ISL6237_B+
PL4
FBMA-L11-201209-121LMA50T_0805
PC46
4.7U_1206_25V6K
2
1
B+
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
5
Title
3VALW/5VALW
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
32
of
39
PJP1
2
B+
1
2
PC84
10U_1206_25V6M
1
2
PC82
1
2
+1.8VP
Imax=3.6A
Ipeak=4.8A
Iocp(minimum)=6A
PQ16
AO4466_SO8
0.1U_0603_25V7K~D
4
PL7
3
2
1
7
LG_1.8
TPS51117RGYR_QFN14_3.5x3.5
+1.8VP
2
5
6
7
8
PQ17
AO4712_SO8
2 1
11
PR95
@ 4.7_1206_5%
D
D
D
D
10
TRIP_1.8 1
2
7.68K_0402_1%
V5DRV_1.8
PR94
0_0603_5%
PC91
47P_0402_50V8J
2
1
DRVL
PR90
PC89
4.7U_0805_10V6K
PC95
PC96
@ 680P_0603_50V8J
PGOOD
1
1
VBST
V5DRV
LX_1.8
15
14
TP
EN_PSV
TRIP
VFB
12
S
S
S
<25> PM_1.8V_PWRGD
V5FILT
UG_1.8
PC79
+
2
3
2
1
LL
13
FB_1.8
DRVH
V5FILT_1.8
VOUT
PGND
PR85
300_0603_5%
1
2
TON
GND
PU7
+5VALW
220U_D2_4VM
1
0_0603_5%
TON_1.8
PC97
1U_0603_10V6K~D
BST_1.8
PC93
.1U_0402_16V7K
@
PR77
EN_1.8
PR93
30.1K_0402_1%
+5VALW
4.7U_0805_6.3V6K
PR92
0_0402_5%~D
2
1
<25,28> SYSON
JUMP_43X118
@
5
6
7
8
PR96
267K_0402_1%
1
2
PC78
10U_1206_25V6M
PC139
2200P_0402_50V7K
2
1
+1.8VP_B++
@
2
PR78
30.1K_0402_1%
PJP2
PR79
21.5K_0402_1%
B+
1
2
PC83
10U_1206_25V6M
1
2
PC81
10U_1206_25V6M
VCCPP_B++
JUMP_43X118
@
PR81
0_0402_5%~D
2
1
PR82
PC90
47P_0402_50V8J
2
1
TPS51117RGYR_QFN14_3.5x3.5
PC86
4.7U_0805_10V6K
PC88
@ 680P_0603_50V8J
PC92
+VCCPP
Imax=5.4A
Ipeak=7.2A
Iocp(minimum)=9A
@
2
220U_D2_4VM
5
6
7
8
PQ19
AO4712_SO8
LG_VCCP
+VCCPP
PC94
4.7U_0805_6.3V6K
PR87
@ 4.7_1206_5%
2 1
TRIP_VCCP
1
2
12.4K_0402_1%
V5DRV_VCCP
11
D
D
D
D
PR91
10
DRVL
LX_VCCP
S
S
S
PGOOD
V5DRV
1
PR86
0_0603_5%
2
VBST
3
2
1
14
15
TP
TRIP
VFB
12
UG_VCCP
3
2
1
V5FILT
13
DRVH
FB_VCCP
PL13
+5VALW
LL
PGND
PC87
1U_0603_10V6K~D
V5FILT_VCCP
VOUT
TON
EN_PSV
GND
PU10
PR84
300_0603_5%
1
2
PQ18
AO4466_SO8
0.1U_0603_25V7K~D
4
TON_VCCP
+5VALW
PC85
1
2
0_0603_5%
PR83
30.1K_0402_1%
BST_VCCP 1
EN_VCCP
PC80
.1U_0402_16V7K
@
SUSP#
<25,28,34>
5
6
7
8
PR80
267K_0402_1%
1
2
1
PR88
8.66K_0402_1%
PR89
21.5K_0402_1%
4
A
ho
Title
1.8V/VCCP
f@
2009/11/10
in
Deciphered Date
xa
2008/11/10
Size
Document Number
Custom
Date:
Rev
1.0
he
Issued Date
Compal Secret Data
tm
ai
l.c
om
LA-5091P

D
Sheet
33
of
39
PJ10
JUMP_43X39
PU9
APL5912-KAC-TRL_SO8
3
4
+1.5VSP
PR97
3K_0402_1%
PC131
@220U_D2_4VM
PR145
2.7K_0402_1%
FB
PC128
0.47U_0402_6.3V6K
EN
POK
VOUT
VOUT
PC99
10U_0805_6.3V6M
VCNTL
VIN
VIN
GND
8
7
PC129
0.01U_0402_25V7K
6
5
9
2
1
2
PC98
1U_0603_10V6K
PR98
10K_0402_1%
1
2
<25,28,33> SUSP#
1
2
1
PC130
10U_0805_6.3V6M
PJ9
@ JUMP_43X39
+5VALW
+1.8V
PU14
APL5508-25DC-TRL_SOT89-3
NC
6
5
+3VALW
NC
VOUT
NC
7
2
VREF
TP
PC133
1U_0603_10V6K
+2.5VSP
GND
1
OUT
PR149
@ 150_1206_5%
2
1
VCNTL
GND
PC137
1U_0603_10V6K
VIN
3
PR148
1K_0402_1%
PC136
4.7U_0805_6.3V6K
PU12
1
IN
+3VS
PC135
4.7U_0805_6.3V6K
PJ11
@ JUMP_43X39
+1.8V
8
9
B
PC138
0.1U_0402_16V7K
2
G
+0.9VSP
PR147
1K_0402_1%
PQ27
2N7002W-T/R7_SOT323-3
PC134
@ 0.1U_0402_16V7K
SUSP
PR146
0_0402_5%
1
2
1
<28>
APL5331KAC-TRL_SO8
PC132
10U_0805_6.3V6M
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
5
Title
1.5VS/0.9VS/2.5VS
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
1
34
of
39
CPU_VID6
<5>
CPU_VID5
<5>
CPU_VID4
<5>
CPU_VID3
<5>
CPU_VID2
<5>
CPU_VID1
<5>
CPU_VID0
<5>
+VCCP
1
2
4.7U_0805_25V6M
PC102
4.7U_0805_25V6M
PC104
1
2
4.7U_0805_25V6M
PC101
1
2
4700P_0402_25V7K
PC100
5
6
7
8
PC105
1U_0402_6.3V6K
2
1
PC118
0.01U_0402_25V7K
2
1
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
2
PR132
2
PR110
2
PR131
PQ21
AO4466_SO8
3
2
1
PC107
0.22U_0603_25V7K
1
2
PL14
1
2
UGATE
BOOT
FB
11
PC110
1000P_0402_50V7K
VDD
COMP
NC
28
1
LGATE_CPU
UGATE_CPU
22
BOOT_CPU
PHASE_CPU
23
PD15
B340A_SMA2
3
2
1
25
24
PC109
680P_0603_50V8J
21
+CPU_CORE
Imax=3A
Ipeak=4A
Iocp(minimum)=7A
2
82P_0402_50V8J
PC114
1200P_0402_50V7K
1
2
1
2
1.54K_0402_1%
PR123
10_0603_5%
1
2
1000P_0402_50V7K
2
+CPU_B+
1
2
PR129
1K_0402_1%
PR130
1.62K_0402_1%
2 2
PR126
@ 3.57K_0402_1%
PH2
@ 10KB_0603_5%_ERTJ1VR103J
1
330P_0402_50V7K
2
PC121
1
PC123
330P_0402_50V7K
PR128
PC117
1000P_0402_50V7K
1.37K_0402_1%
1
2
PR127
0_0402_5%
VSUM
2
1
<5>
+5VS
PC115
0.22U_0603_25V7K
@ 0.068U_0402_10V6K
PC119
0.1U_0402_16V7K
2
1
VSSSENSE
PC116
1
PR125
0_0402_5%
PC120
1
2
PR124
1K_0402_1%
1
2
VCCSENSE
1
2
PR121
10_0603_5%
PC113
1U_0402_6.3V6K
PR122
<5>
PR116
7.68K_0402_1%
2
4
1
26
PQ28
AO4712_SO8
27
PR115
4.7_1206_5%
332K_0402_1%
1
PC112
+CPU_COREP
5
6
7
8
29
VID3
VID4
VID5
VID6
VR_ON
DPRSTP#
PR113
0_0603_5%
1
2
30
PR120
120P_0402_50V8J
B+
31
32
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
33
37
36
39
38
3V3
CLK_EN
PGOOD
GND PAD
PU15
ISL6261ACRZ-T_QFN40_6X6
VW
PC111
2
1
6.81K_0402_1%
20
10
PHASE
VSS
VSSP
OCSET
VIN
1
2
4.12K_0402_1%
SOFT
19
LGATE
18
VCCP
NTC
VSUM
VR_TT#
VO
17
PR118
VID0
DFB
H_PROCHOT#
2
@ 100K_0603_1%_TH11-4H104FT
1
2
PC108
0.015U_0402_16V7K
PR119
PL9
FBMA-L11-201209-121LMA50T_0805
VSUM
PR117
@ 4.22K_0402_1%
RBIAS
DROOP
VID1
15
VID2
PMON
14
PH1
1
DPRSLPVR
RTN
<4> H_PROCHOT#
40.2K_0402_1%
VSEN
1
2
147K_0402_1%
13
PR112
40
41
FDE
12
PWON
1
PR114
VDIFF
1
2
PC106
@ 0.1U_0402_16V7K
<12,17,25> VGATE
2
PR104
2
PR111
2
PR106
2
PR107
2
PR108
PR103
10K_0402_1%
+CPU_B+
PR101
1_0603_5%
PC103
1U_0603_10V6K
+3VS
+5VS
PR102
0_0402_5%
1
2
PR105
0_0402_5%
1
2
CLK_ENABLE#
34
<4,16> H_DPRSTP#
H_PROCHOT#
VR_ON
PR100
0_0402_5%
1
2
35
<6,17> PM_DPRSLPVR
PR109
499_0402_1%
1
2
<25>
PR99
68_0402_5%
16
+CPU_COREP
om
PC122
0.22U_0603_25V7K
ho
f@
+CPU_CORE
Size
Document Number
Custom
Date:
in
Title
LA-5091P
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
Sheet
1
35
of
39
PH3 under CPU botten side :

CPU thermal protection at 85 degree C
Recovery at 45 degree C
VMB
PL10
SMB3025500YA_2P
1
2
JBATT1
VL
+BATT
VL
+3VALWP
PC125
0.01U_0402_25V7K
PR133
47K_0402_1%
PH3
100K_0603_1%_TH11-4H104FT
2
O
-
2
100_0402_1%
EC_SMB_CK1
<25>
2
1
1
PR137
<32>
2
G
PU1B
LM393DG_SO8
VL
PR139
100K_0402_1%
PR140
100K_0402_1%
@
1
PJSOT24C_SOT23-3
PD11
PD10
PJSOT24C_SOT23-3
<25>
EC_SMB_DA1
BATT_TEMP <25>
2
100_0402_1%
PC127
1000P_0402_50V7K
2
1K_0402_1%
1
PR136
1
PR142
PC126
0.22U_0603_25V7K
2
1
TM_REF1
+3VALWP
PR138
21.5K_0402_1%
1
2
PR141
6.49K_0402_1%
PR135
13.7K_0402_1%
1
2
MAINPWON
2
SUYIN_200070MR007G101
DC040901170
PR134
47K_0402_1%
1
PC124
1000P_0402_50V7K
EC_SMDA
EC_SMCA
PQ22
2N7002W-T/R7_SOT323-3
47K_0402_1%
PR155
1K_0402_1%
1K_0402_5%
2
2
1
1
PR154
PR153
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
GND
GND
A/D
Issued Date
Compal Secret Data
2008/11/10
Deciphered Date
2009/11/10
A
Title
BATTERY CONN/OTP
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P

D
Sheet
36
of
39
Version change list (P.I.R. List)

Item
Date
Page 1 of 1
Fixed Issue
2009/1/12
Circuit issue
2009/1/12
System can't boot to S0
2009/1/12
Rev.
PG#
Modify List
13
Change JP24 pin definition
0.2
12
MCH_CLKREQ# connection move from U11.21 to U11.37
Card reader remove crystal and use

48MHz from CLK generator
0.2
12
23
Pop R295, R137 change from 33 ohm to 22 ohm

Pop R440, de-pop C511, C515, Y4
2009/1/12
WWAN function de-pop
0.2
19
De-pop C106, C196, C223, R75, R114, R115, JP56
2009/1/12
For S5 +3VS back drive issue
0.2
17
De-pop R284
2009/1/12
Material change
0.2
27
Change C233 and C363 to small package
2009/1/12
Codec can use 5V level for analog

power
0.2
20
De-pop U20, C407 and pop R293
2009/1/12
LED circuit modify
0.2
22
1. JP62.11 as NC and JP62.3 connects to +5VALW.

2. Remove R294 and R576, and add serial resistors R314 and R315.
2009/1/13
Change material
0.2
21
Change Audio jack (JP60,JP61) to DC230005P00
10
2009/1/13
Change material
0.2
27
Change USB (JP16) connector to DC233004Q00
11
2009/1/13
Change material
0.2
26
12
2009/1/14
Change material
0.2
14
13
2009/1/14
Swing is too big for SATA

eye's diagram
0.2
16
Delete R12, and tied SATARBIASN & SATARBIASP together

and connect to GND through a 24.9 ohm resistor
14
2009/1/15
For double place EMI solution
0.2
27
Delete R39,R40,R74,R88,L63,L65,D23,D25
15
2009/1/16
Board ID function
0.2
25
Pop R122, and change R127 to 8.2k
16
2009/1/17
Change pin out for LVDS connector
0.2
13
Swap INVT_PWM from JP24.3 to JP24.7
17
2009/1/17
Add control backlight function
0.2
13
Change Q80 to SB93457008L, pop Q80, C829, R1158, Q81,R1159, and de-pop L18
18
2009/1/17
Current leakage
0.2
28
De-pop R298, pop R297
19
2009/1/19
RGB EA fail
0.2
14
Change L1,L3,L4 to SM01000AO0L
20
2009/1/19
Change material
0.2
24
Change JP71 to DC230901190
21
2009/1/20
add EMI solution
0.2
27
Add R39,R40,R74,R88,@D23,@D25,@L63,@L65
22
2009/1/20
For layout require
0.2
13
change R1006,R1007 to 0402 size
23
2009/1/20
For circuit design
0.2
13
change R1159 to 0402 size
24
2009/1/21
LAN LED reversed
0.2
24
Update JP71 symbol
0.2
Change SPI ROM (U28) to SA00000XT00

Change Bead (L5,L19) to SM01003000L
ho
f@
Hardware-PIR-I
Size
Document Number
Custom
Date:
in
Title
LA-5091P
Rev
1.0
xa
2009/11/10
Deciphered Date
he
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
Sheet
E
37
of
39

Item
Date
Page 1 of 1
Fixed Issue
2009/1/21
Without beep when unplug RAM
26
2009/1/21
Speaker pin out reversed
27
2009/1/21
28
2009/1/21
29
Rev.
PG#
Modify List
20
Add C217,R1160,R1161,C213,C833
0.2
21
Modify JP55 pin definition
Update SATA symbol
0.2
22
Modify JP48 pin name
Remove WWAN signals
0.2
27
Change JP72 to 10 pin connector
2009/2/2
De-pop material
0.2
28
De-pop R302 and Q28
30
2009/2/6
Choose 48M function
0.2
23
Pop R299
31
2009/2/6
card reader INF installation issue
0.2
23
De-pop R436
32
2009/2/10
Fine tune LPC_FRAME# overshoot
0.3
16
Add R900
33
2009/2/18
Move cap to USB board
0.3
27
De-pop C233
34
2009/2/20
Solve "Zi Zi" noise
0.3
20
De-pop R1160,R1161 and remove C217
35
2009/2/20
Reserve for ESD
0.3
26
Add C900,D50 but de-pop
36
2009/2/27
Change CPU form N270 to N280
0.3
37
2009/2/27
To meet crystal requirement
0.3
25
Change C160 and C161 from 15pF to 27pF
38
2009/3/3
Modify board ID
1.0
25
Change R127 form 8.2k to 18k
39
2009/3/3
remove on board power switch
1.0
26
de-pop SW2
40
2009/3/4
WWAN concern
1.0
12
Add C903,C904,C905 and change C181,C198 from 0.1uF to 47pF
41
2009/3/10
USB modem issue
1.0
23
Reserve USB port 2 to WLAN and reserve USB port 6 to Card reader and add
R1162,R1163,R1164,R1165,R1166,R1167,R1168,R1169
42
2009/3/10
1.0
19
Delete R75 and add J3
43
2009/3/11
Modify H4 and H23
1.0
29
Change H4 from H_3P0X4P0 to H_2P8X3P8 and H23 from H_3P0 to H_2P8.
44
2009/3/11
For beep noise
1.0
20
Add D1 and R1170
45
2009/3/31
1.0
10,25
Change C260,C276,C281,C330 to SE107475M0L, change C831 to SE071101J80
25
0.2
4,5,12
For derating concern
change X1 part
Change CPU P/N to N280 and de-pop R82 and pop R81 for FSB frequency to 667MHz
2008/11/10
Issued Date
Compal Secret Data
2009/11/10
Deciphered Date
A
Title
Hardware-PIR-II
Size
Document Number
Custom
Date:
Rev
1.0
LA-5091P
Sheet
E
38
of
39
Page 1 of 1 for PWR
RTC Battery Pin define
Reason for change
Rev.
PG#
Phase
0.1
JP79 connection pin1 exchange pin2
1/13
Battery connect placement from TOP to Bottom
0.1
JABTT1 footprint change to SUYIN_200070MR007G101ZR_7P-T
1/13
0.1
PQ5,PQ6,PQ11,PQ12 P/N change from SB00000AU00 to SB00000IA00

PQ16,PQ18 P/N change from SB00000920L to SB00000CG00
PQ17,PQ19 P/N change from SB000004T8L to SB00000AJ00
1/14
COST
Modify load line setting
0.1
PR116 change from 11.68K to 7.68K

PR128 change from 1.82K to 1.37K
1/14
Modify charger current setting
0.1
PR36 change from 174K to 107K
1/14
B
B
0.1
PU5 P/N change from SA00002D200 to SA00002V40L

PU2 P/N change from SA009200010 to SA00002E200
PC24 P/N change from SE071471J80 to SE074471K80
1/17
COST
For EMI
0.1
Add PC139 2200PF
1/17
Battery cell setting
0.1
Add PR156 0
Unpop PR32 0
1/17
Modify P/N for unify
0.2
PR81, PR92 P/N change from SD02800008L to SD028000080

PR142, PR154 P/N change from SD03410018L to SD034100180
PR138 P/N change from SD034215280 to SD03421528L
PR133, PR134 P/N change from SD034470280 to SD03447028L
PC105, PC113 P/N change from SE000000K80 to SE000000K8L
PC82, PC85 P/N change from SE042104K8L to SE042104K80
PC11 P/N change from SE053106Z80 to SE053106Z8L
PC87, PC97 P/N change from SE080105K8L to SE080105K80
2/18
8
9
10
Change P/N for Lead Free
0.3
PR128 P/N change from SD034137100 to SD03413718L

PR3 P/N change from SD027825200 to SD027825280
3/18
X build
11
Change drive IC voltage input resister for suqence
0.3
PR84 change from 0 to 300

PR85 change from 0 to 300
3/18
X build
12
Change P/N for approve
0.3
PU5 P/N change from SA00002V40L to SA00002V400
3/19
X build
13
Protect Charger IC burn out for Adapter Inrush

Current
0.3
Add NonPop PD9 SC4LZ24B0T1 S ZEN DIO RLZ24B (LL-34)

Add PR150
SD00200008L S RES 1/8W 0 +5% 0805
3/27
X build
Reduce CPU Switch phase ring for High speed trace
0.3
Pop PR115 S RES 1/4W 4.7 +-5% 1206

Pop PC109 S CER CAP 680P 50V J NPO 0603
4/17
X build
2009/11/10
Deciphered Date
5
Title
PWR-PIR
Size
Document Number
Custom
Date:
LA-5091P
ho
2008/11/10
Issued Date
Compal Secret Data
tm
ai
l.c
om
Enter windows hang
f@
14
Rev
1.0
he
Date
RTC Battery can not work
Modify List
in
Fixed Issue
xa
Item
Sheet
1
39
of
39

Dell Mini 10 - Compal La-5091p Kiu20 - Rev 1.0sec

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A

MODEL )AME : KIU20

Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

Wednesday, April 22, 2009

Compal Electronics, Inc.

Compal Secret Data

Model )ame : KIU20

1.8V DDRII 400/533

USB daughter board

AMP & Speaker

Through LVDS cable

Compal Electronics, Inc.

Compal Secret Data

Wednesday, April 22, 2009

External PCI Devices

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VS always on power rail

SLP_S3# SLP_S4# SLP_S5#

ICH7M SM Bus address

Compal Electronics, Inc.

Compal Secret Data

Wednesday, April 22, 2009

Close to CPU pin

Close to CPU pin

H_THERMDA, H_THERMDC routing together.

CPU THERMAL SENSOR

Compal Electronics, Inc.

Compal Secret Data

Zo=27.4ohm +/-15%, make

Close to CPU pin

This shall place near CPU

CPU N270 P/N: SA00002O31L

Wednesday, April 22, 2009

Length match within 25 mils

PLACE IN CORRIDOR AND CLOSE TO CPU

Compal Electronics, Inc.

Compal Secret Data

Wednesday, April 22, 2009

Strap Pin Table

Share +DIMM_VREF for

C50 be placed <100mils

Compal Electronics, Inc.

Compal Secret Data

Wednesday, April 22, 2009

DDR2 SYSTEM MEMORY

Compal Electronics, Inc.

Compal Secret Data

Wednesday, April 22, 2009

<13> LVDSAC<13> LVDSAC+

<13> LVDSA0<13> LVDSA1<13> LVDSA2<13> LVDSA0+

Compal Electronics, Inc.

Compal Secret Data