A

Compal confidential

Schematics Document
Mobile Arrandale rPGA989 with
Intel PCH(Ibex Peak-M) core logic

2009-10-23

Rev 1.0

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
E

of

55

Compal confidential

Fan conn

Calpella Consumer 14" UMA +Switchable

Page 6

CK505

Mobile Arrandale

32QFN

Clock Generator
ICS9LRS3197AKLFT

P19

ATI M93

2C CPU + GMCH

PCIE-Express 16X
page 24,25,26,27,28

Socket-rPGA989
VRAM DDR3
512MB

Dis

LCD Conn.

Page 6,7,8,9,10

page 21

Dis

page 29

Dis

Dis

DDR3 SO-DIMM X2
BANK 0, 1, 2, 3

P17, 18

Dual Channel

UMA

MUX

CRT

DDR3 1066/1333 MHz 1.5V

Mini-Card x 2
FDI BUS

page 20

DMI X4

USB conn x3

P31

P37

UMA

MUX

BT Conn

P37

USB2.0 X11

Dis

USB Camera

Intel PCH

HDMI Conn.
page 23

Azalia

Ibex Peak-M
FCBGA 951

PCI-E BUS*4

Finger print

SATA Master-1
SATA Slave

Cardreader

New Card

SPI

P37

P33

Page 11,12,13,14,15,16

8111DL VB
Mini-Card Mini-Card
8103EL
WLAN
WWAN
(10/100 /Giga LAN)P32
P31
P31

P21

MDC Conn

P34

USB2.0 X1

LPC BUS

P31

Audio CKT
Codec_IDT92HD80

Audio Jack

P34

P38

P35

SPI ROM 16M

MX25L1605DM2I-12G

RJ45/11 CONN
P32

4M Bytes

ENE
KB926

SATA HDD Connector

P30

Version D2

P38

SATA ODD Connector

P30

RTC CKT.

LED

P11

Touch Pad CONN.

Dock
P40

Int.KBD
Multi-Bay

P39

P40

USB2.0*1

P30

RGB

ACCELEROMETER
ST

SPI ROM
WIESON G6179

RJ45
P30

SPDIF

e-SATA Connector

P37

P38

MIC*1

USB Board Conn

USB conn x2

P37
4

256K bits

LINE-OUT*1

K/B backlight Conn

Capsense switch Conn

P40

P40

Compal Secret Data

Security Classification

DC/DC Interface CKT.

P41

2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P36

Title

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom
Calpella
Date:

Rev
1.0

DIS LA-4107P

Monday, November 09, 2009

Sheet
E

of

55

Symbol Note :

Voltage Rails

O MEANS ON

USB assignment:

X MEANS OFF

: means Digital Ground

USB-0 Right side

USB-1 Right side
USB-2 Left side(with ESATA)

: means Analog Ground

power
plane

USB-3 Docking
USB-4 Camera

@ : means just reserve , no build

+5VALW

+B

+1.5V

+5VS
+3VS

+3VALW

USB-6 X
USB-7 X

BATT @ : means need be mounted when 45 level assy or rework stage.

+1.5VS
+0.75VS

USB-8 MiniCard(WWAN/TV)
USB-9 New card

CONN@ : means ME part

+VCCP

State

USB-5 WLAN

45@ : means need be mounted when 45 level assy or rework stage.

USB-10 Cardreader

SG@ : means stuff when Switchable graphic

+CPU_CORE
+1.05VS

USB-11 Finger Printer

USB-12 BT

PA@ : Only For PA

+1.8VS

OPP@ : Only For OPP

PCIe assignment:
PCIe-1 WWAN

DIS@ : means stuff when DIS only

S0

DEBUG@ : means stuff when need Mini Card LPC debud card

S1

8111DL@ : means stuff for 8111DL

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

PCIe-2 WLAN
PCIe-3 LAN
PCIe-4 New card
PCIe-5 X

8103EL@ : means stuff for 8103EL

PCIe-6 X

SATA assignment:
SATA0 HDD
SATA1 ODD
SATA2 X
SATA3 X

SATA4 ESATA
SATA5 Mulit-Bay

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

SOURCE

XDP

KB926

KB926

BATT

Thermal
Sensor

SODIMM

WLAN
CLK CHIP WWAN

M93
Thermal NB10M-GE Cap sensor
board
Sensor

X
X

X
X

NEW
CARD

PCH I2C / SMBUS ADDRESSING

G sensor

X
X

PCH

PCH

PCH

+3VS

+5VL

+3VS

+3VS

+3VALW

+5VL

+3VALW

M93 SMBUS Control Table

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

G sensor

1D

00011101

NAL70 SKUs

+3VS

PA@
ZZZ1

PCB part number

DA80000GL00
DAZ0BI00200
OPPDAZ0BI00300

Stencil Memo:

OPP@
ZZZ2

PCB
PA

SOURCE
D_EDID_DATA
D_EDID_CLK
D_CRT_DDC_DATA
D_CRT_DDC_DATA
HDMIDAT_VGA
HDMICLK_VGA

M93

LVDS

CRT

HDMI

PA:

PJ1, PJP903, PJP301, PJP302, PJP303, PJP304, PJP401,

PJP601, PJP602, PJP603, PJP501, PJP901, PJP902

PJ1, PJP301, PJP302, PJP303, PJP304, PJP401,

PJP601, PJP602, PJP603, PJP501, PJP901, PJP902, JP303

PCB-MB

PCB-MB

PCH version

M93

OPP:

M93

Stand-off Location:

A1 QV73 SA00002KV10
B0 QLLT SA00002KV30
B1 QMGS SA00002KV60

H12, H14

B3 QMNT SA00003N730
Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Notes List

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

Rev
1.0
Sheet

of

55

1A

0.3A

Dock con

+V_BATTERY

60mA

Dock con

+3VAUX_BT

1.3A

INVPWR_B+

LVDS CON
EC_ROM

DOCK_VIN

VL

20mA

+5VL

10mA

+3VL_EC

EC

7.9A

VIN

7947mA

+3VALW

50mA

+3V_LAN

7.05A

+3V_PEC

169mA

B++

500mA

201mA

+USB_VCC

500mA

7.7A

+5VALW

+5VALW_LED

6.1A

+3VS_WLAN

Mini card-WLAN
250mA

USB-L(ESATA)

20mAx4

LED

600mA
300mA

+1.8VSDGPU

35mA

MDC

+3VS_HDA
8 A

+1.5V_B+

DDR3

+1.5V
380mA

650mA

+0.75V

3.7 X 3=11.1V
1A
1650mA

+1.5VS_WLAN

1mA

800Mhz 4G x2

0.5A

BATT

0.5A

+1.5VS
650mA

+1.5VS_PEC

650mA

5.2A

+1.1VSDGPU

3A

60mA

Mini card-WLAN

18.24A

2.89A

VCCP_B+

25.24A

1.8A

M93 GPU

1300mA

M93 GPU
+VCCP

18A
80mA

+1.05V_VCCP
7A

7A

+1.05VS

CODEC 92HD81
INT_MIC

DDR3 VRAM

162mA

M93 GPU

+AVDD_CODEC

New card

1300mA
2.2A

G-SENSOR

150mA

Mini card-WWAN

+1.5VSDGPU

1mA

+3VS_VGA

500mA

3A

CODEC I/O

+3VS_ACL

DDR3

60mA

2.5A

M93 GPU

CPU

20A
2.13A

CPU

DDR3

+5VS

3A

PCH

850mA

+1.8VS

DC

Mini card-WWAN

1A

USBX2-R

0.1A

B+

1A

+3VS_WWAN

1A

PCH

LVDS CON

+3VS_CK505

1A

NEW CARD

1.5A

+LCDVDD

250mA

LAN

275mA

PCH

530mA
1A

CODEC 92HD81

Finger printer

1.5A

+3VS

275A

25mA

+3VS_DVDD

541mA

AC

New card

INT_MIC

CIR

201mA

BLUE TOOTH

1.3A

+3VS_PEC

SPI ROM(PCH)

25mA

7302mA

60mA

1A

PCH

50mA/4.75V

CPU

120mA

+1.05VS_CK505

100mA

PCH

CODEC PVDD
ODD
HDD
Multi Bay

1A

+CRT_VCC

CRT CONN

+USB_CAM
+5VS_LED

PC Camera
20mAx6

LED

100mA

+5VSDGPU

M93 GPU

5.49A

1.72A

1.3A

CPU_B+

+VCC_CORE

GFX_B+

+GFX_CORE

VGA_B+

+VGA_CORE

48A/1.05V

15A/1.05V

10A/1.1V

CPU
CPU
M93 GPU

Compal Secret Data

Security Classification

Issued Date

2007/08/28

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Power delevry

Size
Document Number
Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

1

Sheet

of

55

Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Notes List

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

Rev
1.0
Sheet

of

55

Layout rule 10mil

width trace length <
0.5", spacing 20mil

COMP3

AT24

COMP2

R5 1

2 49.9_0402_1% COMP1

G16

COMP1

R7 1

2 49.9_0402_1% COMP0

AT26

COMP0

H_CATERR#

H_PECI_ISO
2
0_0402_5%

H_PROCHOT#

<49> H_PROCHOT#

H_THERMTRIP#

<14,26> H_THERMTRIP#

R20

R21

R23

<46> VTTPWRGOOD

H_PWRGD_XDP

<14> BUF_PLT_RST#

AP26

RESET_OBS#

H_PM_SYNC_R
2
0_0402_5%

AL15

PM_SYNC

2SYS_AGENT_PWROK
0_0402_5%

AN14

VCCPWRGOOD_1

2 VCCPWRGOOD_0
0_0402_5%

AN27

VCCPWRGOOD_0

VDDPWRGOOD_R

R1250
2K_0402_5%
1
2

2
R1249
R25 1
R26

1
1.5K_0402_1%
2 H_PWRGD_XDP_R
0_0402_5%

PLT_RST#_R

1.5K_0402_1%

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

PEG_CLK
PEG_CLK#

CLK_EXP
CLK_EXP#

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A18
A17

CLK_EXP <12>
CLK_EXP# <12>

OK

eDP

2 51_0402_1%

XDP_TMS

@ R4 1

2 51_0402_1%

XDP_PREQ# @ R6 1

2 51_0402_1%

XDP_TDO

2 51_0402_1%

R8 1

This shall place near CPU

XDP_TCK

F6

SM_DRAMRST#

AL1
AM1
AN1

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXT_TS#[0]
PM_EXT_TS#[1]

AN15
AP15

PM_EXTTS#0
PM_EXTTS#1

PRDY#
PREQ#

AT28
AP27

XDP_PRDY#
XDP_PREQ#

TCK
TMS
TRST#

AN28
AP28
AT27

XDP_TCK
XDP_TMS
XDP_TRST#

TDI
TDO
TDI_M
TDO_M

AT29
AR27
AR29
AP29

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

DBR#

AN25

XDP_DBRESET#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

R14

T63 PAD
2 0_0402_5%

@ R9 1

PM_EXTTS#1_R <17,18>
from DDR

+3VS

XDP_DBRESET#
XDP_DBRESET#

<13>

R27

2 10K_0402_5%

PM_EXTTS#1

R29

2 10K_0402_5%

R30

2 0_0402_5%

XDP_TDI

@ R32

2 0_0402_5%

XDP_TDO

PWM Fan Control circuit

+5VS

+1.5V

1 68_0402_5%

SM_DRAMRST#

XDP_TDI_M

@ R37

2 0_0402_5%

R40

2 100_0402_1%

SM_RCOMP1

R41

2 24.9_0402_1%

SM_RCOMP2

R42

2 130_0402_1%

XDP_TRST#

R39

3
4

1
2
GND
GND
B

ACES_88231-02001
CONN@

+FAN
PCH_DDR_RST

2 51_0402_1%

C1387
0.1U_0402_16V4Z

<14>
D Q102

C1430
470P_0402_50V7K

@ D57

G
<39>

RLZ5.1B_LL34

FAN_PWM

SI3456BDV-T1-E3_TSOP6

Change PCB Footprint from

ACES_85204-02001_2P to
ACES_88231-02001_2P

SM_RCOMP0

R1207
100K_0402_5%

2 0_0402_5%

RB751V_SOD323

<17,18>

Q104
BSS138_NL_SOT23-3

DDR3 Compensation Signals

R38

XDP_TDO_R

DRAMRST#

C1386
4.7U_0805_10V4Z

1
2
1

1
2
5
6

2 68_0402_5%

JP2
R1206
1K_0402_1%

H_CPURST#_R @ R36

11/01 update

D56

2 49.9_0402_1%

R34
0_0402_5%

R35

R11

@ R1205 0_0402_5%
1
2

+VCCP

Processor Pullups

H_PROCHOT#

JTAG MAPPING

XDP_TDO_M

2 1K_0402_5%

1 @
C1388
0.1U_0402_16V4Z

+VCCP
PM_EXTTS#0

R603 1

IC,AUB_CFD_rPGA,R1P0
CONN@

R28
750_0402_1%

XDP_TDI_R

H_CATERR#

2 51_0402_1%

Design guide
1.11update,PLTRST series
resittor 1.5K, PL
resistor 750 ohm

THERMTRIP#

CLK_CPU_XDP
CLK_CPU_XDP#

E16
D16

@ R2 1

<14> H_CPUPWRGD

H_CPURST#_R
2
0_0402_5%

AK15

PROCHOT#

AR30
AT30

+VCCP

XDP_TDI

H_CPUPWRGD

AN26

PECI

PWR MANAGEMENT

<13> H_PM_SYNC

R19

AT15

CATERR#

BCLK_ITP
BCLK_ITP#

CLK_CPU_BCLK <14>
CLK_CPU_BCLK# <14>

H_CPURST#

AK14

SKTOCC#

THERMAL

R10

AH24

CLK_CPU_BCLK
CLK_CPU_BCLK#

JTAG & BPM

TP_SKTOCC#

T1

2009.08.12 Remove the XDP connector

A16
B16

BCLK
BCLK#

CLOCKS

AT23

COMP2

DDR3
MISC

COMP3

2 20_0402_1%

MISC

2 20_0402_1%

R3 1

H_PECI

JCPU1B

R1 1

PAD

<14>

2009.08.17 change the Q104 to BSS138 to

follow Intel's design guid.
1.5VSCPU_DRAM_PWRGD

Layout Note:Please these

resistors near Processor

R1208
2

1.5VSCPU_DRAM_PWRGD
+3VALW

+1.5V

<47>
1.5K_0402_1%
1

@ R31
2

1.1K_0402_1%
1

PM_DRAM_PWRGD

VDDPWRGOOD_R

1
2
0_0402_5%

NC7SZ08P5X_NL_SC70-5

@ R33
3K_0402_1%

R1248
750_0402_1%
2

<13> PM_DRAM_PWRGD

U57

VTTPWRGOOD

R1209

Compal Secret Data

Security Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

of

55

Layout rule trace

length < 0.5"
JCPU1E
JCPU1A

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B24
D23
B23
A22

<13>
<13>
<13>
<13>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

D24
G24
F23
H23

<13>
<13>
<13>
<13>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

D25
F24
E23
G23

<13>
<13>
<13>
<13>
<13>
<13>
<13>
<13>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

E22
D21
D19
D18
G21
E19
F21
G18

<13>
<13>
<13>
<13>
<13>
<13>
<13>
<13>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

D22
C21
D20
C18
G22
E20
F20
G19

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

<13> FDI_FSYNC0
<13> FDI_FSYNC1

F17
E17

FDI_FSYNC[0]
FDI_FSYNC[1]

<13> FDI_INT

C17

FDI_INT

<13> FDI_LSYNC0
<13> FDI_LSYNC1

F18
D17

FDI_LSYNC[0]
FDI_LSYNC[1]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N15

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P15

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N15

C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_N[0..15] <24>

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P15

C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

PCIE_CTX_GRX_P[0..15] <24>

EXP_RBIAS

R44
R45

1
1

2 49.9_0402_1%
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

2 750_0402_1%
PCIE_CRX_GTX_N[0..15] <24>

+V_DDR_CPU_REF0
+V_DDR_CPU_REF1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

RSVD32
RSVD33

AJ13
AJ12

RSVD34
RSVD35

AH25
AK26

RSVD36
RSVD_NCTF_37

AL26
AR2

RSVD38
RSVD39

AJ26
AJ27

RSVD_NCTF_40
RSVD_NCTF_41

AP1
AT2

RSVD_NCTF_42
RSVD_NCTF_43

AT3
AR1

PCIE_CRX_GTX_P[0..15] <24>
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

B19
A19
@ R50
@ R51

1
1

2 0_0402_5%
2 0_0402_5%

A20
B20
U9
T9
AC9
AB9

C1
A3

J29
J28
A34
A33
C35
B35

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RESERVED

<13>
<13>
<13>
<13>

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

PCI EXPRESS -- GRAPHICS

A24
C23
B22
A21

Intel(R) FDI

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI

<13>
<13>
<13>
<13>

EXP_ICOMPI

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65

E15
F15
A2
D15
C15
AJ15
AH15

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

@ R48
@ R49

2 0_0402_5%
2 0_0402_5%

1
1

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD_NCTF_23
RSVD_NCTF_24

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

RSVD26
RSVD27
RSVD_NCTF_28
RSVD_NCTF_29
RSVD_NCTF_30
RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0
CONN@

VSS

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

IC,AUB_CFD_rPGA,R1P0
CONN@

CRB 0.9 change to GND

CFG Straps for PROCESSOR

CFG0

@ R52

CFG4

2 3.01K_0402_1%

PCI-Express Configuration Select

1: Disabled; No Physical
Display Port

Not applicable for Clarksfield Processor

CFG4
CFG3

R54

2 3.01K_0402_1%

CFG3-PCI Express Static Lane Reversal

CFG3

1: Normal Operation
0: Lane Numbers Reversed
15 -> 0, 14 ->1, .....

2 3.01K_0402_1%

CFG4-Display Port Presence

1: Single PEG
0: Bifurcation enabled

CFG0

@ R53 1

attached to Embedded Display Port

0: Enabled; An external
Display Port
device is connected to the
Embedded Display Port

CFG7 @ R55

2 3.01K_0402_1%

Only temporary for early

CFD samples (rPGA/BGA)
Only for pre ES1 sample
4

PD
3.01K on CFG7 for PCIE Jitter
don't staff

CFG7

WW33
WW41

Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

of

55

JCPU1D
JCPU1C

<17> DDR_A_D[0..63]

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

<17> DDR_A_BS0
<17> DDR_A_BS1
<17> DDR_A_BS2

AC3
AB2
U7

<17> DDR_A_CAS#
<17> DDR_A_RAS#
<17> DDR_A_WE#

AE1
AB3
AE9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AA6
AA7
P7

M_CLK_DDR0 <17>
M_CLK_DDR#0 <17>
DDR_CKE0_DIMMA <17>

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

Y6
Y5
P6

M_CLK_DDR1 <17>
M_CLK_DDR#1 <17>
DDR_CKE1_DIMMA <17>

SA_CS#[0]
SA_CS#[1]

AE2
AE8

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

AD8
AF9

M_ODT0 <17>
M_ODT1 <17>

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

DDR SYSTEM MEMORY A

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

B9
D7
H7
M7
AG6
AM7
AN10
AN13

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

C9
F8
J9
N9
AH7
AK9
AP11
AT13

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

C8
F9
H9
M9
AH8
AK10
AN11
AR13

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

W8
W9
M3

M_CLK_DDR2 <18>
M_CLK_DDR#2 <18>
DDR_CKE2_DIMMB <18>

V7
V6
M2

M_CLK_DDR3 <18>
M_CLK_DDR#3 <18>
DDR_CKE3_DIMMB <18>

AB8
AD6

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

SB_ODT[0]
SB_ODT[1]

AC7
AD1

M_ODT2 <18>
M_ODT3 <18>

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

D4
E1
H3
K1
AH1
AL2
AR4
AT8

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D5
F4
J4
L4
AH2
AL4
AR5
AR8

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

<18> DDR_B_D[0..63]

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

DDR_A_DM[0..7]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

<17>

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

<17>

<17>

DDR_A_MA[0..15] <17>

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

<18> DDR_B_BS0
<18> DDR_B_BS1
<18> DDR_B_BS2

AB1
W5
R7

<18> DDR_B_CAS#
<18> DDR_B_RAS#
<18> DDR_B_WE#

AC5
Y7
AC6

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

DDR_B_DM[0..7] <18>

DDR SYSTEM MEMORY - B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

<18>

<18>

DDR_B_MA[0..15] <18>

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
CONN@

Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

of

55

DIS@
C987
0_0805_5%

+VCC_CORE

H_PSI# <49>
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR_R R58

H_VID[0..6]

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

0.6A

<49>

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

J22
J20
J18
H21
H20
H19
1

L26
L27
M26

to power
1

2 0_0402_5%

H_DPRSLPVR <49>

IC,AUB_CFD_rPGA,R1P0
CONN@

+VCCP

1
2

10K_0402_5%

+VCCP

C60
1U_0603_10V4Z

C59
1U_0603_10V4Z

C58
1U_0603_10V4Z

C57
1U_0603_10V4Z

C56
1U_0603_10V4Z
1

+1.8VS

C83
4.7U_0603_6.3V6K

+1.5VS

C66
22U_0805_6.3V6M

C65
22U_0805_6.3V6M

+VCCP

PEG & DMI

POWER

P10
N10
L10
K10

C82
10U_0805_6.3V6M

2 0_0603_5%

to power

CPU VIDS

VTT0_59
VTT0_60
VTT0_61
VTT0_62

1 1K_0402_5%

C72
10U_0805_6.3V6M

AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

R128 2

C79
1U_0603_10V4Z

R57

1.1V

+VTT_43

1.8V

2 0_0603_5%

C76
10U_0805_6.3V6M

C75
22U_0805_6.3V6M

R56

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR

DIS@

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

+VCCP
+VTT_44

PSI#

VTT1_45
VTT1_46
VTT1_47

<50>
<50>
<50>
<50>
<50>
<50>
<50>

@
R1186

SG@ R43 1
2 249_0402_1%
GFXVR_EN
AR25
GFXVR_EN <50>
GFXVR_DPRSLPVR
AT25
GFXVR_DPRSLPVR <50>
GFXVR_IMON
AM24
GFXVR_IMON <50>

C78
22U_0805_6.3V6M

+VTT_43
+VTT_44

J24
J23
H25

GFXVR_DPRSLPVR

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

C81
2.2U_0603_6.3V4Z

C70
22U_0805_6.3V6M

C69
10U_0805_6.3V6M

2009. 08.17 Change C61,C62,

C67,C68,C69,C76 to 10u

C74
22U_0805_6.3V6M

C73
22U_0805_6.3V6M

C68
10U_0805_6.3V6M

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

FDI

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

C67
10U_0805_6.3V6M

+VCCP

3A

AM22
AP22
AN22
AP23
AM23
AP24
AN24

C64
220U_D2_2VY_R15M

2009. 11.05 change C996

to ESR 7m ohm

VCC_AXG_SENSE <50>
VSS_AXG_SENSE <50>

2009. 11.05 change R43

from 4.7K
to 249 ohm
GFXVR_VID_0

C71
10U_0805_6.3V6M

Add for RF

VCC_AXG_SENSE
VSS_AXG_SENSE

C77
22U_0805_6.3V6M

SG@

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

AR22
AT22

C80
1U_0603_10V4Z

- 1.5V RAILS

C63
22U_0805_6.3V6M

C62
10U_0805_6.3V6M

C61
10U_0805_6.3V6M

47P_0402_50V8J

47P_0402_50V8J
C1400

47P_0402_50V8J
C1399

C1397

47P_0402_50V8J
C1398

+
1

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

DDR3

SG@ 1

VAXG_SENSE
VSSAXG_SENSE

SENSE
LINES

47P_0402_50V8J
C1392

+VCCP

15A

GRAPHICS VIDs

47P_0402_50V8J
C1391

C1389
C52
10U_0805_6.3V6M

C51
10U_0805_6.3V6M

C50
10U_0805_6.3V6M

47P_0402_50V8J
C1390

C43
10U_0805_6.3V6M

C42
10U_0805_6.3V6M

C41
10U_0805_6.3V6M
C49
10U_0805_6.3V6M

C40
10U_0805_6.3V6M
C48
10U_0805_6.3V6M

C996
330U_D2_2VY_R7M

1.1V RAIL POWER

2 @

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

GRAPHICS

C990
10U_0805_6.3V6M

2 @

1
SG@

C994
22U_0805_6.3V6M

SG@2

1
SG@

C989
10U_0805_6.3V6M

SG@2

1
SG@

C993
22U_0805_6.3V6M

SG@2

1
SG@

C988
22U_0805_6.3V6M

SG@ 2

C991
22U_0805_6.3V6M

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

CPU

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

+VCCP

CPU CORE SUPPLY

to power
VTT_SELECT

G15

VTT_SELECT <46>

H_VTTVID1 = Low, 1.1V(Clarksfield)

H_VTTVID1 = High, 1.05V(Auburndale)

ISENSE

AN35

IMVP_IMON <49>
to power

SENSE LINES

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

C995
330U_D2_2V_Y

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

+VCCP

18A

JCPU1G
C987
22U_0805_6.3V6M

48A

47P_0402_50V8J

+GFX_CORE

Add for RF

POWER

JCPU1F

VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT

AJ34 VCCSENSE_R
AJ35 VSSSENSE_R
B15
A15

R59
R60

1
1

2
2

VSS_SENSE_VTT R203 1

0_0402_5%
0_0402_5%

VCCSENSE
VSSSENSE

2 0_0402_5%

VCCSENSE <49>
VSSSENSE <49>

VTT_SENSE <46>

Near Processor
+VCC_CORE
VCCSENSE

R61

2 100_0402_1%

VSSSENSE

R62

2 100_0402_1%

2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IC,AUB_CFD_rPGA,R1P0
CONN@
5

Compal Secret Data

Security Classification

Title

Compal Electronics, Inc.

Auburndale(4/5)-PWR

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

of

55

VSS

IC,AUB_CFD_rPGA,R1P0
CONN@

2 @

1
+
2

1
+
2

1
+
2

1
+
2

47P_0402_50V8J

47P_0402_50V8J
C1404

47P_0402_50V8J
C1403

47P_0402_50V8J
C1402

C95
10U_0805_6.3V6M
C1401

C94
10U_0805_6.3V6M

C107
10U_0805_6.3V6M

C106
10U_0805_6.3V6M

C93
10U_0805_6.3V6M

C92
22U_0805_6.3V6M

C118
22U_0805_6.3V6M

2 @

C121
22U_0805_6.3V6M

C91
10U_0805_6.3V6M
C103
10U_0805_6.3V6M

C90
10U_0805_6.3V6M
C102
10U_0805_6.3V6M

C89
22U_0805_6.3V6M
C101
10U_0805_6.3V6M

C86
22U_0805_6.3V6M

C85
22U_0805_6.3V6M

C88
22U_0805_6.3V6M
C100
10U_0805_6.3V6M

Reserve for RF

between
Inductor and
socket

C111
330U_D2_2VM_R9M

C110
330U_D2_2VM_R9M

C108
330U_D2_2VM_R9M

C104
10U_0805_6.3V6M

Inside cavity

C99
10U_0805_6.3V6M

C98
10U_0805_6.3V6M

C105
10U_0805_6.3V6M

C119
22U_0805_6.3V6M

C116
22U_0805_6.3V6M

C97
10U_0805_6.3V6M

C115
10U_0805_6.3V6M

C84
22U_0805_6.3V6M

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

C96
10U_0805_6.3V6M

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

C114
10U_0805_6.3V6M

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

C982

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

47P_0402_50V8J

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

330uF 9mohm

VSS

NCTF

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

JCPU1I

C87
22U_0805_6.3V6M

CPU CORE

+VCC_CORE
JCPU1H

C109
330U_D2_2VM_R9M

C120
22U_0805_6.3V6M

C117
10U_0805_6.3V6M

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

VSS_NCTF1_R
VSS_NCTF2_R
VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R
VSS_NCTF6_R
VSS_NCTF7_R

IC,AUB_CFD_rPGA,R1P0
CONN@

Compal Secret Data

Security Classification
2008/03/13

Issued Date

2009/05/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

10

of

55

+RTCVCC

ICH_RTCX1

2 1M_0402_5%

R66

2 330K_0402_5% PCH_INTVRMEN

2 10K_0402_5%

SIRQ

@ R67

2 1K_0402_5%

SB_SPKR

LOW=Default
HIGH=No Reboot *

A16

INTRUDER#

PCH_INTVRMEN

A14

INTVRMEN

HDA_BIT_CLK

A30

HDA_BCLK

HDA_SYNC

D29

HDA_SYNC

CLRP2
SHORT PADS

1
1
1
1

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

2
2
2
2

SB_SPKR

P1

HDA_RST#

C30

HDA_RST#

<34> HDA_SDIN0

HDA_SDIN0

G30

HDA_SDIN0

<34> HDA_SDIN1

HDA_SDIN1

F30

HDA_SDIN1

<34>

SB_SPKR

1
R1161 1
R78

<34> HDA_RST#_MDC
<34,39> HDA_RST#_CODEC

2
2 33_0402_5%
33_0402_5%

HDA_BITCLK_CODEC

E32

HDA_SDIN2

2 22P_0402_50V8J

HDA_SDOUT_CODEC

F32

HDA_SDIN3

R81
R82

C34

LDRQ0#
LDRQ1# / GPIO23

A34
F34

SERIRQ

AB9

SIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AK7
AK6
AK11
AK9

SATA_TXN0_C
SATA_TXP0_C

C126
C127

1
1

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AH6
AH5
AH9
AH8

SATA_TXN1_C
SATA_TXP1_C

C130
C131

1
1

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1
SATA_TXP1

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF11
AF9
AF7
AF6

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AH3
AH1
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AD9
AD8
PA@C128
C128
AD6 SATA_TXN4_C PA@
PA@C129
AD5 SATA_TXP4_C PA@C129

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AD3
AD1
PA@C1276
C1276
AB3 SATA_TXN5_C PA@
PA@C1277
AB1 SATA_TXP5_C PA@C1277

SPKR

2 22P_0402_50V8J

<34> HDA_SDOUT_MDC
<34> HDA_SDOUT_CODEC

FWH4 / LFRAME#

2 33_0402_5%
2 33_0402_5%

1
1

HDA_SDOUT

B29

HDA_SDO

ME_EN#

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

PAD

T16

M3

JTAG_TCK

PCH_JTAG_TMS

K3

JTAG_TMS

PCH_JTAG_TDI

K1

JTAG_TDI

PCH_JTAG_TDO

J2

JTAG_TDO

PCH_JTAG_RST#

J4

TRST#

SATAICOMPO

AF16

SATAICOMPI

AF15

LPC_FRAME#
LDRQ0#
LDRQ1#

T13
T14

<31,39>

PAD
PAD
SIRQ

<39>

SATA_RXN0_C <30>
SATA_RXP0_C <30>
SATA_TXN0 <30>
SATA_TXP0 <30>
SATA_RXN1_C <30>
SATA_RXP1_C <30>
SATA_TXN1 <30>
SATA_TXP1 <30>

HDD

ODD

SATA2 SATA3 don't

support on HM55

R89

1
1

1
1

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

SATA_RXN4_C
SATA_RXP4_C
SATA_TXN4
SATA_TXP4

2 0.01U_0402_50V7K
2 0.01U_0402_50V7K

SATA_RXN5_C
SATA_RXP5_C
SATA_TXN5
SATA_TXP5

2 37.4_0402_1%

SATA_RXN4_C <37>
SATA_RXP4_C <37>
SATA_TXN4 <37>
SATA_TXP4 <37>
SATA_RXN5_C <30>
SATA_RXP5_C <30>
SATA_TXN5 <30>
SATA_TXP5 <30>

E SATA
Multi Bay

+3VALW

+1.05VS

+3VALW

+3VALW

+3VALW

SPI_CLK_PCH

<38> SPI_CLK_PCH
1

2 10K_0402_5%

SPI_SB_CS#

R654 1

2 15_0402_5%

SPI_SB_CS#

<38> SPI_SB_CS#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

SATALED#

T3

AY1

SPI_MOSI

SATA0GP / GPIO21

Y9

SATA1GP / GPIO19

V1

R91

2 10K_0402_1%

R86
@ 200_0402_5%

+3VS

R84
@ 200_0402_5%

@
R85
20K_0402_5%

SPI_SO_R

SPI_SO_R

AV1

SPI_MISO

GPIO21
GPIO19

PCH_JTAG_TMS

PCH_JTAG_TDO

R684
@ 100_0402_1%

R683
@ 100_0402_1%

@
R685
10K_0402_1%

PCH_JTAG_RST#
B

R88
@ 10K_0402_5%

IBEXPEAK-M_FCBGA1071

2 15_0402_5%

R655 1

<38>

SPI_SI

SPI_SI

R87
@ 20K_0402_5%

PCH_JTAG_TDI

<38>

SPI_SO_R

2 10K_0402_5%

<40>

SATA_LED#

R657
B

SPI

R656

+3VS

PCH_JTAG_TCK

<31,39>
<31,39>
<31,39>
<31,39>

SRTCRST#

SM_INTRUDER#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

RTCRST#

D17

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

R1159
R73
R1160
R75

HDA_BITCLK_MDC
HDA_BITCLK_CODEC
HDA_SYNC_MDC
HDA_SYNC_CODEC

C14

ICH_SRTCRST#

LPC

2 20K_0402_1%

RTCX1
RTCX2

ICH_RTCRST#

RTC

CLRP1
SHORT PADS

D33
B33
C32
A32

IHDA

R70

B13
D13

SATA

2 20K_0402_1%

ICH_RTCX1
ICH_RTCX2

JTAG

<34>
<34>
<34>
<34>

@ C54

R64

C124
1U_0603_10V4Z
R69

C125
1U_0603_10V4Z

U1A
1

+RTCVCC

@ C53

SM_INTRUDER#

R65

+3VS

INTVRMEN
H Integrated VRM enable
L Integrated VRM disable

C123
18P_0402_50V8J

4
OSC
NC

NC
2

OSC

C122
18P_0402_50V8J

1
D

Y1
32.768KHZ_12.5PF_Q13MC14610002

2 10M_0402_5% ICH_RTCX2

R63

+3VS

HDA_SDO
1

HDA_SYNC
R1255

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

D
Q113
2N7002_SOT23-3

2
G

ME_EN

PCH JTAG Disable

RefDes
ES1

Enable iTPM=Stuff

ES2

ES1

ES2

@ BATT1

R86

No Install

200ohm

R684

No Install No Install

PCH_JTAG_TDO
ME_EN#

<39>

PCH_JTAG_TCK
2
51_0402_5%

PCH JTAG Enable

PCH Pin

Disable iTPM=No Stuff

100K_0402_5%

1
R90

This signal has a weak internal pull down.

This signal can't PU

HDA_DOCK_EN#

+RTCVCC

+3VL

H=>security measures defined in the Flash

Descriptor will be in effect (default)

W=20mils

L=>Flash Descriptor Security will be overridden

R1256
100K_0402_5%
2

SPI_MOSI
9/11 Add for ME_EN

This signal has a weak internal pull down.

CR2032 RTC BATTERY

D3

W=20mils

BATT1.1

ME debug mode , this signal has a weak internal PU

1
3

JBATT1
R94 1

2 1K_0402_5%

W=20mils

DAN202U_SC70
C132
2.2U_0603_6.3V4Z

1
2
3
4

100ohm

No Install No Install

200ohm

200ohm

No Install No Install
No Install No Install

R683

100ohm

100ohm

R85

200ohm

200ohm

20Kohm

No Install

R685

100ohm

100ohm

10Kohm

No Install

R90

51ohm

51ohm

51ohm

R87

20Kohm

20Kohm

No Install No Install

R88

10Kohm

10Kohm

No Install No Install

PCH_JTAG_TDI

1
2
GND
GND

PCH_JTAG_TCK

ACES_85205-02001
CONN@

Place near IBEX-M

No Install

R84
PCH_JTAG_TMS

51ohm
A

PCH_JTAG_RST#

Disable iTPM=No Stuff

Enable iTPM=Stuff

+3VS

iTPM ENABLE/DISABLE
+3VS

GPIO21
GPIO19

@ R68

2 1K_0402_5%

SPI_SI

SI
4

R92

1 10K_0402_5%

R93

1 10K_0402_5%

Compal Secret Data

Security Classification
Issued Date

Reserve GPIO1921 PD for LPM enable power saving

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

11

of

55

EC_LID_OUT#

R95

2 10K_0402_5%

SMBCLK

R96

2 2.2K_0402_5%

SMBDATA

R97

2 2.2K_0402_5%

SML0CLK

R98

2 2.2K_0402_5%

SML0DATA

R99

2 2.2K_0402_5%

SML0ALERT#

R100 1

2 10K_0402_5%

SML1ALERT#

R101 1

2 10K_0402_5%

SML1CLK

R103 1

2 2.2K_0402_5%

SML1DATA

R104 1

2 2.2K_0402_5%

+3VALW
+3VS
+3VS
+3VS
R105
2.2K_0402_5%
Q1A

R106
2.2K_0402_5%

SMBDATA

6
Q1B

SMBCLK
U1B

SMB_DATA_S3

2N7002DW-7-F_SOT363-6

SMB_DATA_S3

<17,18,19,30>

SODIMMClock genG sensor

XDP
SMB_CLK_S3

SMB_CLK_S3

<17,18,19,30>

2N7002DW-7-F_SOT363-6
SMBCLK

<31>
<31>
<31>
<31>

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

C135 1
C136 1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

LAN

<32>
<32>
<32>
<32>

PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3

C137 1
C138 1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PCIE_RXN3
PCIE_RXP3
GLAN_C_TXN
GLAN_C_TXP

AU30
AT30
AU32
AV32

PERN3
PERP3
PETN3
PETP3

New Card

<31>
<31>
<31>
<31>

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

C139 1
C140 1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

BA32
BB32
BD32
BE32

PERN4
PERP4
PETN4
PETP4

CLKREQ_WWAN#_R

10K_0402_5%

CLKREQ_WLAN#

+3VS

R677 1

10K_0402_5%

CLKREQ_LAN#

+3VALW

R415 1

10K_0402_5%

CLKREQ_EXP#_R

+3VALW

R503 1

10K_0402_5%

OK

OK

WWAN

WLAN

PCIE7 PCIE8 don't

support on HM55

PCIECLKREQ4#

AT34
AU34
AU36
AV36

PERN7
PERP7
PETN7
PETP7

BG34
BJ34
BG36
BJ36

PERN8
PERP8
PETN8
PETP8

AK48
AK47

CLKOUT_PCIE0N
CLKOUT_PCIE0P

R107 1
R108 1

2 0_0402_5%
2 0_0402_5%

<31> CLKREQ_WWAN#

R80

2 100_0402_5% CLKREQ_WWAN#_R

P9

<31> CLK_PCIE_WLAN#
<31> CLK_PCIE_WLAN

R109 1
R110 1

CLK_PCIE_WLAN#_R
CLK_PCIE_WLAN_R

AM43
AM45

2 0_0402_5%
2 0_0402_5%

U4

<31> CLKREQ_WLAN#

OK
B

LAN+Card reader

R111 1
R112 1

<32> CLK_PCIE_LAN#
<32> CLK_PCIE_LAN

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

AM47
AM48
N4

<32> CLKREQ_LAN#

OK
New Card

<31> CLK_PCIE_EXP#
<31> CLK_PCIE_EXP
<31> CLKREQ_EXP#

PA@
PA@

R114 1
R115 1

2 0_0402_5%
2 0_0402_5%

PA@

R83

2 100_0402_5% CLKREQ_EXP#_R

CLK_PCIE_EXP#_R
CLK_PCIE_EXP_R

AH42
AH41
A8
AM51
AM53

+3VALW

R756 1

2 100_0402_5% PCIECLKREQ4#

+3VALW

R757 1

2 10K_0402_5%

PAD
PAD

R606 1

2 10K_0402_5%

AJ50
AJ52

PCIECLKREQ5#

H6

T61
T62

AK53
AK51

PEG_B_CLKRQ#

P13

PAD
PAD
+3VALW

T59
T60

M9

SMBus
PCI-E*

PERN6
PERP6
PETN6
PETP6

<31> CLK_PCIE_WWAN#
<31> CLK_PCIE_WWAN

CLK_PCIE_WWAN#_R
CLK_PCIE_WWAN_R

BA34
AW34
BC34
BD34

PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P

PEG_B_CLKRQ# / GPIO56

WLAN

WWANNew card

SML0ALERT#

SML0CLK

C6

SML0CLK

SML0DATA

G8

SML0DATA

SML1ALERT# / GPIO74

M14

SML1ALERT#

SML1CLK / GPIO58

E10

SML1CLK

R215

0_0402_5%

SMB_EC_CK2

<39>

SML1DATA / GPIO75

G12

SML1DATA R231

0_0402_5%

SMB_EC_DA2

<39>

SMBDATA <31>

@
R1194
2.2_0402_5%

Q4A

T13
T11

CL_RST1#

T9

PEG_A_CLKRQ# / GPIO47

H1

PEG_CLKREQ# R102 1

AD43
AD45

L_CLK_PCIE_VGA#
L_CLK_PCIE_VGA

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AT1
AT3

SMB_EC_DA2

6
Q4B

SMB_EC_CK2

THERM_CLK_GPU

THERM_DAT_GPU

<26>

THERM_CLK_GPU

<26>

2 10K_0402_5%
R604 1
R605 1

2 0_0402_5%
2 0_0402_5%

CLK_EXP# <6>
CLK_EXP <6>
CLK_DP#
CLK_DP

T71
T72

CLK_PCIE_VGA#
CLK_PCIE_VGA

<24>
<24>

OK

OK

PAD
PAD

Nvidisa thermall sensor

CLK_DMI# <19>
CLK_DMI <19>

CLKIN_BCLK_N
CLKIN_BCLK_P

AP3
AP1

CLK_BUF_BCLK# <19>
CLK_BUF_BCLK <19>

CLKIN_DOT_96N
CLKIN_DOT_96P

F18
E18

CLK_BUF_DOT96# <19>
CLK_BUF_DOT96 <19>

OK

AH13
AH12

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

OK

OK

10/23 Reserve the Y2 for Intel PCH jitter issue.

OK

XTAL25_IN

REFCLK14IN

P41

CLKIN_PCILOOPBACK

J42

CLK_14M_PCH
CLK_PCI_FB

XTAL25_IN
XTAL25_OUT

AH51
AH53

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

AF38

R116 1

<19>
<19>

XTAL25_OUT

@ R113 1

2 1M_0402_5%
B

@
1

OK

<19>

CLKOUTFLEX0 / GPIO64

T45

CLKOUTFLEX1 / GPIO65

P43

CLKOUTFLEX2 / GPIO66

T42

CLKOUTFLEX3 / GPIO67

N50 R1021

OK

<14>

Y2
2

2 22_0402_5%

C1407

Add for RF
1

+1.05VS

CLK_48M_CR

<33>

Compal Secret Data

Security Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

R1225
0_0402_5%

2 @
2 90.9_0402_1%

THERM_DAT_GPU

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

AW24
BA24

CLKIN_DMI_N
CLKIN_DMI_P

1 @
C1406
12P_0402_50V

+3VS_VGA

For Intel LAN only

CL_CLK1

AN4
AN2

9/11 Change from +3VS to +3VS_VGA

+3VS_VGA

CL_DATA1

Add for RF

PCH

25MHZ_20P_1BG25000CK1A

PCIECLKRQ3# / GPIO25

IBEXPEAK-M_FCBGA1071

<39>

SMBCLK <31>

SMBDATA

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

EC_LID_OUT#

SMBCLK

J14

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PCIECLKRQ2# / GPIO20

PCIECLKRQ5# / GPIO44

H14

DTS , read from EC

Link

10K_0402_5%

PERN5
PERP5
PETN5
PETP5

Controller

R411 1

BF33
BH33
BG32
BJ32

B9

C8

SMBDATA
SML0ALERT# / GPIO60

PEG

R405 1

+3VS

+3VALW

PERN2
PERP2
PETN2
PETP2

SMBCLK

From CLK BUFFER

AW30
BA30
BC30
BD30

SMBALERT# / GPIO11

Clock Flex

PA@
PA@

PERN1
PERP1
PETN1
PETP1

WLAN

BG30
BJ30
BF29
BH29

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

C141
18P_0402_50V8J

C133 1
C134 1

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

<31>
<31>
<31>
<31>

EC_LID_OUT#

12P_0402_50V J

WWAN

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

Title

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

12

of

55

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BC24
BJ22
AW20
BJ20

<7>
<7>
<7>
<7>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BD24
BG22
BA20
BG20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

<7>
<7>
<7>
<7>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

BE22
BF21
BD20
BE18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

<7>
<7>
<7>
<7>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

BD22
BH21
BC20
BD18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

R118 1

2 49.9_0402_1%

DMI_IRCOMP

DMI_ZCOMP

BF25

DMI_IRCOMP

4mil width and place

within 500mil of the PCH

FDI

BH25

DMI

+1.05VS

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

IGPU_BKLT_EN

U1D

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

<22> IGPU_BKLT_EN
<21> I_ENAVDD

IGPU_BKLT_EN
I_ENAVDD

T48
T47

L_BKLTEN
L_VDD_EN

<22> DPST_PWM

DPST_PWM

Y48

L_BKLTCTL

+3VS
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

BJ14

FDI_INT

FDI_FSYNC0

BF13

FDI_FSYNC0

FDI_FSYNC1

BH13

FDI_FSYNC1

<7>

FDI_LSYNC0

BJ12

FDI_LSYNC0

<7>

FDI_LSYNC1

BG14

FDI_LSYNC1

<7>

<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>

AB48
Y45

<22> I_EDID_CLK
<22> I_EDID_DATA

SG@

SG@1
2
AB46
1 R771
2 10K_0402_5% V48
SG@ R772
10K_0402_5%
R7731
2 2.37K_0402_1% AP39
AP41
PAD T69
AT43
AT42

Close PCH and mini space 20mil

<7>
<7>

2 0_0402_5%

<39> PM_PWROK
R120 2

R121 1
@ R379 1

<39> M_PWROK

2 0_0402_5%
2 0_0402_5%

R122

R151 1
2 10K_0402_5%
PM_PWRBTN#_R
R125 1

<26,39> EC_ACIN

2 0_0402_5%
EC_ACIN
LOW_BAT#
PM_RI#

LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

<22> I_LVDS_A0+
<22> I_LVDS_A1+
<22> I_LVDS_A2+

BB48
BA50
AY49
AV48

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AP48
AP47

LAN_RST#
DRAMPWROK
RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

Y1

PM_CLKRUN#

ICH_PCIE_WAKE#

LVDSB_CLK#
LVDSB_CLK

AY53
AT49
AU52
AT53

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AY51
AT48
AU50
AT51

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

SUS_STAT# / GPIO61

P8

PM_SUS_STAT#

SUSCLK / GPIO62

F3

SUS_CLK

AA52
AB53
AD53

CRT_BLUE
CRT_GREEN
CRT_RED

SLP_S5# / GPIO63

E4

SLP_S5# <39>

SLP_S4#

H7

SLP_S4# <39>

SLP_S3#

P12

SLP_S3# <39>

SLP_M#

K8

TP23

N2

<31,32>

T17
T18

I_BLUE
I_GREEN
I_RED

<22> I_BLUE
<22> I_GREEN
<22> I_RED
<20> I_CRT_DDC_CLK
<20> I_CRT_DDC_DATA
SG@
1 R774
1
SG@ R775

<22> I_CRT_HSYNC
<22> I_CRT_VSYNC

Can be left NC when IAMT is

not support on the platfrom

2
2

0_0402_5%
HSYNC
VSYNC
0_0402_5%

CRB0.9 change to 0 ohm

F14

RI#

PMSYNCH
SLP_LAN# / GPIO29

BJ10

H_PM_SYNC

<6>

If not using integrated

LAN,signal may be left as NC.

F6

R_EC_RSMRST#

CRT_DDC_CLK
CRT_DDC_DATA

Y53
Y51

CRT_HSYNC
CRT_VSYNC

AD48
AB51

DAC_IREF
CRT_IRTN

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

BG44
BJ44
AU38

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

DDPC_CTRLCLK
DDPC_CTRLDATA

Y49
AB49

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

BE44
BD44
AV40

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

DDPD_CTRLCLK
DDPD_CTRLDATA

V51
V53

T51
T53

U50
U52

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

BC46
BD46
AT38

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

IBEXPEAK-M_FCBGA1071

06/19 HDMI data 0 and data 2 reverse

CRB0.9 change to 1K_0402_0.5%

IBEXPEAK-M_FCBGA1071

D37
PM_PWROK 2

MEPWROK

ICH_PCIE_WAKE#

LVD_VREFH
LVD_VREFL

BB47
BA52
AY48
AV47

9/11 GPIO30 change to

SUS_PWR_DN_ACK

C16

PWROK

J12

BF45
BH45

Display Port D

D9

R_EC_RSMRST#
R123 1
2
100_0402_5%
R124 2
1 10K_0402_5%
SUS_PWR_DN_ACK
<39> SUS_PWR_DN_ACK
+3VALW

CLKRUN# / GPIO32

K5

<39> EC_RSMRST#

<39> PWRBTN_OUT#

SYS_PWROK

2 10K_0402_5% A10

PM_DRAM_PWRGD

<6> PM_DRAM_PWRGD

M6
B17

10K_0402_5%

WAKE#

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK
SDVO_CTRLDATA

AV53
AV51

2 0_0402_5%

SYS_RESET#

LVD_IBG
LVD_VBG

<22> I_LVDS_A0<22> I_LVDS_A1<22> I_LVDS_A2-

R126
1K_0402_0.5%

R365 1
@ R373 1

VGATE

T6

System Power Management

<19,49>

0_0402_5%
1
2SYS_RST#
R119

BJ48
BG48

Display Port C

XDP_DBRESET#

BJ46
BG46

SDVO_STALLN
SDVO_STALLP

L_CTRL_CLK
L_CTRL_DATA

<22> I_LVDS_ACLK<22> I_LVDS_ACLK+

Checklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable
<6> XDP_DBRESET#

L_DDC_CLK
L_DDC_DATA

SDVO_TVCLKINN
SDVO_TVCLKINP

Display Port B

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

SDVO

<7>
<7>
<7>
<7>

100K_0402_5%
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

Digital Display Interface

1
U1C

EDID_CLK and EDID_DATA single

end and keep 30 mil with other
LVDS signal avoid noise

R770

LVDS

CRT

RB751V_SOD323
I_BLUE

+3VS

I_GREEN
SYS_RST#

@ R133

2 10K_0402_5%

R129

2 8.2K_0402_5%

I_RED

PM_CLKRUN#

1
SG@R776
1
SG@R777
1
SG@R778

2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

Place the 3 resistors close to IBEX

+3VALW
2 8.2K_0402_5%

PM_RI#

R136

2 10K_0402_5%

ICH_PCIE_WAKE#

R137

2 10K_0402_5%

EC_ACIN

R138

1 8.2K_0402_5%

R1221 1

2 0_0402_5%
+RTCVCC

Check PM_SLP_LAN#

<44> +3_5V PWR_OK

+3_5V PWR_OK
@ R1217 1

2 1K_0402_5% 2

R_EC_RSMRST#

@ U59A
LM358ADT_SO8
2.2K_0402_5%

R1218

+RTCVCC

R134

LOW_BAT#

change to 2.2K

Compal Secret Data

Security Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

13

of

55

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

G38
H51
B37
A44

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_REQ0#
PCI_REQ1#
DGPU_SELECT#
PCI_REQ3#

F51
A46
B45
M53

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

8.2K_0804_8P4R_5%
RP5
PCI_REQ3#
PCI_PIRQF#
PCI_PERR#
PCI_LOCK#

1
2
3
4

8
7
6
5
8.2K_0804_8P4R_5%
+3VS
RP6

PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQG#
PCI_PIRQC#

1
2
3
4

8
7
6
5
8.2K_0804_8P4R_5%
RP7

PCI_PIRQE#
PCI_STOP#
PCI_IRDY#
DGPU_SELECT#

1
2
3
4

8
7
6
5
8.2K_0804_8P4R_5%

<22> DGPU_SELECT#

PCI_GNT0#
PCI_GNT1#
DGPU_PWM_SELECT#
PCI_GNT3#

T70 PAD

R150
2
1
0_0402_5%

ACCEL_INT

<30> ACCEL_INT

<39>

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

F48
K45
F36
H53

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

B41
K53
A36
A48

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

K6

PCI_RST#

<39> PCI_SERR#

PCIRST#

PCI_SERR#
PCI_PERR#

E44
E50

PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#

A42
H44
F46
C46

IRDY#
PAR
DEVSEL#
FRAME#

PCI_LOCK#

D49

PLOCK#

PCI_STOP#
PCI_TRDY#

D41
C48

STOP#
TRDY#

M7

PME#

D5

PLTRST#

NV_ALE
NV_CLE

BD3
AY6

SERR#
PERR#

Low=Configures DMI for ESI

compatible operation(for
servers only.Not for
mobile/desktops)

<39> PCI_PME#
<24,31,32>

PLT_RST#

PLT_RST#

R_CLK_PCI_FB
R_CLK_PCI_EC
R_CLK_DEBUG_PORT_1

N52
P53
P46
P51
P48

it have weak internal PU 20K

NV_WR#0_RE#
NV_WR#1_RE#

AY8
AY5

NV_WE#_CK0
NV_WE#_CK1

AV11
BF5

B25
D25

TACH3 / GPIO7

<39>

EC_SMI#

EC_SMI#

F10

GPIO8

<51> DGPU_PWROK

<31>

R145 1

2 10K_0402_5%

DGPU_PWR_EN

GPIO27

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

H
L

On-Die
voltage regulator enable
On-Die PLL Voltage Regulator disable

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

USBRBIAS

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

R155 1

<37>
<37>
<37>
<37>
<37>
<37>
<36>
<36>
<21>
<21>
<31>
<31>

<31>
<31>
<31>
<31>
<33>
<33>
<37>
<37>
<37>
<37>

<31> WWAN_DETECT#
<40> HDDHALT_LED#

ESATA

PAD
PAD

AF48
AF47

T21
T22

PAD
PAD

K9

LAN_PHY_PWR_CTRL / GPIO12

A20GATE

T7

GPIO15

DGPU_HOLD_RST#

AA2

DGPU_PWROK

F38
Y7

SCLOCK / GPIO22
GPIO24

AB12

GPIO27

V13

GPIO28

H_STP_PCI#

M11

STP_PCI# / GPIO34

V6

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AM3

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

AM1

TACH0 / GPIO17

H10

U2

PECI

GATEA20 <39>

RCIN#
PROCPWRGD
THRMTRIP#

CLK_CPU_BCLK#

PCH_PECI_R

T1

KB_RST#

R144

BE10

H_CPUPWRGD

BD10 H_THERMTRIP#_L

SATA2GP / GPIO36

TP1

BA22

VGA_PRSNT_L#

AB13

SATA3GP / GPIO37

TP2

AW22

SLOAD / GPIO38

TP3

HDDHALT_LED#

P3

SDATAOUT0 / GPIO39

TP4

AY45

PCIECLKREQ6#

H3

PCIECLKRQ6# / GPIO45

TP5

AY46

PCH_DDR_RST

F1

EC_SCI#

R166 1

2 10K_0402_5%

+3VS

TP6

SDATAOUT1 / GPIO48

TP7

AV45

DGPU_EDIDSEL#

MB USB

AA4

SATA5GP / GPIO49

TP8

AF13

KB_RST#

GPIO57

TP9

M18

TP10

N18

TP11

EHCI 1 9/11 GPIO57 for VGA Board ID

WLAN

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

WWAN
New Card
EHCI2

BT

BT_OFF

F8

<37>

WXMIT_OFF#

<31>

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

R167 1

2 10K_0402_5%

R171 1
OPP@
DGPU_PWR_EN
R172 1

2 10K_0402_5%

DGPU_HPD_INT#
R173 1
OPP@
VGA_PRSNT_L#
R175 1

2 10K_0402_5%

AJ24

TP12

AK41

DGPU_HOLD_RST#

R176 1

2 10K_0402_5%

TP13

AK42

WWAN_DETECT#

R178 1

2 10K_0402_5%

TP14

M32

GATEA20

R180 1

2 10K_0402_5%

TP15

N32

PCH_TEMP_ALERT# R181 1

2 10K_0402_5%

TP16

M30

HDDHALT_LED#

R169 1

2 10K_0402_5%

TP17

N30

GPIO48

R170 1

2 10K_0402_5%

TP18

H12

GPIO22

R168 1

2 10K_0402_5%

TP19

AA23

DGPU_PWROK

R874 1

2 10K_0402_5%

NC_1

AB45

NC_2

AB38

NC_3

AB42

INIT3_3V

NC_4

AB41
T39

This signal has weak internal

PU, can't pull low

NC_5
INIT3_3V#

EXP_CPPE# <31>

TP24

P6

<12> CLK_PCI_FB
<39> CLK_PCI_EC
<31> CLK_DEBUG_PORT_1

R158 1
R160 1

PCI_GNT0#

@ R163 1

2 1K_0402_5%

R162 1

2 22_0402_5%

PCI_GNT1#

@ R164 1

2 1K_0402_5%

R_CLK_DEBUG_PORT_1

2 10K_0402_5%

T48

PAD

C10
+3VALW

10/06 Add M93 and Park VGA ID pin (GPIO28, 57)

Boot BIOS Strap

+3VALW
USB_OC#0
WXMIT_OFF#
BT_OFF
USB_OC#2

USB_OC#6
USB_OC#5
USB_OC#4
EXP_CPPE#

1
1
1
1

1
1
1
1

R1170
R1171
R1172
R1173

R1174
R1175
R1176
R1177

2
2
2
2

2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2 10K_0402_5%

IBEXPEAK-M_FCBGA1071
IBEXPEAK-M_FCBGA1071
R_CLK_PCI_FB
2 22_0402_5%
R_CLK_PCI_EC
2 22_0402_5%

<6,26>

+VCCP

BB22

PCIECLKRQ7# / GPIO46

Finger print

H_THERMTRIP#

V3

AB6

Cardreader

<6>

SATACLKREQ# / GPIO35

AB7

GPIO57

<6>

R147
56_0402_5%

PCH_TEMP_ALERT#

USB Camera

H_PECI

2 54.9_0402_1%

1
R146

GPIO48

Dock

<6>

KB_RST# <39>

MB
<39> PCH_TEMP_ALERT#

OK

2 0_0402_5%

AV43

<6> PCH_DDR_RST

<6>

CLK_CPU_BCLK

BG10

DGPU_PWR_EN

WWAN_DETECT#

GATEA20

SATA4GP / GPIO16

PCH_GPIO28

2 22.6_0402_1%

USB_OC#0
BT_OFF
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
EXP_CPPE#

T19
T20

PCH_GPIO15

Within 500
mils

N16
J16
F16
L16
E14
G16
F12
T15

AH45
AH46

PCH_GPIO12

XMIT_OFF

XMIT_OFF

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

GPIO22

<23,40,41,47,51>

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USBRBIAS

TACH2 / GPIO6

J32

GPIO35

AV7

USBRBIAS#

D37

EC_SCI#

Internal VccVRM Option

AU2

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

TACH1 / GPIO1

DGPU_HPD_INT#

NV_ALE
NV_CLE
+3VS

BMBUSY# / GPIO0

C38

EC_SCI#

<24> DGPU_HOLD_RST#

Check list Rev0.8 section1.23.2 If not

implemented, the Braidwood interface
signals can be left as No Connect (NC).

NV_RB#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

Y3

DGPU_EDIDSEL#

<39>

<23> DGPU_HPD_INT#

H Intel ME Crypto Transport

Layer Security(TLS) chiper suite
with confidentiality

NV_RCOMP

GNT2
Default-Internal pull up

GPIO15
L Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

PCH_GPIO0

8
7
6
5

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

2 1K_0402_1%

<20,22> DGPU_EDIDSEL#

1
2
3
4

AV9
BG8

R140 1

+3VS

MISC

PCI_PIRQH#
PCI_TRDY#
PCI_FRAME#
PCI_REQ1#

NV_DQS0
NV_DQS1
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

This signal has a weak internal

pull up ,can't Pull low

CPU

C/BE0#
C/BE1#
C/BE2#
C/BE3#

RP4

AY9
BD1
AP15
BD8

GPIO

J50
G42
H47
G34

8.2K_0804_8P4R_5%

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NCTF

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

NVRAM

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

8
7
6
5

USB

1
2
3
4

U1F

GPIO8

PCI

PCI_DEVSEL#
PCI_SERR#
PCI_REQ0#
PCI_PIRQB#

U1E

+3VS

RSVD

RP3

PCI_GNT0# PCI_GNT1# Boot BIOS

Location
0
0
LPC
0

Reserved(NAND)

PCI

SPI

R179 1

Intel Anti-Theft Techonlogy

High=Endabled
NV_ALE
Low=Disable(floating)

+1.8VS
NV_ALE

@ R174 1

2 1K_0402_5%

DMI Termination Voltage

Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
Weak internal
PU,Do not pull low

2 0_0402_5%

NV_CLE

+3VS

@ R184 1

NV_ALE
Enable Intel Anti-Theft
Technology 8.2K PU to +3VS

M93

Disable Intel Anti-Theft

Technologyfloating(internal PD)

M93-LP

GPIO57

GPIO28

High

High

High

Low

EC_SMI#

R157 1

2 10K_0402_5%

PCH_GPIO15

R159 1

2 1K_0402_5%

PCH_GPIO12

R811 1

2 10K_0402_5%

PCIECLKREQ6#

R812 1

2 10K_0402_5%

PCH_DDR_RST

R813 1

2 10K_0402_5%

PCH_GPIO28 PA@ R814 1

2 10K_0402_5%

GPIO57

R182 1

2 10K_0402_5%

GPIO35

R165 2

1 10K_0402_5%

VGA_PRSNT_L# SG@
SG@R911
R911 1

2 10K_0402_5%

GPIO57

2 10K_0402_5%

PCH_GPIO28 OPP@ R1263 1

2 10K_0402_5%

NV_CLE

Park

DMI termination voltage.

weak internal PU, don't PD

Park-LP

+3VS

Low
Low

High
Low

2 1K_0402_5%

@ R1257

@ R183 1

2 1K_0402_5%

@U2
@
U2

IN1

IN2

PCI_GNT3#

PLT_RST#

Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009. 09.20 un-stuff R185 PD for PLT_RST#

5

Compal Secret Data

Security Classification

SN74AHC1G08DCKR_SC70-5

@ R185
100K_0402_5%

Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default *

<6> BUF_PLT_RST#

A16 swap overide Strap/Top-Block

Swap Override jumper

Title

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

14

of

55

10/1 L45 can use 0 ohm when DIS only

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

+3VS

L38

0.357A

VCC3_3[10]

M36

VCC3_3[11]

N36

VCC3_3[12]

P36

VCC3_3[13]

U35

VCC3_3[14]

AD13

3.208A

VCCSATAPLL[1]
VCCSATAPLL[2]

+V1.1A_INT_VCCSUS
2
0.1U_0402_16V4Z

2 0.1U_0402_16V4Z

C179

VCCIO[9]

AH22
2

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22
+3VS

0.4A@3.3V

2
0.1U_0402_16V4Z

C185
+VCCP

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

A12

V_CPU_IO[1]
V_CPU_IO[2]

VCCRTC

2mA

IBEXPEAK-M_FCBGA1071

6mA

VCCVRM[4]

AT20

VCCIO[10]

AH19

VCCIO[11]

AD20

VCCIO[12]

AF22

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

AD19
AF20
AF19
AH20

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

AB19
AB20
AB22
AD22

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

AA34
Y34
Y35
AA35

VCCSUSHDA

L30

AN30
AN31

@ R189 1

Delete L4

+1.05VS

+1.8VS

VCCIO[54]
VCCIO[55]
VCC3_3[1]

AT22

VCCVRM[1]

0.035A

BJ18

VCCFDIPLL

6mA

AM23

VCCIO[1]

0_0402_5%

VCCVRM[2]

AT24

VCCDMI[1]

AT16

VCCDMI[2]

AU16

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AM8
AM9
AP11
AP9

C160
0.1U_0402_16V4Z

LVDS

0.061A

+VCCP

R671

2 0_0402_5%

+1.8VS

@ R672

2 0_0402_5%

+3VS

+3VS

0.085A

@ R190 1

+1.05VS

+1.05VS

+1.05VS_VCCFDIPLL

0_0402_5%

Delete L5

+1.05VS_L
R191
1
2
0_0603_5%

+V1.05S_VCCA_A_DPL_L
R192
L6
1
2
1
2
0_0603_5%
10UH_LB2012T100MR_20%_0805

+1.05VS

1 @
R194
R195
R198
R200

1
1
1
1

+3.3A_1.5A_VCCPAZSUS

2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

+V1.05S_VCCA_B_DPL_L
R201
L7
1
2
1
2
0_0603_5%
10UH_LB2012T100MR_20%_0805

+V1.05S_VCCA_A_DPL
1
2

+PCH_VCC1_1_20
+PCH_VCC1_1_21
+PCH_VCC1_1_22
+PCH_VCC1_1_23

2
+1.05VS

+
2

+5VALW +3VALW

Delete R193

D4
RB751V_SOD323

R196
100_0402_5%

+V1.05S_VCCA_B_DPL

+3VALW

+5VS

+3VS

R197

D5
RB751V_SOD323

100_0402_5%

ICH_V5REF_RUN

ICH_V5REF_SUS
1
+
2

20 mils
1

20 mils
1

C194
1U_0402_6.3V4K_X5R

C195
1U_0402_6.3V4K_X5R

9/20 Un-stuff C187,C192 to follow Intel check list

Issued Date

Compal Secret Data

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C148
10U_0805_6.3V6M

IBEXPEAK-M_FCBGA1071

Security Classification

C147
0.01U_0402_25V7K

VCC CORE

C146
10U_0603_6.3V6M

C145
1U_0402_6.3V6K

+1.05VS_VCCFDIPLL

+3VS

0.156A

AN35

2 @

C197
0.1U_0402_16V4Z

C196
0.1U_0402_16V4Z

2mA@3.3V

AU18

HDA

C190
0.1U_0402_16V4Z

C189
0.1U_0402_16V4Z

C188
4.7U_0603_6.3V6K

2
+RTCVCC

CPU

0.1A@1.1V
AT18

VCCSUS3_3[32]

+1.05VS

C184
1U_0402_6.3V6K

VCCSUS3_3[29]

SATA

P18

PCI/GPIO/LPC

2
0.1U_0402_16V4Z

C182

DCPSUS

+3VALW

0.2A@3.3V

Y22

C682 1
2 0.1U_0402_16V4Z
+1.8VS

0.1A@1.1V

AK3
AK1

RTC

+3VS
C176 1

C177

VCC3_3[4]

AD35

+3VS

+1.05VS_VCCAPLL

0.032A

AB35

DIS@
C999
0_0805_5%

C183
10U_0805_6.3V6M

VCCIO[2]

J38

VCC3_3[9]

AB34

VCC3_3[3]

SG@
2

+1.8VS

AF34
AH34

VCC3_3[8]

VCC3_3[2]

SG@
2

2 0_0603_5%
SG@

VCCIO[21]
VCCIO[22]
VCCIO[23]

ICH_V5REF_RUN

SG@
2

R779 1

+VCCSST

2
0.1U_0402_16V4Z

AH23
AJ35
AH35

0.073A
VCCADPLLB[1]
VCCADPLLB[2]

K49

2 0_0402_5%

C175
1U_0402_6.3V6K

0.072A

V5REF

>1mA

AP43
AP45
AT46
AT45

VCCADPLLA[1]
VCCADPLLA[2]

0_0603_5%

C167
1U_0402_6.3V6K

BB51
BB53

L45

C174
1U_0402_6.3V6K

C173
1U_0402_6.3V6K

0.035A
VCCVRM[3]

BD51
BD53

+1.05VS

DCPRTC

AU24

+V1.05S_VCCA_B_DPL

ICH_V5REF_SUS

DIS@

2 0_0402_5%

C172
0.1U_0402_16V4Z

+V1.05S_VCCA_A_DPL

+1.05VS

F24

C178
0.1U_0402_16V4Z

+1.8VS

V9

V23

V5REF_SUS

>1mA

+VCCRTCEXT
2
0.1U_0402_16V4Z

U23

VCCIO[56]

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

SG@
R1230
DIS@
R1231

C166 1

VCCSUS3_3[28]

AH39

HVCMOS

VCCME[12]

+1.8VS

DMI

VCCME[11]

Y42

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

VSSA_LVDS

PCI E*

Y41

+1.05VS

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

VCCALVDS

AH38

NAND / SPI

VCCME[10]

VCCAPLLEXP0.042A

FDI

VCCME[9]

Y39

0.030A

C186
220U_D2_2VY_R15M

V42

VCCIO[24]

BJ24

VSSA_DAC[2]

AF51

C191
220U_B_2.5VM_R15M

VCCME[8]

AK24

C187
1U_0402_6.3V6K

VCCME[7]

V41

C159
10U_0805_6.3V6M

V39

0_0402_5%

Delete L3

C165
1U_0402_6.3V6K

1.998A

C170
10U_0603_6.3V6M

C161
1U_0402_6.3V6K

C163
10U_0805_6.3V6M

C162
10U_0805_6.3V6M

VCCME[6]

+1.05VS_APLL
@ R188 1

C164
1U_0402_6.3V6K

VCCME[5]

C181
10U_0805_6.3V6M

AF41

C193
1U_0402_6.3V6K

VCCME[4]

AF53

0.059A

C180
1U_0402_6.3V6K

C153
1U_0402_6.3V6K

VCCME[3]

AF43

AE52

VSSA_DAC[1]

C1000

AD41

AE50

VCCADAC[2]

+3VS

+1.05VS
+3VALW

VCCADAC[1]

10U_0805_6.3V6M

VCCME[2]

0.069A

C999

AD39

AF42

VCCME[1]

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4] 1.524A
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

0.01U_0603_16V7K

DCPSUSBYP

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

C998

AD38

0.344A

0.01U_0603_16V7K

+1.05VS

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

C169
1U_0402_6.3V6K

VCCLAN[2]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
0.163AVCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

C168
1U_0402_6.3V6K

AF24

V24
V26
Y24
Y26

C158
0.1U_0402_16V4Z

VCCLAN[1]

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

0.052A

C157
0.1U_0402_16V4Z

VCCACLK[2]

AF23

C150
1U_0402_6.3V6K

AP53

2 C152
Y20
0.1U_0402_16V4Z

VCCACLK[1]

+1.05VS

C171
0.1U_0402_16V4Z

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

AP51

USB

Clock and Miscellaneous

POWER

U1J

PCI/GPIO/LPC

C144
1U_0402_6.3V6K

C143
10U_0805_6.3V6M

0_0402_5%

Delete L1

+3VS
PA@ L45
2
1
MURATA_BLM18AG601SN1D_0603

POWER

U1G

CRT

+1.05VS
2

C149
0.1U_0402_16V4Z

+VCCP_VCCA_CLK
@ R186 1

C192
1U_0402_6.3V6K

+1.05VS

Title

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

15

of

55

U1I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

U1H
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

AB16

VSS[0]

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071
A

Compal Secret Data

Security Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

IBEX-M(6/6)-GND

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

16

of

55

1
2

DDR_A_DM1
DRAMRST#

DRAMRST#

<6,18>

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29

Layout Note:
Place near JDIMM1

DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDR_A_MA3
DDR_A_MA1
<8> M_CLK_DDR0
<8> M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

<8> DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

<8> DDR_A_WE#
<8> DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

<8> DDR_CS1_DIMMA#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
B

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 R207
2
10K_0402_5%

1
2

R208
10K_0402_5%

C220
0.1U_0402_16V4Z

C219
2.2U_0402_6.3V6M

+3VS
A

2009. 08.17 no stuff C204

<8>

C204
10U_0603_6.3V6M

C203
10U_0603_6.3V6M

C201
10U_0603_6.3V6M

DDR_A_MA6
DDR_A_MA4

DDR_A_MA11
DDR_A_MA7

DDR_A_MA15
DDR_A_MA14

C45
47P_0402_50V8J

206

DDR_CKE1_DIMMA

G2

DDR_CKE1_DIMMA

DDR_A_MA8
DDR_A_MA5

2 @

DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#

M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>

DDR_CS0_DIMMA#
M_ODT0
M_ODT1

DDR_CS0_DIMMA#
M_ODT0 <8>
M_ODT1 <8>

<8>

+VREF_CA

1
+
2

2009.08.17 change the

C200 to ESR 12m ohm

Layout Note:
Place near JDIMM1.203 & JDIMM1.204
+V_DDR_CPU_REF
+0.75VS
1
R877

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

2
0_0402_5%

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

PM_EXTTS#1_R <6,18>
SMB_DATA_S3 <12,18,19,30>
SMB_CLK_S3 <12,18,19,30>

+0.75VS

0.65A@0.75V

DDR3 SO-DIMM A
REVERSE

+0.75VS

Compal Secret Data

Security Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

R206
1K_0402_1%

C44
47P_0402_50V8J

DDR_A_MA12
DDR_A_MA9

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

+V_DDR_CPU_REF

Add for RF

C214
2.2U_0402_6.3V6M

DDR_A_BS2

<8> DDR_A_BS2

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2 0_0402_5%

DDR_A_D12
DDR_A_D13

C213
0.1U_0402_16V4Z

DDR_CKE0_DIMMA

<8> DDR_CKE0_DIMMA

R205
1K_0402_1%

+V_DDR_CPU_REF0

0_0402_5%

C200
330U_D2_2VY_R9M

G1

@ R898 1

+1.5V
C

C212
0.1U_0402_16V4Z

205

47P_0402_50V8J

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

47P_0402_50V8J
C1396

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

R884 1

<8> DDR_A_DQS#[0..7]
<8> DDR_A_MA[0..15]

DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7

<8> DDR_A_DQS[0..7]

C211
0.1U_0402_16V4Z

DDR_A_D26
DDR_A_D27

C210
0.1U_0402_16V4Z

DDR_A_DM3

C209
0.1U_0402_16V4Z

DDR_A_D24
DDR_A_D25

C208
10U_0603_6.3V6M

DDR_A_D18
DDR_A_D19

2
DDR_A_D4
DDR_A_D5

C202
10U_0805_6.3V6M

DDR_A_DQS#2
DDR_A_DQS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

+VREF_DQ_DIMMA

C207
10U_0603_6.3V6M

DDR_A_D16
DDR_A_D17

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

+1.5V
+V_DDR_CPU_REF

<8> DDR_A_DM[0..7]

C218
1U_0402_6.3V6K

DDR_A_D10
DDR_A_D11

<8> DDR_A_D[0..63]

C206
10U_0603_6.3V6M

DDR_A_DQS#1
DDR_A_DQS1

CONN@

C217
1U_0402_6.3V6K

DDR_A_D8
DDR_A_D9

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C205
10U_0603_6.3V6M

DDR_A_D2
DDR_A_D3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C216
1U_0402_6.3V6K

DDR_A_DM0

C215
1U_0402_6.3V6K

C1058
2.2U_0603_6.3V4Z

2
D

C1057
0.1U_0402_10V6K

DDR_A_D0
DDR_A_D1

47P_0402_50V8J
C1395

3A@1.5V

JDIMM1
+VREF_DQ_DIMMA

+1.5V

C1393

+1.5V

47P_0402_50V8J
C1394

+VREF_DQ_DIMMA

Title

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P

Monday, November 09, 2009

Sheet
1

17

of

55

+1.5V

+1.5V

<8> DDR_B_D[0..63]

<8> DDR_CS3_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
B

DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
1 R210
2
10K_0402_5%

C242
0.1U_0402_16V4Z

C241
2.2U_0402_6.3V6M

+3VS
A

R211
1

10K_0402_5%

205

G1

G2

206

Layout Note:
Place near JDIMM2

<8>

DDR_B_MA11
DDR_B_MA7

2009. 08.17 no stuff C228,C229

DDR_B_MA6
DDR_B_MA4

+1.5V

DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 <8>
DDR_B_RAS# <8>

DDR_CS2_DIMMB#
M_ODT2

DDR_CS2_DIMMB#
M_ODT2 <8>

M_ODT3

<8>

M_ODT3 <8>

DDR_B_D36
DDR_B_D37

2 @

2 @

Layout Note:
Place near JDIMM2.203 & JDIMM2.204
B

+0.75VS

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

PM_EXTTS#1_R <6,17>
SMB_DATA_S3 <12,17,19,30>
SMB_CLK_S3 <12,17,19,30>
+0.75VS

DDR3 SO-DIMM B
REVERSE

0.65A@0.75V

+0.75VS
CONN@

Compal Secret Data

Security Classification
Issued Date

2008/03/13

Deciphered Date

2009/05/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

+VREF_CA

DDR_B_DM4
DDR_B_D38
DDR_B_D39

C234
0.1U_0402_16V4Z

DDR_B_WE#
DDR_B_CAS#

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

C233
0.1U_0402_16V4Z

<8> DDR_B_WE#
<8> DDR_B_CAS#

DDR_CKE3_DIMMB

C232
0.1U_0402_16V4Z

<8> DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

DDR_B_D30
DDR_B_D31

C231
0.1U_0402_16V4Z

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_DQS#3
DDR_B_DQS3

C230
10U_0603_6.3V6M

DDR_B_MA3
DDR_B_MA1
<8> M_CLK_DDR2
<8> M_CLK_DDR#2

DDR_B_D28
DDR_B_D29

C229
10U_0603_6.3V6M

DDR_B_MA8
DDR_B_MA5

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D22
DDR_B_D23

C228
10U_0603_6.3V6M

DDR_B_MA12
DDR_B_MA9

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_B_DM2

C227
10U_0603_6.3V6M

DDR_B_BS2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_B_D20
DDR_B_D21

C240
1U_0402_6.3V6K

<8> DDR_B_BS2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

<6,17>

C226
10U_0603_6.3V6M

DDR_CKE2_DIMMB

DRAMRST#

DDR_B_D14
DDR_B_D15

C239
1U_0402_6.3V6K

<8> DDR_CKE2_DIMMB

DDR_B_DM1
DRAMRST#

C225
10U_0603_6.3V6M

2 0_0402_5%

C238
1U_0402_6.3V6K

DDR_B_D26
DDR_B_D27

@ R899 1

+V_DDR_CPU_REF1

C224
10U_0603_6.3V6M

DDR_B_DM3

2 0_0402_5%

DDR_B_D12
DDR_B_D13

C237
1U_0402_6.3V6K

DDR_B_D24
DDR_B_D25

R885 1

DDR_B_D6
DDR_B_D7

C223
10U_0603_6.3V6M

DDR_B_D18
DDR_B_D19

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_DQS#2
DDR_B_DQS2

+V_DDR_CPU_REF

<8> DDR_B_MA[0..15]

DDR_B_D16
DDR_B_D17

DDR_B_D4
DDR_B_D5

C47
47P_0402_50V8J

DDR_B_D10
DDR_B_D11

<8> DDR_B_DQS[0..7]

DDR_B_DQS#1
DDR_B_DQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_B_D8
DDR_B_D9

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C46
47P_0402_50V8J

DDR_B_D2
DDR_B_D3

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C1060
2.2U_0603_6.3V4Z

DDR_B_DM0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C235
0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

C1059
0.1U_0402_10V6K

C221
2.2U_0402_6.3V6M

+VREF_DQ_DIMMB

<8> DDR_B_DM[0..7]

JDIMM2

<8> DDR_B_DQS#[0..7]

3A@1.5V
+VREF_DQ_DIMMB
+VREF_DQ_DIMMB

Title

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Sheet

Monday, November 09, 2009

1

18

of

55

+1.5VS_CK505
+1.05VS_CK505
+1.05VS_CK505
+3VS_CK505

+3VS_CK505

80mA

CLK_14M_PCH @ C808 1

+1.5VS_CK505

2 10P_0402_50V8J

U3

9/11 non-stuff R216

OK

R221 1
R223 1

CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#

<12> CLK_BUF_CKSSCD
CKSSCD <12> CLK_BUF_CKSSCD#

2 33_0402_5%
2 33_0402_5%

R219 1
R220 1

2 33_0402_5%
2 33_0402_5%

9
10
11
12
13
14
15
16

L_CLK_DMI
L_CLK_DMI#
L_CLK_BUF_CKSSCD
L_CLK_BUF_CKSSCD#
CPU_STOP#

VSS_SATA
SRC_1/SATA
SRC_1#/SATA#100MHz
VSS_SRC
SRC_2
SRC_2# 100MHz
VDD_SRC_IO
CPU_STOP#

24
23
22
21
20
19
18
17

VDD_CPU
CPU_0

133MHz CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC

R_CKPWRGD

R226 1
R237 1

2 0_0402_5%
2 0_0402_5% CKPWRGD

L_CLK_BUF_BCLK
L_CLK_BUF_BCLK#

R224 1
R225 1

2 33_0402_5%
2 33_0402_5%

+3VS

33

ICS9LRS3197AKLFT MLF 32P

SRC/SATA(100MHz)

REF(14.318MHz)

DOT_CLK(96MHz)

27MHz

27MHz_SS

2009.10.21 change the C259, C260 to 22P

CLK_XTAL_OUT
CLK_XTAL_IN

+3VS_CK505

Y3
1
C259
22P_0402_50V8J

2 14.318MHZ_16PF_7A14300083
C260
22P_0402_50V8J

R607
10K_0402_5%

<49>

CLK_EN#

+3VS_CK505

0(default)

133MHz

133MHz

100MHz

100MHz

CPU_STOP#

R234 1

CPU_1

CPU_0

CLK_EN# 2
G

2
Q30
2N7002_SOT23-3

2 10K_0402_5%
2 10K_0402_5%

Routing the trace at least 10mil

+1.5VS_CK505

+3VS

R247 1

2 10K_0402_5%

CPU_SEL During CK_PEWGD Latch Pin1

@
R244 1

BCLK OK

R218
1
2
0_0805_5%

CKPWRGD

PIN 30

CLK_BUF_BCLK <12>
CLK_BUF_BCLK# <12>

+1.05VS_CK505

+VCCP

Vendor suggests 22pF

<13,49>

Place close to U3

2
1

SLG8SP585
SLG8SP587

133MHz
SRC(100MHz_SS)

0_0805_5%

pin8
is GND (for DELLHP)
pin8 is 48MHz (For ABO or 030)
RealtekSA00002Y010
* IDTSA00002Y500
IDTSA00002WX00

Number

VGATE

+3VS_CK505
R212
1

Number of Clock Outputs

Output

14M OK
D

+3VS

REF_0/CPU_SEL

+1.5VS

R228
0_0603_5%
1
2
1

2
@ R229
@R229
0_0603_5%

2
B

Near pin1 Near pin17

SI

C250
0.1U_0402_16V4Z

OK

CLK_DMI
CLK_DMI#

CLK_14M_PCH <12>

CLK_XTAL_IN
CLK_XTAL_OUT

C247
0.1U_0402_16V4Z

L_27M_CLK
L_27M_SSC

133_0402_5%
133_0402_5%

C249
0.1U_0402_16V4Z

CLK_DMI
CLK_DMI#

@ R216 2
@ R217 2

C254
0.1U_0402_16V4Z

<12>
DMI<12>

27M

27M_CLK
27M_SSC

C246
0.1U_0402_16V4Z

27M_CLK
27M_SSC

SMB_CLK_S3 <12,17,18,30>
SMB_DATA_S3 <12,17,18,30>
R222 2
1 33_0402_5% CLK_14M_PCH

C253
0.1U_0402_16V4Z

OK

<26>
<26>

SMB_CLK_S3
SMB_DATA_S3
REF_0/CPU_SEL

32
31
30
29
28
27
26
25

SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#

C248
0.1U_0402_16V4Z

VDD_DOT
VSS_DOT
DOT_96
DOT_96# 96MHz
VDD_27
27MHZ
27MHZ_SS
VSS_27

C245
10U_0805_10V4Z

OK

1
2
3
4
5
6
7
8

1 33_0402_5%L_CLK_BUF_DOT96
1 33_0402_5%L_CLK_BUF_DOT96#

R213 2
R214 2

C252
10U_0805_10V4Z

CLK_BUF_DOT96
CLK_BUF_DOT96#

<12> CLK_BUF_DOT96
DOT96 <12> CLK_BUF_DOT96#

TGND

250mA

Near pin24

Reserve low power clock generator solution

Compal Secret Data

Security Classification
2007/08/28

Issued Date

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Clock Generator CK505

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Sheet

Monday, November 09, 2009

1

19

of

55

BLUE
GREEN
RED

RED

<36>

GREEN

GREEN

<36> D_HSYNC
<36>
BLUE

C268
0.1U_0402_16V4Z
1
2

VSYNC_G_A

R274 1

D_VSYNC

2 0_0402_5%

U6
SN74AHCT1G125GW_SOT353-5

SG@ R272
2.2K_0402_5%

R271
4.7K_0402_5%
SG@

@ C269
5P_0402_50V8C

D_DDCDATA

1
3

DAN217T146_SC59-3

1
3

DAN217T146_SC59-3

R273 SG@
2.2K_0402_5%

I_CRT_DDC_DATA

@ C270
5P_0402_50V8C

Q2A

SG@
2N7002DW-7-F_SOT363-6
3

2
D_DDCCLK
D_DDCDATA <36>
D_DDCCLK <36>

I_CRT_DDC_DATA <13>

R270
4.7K_0402_5%

+3VS

+3VS

D_HSYNC

2 0_0402_5%

5
1

CRT_VSYNC

<22> CRT_VSYNC

R269 1

+CRTVDD
1

+CRTVDD

CRT_HSYNC

P
OE#

<22> CRT_HSYNC

Place close to
JCRT1

DGPU_EDIDSEL#

SUYIN_070546FR015S263ZR
CONN@

1 10K_0402_5%

U5
SN74AHCT1G125GW_SOT353-5
HSYNC_G_A
Y 4

P
OE#

5
1

R815 2

D8

16
17

C267
0.1U_0402_16V4Z
1
2

BLUE

<36> D_VSYNC

+5VS

+5VS

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED

1
0.1U_0402_16V4Z
C266
JCRT1

<36>

W=40mils

1.1A_6VDC_FUSE

1
RB491D_SC59-3

CRT Connector

F1
1

D7

D9

D6

+CRTVDD

DAN217T146_SC59-3

+RCRT_VCC

+5VS

IGPU
I_CRT_DDC_CLK

I_CRT_DDC_CLK <13>

Q2B
2N7002DW-7-F_SOT363-6

R900 1

2 0_0402_5%

DGPU_EDIDSEL

+3VS_VGA

R879
4.7K_0402_5%

D_DDCDATA

D_CRT_DDC_DATA <26>
5

Q11A
3

2N7002DW-7-F_SOT363-6
3

D_DDCCLK

R878
4.7K_0402_5%

DGPU
4

D_CRT_DDC_CLK <26>

Q11B
2N7002DW-7-F_SOT363-6

CRT Termination/EMI Filter

<22>

M_RED

<22> M_GREEN

M_RED

L8 1

2 HLC0603CSCCR11JT_0603

RED

M_GRN

L9 1

2 HLC0603CSCCR11JT_0603

GREEN

M_BLU

L10 1

2 HLC0603CSCCR11JT_0603

BLUE

2
1

R902
10K_0402_5%

<14,22> DGPU_EDIDSEL#

DGPU_EDIDSEL#

2
G

2007/08/28

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

DGPU_EDIDSEL <22,40>

SG@
Q12
2N7002_SOT23-3

Compal Secret Data

Security Classification
Issued Date

DGPU_EDIDSEL

C276
10P_0402_50V8J

C275
10P_0402_50V8J

C274
10P_0402_50V8J

C273
22P_0402_50V8J

C272
22P_0402_50V8J

R277
150_0402_1%

R276
150_0402_1%
2
1

1
2

R275
150_0402_1%
2
1

M_BLUE

C271
22P_0402_50V8J

+3VS
<22>

Title

Compal Electronics, Inc.

CRT Connector

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
E

20

of

55

LVDS CONN & USB Camera + Dig Mic

+3VS

+LCDVDD

LVDS_A2- <22>
LVDS_A2+ <22>
LVDS_A1- <22>
LVDS_A1+ <22>
LVDS_A0- <22>
LVDS_A0+ <22>
LVDS_ACLK- <22>
LVDS_ACLK+ <22>

C281
0.1U_0402_16V4Z

R278
22_0805_5%

C282
0.1U_0402_16V4Z

LVDS_EDID_CLK
LVDS_EDID_DATA

R281 1
100_0402_1%

R280
2

DMIC_DAT <34>
DMIC_CLK <34>
+5VS
LVDS_INV_PWM <22>
BKOFF# <39>
DAC_BRIG <39>

Add for RF

VIN

IO1

IO2 GND

2N7002DW-7-F_SOT363-6
Q3A

C283
4.7U_0805_10V4Z

100K_0402_5%
C284

@ R1196
2.2_0402_5%

01/03 Change to 0.047u to meet T1 timing

+USB_CAM
1

LVDS_EDID_CLK <22>
LVDS_EDID_DATA <22>

@ C1414
12P_0402_50V J

BKOFF#

USB20_P4

1
C1369
680P_0402_50V7K

Limited Current < 1A

IGPU

<13>

I_ENAVDD

I_ENAVDD

C286
680P_0402_50V7K

SG@ R283
100K_0402_5%
@ R282
10K_0402_5%

SG@
Q33
2N7002_SOT23-3

2
G

PJLCR05

0.047U_0402_16V7K

LVDS_INV_PWM
DMIC_DAT
DMIC_CLK
+5V_LOGO
LVDS_INV_PWM
BKOFF#
DAC_BRIG

C280
4.7U_0805_10V4Z

USB20_N4

1
1

R279
1M_0402_5%

2
G

LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+

D59
+5VALW

+3VS
Q13
SI2301BDS-T1-E3_SOT23-3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

6 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

+5VALW

JLVDS1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

ACES_88242-4001
CONN@

+LCDVDD
1

+LCDVDD

D_ENAVDD

<24> D_ENAVDD

5
4

DGPU

EMI request.

R880
2.2K_0402_5%

26

Must close JLVDS1pin 24

+3VS

Q3B
2N7002DW-7-F_SOT363-6

22P_0402_50V8J

C1412

Add for RF

22P_0402_50V8J
C1413

USB20_P4
USB20_N4

USB20_P4
USB20_N4

Reserve for RF

LVDS_ACLK+

47P_0402_50V8J

C1411

1
2

C279
680P_0402_50V7K

C278
680P_0402_50V7K

C1410

47P_0402_50V8J

C277
680P_0402_50V7K

2
<14>
<14>

LVDS_ACLK-

5P_0402_50V

INVPWR_B+

C1409

+LCDVDD

C1408

+3VS
D

5P_0402_50V

Add for RF

R285
2.2K_0402_5%
1

R284
2.2K_0402_5%
LVDS_EDID_CLK
LVDS_EDID_DATA

DMIC_DAT

DMIC_CLK

@ C287
220P_0402_25V8J

@ C288
220P_0402_25V8J
B+

INVPWR_B+

L12 1
2
FBMA-L11-201209-221LMA30T_0805

USB Camera

+USB_CAM

Add for RF

1
1

C290
10U_0805_6.3V6M

IN

OUT

GND

SHDN

BYP

R286
215K_0402_1%
1

R288
0_0402_5%

47P_0402_50V8J

C1415

U7
1

C289
10U_0805_6.3V6M

+5VS

G916T1UF SOT23 5P

2
R287
100K_0402_1%

C981
47P_0402_50V8J

+USB_CAM is +3.9VS, R286:215K; R287:100Kohm

+USB_CAM=1.25(1+R1091/R1093)

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

LCD CONN.

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

21

of

55

LVDS Switch

LVDS I2C switch

+3VS

DGPU_EDIDSEL

Thermal_GND

<21>

+3VS

<14>

SG@
4

DGPU

6
2

<26> DGPU_BKL_EN

R886
10K_0402_5%

DIS ONLY (LVDS)

RP36 4
3

D_LVDS_A1D_LVDS_A1+

RP37 4
3

D_LVDS_A2+
D_LVDS_A2-

RP38 3
4

D_LVDS_ACLKD_LVDS_ACLK+

RP39 4
3

1
2
DIS@
1
2
DIS@
2
1
DIS@
1
2
DIS@

ENBKL

<39>

SG@Q111B
2N7002DW-7-F_SOT363-6

DGPU_SELECT
3

9/20 Follow Intel check list to add PU resistors for EDID signals

D_LVDS_A0D_LVDS_A0+

SG@ Q111A
2N7002DW-7-F_SOT363-6

Q21B
2N7002DW-7-F_SOT363-6

<13> IGPU_BKLT_EN

Q21A
2N7002DW-7-F_SOT363-6

@ R1262
4.7K_0402_5%

<13> I_EDID_CLK

TS3DV520ERHUR_QFN56_11X5~D
SG@

SG@
R883
4.7K_0402_5%

IGPU

SG@
1

<13> I_EDID_DATA

IGPU

<14,20>

DGPU_EDIDSEL#

R1261
4.7K_0402_5%

LVDS_A0LVDS_A0+
0_0404_4P2R_5%
LVDS_A1LVDS_A1+
0_0404_4P2R_5%
LVDS_A2+
LVDS_A20_0404_4P2R_5%
LVDS_ACLKLVDS_ACLK+
0_0404_4P2R_5%

D_EDID_CLK

0_0402_5%

D_EDID_DATA

0_0402_5%

DGPU_SELECT#

DGPU_SELECT#
SG@

DGPU_SELECT#

LVDS_EDID_CLK

1
6
9
13
16
21
24
28
33
39
44
49
53
55

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

R790
1
2
0_0402_5%
SG@

SG@ Q34B
2N7002DW-7-F_SOT363-6

17

<21>

SG@ Q35A
2N7002DW-7-F_SOT363-6

SG@Q35B
2N7002DW-7-F_SOT363-6

57

NC
NC
NC
NC

SEL

+3VS

LVDS_EDID_DATA

DIS@
2 R1228 LVDS_EDID_CLK
DIS@
2 R1229 LVDS_EDID_DATA

DGPU_BKL_EN

1
R799

2 DIS@
0_0402_5%

IGPU_BKLT_EN

1
R1226

2 @
0_0402_5%

LVDS PWM switch

+3VS

ENBKL

52
5
54
51

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2

<26> D_EDID_CLK

LVDS_A0+ <21>
LVDS_A0- <21>
LVDS_A1+ <21>
LVDS_A1- <21>
LVDS_A2+ <21>
LVDS_A2- <21>
LVDS_ACLK+ <21>
LVDS_ACLK- <21>

SG@ Q34A
2N7002DW-7-F_SOT363-6

@
R891
4.7K_0402_5%

@
R889
4.7K_0402_5%

@ R890 2

1 0_0402_5%

INV_PWM

<39>

46
45
41
40
35
34
30
29
25
26

DGPU

I_LVDS_A0+
I_LVDS_A0I_LVDS_A1+
I_LVDS_A1I_LVDS_A2+
I_LVDS_A2I_LVDS_ACLK+
I_LVDS_ACLK-

LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_ACLK+
LVDS_ACLK-

<26> D_EDID_DATA

LOW: B1 to A
High: B2 to A

<13>
<13>
<13>
<13>
<13>
<13>
<13>
<13>

I_LVDS_A0+
I_LVDS_A0I_LVDS_A1+
I_LVDS_A1I_LVDS_A2+
I_LVDS_A2I_LVDS_ACLK+
I_LVDS_ACLK-

2
3
7
8
11
12
14
15
19
20

IGPU

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1

SG@ C1005
4.7U_0805_10V4Z

48
47
43
42
37
36
32
31
22
23

4
10
18
27
38
50
56

D_LVDS_A0+
D_LVDS_A0D_LVDS_A1+
D_LVDS_A1D_LVDS_A2+
D_LVDS_A2D_LVDS_ACLK+
D_LVDS_ACLK-

VCC
VCC
VCC
VCC
VCC
VCC
VCC

SG@ C1004
0.1U_0402_16V4Z

DGPU
<24> D_LVDS_A0+
<24> D_LVDS_A0<24> D_LVDS_A1+
<24> D_LVDS_A1<24> D_LVDS_A2+
<24> D_LVDS_A2<24> D_LVDS_ACLK+
<24> D_LVDS_ACLK-

Backlight Enable

<20,40>

U35

<21>

+3VS

DGPU

1 SG@
C1013
2

0.1U_0402_16V4Z

1 SG@
C1012

0.1U_0402_16V4Z

1 SG@
C1011

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
3

@
Q36B

2
G

<13> DPST_PWM

@
DIS@ R892 1
Q114
2N7002_SOT23-3
R1227
SG@
2

2 0_0402_5% D_INV_PWM

0_0402_5% DPST_PWM

<24> D_INV_PWM

2N7002DW-7-F_SOT363-6
1 SG@
C1014

IGPU

CRT Switch

LVDS_INV_PWM

@
Q36A
2N7002DW-7-F_SOT363-6
2

2
+3VS

U43

IGPU

<26>
<26>
<26>
<26>
<26>

D_RED
D_GREEN
D_BLUE
D_CRT_HSYNC
D_CRT_VSYNC

24
22
18
17
14

A0
B0
C0
D0
E0

<13>
<13>
<13>
<13>
<13>

I_RED
I_GREEN
I_BLUE
I_CRT_HSYNC
I_CRT_VSYNC

23
21
16
15
13

A1
B1
C1
D1
E1

SEL

SG@ R1237 0_0402_5%

12
1
2DGPU_SELECT#

YA
YB
YC

2
5
6

M_RED
M_GREEN
M_BLUE

YD
YE

8
11

CRT_HSYNC
CRT_VSYNC

GND
GND
GND
GND

3
7
10
20

CRT_HSYNC
CRT_VSYNC

D_RED
D_GREEN
D_BLUE
D_CRT_HSYNC
D_CRT_VSYNC

<20>
<20>

R893
R894
R895
R896
R897

2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@

1
1
1
1
1

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

DIS ONLY (CRT)

M_RED
<20>
M_GREEN <20>
M_BLUE
<20>

SG@ R882
10K_0402_5%

M_RED
M_GREEN
M_BLUE
CRT_HSYNC
CRT_VSYNC

DGPU_SELECT

VDD
VDD
VDD
VDD

DGPU_SELECT#

DGPU

1
4
9
19

+3VS

2
G

SG@
Q37
2N7002_SOT23-3

9/11 Q37 change to single package

PI3V512QE_QSOP24
SG@

Compal Secret Data

Security Classification
Issued Date

2007/09/29

Deciphered Date

2007/09/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

LVDS Switch

Size Document Number

Custom Calpella DIS
Date:

Rev
1.0

LA-4107P
Sheet

Monday, November 09, 2009

1

22

of

55

+3VS_VGA

2 0_0402_5%

C376 2

1 0.1U_0402_16V4Z HDMICLK+

@R866
@
R866

R571
2.2K_0402_5%

WCM-2012-900T_0805
HDMI_R_CLK+
3

+3VS_VGA
R572
2.2K_0402_5%
2

<26> HDMI_C_CLK+

HDMI_R_CLK-

<26> HDMI_C_CLK-

1
L28

1 0.1U_0402_16V4Z HDMICLK-

@R859
@
R859
C375 2

<26> HDMIDAT_VGA

@R868
@
R868

0_0402_5%

2 0_0402_5%

<26> HDMI_C_TX0<26> HDMI_C_TX0+

1 0.1U_0402_16V4Z HDMI_TX_0-

C377 2

1 0.1U_0402_16V4Z HDMI_TX_0+

C378 2

<26> HDMICLK_VGA

L29
2

Q5B
@ R575 1
2N7002DW-7-F_SOT363-6
3

Q5A
2N7002DW-7-F_SOT363-6
HDMIDAT

2 0_0402_5%
HDMICLK

HDMI_R_TX0-

@R576
@
R576 1

2 0_0402_5%

WCM-2012-900T_0805
HDMI_R_TX0+
3

@R869
@
R869

@R870
@
R870

2 0_0402_5%

0_0402_5%

L30
<26> HDMI_C_TX1<26> HDMI_C_TX1+

C379 2

1 0.1U_0402_16V4Z HDMI_TX_1-

C380 2

1 0.1U_0402_16V4Z HDMI_TX_1+

HDMI_R_TX1-

WCM-2012-900T_0805
HDMI_R_TX1+
3

@R871
@
R871

@R872
@
R872

2 0_0402_5%

0_0402_5%
+5VS_HDMI

L31

U52
SN74AHCT1G125GW_SOT353-5

+5VS_HDMI

HDMI Connector

R1023
100K_0402_5%

HPD

C1246
0.1U_0402_16V4Z
D34
RB411DT146_SOT23-3

0_0402_5%

1
+3VS
R1022
2.2K_0402_5%

C665

3
1

+5VS

HDMI_HPD
2
C1245
0.1U_0402_16V4Z

22N_0402_16V7K

@R873
@
R873

WCM-2012-900T_0805
HDMI_R_TX2+
3

HDMI_R_TX2-

1 0.1U_0402_16V4Z HDMI_TX_2+

<26> HDMI_C_TX2+

C381 2

5
1

1 0.1U_0402_16V4Z HDMI_TX_2-

P
OE#

C382 2

<26> HDMI_C_TX2-

R577
1
2
1.5K_0402_5%
R578
1
2
1.5K_0402_5%

Q19B
SG@

R924
10K_0402_5%

R740

HPD
DGPU_PWR_EN <14,40,41,47,51>

HDMI_R_CLKHDMI_R_CLK+
HDMI_R_TX0HDMI_R_TX0+
HDMI_R_TX1HDMI_R_TX1+
HDMI_R_TX2HDMI_R_TX2+

2N7002DW-7-F_SOT363-6

+5VS

1
SG@
Q19A

+5VS

2
G

DIS@
Q108
2N7002_SOT23-3

12
10
9
7
6
4
3
1

18
16
15
19

HDMIDAT
HDMICLK
HDMI_HPD

U51
NC7SZ08P5X_NL_SC70-5

499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%
499_0402_1%

+5V
SDA
SCL
HP_DET
CKCK+
D0D0+
D1D1+
D2D2+

13
14

CEC
Reserved

2
5
8
11
20
21
22
23
17

GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND

SUYIN_100042MR019S153ZL
CONN@

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

JHDMI1
1

R739
2

R738
2

R737
2

R736
2

R735
2

R734
2

R733
499_0402_1%

P
4

HDMI_DET

<26>

+3VS

C667
0.1U_0402_16V4Z

+5VS_HDMI

2N7002DW-7-F_SOT363-6

C666
22N_0402_16V7K

<14> DGPU_HPD_INT#

HDMICLKHDMICLK+
HDMI_TX_0HDMI_TX_0+
HDMI_TX_1HDMI_TX_1+
HDMI_TX_2HDMI_TX_2+

Title

Compal Electronics, Inc.

HDMI LS & Conn.

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

23

of

55

OPP@
U8
M93-S3-LP

PEG Interface
U8A

LVDS Interface
U8F

VARY_BL
DIGON

AB11
AB12

R928 1
OPP@ R929 1
R930 1

2
2
2

10K_0402_5%
0_0402_5%
0_0402_5%

D_INV_PWM <22>
D_ENAVDD <21>

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_U3P
TXOUT_U3N

AH20
AJ19
AL21
AK20
AH22
AJ21
AL23
AK22
AK24
AJ23

LVTMDP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AL15
AK14

D_LVDS_ACLK+
D_LVDS_ACLK-

<22>
<22>

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AH16
AJ15

D_LVDS_A0+ <22>
D_LVDS_A0- <22>

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AL17
AK16

D_LVDS_A1+ <22>
D_LVDS_A1- <22>

AH18
AJ17

D_LVDS_A2+ <22>
D_LVDS_A2- <22>

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
TXOUT_L3P
TXOUT_L3N

AL19
AK18

216-0749001 A11 M93-S3 FCBGA631

3

AF30
AE31

<7> PCIE_CTX_GRX_P14
<7> PCIE_CTX_GRX_N14

AE29
AD28

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N

PCIE_TX0P
PCIE_TX0N

AH30
AG31

PCIE_CRX_GTX_G_P15
PCIE_CRX_GTX_G_N15

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C776
C777

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

<7>
<7>

PCIE_TX1P
PCIE_TX1N

AG29
AF28

PCIE_CRX_GTX_G_P14
PCIE_CRX_GTX_G_N14

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C778
C779

PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14

<7>
<7>

0.1U_0402_10V6K
0.1U_0402_10V6K

<7> PCIE_CTX_GRX_P13
<7> PCIE_CTX_GRX_N13

AD30
AC31

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

AF27
AF26

PCIE_CRX_GTX_G_P13
PCIE_CRX_GTX_G_N13

2
2

1
1

C780
C781

PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13

<7>
<7>

<7> PCIE_CTX_GRX_P12
<7> PCIE_CTX_GRX_N12

AC29
AB28

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

AD27
AD26

PCIE_CRX_GTX_G_P12
PCIE_CRX_GTX_G_N12

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C782
C783

PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12

<7>
<7>

<7> PCIE_CTX_GRX_P11
<7> PCIE_CTX_GRX_N11

AB30
AA31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

AC25
AB25

PCIE_CRX_GTX_G_P11
PCIE_CRX_GTX_G_N11

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C784
C785

PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11

<7>
<7>

<7> PCIE_CTX_GRX_P10
<7> PCIE_CTX_GRX_N10

AA29
Y28

Y23
Y24

PCIE_CRX_GTX_G_P10
PCIE_CRX_GTX_G_N10

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C786
C787

PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10

<7>
<7>

<7> PCIE_CTX_GRX_P9
<7> PCIE_CTX_GRX_N9

Y30
W31

AB27
AB26

PCIE_CRX_GTX_G_P9
PCIE_CRX_GTX_G_N9

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C788
C789

PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9

<7>
<7>

<7> PCIE_CTX_GRX_P8
<7> PCIE_CTX_GRX_N8

W29
V28

<7> PCIE_CTX_GRX_P7
<7> PCIE_CTX_GRX_N7

V30
U31

<7> PCIE_CTX_GRX_P6
<7> PCIE_CTX_GRX_N6

U29
T28

<7> PCIE_CTX_GRX_P5
<7> PCIE_CTX_GRX_N5

T30
R31

<7> PCIE_CTX_GRX_P4
<7> PCIE_CTX_GRX_N4

R29
P28

<7> PCIE_CTX_GRX_P3
<7> PCIE_CTX_GRX_N3

P30
N31

<7> PCIE_CTX_GRX_P2
<7> PCIE_CTX_GRX_N2

N29
M28

<7> PCIE_CTX_GRX_P1
<7> PCIE_CTX_GRX_N1

M30
L31

<7> PCIE_CTX_GRX_P0
<7> PCIE_CTX_GRX_N0

L29
K30

PA@

PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

LVDS CONTROL

<7> PCIE_CTX_GRX_P15
<7> PCIE_CTX_GRX_N15

PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N

Y27
Y26

PCIE_CRX_GTX_G_P8
PCIE_CRX_GTX_G_N8

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C790
C791

PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8

<7>
<7>

PCIE_TX8P
PCIE_TX8N

W24
W23

PCIE_CRX_GTX_G_P7
PCIE_CRX_GTX_G_N7

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C792
C793

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

<7>
<7>

PCIE_TX9P
PCIE_TX9N

V27
U26

PCIE_CRX_GTX_G_P6
PCIE_CRX_GTX_G_N6

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C794
C795

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

<7>
<7>

PCIE_TX10P
PCIE_TX10N

U24
U23

PCIE_CRX_GTX_G_P5
PCIE_CRX_GTX_G_N5

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C796
C797

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

<7>
<7>

T26
T27

PCIE_CRX_GTX_G_P4
PCIE_CRX_GTX_G_N4

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C798
C799

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

<7>
<7>

T24
T23

PCIE_CRX_GTX_G_P3
PCIE_CRX_GTX_G_N3

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C800
C801

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

<7>
<7>

P27
P26

PCIE_CRX_GTX_G_P2
PCIE_CRX_GTX_G_N2

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C802
C803

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

<7>
<7>

P24
P23

PCIE_CRX_GTX_G_P1
PCIE_CRX_GTX_G_N1

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C804
C805

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

<7>
<7>

M27
N26

PCIE_CRX_GTX_G_P0
PCIE_CRX_GTX_G_N0

0.1U_0402_10V6K
0.1U_0402_10V6K

2
2

1
1

C806
C807

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

<7>
<7>

PCIE_TX7P
PCIE_TX7N

PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

CLOCK

10/30

AK30
AK32

<12> CLK_PCIE_VGA
<12> CLK_PCIE_VGA#

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

R932 1

<14,31,32> PLT_RST#
<14> DGPU_HOLD_RST#

DIS@ R934 1

2 0_0402_5%

SG@

2 0_0402_5%

R935 1

02/03 AMD
2
@ 10K_0402_5%
VGA_PERST#

PCIE_CALRP
N10
AL27

NC_PWRGOOD

PCIE_CALRN

Y22

R931 1

2 1.27K_0402_1%

AA22

R933 1

2 2K_0402_1%

+1.1VSDGPU

PERSTB
216-0749001 A11 M93-S3 FCBGA631
PA@

Compal Secret Data

Security Classification
Issued Date

2009/03/31

Deciphered Date

2010/03/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

PEG & LVDS

Size
Document Number
Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

E

Rev
1.0
Sheet

24

of

55

U8C

<29>

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDA[0..63]

MDA[0..63]

+1.5VSDGPU

R936
100_0402_1%

11/07

+VDD_MEM15_REFD

R937
100_0402_1%

C1087
0.1U_0402_10V6K

+1.5VSDGPU

R938
100_0402_1%

11/07

+VDD_MEM15_REF1

R939
100_0402_1%

C1088
0.1U_0402_10V6K

+1.5VSDGPU +1.5VSDGPU

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

+VDD_MEM15_REFD K26
+VDD_MEM15_REF1 J26

R941
4.7K_0402_5%

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

E32
E30
A21
C21
E13
D12
E3
F4

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7

H28
C27
A23
E19
E15
D10
D6
G5

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

W DQSA_0
W DQSA_1
W DQSA_2
W DQSA_3
W DQSA_4
W DQSA_5
W DQSA_6
W DQSA_7

H27
A27
C23
C19
C15
E9
C5
H4

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

ODTA0
ODTA1

L18
K16

ODTA0
ODTA1

CLKA0
CLKA0B

H26
H25

CLKA0
CLKA0#

CLKA1
CLKA1B

G9
H9

CLKA1
CLKA1#

RASA0B
RASA1B

G22
G17

RASA0#
RASA1#

CASA0B
CASA1B

G19
G16

CASA0#
CASA1#

CSA0B_0
CSA0B_1

H22
J22

CSA0#_0

CSA1B_0
CSA1B_1

G13
K13

CSA1#_0

CKEA0
CKEA1

K20
J17

CKEA0
CKEA1
WEA0#
WEA1#

MVREFDA
MVREFSA

J25
K7

NC_MEM_CALRN0
NC_MEM_CALRN1

W EA0B
W EA1B

G25
H10

R943 1
@ R944 1

2 243_0402_1%
2 243_0402_1%

J8
K25

MEM_CALRP1
NC_MEM_CALRP0

AB16
G14
G20

L10

RSVD#1
RSVD#2
RSVD#3

DRAM_RST

K8
L7

CLKTESTA
CLKTESTB

1
R946
4.7K_0402_5%

R947
4.7K_0402_5%

MAA[12..0]

2 @
2
2 @
2
2
2 @

*
QSA[7..0] <29>

<29>
<29>

CLKA0
CLKA0#

<29>
<29>

CLKA1
CLKA1#

<29>
<29>

RASA0#
RASA1#

<29>
<29>

CASA0#
CASA1#

<29>
<29>

CSA0#_0

<29>

CSA1#_0

<29>

CKEA0
CKEA1

<29>
<29>

WEA0#
WEA1#

<29>
<29>

VRAM_ID0 <26>

VRAM_ID1

VRAM_ID1 <26>

VRAM_ID2

VRAM_ID2 <26>

A_BA[2..0] <29>

VRAM_ID0

VRAM_ID1

VRAM_ID2

Hynix Orion die H5TQ1G63BFR-12C

SA000032400
800MHz

Samsung E die K4W1G1646E-HC12

SA000035700
800MHz

Qimonda IDGH1G-04A1F1C-16X
SA000030800

TBD

TBD

TBD

TBD

TBD

DQMA#[7..0] <29>

ODTA0
ODTA1

VRAM_ID0

MAA[12..0] <29>

A_BA[2..0]

QSA#[7..0]

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

<29>

11/11 HP

216-0749001 A11 M93-S3 FCBGA631

PA@

C1089
2200P_0402_25V7K

R1053 1
R1054 1
R1055 1
R1056 1
R1057 1
R1058 1

2
1

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15

2 243_0402_1%
2 243_0402_1%

+1.8VSDGPU

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1

@ R940 1
@ R942 1

<29> DRAM_RST#

@ R945
4.7K_0402_5%

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MEMORY INTERFACE

Compal Secret Data

Security Classification
Issued Date

2009/03/31

2010/03/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Memory Interface

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

25

of

55

U8B

CONFIGURATION STRAPS
TXCAP_DPA3P
TXCAM_DPA3N

AF2
AF4

HDMI_C_CLK+
HDMI_C_CLK-

TX0P_DPA2P
TX0M_DPA2N

AG3
AG5

HDMI_C_TX0+
HDMI_C_TX0-

TX1P_DPA1P
TX1M_DPA1N

AH3
AH1

HDMI_C_TX1+
HDMI_C_TX1-

TX2P_DPA0P
TX2M_DPA0N

AK3
AK1

HDMI_C_TX2+
HDMI_C_TX2-

TXCBP_DPB3P
TXCBM_DPB3N

AK5
AM3

M93-S3/M92-S2

<25>
<25>

<25>

VRAM_ID1

VRAM_ID1

C1092

C1091

W6
V6

DPC_PVDD / DVPDATA_11
DPC_PVSS / GND

AC6
AC5

DPC_VDD18#1/DVPDAT10
DPC_VDD18#2/DVPDAT23

AA5
AA6

0.1U_0402_10V6K

C1095

C1094

1U_0402_6.3V4Z

C1093

+DPC_VDD10

10U_0603_6.3V6M

TX4P_DPB1P
TX4M_DPB1N

HDMI_C_CLK+
HDMI_C_CLK-

<23>
<23>

HDMI_C_TX0+
HDMI_C_TX0-

<23>
<23>

HDMI_C_TX1+
HDMI_C_TX1-

<23>
<23>

HDMI_C_TX2+
HDMI_C_TX2-

<23>
<23>

STRAPS

U1
W1
U3
Y6
AA1

W3
V2

DVPCNTL_MV1 / TX1P_DPC1P
DVPDATA_9 / TX1M_DPC1N

Y4
W5

DVPDATA_13 / TX2P_DPC0P
DVPCNTL_1 / TX2M_DPC0N

AA3
Y2

VDDR4 / DPCD_CALR

PCIE FULL TX OUTPUT SWING

@ R1187
@ R1188

1 10K_0402_5%
1 10K_0402_5%

2
2

TX_DEEMPH_EN

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED

BIF_GEN2_EN_A

GPIO2

PCIE GNE2 ENABLED

0
D

GPIO8
GPU_GPIO11

R954

R957
R958

1 10K_0402_5%

BIF_VGA DIS

2
2

1 10K_0402_5%
1 10K_0402_5%

BIOS_ROM_EN

AA12

D_BLUE

1
R71
1
R72
1
R74

D_GREEN
D_RED

2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

VIP_DEVICE_STRAP_ENA

@ R961
0_0402_5%
1
2
R1059

H_THERMTRIP#

<51>
<19>

@ 10K_0402_5%

GPU_VID0
27M_SSC

GPU_VID0
27M_SSC

02/01 HP
GPU_CTF
GPU_VID1

<51> GPU_VID1
<28> GPIO21_BBEN

GPIO23_CLKREQB

T82

10/24 ATI change R11/T11 to VSS

300mA
C1104

AC14

HDMI_DET

C1108

AC16

27M_CLK

@ R980 2

1 82.5_0402_1%

Y7
27MHZ_18PF_X3S027000FI1H-X

AF14
AE14
AD14
AM28
AK28

C1275
18P_0402_50V8J

C1113

C1112

2
1+TSVDD
BLM15BD121SN1D_0402
C1111

+1.8VSDGPU

10U_0603_6.3V6M

L52

1U_0402_6.3V4Z

1
3

DAC2

C / NC
Y / NC
COMP / NC
H2SYNC
V2SYNC

VREFG

R974 1
+AVDD

AE23
AD23

+VDD1DI

D_CRT_HSYNC
D_CRT_VSYNC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

<22>
<22>

GPIO21_BB_EN

2 499_0402_1%

L48
1
2
BLM15BD121SN1D_0402

(1.8V@70mA AVDD)

(1.8V@45mA VDD1DI)

AL11
AJ11

GENERICC

<22>

L49

AM12
AK12

1
2
BLM15BD121SN1D_0402

+1.8VSDGPU

+1.8VSDGPU

AK10
AL9
AH12
AM10
AJ9
AL13
AJ13

HSYNC_DAC2
VSYNC_DAC2

T88
T89

AD19
AC19

09/22 HP

AE20
AE17
AE19

R2SET / NC

AG13

DDC1CLK
DDC1DATA

AE6
AE5

DPLL_PVDD
DPLL_PVSS

AUX1P
AUX1N

DPLL_VDDC

DDC2CLK
DDC2DATA

XTALIN
XTALOUT

AUX2P
AUX2N
DDCCLK_AUX5P
DDCDATA_AUX5N

VGA_THERMDA
VGA_THERMDC

1
C1109
18P_0402_50V8J

B2 / NC
B2B / NC

A2VDDQ / NC

XTALOUT

3
4

XTALIN
XTALOUT

0.1U_0402_10V6K

1
2

G2 / NC
G2B / NC

VDD2DI / NC
VSS2DI / NC

@ R981
100_0402_1%
2

XTALIN

R2 / NC
R2B / NC

HPD1

PLL/CLOCK

<19>

D_CRT_HSYNC
D_CRT_VSYNC

AG24
AE22

T4
T2
R5
AD17
AC17

DPLUS
DMINUS

THERMAL

DDC6CLK
DDC6DATA
DDCCLK_AUX3P
DDCDATA_AUX3N

TS_FDO
TSVDD
TSVSS

NC#1
NC#2

SG@

R979 1

VGA Thermal Sensor ADM1032ARMZ

2 715_0402_1%

Closed to U8

DDC/AUX

+DPLL_VDDC

2 1M_0402_5%

VDD1DI
VSS1DI

<22>
H2SYNC

M92-S2/M93-S3

A2VSSQ

9/11 Use Y7 for VGA 27MHz

1

AVDD
AVSSQ

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

0.1U_0402_10V6K

R978
249_0402_1%

+DPLL_PVDD

R12

RSET

AD22

11

0.1U_0402_10V6K

C1107

AH26
AJ27

VSYNC

+DPLL_VDDC
1U_0402_6.3V4Z

<23>

+VREFG_GPU
C1106

C1105

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN

HSYNC
VSYNC

A2VDD / NC

300mA
10U_0603_6.3V6M

L51
2
1
BLM15BD121SN1D_0402

AB13
W8
W9
W7
AD10

+1.8VSDGPU

R977
499_0402_1%

+1.1VSDGPU

L6
L5
L3
L1
K4
AF24

DAC1

0.1U_0402_10V6K

GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
TESTEN

T83
T84
T85
T86
T87

+DPLL_PVDD
1U_0402_6.3V4Z

C1103

2
1
BLM15BD121SN1D_0402

C1102

+1.8VSDGPU

10U_0603_6.3V6M

L50

D_BLUE

AUD[0]

CRT

D_CRT_DDC_CLK
<20>
D_CRT_DDC_DATA
<20>

AD2
AD4
AC11
AC13

+3VS_VGA

@ C36
0.1U_0402_16V4Z

HDMICLK_VGA
HDMIDAT_VGA

HDMICLK_VGA
HDMIDAT_VGA

2
2

GPU_CTF

D_GREEN

AH24
AG25

0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

AMD RESERVED CONFIGURATION STRAPS

C1098

R976

T76

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

T80
T81
1

T75

GPU_GPIO8
GPU_GPIO9

T79

TESTEN

AL25
AJ25

B
BB

10U_0603_6.3V6M

1 R331

G
GB

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

C1097

<22> DGPU_BKL_EN
1K_0402_5%

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_29
GPIO_30

IGNORE VIP DEVICE STRAPS

HSYNC

1U_0402_6.3V4Z

001

V2SYNC

AUD[1]

<22>

C1096

SG@ D42

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

2
G

0.1U_0402_10V6K

T77

<12> THERM_DAT_GPU
<12> THERM_CLK_GPU
<13,39> EC_ACIN

D_RED

C1101

D_EDID_CLK
D_EDID_DATA
GPU_VID1
GPU_VID0

U6
U10
T10
U8
U7
T9
T8
T7@
P10
P4
P2
N6@
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
T11
R11

AM26
AK26

10U_0603_6.3V6M

2 4.7K_0402_5%
2 4.7K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
THERM_DAT_GPU
THERM_CLK_GPU
2 AC_PRE_VGA
RB751V_SOD323

R
RB

C1100

GENERAL PURPOSE I/O

GPIO[13:11]

Q83
2N7002_SOT23-3

I2C

1U_0402_6.3V4Z

R964 1
R965 1
@ R1190 1
@ R1191 1

SCL
SDA

AC_PRE_VGA
01/15 HP

R1
R3

C1099

D_EDID_CLK
D_EDID_DATA

0.1U_0402_10V6K

2 10K_0402_5%

0
ENABLE EXTERNAL BIOS ROM

GENERICC

<6,14>

2 150_0402_1%

GPU_CTF
<22> D_EDID_CLK
<22> D_EDID_DATA

@ R1189 1

H2SYNC

Place the 3 resistors close to U8

06/05 AMD

+3VS_VGA

0
VGA ENABLED

GPIO_22_ROMCSB

ROMIDCFG(2:0)

DPC

Add via

GPIO9
GPIO21

M92-S2/M93-S3

DPC_VSSR#1 / DVPCLK
DPC_VSSR#2 / DVPDAT5
DPC_VSSR#3 / GND
DPC_VSSR#4 / GND
DPC_VSSR#5/ DVPCNTL_MV0

GPIO0

AK8
AL7

DVPDATA_7 / TX0P_DPC2P
DVPDATA_1 / TX0M_DPC2N

RECOMMENDED SETTINGS

TX_PWRS_ENB

Add via
GPU_GPIO0
GPU_GPIO1

AJ7
AH6

V4
U5

DESCRIPTION OF DEFAULT SETTINGS

+3VS_VGA

D_CRT_HSYNC
D_CRT_VSYNC

DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17

PIN

STRAPS

HDMI

AK6
AM5

DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

M93-S3/M92-S2

+DPC_PVDD

+DPC_VDD10

2
1
BLM15BD121SN1D_0402

TX3P_DPB2P
TX3M_DPB2N

DPB

TX5P_DPB0P
TX5M_DPB0N

L47
+1.1VSDGPU

DPA

DVO

0.1U_0402_10V6K

1U_0402_6.3V4Z

10U_0603_6.3V6M

C1090

+DPC_PVDD

DVCNTL_0/ DVPDATA_18
DVCNTL_1 / NC
DVCNTL_2 / NC
DVDATA_12 / DVPDATA_16
DVDATA_11 / DVPDATA_20
DVDATA_10 / DVPDATA_22
DVDATA_9 / DVPDATA_12
DVDATA_8 / DVPDATA_14
DVDATA_7 / DVPCNTL_0
DVDATA_6 / DVPDATA_8
DVDATA_5 / DVPDATA_6
DVDATA_4 DVPDATA_4
DVDATA_3 / DVPDATA_19
DVDATA_2 / DVPDATA_21
DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0

@ R47
10K_0402_5%

1
@ U16

<23>
<23>

AD13
AD11

@ C37
1
2

AE16
AD16

2200P_0402_50V7K

AC1
AC3

@ R46
1

+3VS_VGA

VGA_THERMDA

VGA_THERMDC

THERM#_VGA

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

THERM_CLK_GPU

THERM_DAT_GPU

THERM_SCI#

L46
2
1
BLM15BD121SN1D_0402

+1.8VSDGPU

VRAM_ID0
VRAM_ID2

VRAM_ID0
VRAM_ID2

AE9
L9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

ADM1032ARMZ REEL_MSOP8

10K_0402_5%

AD20
AC20
AB22
AC22

216-0749001 A11 M93-S3 FCBGA631

PA@

Compal Secret Data

Security Classification
Issued Date

2009/03/31

Deciphered Date

2010/03/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HDMI, MSIC & Thermal

Size
Document Number
Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

1

Sheet

Rev
1.0
26

of

55

U8G
+1.8VSDGPU
DP E/F POWER

+DPE_VDD18

AE11
AF11

12/2 AMD
+1.1VSDGPU

+DPF_VDD10

AG14
AH14
AM14
AM16
AM18

DPE_VDD10#1
DPE_VDD10#2

DPA_VDD10#1
DPA_VDD10#2

DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

+DPA_VDD10

AF6
AF7
AE1
AE3
AG1
AG6
AH5

C1119

AG20
AG21

2
1
BLM15BD121SN1D_0402

0.1U_0402_10V6K

0.17A

L54

0.2A
C1118

C1116

NC_DPA_VDD18#1
NC_DPA_VDD18#2

1U_0402_6.3V4Z

DP A/B POWER

DPE_VDD18#1
DPE_VDD18#2

C1117

AG15
AG16
0.1U_0402_10V6K

C1115

1U_0402_6.3V4Z

10U_0603_6.3V6M

C1114

0.2A

10U_0603_6.3V6M

L53
2
1
BLM15BD121SN1D_0402

+1.1VSDGPU
+DPE_VDD18
+1.1VSDGPU

AG19
AF20

DPEF_CALR

DPAB_CALR

DPE_PVDD
DPE_PVSS

DP PLL POWER

NC_DPF_PVDD
NC_DPF_PVSS

DPA_PVDD
DPA_PVSS

DPB_PVDD
DPB_PVSS

AE10

R983 1

AG8
AG7

C1125

C1124

AF10
AG9
AH8
AM6
AM8

0.1U_0402_10V6K

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

1U_0402_6.3V4Z

DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5

0.2A

2 150_0402_1%

AG10
AG11

+1.8VSDGPU

0.02A

+DPA_PVDD

C1131

AG18
AF19

DPB_VDD10#1
DPB_VDD10#2

C1130

2
AF17
150_0402_1%

DPF_VDD10#1
DPF_VDD10#2

L56
2
1
BLM15BD121SN1D_0402

0.2A

+VPB_VDD10

AF8
AF9

0.1U_0402_10V6K

C1128

0.1U_0402_10V6K

C1127

1U_0402_6.3V4Z

12/2 AMD

1U_0402_6.3V4Z

1
R982

0.02A
C1126

AF22
AG22
AF23
AG23
AM20
AM22
AM24

+DPE_PVDD

AE13
AF13

10U_0603_6.3V6M

0.17A

L57

NC_DPB_VDD18#1
NC_DPB_VDD18#2

+DPF_VDD10

+1.8VSDGPU

2
1
BLM15BD121SN1D_0402

DPF_VDD18#1
DPF_VDD18#2

C1123

AF16
AG17

10U_0603_6.3V6M

C1122

C1121

0.11A

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

C1120

1U_0402_6.3V4Z

+DPF_VDD10

C1129

L55
2
1
BLM15BD121SN1D_0402

L58

2
1
BLM15BD121SN1D_0402

216-0749001 A11 M93-S3 FCBGA631

+1.8VSDGPU
PA@

C1134

C1133

10U_0603_6.3V6M

C1132

0.1U_0402_10V6K

0.02A

+DPB_PVDD

1U_0402_6.3V4Z

L59
2
1
BLM15BD121SN1D_0402

Compal Secret Data

Security Classification
2009/03/31

Issued Date

Deciphered Date

2010/03/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

DPX POWER

Size
Document Number
Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

Rev
1.0
Sheet
1

27

of

55

+1.5VSDGPU

+1.8VSDGPU

MEM CLK
+VDDRHA

C1201

C1200

0.1U_0402_10V6K

+VGA_CORE

1U_0402_6.3V4Z

C1199

10U_0603_6.3V6M

L8
H7
+SPV10

H8

C1153

10U_0603_6.3V6M

C1152

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1150

C1151

C1166

10U_0603_6.3V6M

C1165

1U_0402_6.3V4Z

C1164

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1163

C1180

C1193

ISOLATED
CORE I/O

PCIE_PVDD
NC_MPV18

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

M13
M15
M16
M17
M18
M20
M21
N20

NC_SPV18

2A
1

+VGA_CORE

+1.8VSDGPU

2
G

+3VS

@ C1207
2
1

R985
47K_0402_5%
2

0.1U_0402_10V6K

3
A

+5VSDGPU

<41> DGPU_PWR_EN#

100K_0402_5%
Q82B
2N7002DW-7-F_SOT363-6

D64

@
1

Q62A

2
R987 2

<47> 1.1VS_POK

330K_0402_5%

RB751V_SOD323

R990

5
1

<26> GPIO21_BBEN

Compal Secret Data

Security Classification
2009/03/31

Issued Date

2010/03/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C1208
0.01U_0402_16V7K

R991
10K_0402_5%

09/22 HP
09/17 soft start by HP
R984
100K_0402_5%

2
G

1
PA@

Q62B

Q85
SI2301BDS_SOT23

R1252
470_0402_5%

+3VS

216-0749001 A11 M93-S3 FCBGA631

Q82A

2N7002DW-7-F_SOT363-6

Q84
SI2301BDS_SOT23

+3VS_VGA

BBP#1
BBP#2

01/16 HP

A32
AM1
AM32

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

PA@

SPVSS

GND

216-0749001 A11 M93-S3 FCBGA631

SPV10

R986
0_0402_5%

+VGA_CORE

GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55

2N7002DW-7-F_SOT363-6

@
1

1U_0402_6.3V4Z

C1192

1U_0402_6.3V4Z

C1191

1U_0402_6.3V4Z

C1189

1U_0402_6.3V4Z

C1188

C1187

+VGA_CORE

3
+BBP

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20

1U_0402_6.3V4Z

C1179

1U_0402_6.3V4Z

C1178

C1177

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1176

C1175

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1174

C1172

1U_0402_6.3V4Z

2N7002DW-7-F_SOT363-6

C1206

0.1U_0402_10V6K

C1205

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31

BACK BIAS

M11
M12

+BBP
1U_0402_6.3V4Z

J7

0.1U_0402_10V6K

C1204

C1203

1U_0402_6.3V4Z

10U_0603_6.3V6M

C1202

VSSRHA
PLL

AM30

+VGA_CORE

VDDRHA

11/07

0.035A

L62
1
2
MCK1608471YZF 0603

L17
L16

C1194
1U_0402_6.3V4Z
+PCIE_PVDD

L61
1
2
BLM15BD121SN1D_0402

NC#3 / VDDR5
NC#4 / VDDR5

10U_0603_6.3V6M

0.04A

L60
1
2
BLM15BD121SN1D_0402
2
1

NC#1 / VDDR4
DVCLK / VDDR4

10U_0603_6.3V6M

12/02 AMD
+1.5VSDGPU

V11
U11

C1198

01/12 AMD

C1186

C1183

10U_0603_6.3V6M

0.1U_0402_10V6K

1U_0402_6.3V4Z

C1182

C1181

10U_0603_6.3V6M

AA11
Y11

VDDR4#1 / VDDR5
VDDR4#2
VDDR4#3 / VDDR5

10U_0603_6.3V6M

+VDDR4

I/O

AA15
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20
V21
Y13
Y16
Y18
Y21

C1197

V12
Y12
U12

+VDDR4
+1.8VSDGPU

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

1U_0402_6.3V4Z

+1.1VSDGPU

1U_0402_6.3V4Z

AA17
AA18
AB17
AB18

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23

CORE

POWER

M93-S3/M92-S2

2A

C1185

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

+PCIE_VDDC

10U_0603_6.3V6M

AA20
AA21
AB20
AB21

C1196

LEVEL
TRANSLATION

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1170

C1169

C1168

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0603_6.3V6M

C1167

+VDDC_CT

C1171

0.06A

1U_0402_6.3V4Z

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

C1184

+3VS_VGA

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

10U_0603_6.3V6M

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17

C1195

H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

10U_0603_6.3V6M

C1157

C1156

1U_0402_6.3V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

C1161

C1160

2
0.1U_0402_10V6K

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1158

10U_0603_6.3V6M

C1159

0.136A

+1.8VSDGPU

C1155

10U_0603_6.3V6M

C1154

PCIE

1U_0402_6.3V4Z

MEM I/O

C1149

+PCIE_GDDR

U8D

+1.5VSDGPU

+VDDC_CT

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

+1.8VSDGPU

0.5A
1U_0402_6.3V4Z

C1148

C1162

U8E

0.1U_0402_10V6K

C1147

C1145

C1146

1U_0402_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C1144

10U_0603_6.3V6M

C1143

C1142

10U_0603_6.3V6M

1U_0402_6.3V4Z

C1141

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1140

2.2A
1

Title

Compal Electronics, Inc.

Main Power

Size
Document Number
Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

28

of

55

U10
VREFC_A1
VREFD_Q1
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12

MDA[0..63]

<25> MDA[0..63]

MAA[12..0]

MAA[12..0]

QSA[7..0]

QSA[7..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M3
N9
M4

BA0
BA1
BA2

K2
L3
J4
K4
L4

ODT/ODT0
CS
RAS
CAS
WE

F4
C8

DQMA#2
DQMA#0

E8
D4

QSA#2
QSA#0

G4
B8

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D8
C4
C9
C3
A8
A3
B9
A4

MDA0
MDA4
MDA1
MDA6
MDA3
MDA7
MDA2
MDA5

VREFC_A2
VREFD_Q2

M9
H2

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12

+1.5VSDGPU

CK
CK
CKE/CKE0

QSA2
QSA0

MDA20
MDA19
MDA23
MDA18
MDA17
MDA21
MDA22
MDA16

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

J8
K8
K10

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

E4
F8
F3
F9
H4
H9
G3
H8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

A_BA0
A_BA1
A_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

CLKA0
CLKA0#
CKEA0
+1.5VSDGPU

VREFCA
VREFDQ

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M3
N9
M4

BA0
BA1
BA2

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

A2
A9
C2
C10
D3
E10
F2
H3
H10

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

K2
L3
J4
K4
L4

QSA3
QSA1

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

DQMA#3
DQMA#1

E8
D4

QSA#3
QSA#1

G4
B8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E4
F8
F3
F9
H4
H9
G3
H8

MDA26
MDA27
MDA25
MDA24
MDA29
MDA30
MDA28
MDA31

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D8
C4
C9
C3
A8
A3
B9
A4

MDA12
MDA10
MDA15
MDA11
MDA13
MDA8
MDA14
MDA9

VREFC_A3
VREFD_Q3

M9
H2

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12

+1.5VSDGPU

J8
K8
K10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

B3
D10
G8
K3
K9
N2
N10
R2
R10

A_BA0
A_BA1
A_BA2

<25>
<25>
<25>
+1.5VSDGPU

A2
A9
C2
C10
D3
E10
F2
H3
H10

<25>
<25>
<25>
<25>
<25>

U13

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M3
N9
M4

BA0
BA1
BA2

CLKA1
CLKA1#
CKEA1

J8
K8
K10

CK
CK
CKE/CKE0

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K2
L3
J4
K4
L4

ODT/ODT0
CS
RAS
CAS
WE

QSA4
QSA5

F4
C8

DQMA#4
DQMA#5

E8
D4

QSA#4
QSA#5

G4
B8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E4
F8
F3
F9
H4
H9
G3
H8

MDA38
MDA34
MDA32
MDA39
MDA33
MDA37
MDA35
MDA36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D8
C4
C9
C3
A8
A3
B9
A4

MDA44
MDA42
MDA47
MDA40
MDA45
MDA43
MDA46
MDA41

VREFCA
VREFDQ

VREFC_A4
VREFD_Q4
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

A_BA0
A_BA1
A_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

M9
H2

VREFCA
VREFDQ

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M3
N9
M4

BA0
BA1
BA2

CLKA1
CLKA1#
CKEA1

J8
K8
K10

CK
CK
CKE/CKE0

A2
A9
C2
C10
D3
E10
F2
H3
H10

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K2
L3
J4
K4
L4

ODT/ODT0
CS
RAS
CAS
WE

QSA6
QSA7

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

DQMA#6
DQMA#7

E8
D4

QSA#6
QSA#7

G4
B8

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E4
F8
F3
F9
H4
H9
G3
H8

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D8
C4
C9
C3
A8
A3
B9
A4

MDA52
MDA50
MDA54
MDA49
MDA53
MDA51
MDA55
MDA48
MDA56
MDA58
MDA60
MDA61
MDA63
MDA62
MDA57
MDA59

+1.5VSDGPU
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.5VSDGPU

A2
A9
C2
C10
D3
E10
F2
H3
H10

QSA#[7..0]

C1244
0.01U_0402_16V7K

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

+1.5VSDGPU

R1003
4.99K_0402_1%
2

R1002
4.99K_0402_1%

VREFD_Q4
1

VREFC_A4

VREFD_Q3

R1009
C1213
4.99K_0402_1%
2 0.1U_0402_10V6K

R1010
C1214
4.99K_0402_1%
2 0.1U_0402_10V6K

R1011
C1215
4.99K_0402_1%
2 0.1U_0402_10V6K

C1216
0.1U_0402_10V6K
2

Compal Secret Data

2009/03/31

2010/03/31

Deciphered Date

Title

1U_0402_6.3V4Z

C1243

1U_0402_6.3V4Z

C1242

C1241

1U_0402_6.3V4Z

C1240

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1239

1U_0402_6.3V4Z

C1238

C1237

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C1233

C1236

C1232

C1235

C1231

1U_0402_6.3V4Z

C1230

1U_0402_6.3V4Z

C1229

Issued Date

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSDGPU

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

1U_0402_6.3V4Z

C1228

Security Classification

ZQ/ZQ0

1U_0402_6.3V4Z

C1225

1U_0402_6.3V4Z

C1224

RESET

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA

2
1
2

C1223

A1
A11
T1
T11

R1001
4.99K_0402_1%

R1008
C1212
4.99K_0402_1%
0.1U_0402_10V6K

1U_0402_6.3V4Z

C1222

C1221

J2
L2
J10
L10

R995
240_0402_1%

+1.5VSDGPU

VREFC_A3

1U_0402_6.3V4Z

B2
B10
D2
D9
E3
E9
F10
G2
G10

DQSL
DQSU

1
2
1

L9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.5VSDGPU
1U_0402_6.3V4Z

2
56_0402_1% 1

1U_0402_6.3V4Z

CLKA1# 1
R1015

10U_0603_6.3V6M

2
56_0402_1%

10U_0603_6.3V6M

10U_0603_6.3V6M

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

+1.5VSDGPU
10U_0603_6.3V6M

2
A

CLKA1 1
R1014

+1.5VSDGPU
C1217
0.01U_0402_16V7K

C1220

2
56_0402_1% 1

C1219

CLKA0# 1
R1013

10U_0603_6.3V6M

2
56_0402_1%

R1007
4.99K_0402_1%

C1211
2 0.1U_0402_10V6K

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DRAM_RST# T3

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA

VREFD_Q2

R1006
4.99K_0402_1%

C1210
2 0.1U_0402_10V6K

10U_0603_6.3V6M

CLKA0 1
R1012

R1005
C1209
4.99K_0402_1%
0.1U_0402_10V6K
2

C1218

R1004
4.99K_0402_1%

A1
A11
T1
T11

R1000
4.99K_0402_1%

VREFC_A2

ZQ/ZQ0

+1.5VSDGPU

R999
4.99K_0402_1%

VREFC_A1
1

VREFD_Q1
1

R994
240_0402_1%

+1.5VSDGPU

R998
4.99K_0402_1%

R997
4.99K_0402_1%

R996
4.99K_0402_1%

J2
L2
J10
L10

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA

+1.5VSDGPU

+1.5VSDGPU

+1.5VSDGPU

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

RESET

DML
DMU

A1
A11
T1
T11

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

L9

R993
240_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DRAM_RST# T3

C1234

NC
NC
NC
NC

J2
L2
J10
L10

ZQ/ZQ0

DQSL
DQSU

1U_0402_6.3V4Z

A1
A11
T1
T11

B2
B10
D2
D9
E3
E9
F10
G2
G10

RESET

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

L9

DML
DMU

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DRAM_RST# T3

DQSL
DQSU

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

ZQ/ZQ0

R992
240_0402_1%

RESET

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J2
L2
J10
L10

DQSL
DQSU

DML
DMU

C1227

L9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T3

<25> DRAM_RST#

DML
DMU

1U_0402_6.3V4Z

1U_0402_6.3V4Z

QSA#[7..0]

C1226

<25>

<25>
<25>
<25>
<25>
<25>

CLKA0
CLKA0#
CKEA0

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

<25>

<25>
<25>
<25>

DQMA#[7..0]

<25> DQMA#[7..0]

A_BA0
A_BA1
A_BA2

VREFCA
VREFDQ

U12

<25>

<25>
<25>
<25>

M9
H2

U11

Compal Electronics, Inc.

M92-S VRAM

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Sheet

Monday, November 09, 2009

1

29

of

55

HDD Connector
JP3

SATA_RXN0 C466 2
SATA_RXP0 C467 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_RXN0_C
SATA_RXP0_C

SATA_RXN0_C <11>
SATA_RXP0_C <11>

+3VS

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

PA@
D10

+3VS

PA@
1

R364
2 0_0603_5%

PA@

SMB_CLK_S3
U15 PA@

VDDIO absolute man

rating is VDD+0.1
1
PA@

R366
0_0402_5%
2

GND

Reserved

CD-ROM Connector

5
6

+3VS_ACL

Vdd_IO

SMB_CLK_S3 <12,17,18,19>

0011101b

14

SCL / SPC

C465
0.1U_0402_16V4Z

C464
0.1U_0402_16V4Z

C463
0.1U_0402_16V4Z

C462
10U_0805_10V4Z

+5VS

+3VS_ACL_IO

SDA / SDI / SDO

13

SDO

12

Reserved

11

GND

GND

GND

INT 2

Vdd

INT 1

SMB_DATA_S3

SMB_DATA_S3 <12,17,18,19>

R367 PA@
0_0402_5%
2

10
9
8

ACCEL_INT

<14>

CS

JP5

SATA_TXP1
SATA_TXN1

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_TXP1 <11>
SATA_TXN1 <11>

SATA_RXN1_C
SATA_RXP1_C

PA@

SATA_RXN1_C <11>
SATA_RXP1_C <11>
+5VS

Near CONN side.

6
5
4
3
2
1

+5VS

2
SUYIN_127382FR013GX09ZR
CONN@

R368 2

Must be placed in the center of the system.

Placea caps. near ODD CONN.

1
10K_0402_5%

OPP@ C478
10U_0805_10V4Z

OPP@
C473 2
C474 2
OPP@

OPP@ C477
10U_0805_10V4Z

SATA_RXN1
SATA_RXP1

OPP@ C476
1U_0603_10V4Z

DP
V5
V5
MD
GND
GND

HP302DLTR8_ LGA_14P

13
12
11
10
9
8
7

OPP@ C475
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

+3VS_ACL_IO

RB751V_SOD323

Pleace near HDD CONN (JHDD)

+5VS

SUYIN_127072FR022G523_RV
CONN@

+3VS_ACL

PA@

Near CONN side.

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

+3VS_ACL

ACCELEROMETER (ST)

SATA_TXP0 <11>
SATA_TXN0 <11>

C469
10U_0805_6.3V6M

SATA_TXP0
SATA_TXN0

C468
0.1U_0402_16V4Z

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

Multi Bay
+5VS

GND
G1

17
19

SATA_TXP5
SATA_TXN5

SATA_TXP5 <11>
SATA_TXN5 <11>

SATA_RXN5 C1278 2
SATA_RXN5_C
1
SATA_RXP5 C1279 2
SATA_RXP5_C
1
PA@
PA@
0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_RXN5_C <11>
SATA_RXP5_C <11>

PA@ 1
C1281

PA@ 1
C1282

PA@ 1
C1283

PA@ 1
C1284

1
PA@
C1280 +
2

1
@
C1441 +
2

220U_D2_4VM_R15

GND
G2

1
3
5
7
9
11
13
15

150U_B_6.3VM_R40M

GND
TX+
TXGND
RXRX+
GND
GND

10U_0805_10V4Z

18
20

VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND

10U_0805_10V4Z

2
4
6
8
10
12
14
16

1U_0603_10V4Z

JP12

0.1U_0402_16V4Z

Placea caps. near Multi Bay

CONN.

+5VS

CONN@
TYCO_2023087-3
A

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HDD & CDROM

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Rev
1.0

Monday, November 09, 2009

Sheet
1

30

of

55

Mini Card 0--TV

tuner/WWAN/Robson

Mini Card 2---WLAN

SIM card Connector

+3VALW

RW26 1

+1.5VS

+3VS_WWAN

0_0805_5%

+3VS_WLAN

+1.5VS_WWAN

+3VALW

+1.5VS_WLAN

0.1U_0402_16V4Z

0.01U_0402_16V7K 4.7U_0805_10V4Z

CW8

CW9

JP4

+1.5VS_WWAN

CW10

2
2

0.1U_0402_16V4Z

CW12

1
2
3
4
5
6
7

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

0.01U_0402_16V7K
1

CW13

2
0.1U_0402_16V4Z

+3VS_WWAN

0.01U_0402_16V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 @
CW7

1
2
3
4
5
6
7

CW2

2
4.7U_0805_10V4Z

8
9

G1
G2

CW3

1 @
CW1

4.7U_0805_10V4Z
1

CW4

CW5

+1.5VS

RW1 1

0_0805_5%

+1.5VS_WLAN

+3VS

RW2 1

0_0805_5%

+3VS_WLAN

CW6

2
2

0.1U_0402_16V4Z

ACES_88266-07001
CONN@

JP6

+1.5VS_WWAN

54

FOX_AS0B226-S40N-7F
CONN@

+3VS_WWAN

+3VALW

53

GND1

GND2

54

USB20_N5 <14>
USB20_P5 <14>
WL_LED# <40>

XMIT_OFF

DW2
1

Reserve for RF
+1.5VS_WLAN

+3VS_WLAN

FOX_AS0B226-S40N-7F
CONN@

<14>

RB751V_SOD323
XMIT_OFF#
2

UIM_CLK

@ RW23
1
2
0_1206_5%

QW1
SI2305ADS-T1-GE3_SOT23-3

EC_UTX
EC_URX

2 33_0402_5%

+3VALW
+3VS_WLAN
+1.5VS_WLAN

SMBCLK
SMBDATA

+3VS

<14> WXMIT_OFF#

<39>
<39>

RW25 1
EC_URX

@ RW19
1
2 UIM_DATA
47K_0402_5%

UIM_PWR

RB751V_SOD323
M_WXMIT_OFF#
2

+3VS_WWAN
@ RW22
1
2
0_0603_5%
DW1
1

+3VS_WLAN

2 0_0805_5%
2 0_0805_5%

LPC_FRAME# <11,39>
LPC_AD3 <11,39>
LPC_AD2 <11,39>
LPC_AD1 <11,39>
LPC_AD0 <11,39>

C1425

Reserve for RF

XMIT_OFF#
PLT_RST#
@RW13
@
RW13 1
RW15 1

0_0402_5% DEBUG@
0_0402_5% DEBUG@
0_0402_5% DEBUG@
0_0402_5% DEBUG@
0_0402_5% DEBUG@

47P_0402_50V8J

WW_LED# <40>

PCIE_TXN2
PCIE_TXP2

<12> PCIE_TXN2
<12> PCIE_TXP2

USB20_N8 <14>
USB20_P8 <14>

PCIE_C_RXN2
PCIE_C_RXP2

+1.5VS_WLAN
1
2
1
2
1
2
1
2
1
2

39P_0402_50V8J

GND2

<12> PCIE_RXN2
<12> PCIE_RXP2

2 0_0402_5%
2 0_0402_5%

+3VS_WLAN
RW3
RW4
RW5
RW6
RW7

39P_0402_50V8J
C1424

GND1

SMBCLK
SMBDATA

RW12 1
RW14 1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

39P_0402_50V8J
C1423

53

PLT_RST#
<14> CLK_DEBUG_PORT_1

2 0_0805_5%
+3VALW
2 0_0805_5%
+3VS_WWAN
+1.5VS_WWAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C1421

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

47P_0402_50V8J
C1422

WWAN_DETECT#
RW16 1
2 0_0603_5%
1
2
RW17
0_0603_5%

<12> CLKREQ_WLAN#

47P_0402_50V8J

<14> WWAN_DETECT#
+3VS_WWAN

PCIE_TXN1
PCIE_TXP1

M_WXMIT_OFF#
PLT_RST#
@RW9
@
RW9 1
RW11 1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

CLKREQ_WLAN#

<12> CLK_PCIE_WLAN#
<12> CLK_PCIE_WLAN

C1420

<12> PCIE_TXN1
<12> PCIE_TXP1

0_0402_5%
2 PCIE_C_RXN1
2 PCIE_C_RXP1
0_0402_5%

ICH_PCIE_WAKE#
+1.5VS_WWAN
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

39P_0402_50V8J

RW8 1
1
RW10

JP7

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

39P_0402_50V8J
C1419

<12> PCIE_RXN1
<12> PCIE_RXP1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

39P_0402_50V8J
C1418

CLK_PCIE_WWAN#
CLK_PCIE_WWAN

<12> CLK_PCIE_WWAN#
<12> CLK_PCIE_WWAN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

47P_0402_50V8J
C1417

<12> CLKREQ_WWAN#

CLKREQ_WWAN#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

C1416

ICH_PCIE_WAKE#

CW11 @
18P_0402_50V8J

<39> WWAN_POWER_OFF

Express Card Power

Switch

+1.5VS
PA@ C1285
1
2 0.1U_0402_16V4Z
+3VS
PA@
C1288 1

+3VALW

C1289 1
PA@

2 0.1U_0402_16V4Z
17
6

SYSON

<39,40,41,45> SYSON

20

SUSP#

SUSP#

@ R1063 1

+3VALW
<14> EXP_CPPE#

2
4

PLT_RST#

<14,24,32> PLT_RST#

<34,39,41,43,46,47,48,51>

2 0.1U_0402_16V4Z

PA@
R1242

2 100K_0402_5%
2

10

EXP_CPPE#_R

0_0402_5%

18

1.5Vin
1.5Vin

1.5Vout
1.5Vout

3.3Vin
3.3Vin

3.3Vout
3.3Vout

AUX_IN
SYSRST#
SHDN#

AUX_OUT
OC#
PERST#

STBY#

NC

CPPE#

GND

PA@
R1060
R1061
PA@

<14> USB20_N9
<14> USB20_P9

U53 PA@
12
14

Near to Express Card slot.

Close to
JEXP

New Card

11
13

+1.5VS_PEC

3
5

+3VS_PEC

15

+3V_PEC

2 0_0402_5%
2 0_0402_5%

USB9USB9+
EXP_CPPE#
SMBCLK
SMBDATA

<12> SMBCLK
<12> SMBDATA
PA@
<13,32> ICH_PCIE_WAKE#

R1062
1
2
0_0402_5%

19
8

1
1

+3VS_PEC

+1.5VS_PEC
+1.5VS_PEC
+3V_PEC

PCIE_PME#_R
PERST#

+3VS_PEC
PERST#

CLKREQ_EXP#
EXP_CPPE#

<12> CLKREQ_EXP#

16

<12> CLK_PCIE_EXP#
<12> CLK_PCIE_EXP

<12> PCIE_RXN4
<12> PCIE_RXP4

CPUSB#

<12> PCIE_TXN4
<12> PCIE_TXP4

RCLKEN

CLK_PCIE_EXP#
CLK_PCIE_EXP
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

G577NSR91U

internal pull high to 3.3Vaux-in

EC need setting at Hi-Z & output Low

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

27
28

GND
GND

PA@
C1286
0.1U_0402_16V4Z

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

PA@
C1287
4.7U_0805_10V4Z

+1.5VS_PEC

PA@
C1290
0.1U_0402_16V4Z

PA@
C1291
4.7U_0805_10V4Z

+3V_PEC

GND
GND

Compal Secret Data

2007/08/28

Issued Date

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

PA@
C1292
0.1U_0402_16V4Z

29
30

SANTA_130801-5_LT
CONN@

Security Classification

JEXP1

Title

1 PA@
C1293
4.7U_0805_10V4Z

Compal Electronics, Inc.

WLAN, WWAN, New Card

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
E

31

of

55

LAN_DI
OPP@
U14
RTL8103EL-VB

LAN_CS

Place Close to Chip

HSOP

<12> PCIE_RXN3

C1296 2

1 0.1U_0402_16V7K

PCIE_PTX_IRX_N3

21

HSON

<12> PCIE_TXP3

15

<12> PCIE_TXN3

16

HSIN

<12> CLK_PCIE_LAN
<12> CLK_PCIE_LAN#

17
18

REFCLK_P
REFCLK_M

<12> CLKREQ_LAN#

25

CLKREQB

27

PLT_RST#
R1069 1

2 2.49K_0402_1%

<13,31> ICH_PCIE_WAKE#

RSET
LANWAKEB
ISOLATEB

LAN_X1
LAN_X2

41
42

CKXTAL1
CKXTAL2

R1071
0_0402_5%

38

MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC

2
3
5
6
8
9
11
12

RTL8111DL-VB

PERSTB

26
28

+3V_LAN

LED0

RTL8102EL

46

23
24

LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS

33
34
35
32

HSIP

ISOLATEB

+3VS

LAN_ACTIVITY#

2
1

LANLED_ACT#

R1067
300_0402_5%

NC

NC
NC

7
14
31
47

GND
GND
GND
GND

22

GNDTX

LAN_DI
LAN_SK_LAN_LINK#
LAN_CS

C1297
0.1U_0402_16V4Z

48

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

19
30
36
13
10

NC

39

NC
VCTRL12D

44
45

VDD33
VDD33

29
37

AVDD33
NC
NC

1
40
43

LAN_SK_LAN_LINK#

VCTRL12A

Yellow LED+

10

Yellow LED-

RJ45_MIDI3-

PR4-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

RJ45_MIDI2-

PR3-

RJ45_MIDI2+

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

LAN_ACTIVITY#
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

16

DETEC PIN1

13

+3VLAN

11

Green LED+

LANLED_LINK#

12

Green LED-

DETEC PIN2

14

SHLD1

15

TYCO_2041671-1
CONN@

R1068
300_0402_5%

+LAN_VDD12

06/19 Update RJ45 connector library

SHLD1

VCTRL12

LANGND
1

+EVDD12
+LAN_VDD12

C1298

C1299

LANLED_ACT#
2

LANLED_LINK#

0.1U_0402_16V4Z

4.7U_0805_10V4Z

20

ISOLATEB

1 1K_0402_5%

PCIE_PTX_IRX_P3

R1070
1K_0402_1%

JRJ45
+3VLAN

1 0.1U_0402_16V7K

LAN Conn.
+3V_LAN

U14

C1295 2

<14,24,31>

R1066
2
8103EL@

+LAN_CTRL12VDD
@ D43
PACDN042_SOT23~D

Close to Pin45,44
+3V_LAN
1

2 3.6K_0402_5%

C1294
0.1U_0402_16V4Z

PCIE_RXP3

<12>

R1065

CTRL15/VDD33

CTRL15/VDD33

RTL8111DL-VB-GR LQFP 48P

R1072
15K_0402_5%

PA@

@ R1073
0_0402_5%

Y4

LAN_X1

U56 8103EL@
LAN_X2

LAN_MDI0+
LAN_MDI0LAN_CT0

25MHz_20pF_6X25000017
C1305
27P_0402_50V8J

1
2
3
4
5
6
7
8

C1306
27P_0402_50V8J
LAN_CT1
LAN_MDI1+
LAN_MDI1-

RD+
RDCT
NC
NC
CT
TD+
TD-

RX+
RXCT
NC
NC
CT
TX+
TX-

RJ45_MIDI0+
RJ45_MIDI0RJ45_CT0

16
15
14
13
12
11
10
9

RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-

NS681680 LAN

Close to Pin40 for 8111DL

Close to Pin39 for 8111DL

U17 8111DL@
+3V_LAN

2 0.01U_0402_50V7K

1
2
+3V_LAN
R1198 0_0603_5%
8103EL@
+LAN_CTRL12VDD
1
2
LL1
0_0603_5%
1
1
8111DL@
C1300
C1301
0.1U_0402_16V4Z
22U_0805_6.3V6M
2
2 8111DL@

C1313
0.1U_0402_16V4Z

C1312
0.1U_0402_16V4Z

C1427
1
8111DL@

2 0.01U_0402_50V7K

C1428
1
8111DL@

2 0.01U_0402_50V7K

LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

24
23
22
21
20
19
18
17
16
15
14
13

RJ45_CT0 2
C1303
RJ45_CT1 2
C1304
2
C1307
8111DL@
2
C1308
8111DL@

1 1000P_0402_50V7K
RJ45_MIDI0+
RJ45_MIDI01 1000P_0402_50V7K
RJ45_MIDI1+
RJ45_MIDI11 1000P_0402_50V7K
RJ45_MIDI2+
RJ45_MIDI21 1000P_0402_50V7K
RJ45_MIDI3+
RJ45_MIDI3-

R1074 1
2
<36>
<36>
R1075 1
2
<36>
<36>
R1076 1
2
8111DL@
<36>
<36>
R1077 1
2
8111DL@
<36>
<36>

RJ45_MIDI0+
RJ45_MIDI0RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI3+
RJ45_MIDI3-

75_0402_1%
75_0402_1%
75_0402_1%
B

75_0402_1%

NS692405

0303 change to 0805 size by vender's recommand

8103EL@
2
0_0603_5%

C1309
1000P_1808_3KV7K

1.For Giga LAN (RTL8111DL):

Mail source: LANKom: LG-2446S-1 (P/N: SP050005L00)
2nd Source: MHPC: NS892406 (P/N: SP050005900)

@ R1078 1

+3VALW

R1082
0_0603_5%
8111DL@

2 0_0805_5%

80 mils
3
+LAN_VDD12

9/11 Add R1259 for OPP SKU

PA@
<39> LAN_POWER_OFF

R1083
47K_0402_5%
1
2

+3VLAN

R1079

2 0_0805_5%

+3V_LAN

For DIS 8111DL used

+EVDD12

C1321
0.1U_0402_16V4Z

8111DL@

R1197
100K_0402_5%

Note 1: The Trace length

between L1 and 8111DL's Pin
1 must be within 0.5 cm. C262
and C263 to L1 must be within
0.5cm. Refer to Layout guide
for more detail.

C1320
22U_0805_6.3V6M

1
2
0_0603_5%
1

R1081
100K_0402_5%
1
2

L63 1
2
4.7UH_1008HC-472EJFS-A_5%_1008
8111DL@

C1323
1U_0402_6.3V4Z

1
2
3
4
5
6
7
8
9
10
11
12

C1322
1U_0402_6.3V4Z

C1426

LAN_CT0
LAN_MDI0+
LAN_MDI0LAN_CT1
LAN_MDI1+
LAN_MDI1-

R1080
VCTRL12

2 0.01U_0402_50V7K

Q87
SI2301BDS-T1-E3_SOT23-3
2

1
R1199

+EVDD12

Close to Pin48

Close to Pin19

C1311
0.1U_0402_16V4Z

C1310
0.1U_0402_16V4Z

C1318
0.1U_0402_16V4Z

C1317
0.1U_0402_16V4Z

C1316
0.1U_0402_16V4Z

C1315
0.1U_0402_16V4Z

C1314
0.1U_0402_16V4Z

+LAN_VDD12

C1302

Close to Pin 44,45

RJ45_GND

Close to Pin1,37,29,40

+LAN_VDD12

PA@ C1319
1U_0402_6.3V4Z

Close to Pin10,13,30,36

1
2
OPP@ R1259
0_0402_5%

C1429
0.1U_0402_16V4Z

2009. 08.06 Add R1083 and C1319 to solve the 8111 VB power on issue
Compal Secret Data

Security Classification
Issued Date

2007/08/28

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

USB CardReader&CONN

Size Document Number

Custom
Date:

Rev
1.0

Calpella DIS LA-4107P

Monday, November 09, 2009

Sheet
1

32

of

55

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14

RTS5138 ==>For DIS

D

+3VS

+3VS_CR

C1324

R1085

2 0_0805_5%

1 100P_0402_50V8J
RREF

XD_CD#

REFE

2
3

DM
DP

4
5
6

3V3_IN
CARD_3V3
V18

XD_CD#

XDDRY_SDWP_MSCLK 8
XDRE#_MSINS#
9
XDCE#_SDD1
10
XDCLE_SDD0
11
XDALE_SDD7_MSD3
12

SP1
SP2
SP3
SP4
SP5

25

+3VS_CR
+VCC_4IN1
VREG
C1327
1U_0402_6.3V6K

C1326
0.1U_0402_16V4Z

C1325
4.7U_0805_10V4Z

<14> USB20_N10
<14> USB20_P10

SD_WP

MS_CLK
MS_INS#

SD_D1
SD_D0
SD_D7
SD_CD#
SD_D6
SD_CLK
SD_D5
SD_CMD
SD_D4
SD_D3
SD_D2

MS_D7
MS_D3
D

MS_D6
MS_D2
MS_D0
MS_D4
MS_D1
MS_D5
MS_BS

U54

2 6.2K_0603_1%

EPAD

R1084

XD_CD#
XD_RDY
XD_RE#
XD_CE#
XD_CLE
XD_ALE
XD_WE#
XD_WP
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

CR_LED#

GPIO0

17

CLK_IN

24

XD_D7

23

XD_D7

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

XDD6_MSBS
XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1
XDD3_SDD4_MSD4
XDD2_SDCMD
XDD1_SDD5_MSD0
XDD0_SDCLK_MSD2
XDWP#_SDD6
XDWE#_SDCD#

CLK_48M_CR

<12>

RTS5138-GR_QFN24_4X4

Card Reader Connector

JREAD1
XDD0_SDCLK_MSD2
XDD1_SDD5_MSD0
XDD2_SDCMD
XDD3_SDD4_MSD4
XDD4_SDD3_MSD1
XDD5_SDD2_MS_D5
XDD6_MSBS
XD_D7

32
10
9
8
7
6
5
4

XDWE#_SDCD#
34
XDWP#_SDD6
33
XDALE_SDD7_MSD3 35
XD_CD#
40
XDDRY_SDWP_MSCLK39
XDRE#_MSINS#
38
XDCE#_SDD1
37
XDCLE_SDD0
36

11
31

41
42

XD-VCC
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

7 IN 1 CONN

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
7IN1 GND
7IN1 GND

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

XDD0_SDCLK_MSD2
XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1
XDD3_SDD4_MSD4
XDD1_SDD5_MSD0
XDWP#_SDD6
XDALE_SDD7_MSD3
XDD2_SDCMD
XDWE#_SDCD#

SD-WP-SW

XDDRY_SDWP_MSCLK

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

XDDRY_SDWP_MSCLK
XDD1_SDD5_MSD0
XDD4_SDD3_MSD1
XDD0_SDCLK_MSD2
XDALE_SDD7_MSD3
XDRE#_MSINS#
XDD6_MSBS

+VCC_4IN1
C1328
10U_0805_6.3V6M

+VCC_4IN1

7IN1 GND
7IN1 GND
TAITW_R015-B10-LM
CONN@

White
D44
+5VS

R1086 1

2 1.2K_0402_5%

CR_LED#

HT-F196BP5_WHITE

Compal Secret Data

Security Classification
Issued Date

2007/08/28

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

USB CardReader&CONN

Size Document Number

Custom
Date:

Rev
1.0

Calpella DIS LA-4107P

Monday, November 09, 2009

Sheet
1

33

of

55

HDA_RST#

2 100_0402_1%
2 0_0603_5%

R910 1

<36> SPDIF_OUT

2 0_0402_5%

46

SPDIF_OUT

48

R908 1

2 10K_0402_5% 47

+3VS

HP_OUT_L
HP_OUT_R

PORT_C_L
PORT_C_R
VREFOUT_C

19
20
24

MIC_INL
OPP@ C559 1
MIC_INR
OPP@ C560 1
+VREFOUT_INTMIC

DMIC_CLK/GPIO1
DMIC0/GPIO2

SPKR_PORT_D_L+
SPKR_PORT_D_L-

40
41

SPKL+
SPKL-

SPKR_PORT_D_RSPKR_PORT_D_R+

43
44

SPKRSPKR+

15
16

DOCK_MICL
DOCK_MICR

DMIC1/GPIO0/SPDIF_OUT_1
SPDIF_OUT_0
EAPD

PORT_E_L
PORT_E_R

EC_MUTE#

<35,39> EC_MUTE#

35

2
C1069
4.7U_0603_6.3V6M

36

+3VS

+3VS

R1247
4.7K_0402_5%

2
4

DVSS

33
30
26

AVSS
AVSS
AVSS

12
25

CAP2

22

VREFFILT

21

PVSS

V-

DAP

VREG

49

PC_BEEP

92HD80B1X5NLGXYD38 QFN48P

SA00003G700

C1442
100P_0402_50V8J

92HD80

1
C1443
0.01U_0402_16V7K

C1451

2
0.1U_0402_16V4Z

2009.08.18 Add R1247,C1442,C1443 for ESD

<31,39,41,43,46,47,48,51>

OUT

SUSP#

BYP

37

1
2
MIC_IN_L <35>
MIC_IN_R <35>

Int MIC

SPKL+
SPKL-

<35>
<35>

SPKRSPKR+

<35>
<35>

Internal SPKR

2 10K_0402_5%
2 10K_0402_5%
MIC_EXT_L <35>
MIC_EXT_R <35>

1
4

PA@
R1097
1.21K_0402_1%

C1068
10U_0805_10V4Z

MONO_IN

C1453

R447 2

1 47K_0402_5%

C1070 1

9/11 Delete EC_BEEP

2
G

Q38
2N7002_SOT23-3 S

SB_SPKR

SB_SPKR <11>

1
2
@ C1338
10P_0402_25V8K

@
C1337

4.7U_0805_10V4Z

HDA_BITCLK_MDC <11>

C1336

+3VS

2 0.1U_0402_16V4Z

C983 1

2 0.1U_0402_16V4Z

C984 1

2 0.1U_0402_16V4Z

C985 1

2 0.1U_0402_16V4Z

C986 1

2 0.1U_0402_16V4Z

C1444 1

2 0.1U_0402_16V4Z

C1445 1

2 0.1U_0402_16V4Z

C1446 1

2 0.1U_0402_16V4Z

@ C1447 1

2 0.1U_0402_16V4Z

@ C1448 1

2 0.1U_0402_16V4Z

+1.5VS
0.1U_0402_16V4Z

2
0_0603_5%
2
0_0603_5%

+3VS

2
@ R1101
10_0402_5%

Digital MIC

2009.08.18 Add 0.1u for ESD

C1335

2
4
6
8
10
12

GND
GND
GND
GND
GND
GND

H14
HOLEA

R139 1

GNDA

<35,36>

2 0_0603_5%

GND

ACES_88018-124G

13
14
15
16
17
18

H12
HOLEA

1
R1100

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

EXT. MIC

DM0

1000P_0402_50V7K

<11> HDA_SYNC_MDC
<11> HDA_SDIN1
<11> HDA_RST#_MDC

HDA_SYNC_MDC
2 HDA_SDIN1_MDC
33_0402_5%

1
3
5
7
9
11

DOCK MIC

Port F

R909
10K_0402_5%

+3VS

HDA_SDOUT_MDC

SPKR

Port E

+AVDD_CODEC

1/10*Vin
need close to
Codec

MDC 1.5 Conn.

<11> HDA_SDOUT_MDC

INT. MIC

Port D

2009.11.03 Reserve LDO for AVDD power

@ 1
R1098
1
R1099

HP

Port C

Ext MIC

2 0.1U_0402_16V4Z

JP8

Port B

DOCK_MIC_L <36>
DOCK_MIC_R <36>

+VDDA_CODEC

@ R1269
0_0402_5%

G9191-475T1U_SOT23-5

HP Jack

1.21K_0402_1%

GND
SHDN

HP_OUT_L <35>
HP_OUT_R <35>

PA@
R1096

C1452

92HD80 port define

Port A
DOCK HP

Dock HP Jack

DOCK_MICR_C

IN

+AVDD_CODEC
EXTMIC_DET# <35>
SENSE_B# <36>

DOCK_MICL_C

34

U60
1

DOCK_LOUT_C_L <36>
DOCK_LOUT_C_R <36>

MIC_IN_L
MIC_IN_R

1 MONO_IN
0.1U_0402_16V4Z

2
C561

2.2U_0805_16V4Z

+5VALW

W=40Mil

MONO_INR

HDA_RST#_CODEC

2 2.2U_0603_6.3V4Z
2 2.2U_0603_6.3V4Z

PA@1U_0603_10V6K
DOCK_MICL_C
C1333 1
PA@ R1094 1
2
DOCK_MICR_C
C1334 1
PA@ R1095 1
2
PA@1U_0603_10V6K
MIC_EXTL
MIC_EXT_L
C557 1
2 2.2U_0603_6.3V4Z
MIC_EXTR
MIC_EXT_R
C558 1
2 2.2U_0603_6.3V4Z

17
18

MONO_OUT

CAP+

42

PORT_F_L
PORT_F_R

CAP-

150U_Y_6.3VM
31
32

HP1_PORT_B_L
HP1_PORT_B_R

150U_Y_6.3VM
1
2
1
2

1
1
1
1

11

SENSE_A
SENSE_B

HDA_SYNC

HDA_RST#_CODEC

PA@ C1331
PA@ C1332

+AVDD_CODEC
JACK_DET# <36>
HP_DET# <35>
INTMIC_DET# <35>

10

PA@ R679 1
PA@ R446 1

<39> EAPD_CODEC

HDA_SYNC_CODEC

DOCK_LOUT_L
DOCK_LOUT_R

28
29
23

R435
4.7K_0402_5%

<11,39> HDA_RST#_CODEC

HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_or_F

HDA_SDO

SENSE_A
SENSE_B

HDA_SDI

HDA_BITCLK

39
45
13
14

1U_0603_10V4Z

MIC_EXT_L

2 2.49K_0402_1%
2 39.2K_0402_1% JACK_DET#
2 20K_0402_1% HP_DET#
2 10K_0402_1% INTMIC_DET#
2 1000P_0402_50V7K
2 2.49K_0402_1%
2 20K_0402_1% EXTMIC_DET#
2 39.2K_0402_1% SENSE_B#
2 1000P_0402_50V7K

1
1
1
1

R444
1
2 HDA_SDIN0_CODEC
33_0402_5%
HDA_SDOUT_CODEC

SENSE_A
SENSE_B

R1087
PA@R1092
PA@
R1092
R1089
R1090
C1329
R1091
R1088
PA@R1093
PA@
R1093
C1330

R449
10K_0402_5%

HDA_BITCLK_CODEC

<11> HDA_SYNC_CODEC

<21> DMIC_CLK
<21> DMIC_DAT

PVDD
PVDD

+ +

<11> HDA_SDOUT_CODEC

DVDD_IO

27
38

<11> HDA_SDIN0

AVDD
AVDD

<11> HDA_BITCLK_CODEC

DVDD

R1105 OPP@
4.7K_0402_5%

C546 1

9/11 Use +AVDD_CODEC for EXT. MIC reference voltage

C1067
1U_0402_6.3V6K

@R441
@
R441
2
1
47_0402_5%

DVDD_CORE

2
1
1K_0402_5%
R434
4.7K_0402_5%
MIC_EXT_R

PVDD

C562
0.1U_0402_16V4Z

1 10U_0805_10V4Z
1

MIC_IN_L

+AVDD_CODEC
R1260

OPP@ R1200
0_0402_5%

R904 2
1
0_0805_5%

C1066
0.1U_0402_16V4Z

C564
1U_0603_10V6K

C1065

1
0_0805_5%

C1450
4.7U_0603_6.3V6M

U22

C1064
1U_0402_6.3V6K

@ C554
2
1
33P_0402_50V8K

C1063
0.1U_0402_16V4Z

C563
10U_0805_10V4Z
1
2

C1072
10U_0805_10V4Z

2 0_0603_5%

+5VS
R1268 2

OPP@ R1104
4.7K_0402_5%
MIC_IN_R

1 0_0805_5%

+AVDD_CODEC

C1071
4.7U_0603_6.3V6M

R907 1

C551
0.1U_0402_16V4Z

+3VS_HDA

C976
0.1U_0402_16V4Z

+3VS

@ R1267 2

+3VS_DVDD

R437
BLM18BD601SN1D_0603
2
1

C553
1U_0402_6.3V6K

+3VS

1U_0603_10V4Z

+VDDA_CODEC

OPP@ C1339 1

@ R431 1K_0402_5%
+VREFOUT_INTMIC 2
1

OPP@ R1102
+VREFOUT_INTMIC 2
1
0_0402_5%

GNDA
4

Connector for MDC Rev1.5

MDC Standoff

CONN@

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Codec_IDT92HD80
Size Document Number
Custom
Date:

Rev
1.0

Calpella DIS LA-4107P

Monday, November 09, 2009

Sheet
E

34

of

55

SPEAKER
+AVDD_CODEC
JP60

2
1

CONN@

+3VS

9/11 Delete ANA_MIC_DET

2
OPP@ R1106

1
10K_0402_5%

2N7002DW-7-F_SOT363-6
1
6

D15
PSOT24C_SOT23-3

D16
PSOT24C_SOT23-3
MIC_IN_L
1

MIC_IN_R
3

5
6

Q88B

GND1
GND2

OPP@
D62
PACDN042_SOT23-3~D

OPP@ D58
PACDN042_SOT23-3~D

@
Q88A

1
2
3
4

ACES_88231-04001
CONN@

<34> INTMIC_DET#

1
2
3
4

MIC_IN_L
MIC_IN_R

<34>
<34>

JP51

E&T_3806-F04N-02R

4
3
2
1

@
R1103
10K_0402_5%

2
2

4
3
2
1

2N7002DW-7-F_SOT363-6
4
3

1
1

SPK_RSPK_R+
SPK_LSPK_L+

C572
330P_0402_50V7K

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

INTMIC IN

GND2
GND1

2
2
2
2

1
1
1
1

C571
330P_0402_50V7K

R454
R455
R456
R457

SPKRSPKR+
SPKLSPKL+

SPKRSPKR+
SPKLSPKL+

C569
330P_0402_50V7K

<34>
<34>
<34>
<34>

C570
330P_0402_50V7K

6
5

<34> EXTMIC_DET#
<34> HP_DET#

EXTMIC_DET#
HP_DET#
CIR_IN

<36,39> CIR_IN
+5VL
MIC_EXT_R

1
2
3
4
5
6
7
8 G1
9 G2
10
11
12
13
14

15
16

ACES_87213-1400G
CONN@

MIC_EXT_L

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1
5

HP_OUT_R
HP_OUT_L

<34> HP_OUT_R
<34> HP_OUT_L

Q32A
2N7002DW-7-F_SOT363-6

6
2

JP49
MIC_EXT_R
MIC_EXT_L

<34> MIC_EXT_R
<34> MIC_EXT_L

@ D63
PACDN042_SOT23-3~D
1

Q32B
2N7002DW-7-F_SOT363-6

2
1

<34,39> EC_MUTE#

2N7002DW-7-F_SOT363-6
Q39A

R76
10K_0402_5%
@

Audio/B & CIR

HP_OUT_R

+5VALW

Q28B
2N7002DW-7-F_SOT363-6
3
4

Q28A
2N7002DW-7-F_SOT363-6
1
6

HP_OUT_L

HP de pop circuit

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

AMP & Audio Jack

Size Document Number
Custom
Date:

Rev
1.0

Calpella DIS LA-4107P

Monday, November 09, 2009

Sheet
E

35

of

55

Atlas/ Saturn Dock

JDOCK1

<20>
<20>
<20>
<20>
<20>
<20>
<20>
<14>
<14>

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock
off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

PA@

PA@

+3VALW

D45

R1111 1

2 1K_0402_5%

R1112 1

2 1K_0402_5%

2
1

DOCK_PWRON

3
DAN202U_SC70

RJ45_MIDI3RJ45_MIDI3+
RJ45_MIDI2RJ45_MIDI2+
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+

+V_BATTERY

PA@
R1113
10K_0402_5%

CRT_Red
CRT_Green
CRT_Blue
DDC_DATA
DDC_Clock
Hsync
Vsync
USBUSB+
Digital gnd
MDI3MDI3+
MD2IMDI2+
MDI1MDI1+
MDI0MDI0+
Battery out
Battery out

45
46

GND
GND

Digital gnd
TV Luma
TV chroma
TV composite
TV ground
CIR input
PWR_ON
Mute_LED
Sleep Botton
Jack Detect
VOL_up
VOL_down
SPDIF
Audio Output gnd
Right headphone
Left headphone
Mic_Right
Mic_Left
Mic gnd
Dock_present

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

GND
GND
GND
GND

41
42
43
44

PJP903
1

B+

2
G
PA@
Q89
2N7002_SOT23-3

<41,47> SYSON#

PA@

<32>
<32>
<32>
<32>
<32>
<32>
<32>
<32>

RJ45_MIDI3RJ45_MIDI3+
RJ45_MIDI2RJ45_MIDI2+
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+

38
40
34
36
30
32
26
28
22
24
18
20
14
16
10
12
6
8
2
4

2
PAD-OPEN 2x2m

11/07 Delete TVout function from

Docking
VGA_GND
CIR_IN
CIR_IN <35,39>
DOCK_PWRON
D_MUTE_LED
PA@R1107
PA@
R1107 1
2 33_0402_5%
D_DOCK_SLP_BTN#
PA@R1108
PA@
R1108 1
2 33_0402_5%
JACK_DET#
R_VOL_UP#
R1109 1
2 200_0402_5%
R_VOL_DWN#
R1110 1
2 200_0402_5%
SPDIFO_L
PA@
AUDIO_OGND
GNDA PA@
DOCK_LOUT_C_R
DOCK_LOUT_C_R <34>
DOCK_LOUT_C_L
DOCK_LOUT_C_L <34>
DOCK_MIC_R_C
DOCK_MIC_L_C
AUDIO_IGND
GNDA
DOCK_PRESENT @
@R1114
R1114 1
2 2K_0402_5%

MUTE_LED <39>
DOCK_SLP_BTN# <39>
JACK_DET# <34>
DOCK_VOL_UP# <39>
DOCK_VOL_DWN# <39>

+DOCKVIN
+DOCKVIN

CONN@ FOX_QL1122L-H212AR-7F

C1340 1
@

2
1000P_0402_50V7K

C1341 1
@

2
1000P_0402_50V7K

1 PA@

Dock
PRESENT

GNDA

+3VL
2

11/17 Reserve

C1347
220P_0402_50V7K
PA@

C1348
220P_0402_50V7K
2 PA@

1
1
2
B

S
C1349
PA@
1

Q92 PA@
MMBT3904_NL_SOT23-3
R1124
SPDIFO_L

C1350
1

1
1
2
0_0603_5%
C1351
PA@
220P_0402_25V8J
2
PA@

1U_0603_10V6K
PA@

Compal Secret Data

Security Classification
2007/08/28

R1121
2

0.1U_0402_16V7K

Issued Date

GNDA

2009 7/1 Delete Q93, R1120

Q91 PA@
2N7002_SOT23-3

2
G

2
PA@
R1123
47K_0402_5%

C1344
PA@

11/17 Recommend

2
B

DOCK_MIC_L_C

PA@ Q94
MMBT3904_NL_SOT23-3
R1122
1
2
10K_0402_5%

GNDA

SENSE_B# <34>

PA@
R1118
10K_0402_5%
1

2
1

PA@

C1343
2
PA@
C1346
PA@

GNDA GNDA

+3VS

PA@
R1119
10K_0402_5%

0.01U_0402_16V7K

DOCK_MIC_L_C

1
2
L65
FBM-11-160808-601-T_0603

Deciphered Date

2006/03/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1
2
220_0402_5%
PA@

SPDIF_OUT <34>

PA@

C1345
2
PA@

DOCK_LOUT_C_R
DOCK_LOUT_C_L
1

Title

<34> DOCK_MIC_L

L64
FBM-11-160808-601-T_0603
DOCK_MIC_R_C
1
2

1000P_0402_50V7K

R1117
2K_0402_5%
PA@

<34> DOCK_MIC_R

PA@

PA@

PA@
Q90
2N7002_SOT23-3

2
G

22_0402_5%

1
2
1

R_VOL_UP#
R_VOL_DWN#

Need 600 Ohm 500 mA

R1116
DOCK_PRESENT

MIC_Dock

CONA#

1000P_0402_50V7K

R1115
10K_0402_5%

<39>

C1342
1000P_0402_50V7K

0.01U_0402_16V7K

+5VS

RED
GREEN
BLUE
D_DDCDATA
D_DDCCLK
D_HSYNC
D_VSYNC
USB20_N3
USB20_P3

RED
GREEN
BLUE
D_DDCDATA
D_DDCCLK
D_HSYNC
D_VSYNC
USB20_N3
USB20_P3

R1125
110_0402_5%
PA@

Compal Electronics, Inc.

DOCK CONN.

Size Document Number

Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

Rev
1.0
Sheet

36

of

55

+5VALW

Left\ side ESATA/USB combination Connector

Left side USB Power Switch

+USB_VCCC

+USB_VCCC

U55

W=100mils

8
7
6
5

G547F2P81U MSOP 8P
2

1
+
2

JP53

C1355
1000P_0402_50V7K

USB_EN#

OUT
OUT
OUT
OC#

C1354
0.1U_0402_16V4Z

GND
IN
IN
EN#

C1353
150U_B_6.3VM_R40M

C1352
4.7U_0805_10V4Z

1
2
3
4

R479 1
R480 1

<14> USB20_N0
<14> USB20_P0

2 10K_0402_5%

+5VALW

1
2
3
4

USB20_N0_R
USB20_P0_R

PA@
C602 2
1 0.01U_0402_16V7K SATA_RXN4
C603 2
1 0.01U_0402_16V7K SATA_RXP4

USB20_P0

WCM-2012-900T_0805
1 1
2 2

USB20_N0

12
13
14
15

USB20_N0_R

GND
GND
GND
GND
TYCO_1759576-1
CONN@

@ L66

D20
4

+5VALW

Finger printer

USB20_N0_R

D21
IO1

IO2 GND

VIN

GND
A+
ESATA
AGND
BB+
GND

PA@
USB20_P0_R

USB

VBUS
DD+
GND

5
6
7
8
9
10
11

SATA_TXP4
SATA_TXN4

<11> SATA_TXP4
<11> SATA_TXN4
<11> SATA_RXN4_C
<11> SATA_RXP4_C

R1126

2 0_0402_5%
2 0_0402_5%

USB20_P0_R

+5VALW
SATA_TXN4

VIN

IO1

IO2 GND

PJLCR05

SATA_TXP4

PJLCR05

Change Finger printer from USB port7 to USB port 11

PA@

ESD request

+3VS

PA@

PA@R1127
PA@R1127
1
2
0_0603_5%

2
USB20_N11_R
USB20_P11_R
3

PA@ R1129

2 0_0402_5%
2 0_0402_5%

1
1

@ R1130
1
2
0_0402_5%

@ D46
@D46
PACDN042_SOT23-3~D

1
2
3
4
5
6
7
8

JP57

1
2
3
4
5
6
GND
GND

10

GND 8
7
6
5
4
3
2
GND 1

ACES_85201-06051
CONN@

change to New version

Change Bluetooth from USB port 6 to USB port 12

JP24

PA@ R1128
<14> USB20_N11
<14> USB20_P11

BT Connector (SoftBreeze)Need

C1356
0.1U_0402_16V4Z

8
7
6
5
4
3
2
1

USB20_N12_R
USB20_P12_R

R488
R487

2
2

BT_LED <40>
USB20_N12 <14>
USB20_P12 <14>

1 0_0402_5%
1 0_0402_5%
+3VAUX_BT

ACES_87213-0800G
CONN@

D23
4

+5VALW
USB20_N12_R

VIN

USB20_P12_R

IO1

IO2 GND

PRTR5V0U2X_SOT143-4

ESD request

USB cable connector for Right side

11
12

0.1U_0402_16V4Z

@
R493
100K_0402_5%

C606

C605
1U_0603_10V4Z

0_0603_5%

USB20_N1
USB20_P1

+3VS

<14>
<14>

USB_EN#

R491

1
2
3
4
5
6
7
8
9
10

<39> USB_EN#
<14> USB20_N2
<14> USB20_P2

1
2
3
4
5
6
7
8
9
10

+3VAUX_BT

Q20
SI2301BDS-T1-E3_SOT23-3

JP55
+5VALW

0.01U_0402_16V7K

<14>

GND1
GND2

BT_OFF

R494 1

2 10K_0402_5%

C609 1

C607

C608

2
4.7U_0805_10V4Z

2 0.1U_0402_16V4Z

ACES_87213-1000G
CONN@

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

USB, BT, eSATA

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

37

of

55

SPI ROM => 256K (EC code)

+3VL

U25
U25 CONN@
20mils

C610
0.1U_0402_16V4Z

3
7

2
<39>

FSEL#

<39>

SPI_CLK

<39>

FWR#

SPI_FSEL#
2
0_0402_5%
SPI_CLK_R
2
0_0402_5%
SPI_FWR#
2
0_0402_5%

1
R495
1
R496
1
R497

1
6
5

VCC

VSS

MX25L2005CMI-12G SOP 8P

HOLD
S
C
D

SPI_SO 1
R498

FRD#
2
33_0402_5%

FRD#

<39>

WIESON G6179 8P SPI

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH

WIESO_G6179-100000_8P

S IC FL 2M MX25L2005CMI-12G SOP 8P (MXIC)

S IC FL 2M W25X20AVSNIG SOIC 8P (WINBOND)

SA00003GK00

@ R233
SPI_CLK_R 1

SA00003GM00

@ C391
1
2

33_0402_5%

22P_0402_50V8J

SPI ROM on PCH => 4M (ME code + System BIOS)

+3VS
+3VS
1
2 SPI_WP#
3.3K_0402_5%

R659 1

2 SPI_HOLD#
3.3K_0402_5%

+3VS

C773
0.1U_0402_16V4Z

U31 CONN@
8

@ R660
1K_0402_5%
R661
SPI_SB_CS# 1

<11> SPI_SB_CS#

<11>

SPI_WP#

SPI_HOLD#

SPI_CLK_PCH 15_0402_5%

<11> SPI_CLK_PCH
B

SPI_SI

SPI_SI

U31

R658 1

VCC

VSS

32M AT25DF321-SU SOIC 8P

HOLD
S
C
D

R662
Q

SPI_SO_L 1

WIESON G6179 8P SPI

PA/OPP

SPI_SO_R

SPI_SO_R <11>

15_0402_5%

S IC FL 32M AT25DF321-SU SOIC 8P

SA000031Q00

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

BIOS ROM

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

38

of

55

+3VL_EC
+3VS

V AD_BID max

0V

0V

0V

Blade SG

8.2K+/-5%

0.216V

0.250V

0.289V

Bee UMA

18K+/-5%

0.436V

0.503V

0.538V

+3VL

+3VL_EC
R511
1

+EC_AVCC

0.875V

R512 1
R513 1

@ R516
2

2
33_0402_5%

<14> CLK_PCI_EC

U27

1
2
3
4
5
7
8
10

CLK_PCI_EC
PCI_RST#
ECRST#

12
13
37
20
38

2
R518
0_0402_5%

J4

KSI0
KSI1
KSI2
2009.08.17 R526 PU change the
KSI3
connection from +3VL to +3VALW
KSI4
+3VALW
PCI_RST#
KSI5
+3VS
KSI6
KSI7
KSO0
KSO1
R523
KSO2
100K_0402_5%
KSO3
R526
R525
KSO4
10K_0402_5%
10K_0402_5%
KSO5
KSO6
KSO7
KSO8
LID_SW#
TP_BTN#
KSO9
KSO10
KSO11
change to Pin75
KSO12
KSO13
KSO14
KSO15
+3VL_EC
+3VALW
TP_BTN#
<40>
TP_BTN#
CONA#
<36> CONA#
JOPEN

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

1
2

<14> PCI_PME#

R1132 1
OPP@

<40> WL_BLUE_BTN

EC_PME#

2
0_0402_5%

EC_PME#

2
0_0402_5%

EC_PME#

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

<13>
<13>
<14>
<40>

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK_R
ESB_DAT_R
EC_PME#

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#

PCI_RST#

EC_ACIN

<13,26> EC_ACIN
C646
0.1U_0402_16V4Z

WWAN_POWER_OFF
EC_UTX
EC_URX
ON/OFFBTN#
DIM_LED
<41>
DIM_LED
NUM_LED#
2 4.7K_0402_5%<40> NUM_LED#

<31> WWAN_POWER_OFF
<31>
EC_UTX
<31> EC_URX
<40> ON/OFFBTN#
+3VL_EC

R538 1

C647
15P_0402_50V8J
1
2

EMI solution
<36> DOCK_SLP_BTN#

77
78
79
80

AVCC
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

PA@
R595 1
2
0_0402_5%

ON/OFFBTN#

CRY2

Y6
3

PS2 Interface

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

SPI Flash ROM

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

NC

OSC

NC

OSC

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

@
R539
20M_0402_5%

4
1

CRY1

DAC_BRIG <21>
VCTRL
<43>
IREF
<43>
AC_SET
<43>

EC_MUTE#
USB_EN#
I2C_INT#
MUTE_LED
TP_CLK
TP_DATA

97
98
99
109

73
74
89
90
91
92
93
95
121
127

R527
R528
R529

1
1
1

2
2
2

CIR_IN
PCH_TEMP_ALERT#
FSTCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN

124

KB926QFD3_LQFP128_14X14

11/09 don't stuff when use C0

FRD#
FWR#
SPI_CLK
FSEL#

33_0402_5%
33_0402_5%
33_0402_5%

2 10K_0402_5%

FRD#
FWR#
SPI_CLK
FSEL#

<38>
<38>
<38>
<38>

+5VL

CIR_IN
<35,36>
PCH_TEMP_ALERT# <14>
FSTCHG <43>
STD_ADP <43>
CAPS_LED# <40>
BAT_LED# <40>
ON/OFFBTN_LED# <40>
SYSON
<31,40,41,45>
VR_ON
<49>

KSO15

@C618
@
C618 1

2 100P_0402_50V8J

KSO10

@C619
@
C619 1

2 100P_0402_50V8J

KSO11

@C620
@
C620 1

2 100P_0402_50V8J

KSO14

@C621
@
C621 1

2 100P_0402_50V8J

KSO13

@C622
@
C622 1

2 100P_0402_50V8J

KSO12

@C625
@
C625 1

2 100P_0402_50V8J

KSO3

@C626
@
C626 1

2 100P_0402_50V8J

KSO6

@C627
@
C627 1

2 100P_0402_50V8J

KSO8

@C628
@
C628 1

2 100P_0402_50V8J

KSO7

@C629
@
C629 1

2 100P_0402_50V8J

KSO4

@C631
@
C631 1

2 100P_0402_50V8J

KSO2

@C632
@
C632 1

2 100P_0402_50V8J

KSI0

@C633
@
C633 1

2 100P_0402_50V8J

KSO1

@C634
@
C634 1

2 100P_0402_50V8J

KSO5

@C635
@
C635 1

2 100P_0402_50V8J

KSI3

@C636
@
C636 1

2 100P_0402_50V8J

KSI2

@C637
@
C637 1

2 100P_0402_50V8J

KSO0

@C638
@
C638 1

2 100P_0402_50V8J

KSI5

@C639
@
C639 1

2 100P_0402_50V8J

KSI4

@C640
@
C640 1

2 100P_0402_50V8J

KSO9

@C641
@
C641 1

2 100P_0402_50V8J

KSI6

@C642
@
C642 1

2 100P_0402_50V8J

KSI7

@C643
@
C643 1

2 100P_0402_50V8J

KSI1

@C644
@
C644 1

2 100P_0402_50V8J

KSO2

R1219 1

2 47K_0402_5%

KSO1

R1220 1

2 47K_0402_5%

+3VL_EC

1
10K_0402_5%
ENBKL
2
@ R741

EC_RSMRST# <13>
EC_LID_OUT# <12>
EC_ON
<44>
WL_BLUE_LED# <40>
2 22_0402_5%BKOFF#
M_PWROK <13>
TP_LED# <40>

R536 100_0402_5%
1
2
BKOFF#

PM_PWROK <13>
<21>

PV PWROK sequence issue

+3VL_EC

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

+3VL_EC

D24

ADP_ID

14" INT_KBD
CONN.( TYPE "D"
KB)
JP19 CONN@

C648
4.7U_0603_6.3V6K

RB751V_SOD323

R540
10K_0402_5%
D25

NMI_DBG#

+3VL_EC

L27
1
2
0_0603_5%

AC_IN

2 PCI_SERR#

PCI_SERR# <14>

RB751V_SOD323

R541
150K_0402_5%
D26
2

1
10K_0402_5%

SLP_S4#
SLP_S4# <13>
ENBKL
ENBKL
<22>
EAPD_CODEC
EAPD_CODEC <34>
LAN_POWER_OFF_R
SUSP#
SUSP#
<31,34,41,43,46,47,48,51>
PWRBTN_OUT#
PWRBTN_OUT# <13>
NMI_DBG#

ACIN

ACIN

ACES_85201-2405

<43>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

2
100P_0402_50V8J

RB751V_SOD323

C651

@
R545
1

1
@
R544
2

2
1

2
0.1U_0402_16V4Z

+3VS
4.7K_0402_5%

PA@
R1254

EC_RSMRST#
100
101 R535 1
2
EC_ON 0_0402_5%
102
WL_BLUE_LED#
103
PM_PWROK_R
104
BKOFF#_R R1222 1
105
M_PWROK
106
TP_LED#
107
108

1
+3VS
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

+3VL_EC +3VL_EC

L26
0_0603_5%

1
C650

2 4.7K_0402_5%
2 4.7K_0402_5%

AC_LED# <42>

DOCK_VOL_UP# <36>
DOCK_VOL_DWN# <36>

V18R

9/11 Cap. sensor board change to +3VL

LAN_POWER_OFF_R

R519 1
R520 1

2 0_0402_5%

DOCK_VOL_UP#
DOCK_VOL_DWN#

For C
Revision

1
+EC_AVCC

PV check BOM structure

TP_CLK
<40>
TP_DATA <40>
R524

119
120
126
128

110
112
114
115
116
117
118

+3VL_EC

EC DEBUG port

R1169
10K_0402_5%
I2C_INT#

EC_MUTE# <34,35>
USB_EN# <37>
I2C_INT# <40>
MUTE_LED <36>

+3VL_EC

SUS_PWR_DN_ACK <13>

DAC_BRIG
VCTRL
IREF
AC_SET

83
84
85
86
87
88

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0

C649
15P_0402_50V8J

<40> ESB_CLK
<40> ESB_DAT

BATT_TEMP <42>
BATT_OVP <42>
ADP_I
<43>
ADP_ID
<42>

9/11 Pin 76 change to SUS_PWR_DN_ACK

ECAGND

PA@
R1253

BATT_TEMP
BATT_OVP
ADP_I
ADP_ID
Board_ID
SUS_PWR_DN_ACK

R530

32.768KHZ_12.5PF_Q13MC14610002

R543
1
2
0_0402_5%

68
70
71
72

INV_PWM <22>
FAN_PWM <6>
ME_EN
<11>
ACOFF
<43>
0.01U_0402_16V7K
ECAGND
C624
1
2

SPI Device Interface

SM Bus

<32> LAN_POWER_OFF

63
64
65
66
75
76

2 22_0402_5%

+5V_TP

GPIO

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

@ R1204 1
FAN_PWM
ME_EN
ACOFF

21
23
26
27

R534

1
C645
0.1U_0402_16V4Z

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

MISC

9/11 Pin26 change to ME_EN

ATE_TEST <41>

PWM Output

GND
GND
GND
GND
GND

@ R533 1

R532
10K_0402_5%<40,42>
<40,42>
<12>
<12>

@ R531
10K_0402_5%

For EMI

R1265
100K_0402_5%

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

11
24
35
94
113

33K_0402_5%

Board_ID

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

Board ID pin

OPP@ R1264
2

1
1
R1240
PA@
2

Rb

8.2K_0402_5% 100K_0402_5%

R1239
2

Ra

25
26

+3VL_EC

Add R1265 for ATE test jig

R522
8.2K_0402_5%

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

R521
8.2K_0402_5%

1
0.1U_0402_16V4Z

SUSP#

PCI_RST#

<14>
EC_SCI#
<11,34> HDA_RST#_CODEC
1

2
C630
SYSON

<14>

2
47K_0402_5%

R517

2 10K_0402_5%

+3VL 10/26

2
0_0805_5%

2 2.2K_0402_5%
2 2.2K_0402_5%

<14>
GATEA20
<14>
KB_RST#
<11>
SIRQ
<11,31> LPC_FRAME#
<11,31> LPC_AD3
<11,31> LPC_AD2
<11,31> LPC_AD1
<11,31> LPC_AD0

15P_0402_50V8J

DOCK_VOL_DWN# R1224 1

+3VL_EC
SMB_EC_DA1
SMB_EC_CK1

@ C623
1

+3VL_EC

2 10K_0402_5%

0.819V

100P_0402_50V8J
DOCK_VOL_UP# R1223

0.712V

2
2
1000P_0402_50V7K

C617

VCC
VCC
VCC
VCC
VCC
VCC

33K+/-5%

2
2
0.1U_0402_16V4Z

C616

V AD_BID min

BATT_OVP

G1
G2

V AD_BID typ

C615

C612

1000P_0402_50V7K
1

Rb

Blade UMA

C614

0.1U_0402_16V4Z
1

C613

Board ID

Bee DIS

0.1U_0402_16V4Z
1
1

67

100K+/-5%

AGND

Ra

69

3.3V+/-5%

9
22
33
96
111
125

VCC

PA@
R546
R547
PA@

2
1
1

2 0_0402_5%
2 0_0402_5%

C652 @
10P_0402_50V8J
ESB_CLK_R
ESB_DAT_R

Compal Secret Data

Security Classification
Issued Date

2007/08/28

Deciphered Date

2006/07/26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

EC KB926/KB Conn.

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet

39

of

55

System & Caps-Lock LED

Switch function LED(test)

D52

White

Q110A
2

<14,23,41,47,51> DGPU_PWR_EN

Q110B
DGPU_EDIDSEL <20,22>

AMBER

R1140
10K_0402_5%

+5VALW_LED

200_0402_5%

System
Power LED

1
2

5
6

White

QSMF-C16E_AMBER-WHITE
TP_LED#

TP_LED#

<39>

2
G
Q95
S
2N7002_SOT23-3

D60, D61 will light when switch to DIS mode

+3VS

R1141

HT-F196BP5_WHITE

HDD LED

R1139
200_0402_5%
Amber
QSMF-C16E_AMBER-WHITE

AMBER

ON/OFFBTN_LED#

AMBER
White D51
OPP@

TP_BTN# <39>

PR

PA
+5VS_LED D50
PA@

QSMF-C16E_AMBER-WHITE

+5VS_LED

R1134 @
10K_0402_5%

White

R1138
200_0402_5%
2

Amber

White

Amber

<14> HDDHALT_LED#

@
D61
LTST-C191TBKT-5A_BLUE_0603~D

SW1
TJG-533-V-T/R_6P
3
1

R1137
200_0402_5%

On (TP_LED#=L)-> White
Off (TP_LED#=H)-> Amber

White
<11> SATA_LED#

@
D60
HT-F196BP5_WHITE

R1136
200_0402_5%

200_0402_5%

D49
White

Battery
Charge LED

HT-F196BP5_WHITE

+5VALW_LED

2 1

2N7002DW-7-F_SOT363-6
4
3 1

R1135

2 1

6 1

BAT_LED#

D48
<39>

@
R1246
470_0402_5%

2N7002DW-7-F_SOT363-6

White

+5VS_LED

@
R1243
200_0402_5%
1

+5V_TP

TouchPAD ON/OFF LED

Cap lock

+5VS_LED

470_0402_5%

HT-F196BP5_WHITE

R1133
2

<39> CAPS_LED#

TP ON/OFF

T/P Board (Inculde T/P_ON/OFF)

+5VS

White
D47

Change the Cap sensor board power plan to +3VL

R1153
R1154

2 0_0402_5%
2 0_0402_5%

1
1

@
1

C1362
15P_0402_50V8J

C1365
2

33_0402_5%

15P_0402_50V8J

2
2

4.7U_0603_6.3V6K

33_0402_5%

15P_0402_50V8J
1

1
2
3
4
5
6
7
8
9
10
GND
GND

ACES_85201-1005N
CONN@

C1366

<31,39,41,45> SYSON

1
2
3
4

1
2
3
4

TP_CLK
TP_DATA

TP_CLK
TP_DATA

ACES_85201-04051
CONN@

SYSON 2
G

G1
G2

C1359
0.1U_0402_16V4Z

JP23

5
6

I2C_INT#
1

1
1

Q96 @
SI2301BDS-T1-E3_SOT23-3

2
NUM_LED#

@ Q97
2N7002_SOT23-3

@ C1363
100P_0402_50V8J

<39>
<39>

@ C1364
100P_0402_50V8J

Mini card LED

Keyboard backlight
Conn

+3VS

R1156
10K_0402_5%
2

ON/OFF Button Connector

@ R1150
10K_0402_5%

ESB_CLK

@ R1155
2

C1449

Cypress

JP59

+5V_TP

<39> NUM_LED#
<39,42> SMB_EC_DA1
<39> ON/OFFBTN#

33P_0402_50V8K

PA@
SMB_EC_DA1
OPP@

2 0_0603_5%

3
1
2
3
4
5
6
7
8
9
10
11
12

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2
2
2
2

C1358
2

1
1
1
1

C1361
0.1U_0402_16V4Z

R1148
R1149
R1151
R1152

@ R1145
2

C1360
15P_0402_50V8J

OPP@
SMB_EC_CK1 PA@
ESB_CLK
PA@
ESB_DAT
PA@

WL_BLUE_LED#

<39> ON/OFFBTN_LED#
<39,42> SMB_EC_CK1
<39> ESB_CLK
ENE
<39> ESB_DAT
<39>
I2C_INT#

R1144 1
ESB_DAT

2 0_0402_5%
2 0_0402_5%

PA@ R1258
2
1
0_0805_5%

1
1

R1146
R1147

+5V_TP

OPP@
OPP@

+5VALW

R1143
0_0805_5%
OPP@

@ R1142
2
1
0_0805_5%

2009.10.23 Change R1151 to 300 ohm bead and

add C1449 for EMI
<39> WL_BLUE_BTN

D53
PSOT24C_SOT23-3

Capacitor Sensor Conn

T/P Board Conn

+3VL +5VALW_LED

TP_DATA
TP_CLK

9/11 reserve +3VL power for cypress Cap. board

+5VS_LED +3VS

+5VALW_LED

0_0805_5%
G1
G2

5
6

WL_BLUE_LED# <39>

JP9
2

1
2
3
4

1
2
3
4

Q98
2N7002_SOT23-3
G1
G2

5
6

<37>

BT_LED

ACES_85201-04051
CONN@

R1158
100K_0402_5%

2
G

ACES_85201-04051
CONN@

1
2
3
4

@ R1157
1

ON/OFFBTN#
ON/OFFBTN_LED#

+5VS_LED

JP10
1
2
3
4

Change the Lid switch power plan to +3VALW

<31>

WW_LED#

D54
1

RB751V_SOD323
2

1
D55

1
2
3
4

1
2
3
4

G1
G2

5
6

ACES_85201-04051
CONN@

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

WL_BLUE_LED#

2
RB751V_SOD323

JP11

LID_SW#
1

WL_LED#

+3VALW

C1368
0.1U_0402_16V4Z

<39>

C1367
10P_0402_25V8K

Lid Switch
Connector

<31>

Title

Compal Electronics, Inc.

KBD, ON/OFF, SW, CIR

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
E

40

of

55

9/20 change the C676 from 0.1u to 0.022u for power sequence.

2 0.1U_0402_10V6K

2 0.1U_0402_10V6K

C1438

2 0.1U_0402_10V6K

SG@ R1272 0_0402_5%

DGPU_PWR_EN# 1
2
DGPU_PWR_EN#

2
G

SG@
Q18

SUSP

JP303

+1.5VS
1

SG@
C1440

+1.5VSDGPU
2

1
@ R1275

SG@
Q17A

0_0402_5%

R917
470_0402_5%

SG@R1273 0_0402_5%
DGPU_PWR_EN# 1
2
SUSP

@ R1274 0_0402_5%
Q17B
SG@
2N7002DW-7-F_SOT363-6

2N7002_SOT23-3

+1.8VSDGPU
2 0_0603_5%

DGPUPWREN

SG@

1
R594
470_0402_5%

1
2

1
SG@

5A

2N7002DW-7-F_SOT363-6

C1454

SG@

C1074
0.1U_0402_16V4Z

1K_0402_5%

+1.8VS
R1202 1
DIS@

+1.5VSDGPU
FDMC8296_POWER33-8-5
SG@ U50
1
2
5
3

300 mA

SG@

SG@ R1271
750K_0402_5%

R916
DGPU_PWR_EN#

1
SG@

1U_0402_6.3V6K

C1078
1U_0402_6.3V4Z

C1076
10U_0805_10V4Z

+5VSDGPU
2 0_0603_5%

+5VS

C770

R1270
750K_0402_5%

+1.5V to +1.5VS_NV Transfer

B+

1
SG@

R1216
0_0402_5%

9/20 change the C770 from 0.1u to 0.022u for power sequence.

+1.8VSDGPU

SI2301BDS-T1-E3_SOT23-3

+1.5VS

C1437

+1.5V

Q109

SG@

+1.8VS

R1201 1

C1434

+1.8VS to +1.8VSDGPU Transfer

+5VS to +5VSDGPU Transfer

2N7002DW-7-F_SOT363-6

2 0.1U_0402_10V6K

0.1U_0402_25V4K

+1.5V

C1432

SUSP

C677
4700P_0402_25V7K

Q8B

+1.5V to +1.5VS Transfer

C676
0.022U_0402_25V7K

C1081
10U_0805_10V4Z

Q10A
2N7002DW-7-F_SOT363-6

Q10B
2N7002DW-7-F_SOT363-6

01/03 Sparate+5VS
and +3VS power
timing

R584
470_0402_5%
SUSP

C1436
10U_0805_10V4Z

2
RUNON_1.5VS

C1435
0.1U_0402_16V4Z

150K_0402_5%

1
R1251

R918
150K_0402_5%

RUNON

R585
470_0402_5%
SUSP

2
RUNON_3VS

FDMC8296_POWER33-8-5
U58
1
2
5
3

0.022U_0402_25V7K

10U_0805_10V4Z

C669
4

330K_0402_5%

+1.5VS

B+
C674
10U_0805_10V4Z

1
1

R581

+1.5V

SI7326DN-T1-E3_PAK1212-8
U29
1
2
5
3

B+

+1.5V to +1.5VS Transfer

+3VS

C675
330K_0402_5%

R583

+3VALW

10U_0805_10V4Z

B+

+3VALW to +3VS Transfer

C672
10U_0805_10V4Z

SI7326DN-T1-E3_PAK1212-8 +5VS
U28
1
2
5
3

C671
0.1U_0402_16V4Z

+5VALW

C673
0.1U_0402_16V4Z

+5VALW to +5VS Transfer

C1079
0.1U_0402_16V4Z

C1433
10U_0805_10V4Z

PAD-OPEN 4x4m

9/20 change R593 to 22ohm for Intel check list update.

R591

R592

R593

+3VALW

JP304
3

R1203
1
D

2
G
S

<39> DIM_LED

<39> ATE_TEST

1 1

DGPU_PWR_EN#
2

SG@

2
G

6
1

2N7002DW-7-F_SOT363-6
4
3
2

2N7002DW-7-F_SOT363-6

R925

DGPU_PWR_EN# <28>

SG@
Q86
2N7002_SOT23-3

DIM_LED#

100K_0402_5%
2
1

1
5

Compal Secret Data

Security Classification

H19
H20
H11
HOLEC HOLEC HOLEA 1

H18
HOLEA

H17
HOLEA

H16
HOLEA

H15
HOLEA

H10
HOLEA

H9
HOLEA

H8
HOLEA

H7
HOLEA

H6
HOLEA

H5
HOLEA

H13
H4
HOLEC HOLEA

H3
HOLEA

H1
HOLEA

<31,34,39,43,46,47,48,51>
<14,23,40,47,51> DGPU_PWR_EN

SUSP#

+3VS

JP305
3

@ Q101

R1266
1K_0402_5%

Q6B
5

R926
10K_0402_5%

FM1
1

FM2

FM3
1

FM4 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

SI2301BDS-T1-E3_SOT23-3

+5VS_LED

Q6A

SI2301BDS-T1-E3_SOT23-3
Q115

<47>

R1245
1
2
0_0603_5%

100K_0402_5%
SUSP

1 PAD-OPEN 2x2m
C1370
0.1U_0402_16V4Z

+5VS

100K_0402_5%
<36,47> SYSON#

10/28 Add for ATE test jig.

R587

+5VALW

@
Q100
2N7002_SOT23-3

R586

<31,39,40,45> SYSON

+3VS

DIM_LED 2
G

+3VL

DIM_LED#

Q103
2N7002_SOT23-3

9/20 change R590 to 220ohm for Intel check list update.

+3VL

@ R1162
10K_0402_5%

2
3
SUSP

@ Q99

SUSP

SYSON#

Q7B

470_0402_5%
2N7002DW-7-F_SOT363-6

S 2N7002_SOT23-3

2
G

SUSP

Q7A

2
6

22_0402_5%
2N7002DW-7-F_SOT363-6

Q112

2
6
SUSP

470_0402_5%

5
4

SUSP

Q8A

Q9B

470_0402_5%
2N7002DW-7-F_SOT363-6

2
3

2N7002DW-7-F_SOT363-6

6
2
1

SUSP

2N7002DW-7-F_SOT363-6

Q9A

220_0402_5%

470_0402_5%

SI2301BDS-T1-E3_SOT23-3

470_0402_5%

+5VALW_LED
R1244
1
2
0_0603_5%

R590

+5VALW

DIM LED

+1.05VS

R589

+0.75VS

R588

+1.5V

+1.5VS

+3VS

+5VS

+VCCP

Discharge circuit

1
1

PAD-OPEN 2x2m
C1371
0.1U_0402_16V4Z

2
A

Compal Electronics, Inc.

DC/DC Interface

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

41

of

55

+3VALW

connect to KBC pin97

BATT

AC_LED# <39>

PC5
1000P_0402_50V7K
2
1

PC3
1000P_0402_50V7K

PC4
100P_0402_50V8J
2
1

PD1
PJSOT24CW _SOT323

2
1
PC2
100P_0402_50V8J

PU1A
LM358ADT_SO8

BATT_OVP <39>

0
-

PR5
10K_0402_5%
2
1

PJP1

1
2

ADPIN

PL2
SMB3025500YA_2P
2
1

105K_0402_1%
PR6 1
2

PL1
SMB3025500YA_2P
1
2

+DOCKVIN

5
4
3
2
1

VIN

RLZ3.6B_LL34

1
2
PR3
10K_0402_5%

0.01U_0402_25V7K
PC6

5
4
3
2
1

2
ADP_SIGNAL

@1000P_0402_50V7K

499K_0402_1%
PR4 1
2

PD4
PR2
10K_0402_5%

ACES_88334-057N

PR8
2K_0402_5%

2 1

ADP_ID <39>
PC12

+5VALW
0.01U_0402_25V7K
PC1

100K_0402_5%

340K_0402_1%
PR1 1
2

PQ3
TP0610K-T1-E3_SOT23-3
+3VL
1 PR9
2

VMB
PL3
HCB2012KF-121T50_0805
2
PL4
HCB2012KF-121T50_0805
1
2

PJP2

BATT

1
PJSOT24CW _SOT323

PC8
1000P_0402_50V7K

2
PD3

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

PD2

EC_SMD
EC_SMC

8
7
6
5
4
3
2
1
GND
GND

8
7
6
5
4
3
2
1
9
10

PC9
0.01U_0402_50V4Z

SUYIN_200275MR008GXOLZR

PR7
604K_0402_1%
1
2

+5VS

CPU

3
1

2
1

PJSOT24CW _SOT323

PH1
10K_TH11-3H103FT_0603_1%

PR14
100_0402_5%

PC10
0.22U_0603_10V7K

PR15
150K_0402_1%

8
-

PR11
150K_0402_1%
PR12
2.37K_0402_1%

+3VL

PR16
6.49K_0402_1%
1
2

<43>

0
G

+5VALW

BAT_ID

SMB_EC_CK1 <39,40>

SMB_EC_CK1

EN0_TRIP <44>

PR10
200K_0402_1%
1
2

SMB_EC_DA1 <39,40>

PQ1
SSM3K7002FU_SC70-3

2
G

PU1B
LM358ADT_SO8

PC11
1000P_0402_50V7K

SMB_EC_DA1

PR13
100_0402_5%

PR17
1K_0402_5%

BATT_TEMP <39>

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DC Connector/CPU_OTP

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

D

Sheet

42

of

55

P4

B+

BATT
VIN

P2

EXTPWR

LODRV

23

PC135
470P_0603_50V8J

DPMDET

3
2
1

PC119
1U_0603_10V6K

21

<42>

BATT

SRP

PC122
@0.1U_0603_25V7K

PR122
681K_0402_1%
1
2

<39>

PR121
200K_0402_1%

IREF

PR120
2
1
133K_0402_1%

PC124
0.1U_0603_25V7K

SRN

PR123
1M_0402_5%
1
2

BAT_ID

PC121
100P_0402_50V8J
2
1

PC120
0.22U_0603_10V7K
2
1
2

PC123
0.1U_0402_10V7K

47K_0402_5%
PR119
2
G

VIN

PD104
1SS355_SOD323-2

BQ24740VREF

D
PQ111
SSM3K7002FU_SC70-3

20

19

18

PR117
100K_0402_5%
1
2

PC118
0.1U_0402_10V7K

CELLS

SRP

SRN

BAT
17

16

15

PR118
10K_0402_5%
1
2

ADP_I

22

IADAPT

PR116
15K_0402_1%

PGND
SRSET

IADAPT

ISYNSET

3
0.015_1206_1%

1
1

14
PR115
100K_0402_1%

3
5
6
7
8
PQ110
AO4468L_SO8

DL_CHG

PR141
4.7_1206_5%

<39>

PC130
270P_0402_50V7K

1
REGN

PC136
4.7U_0805_25V6-K

24

REGN

PR112
1

VADJ

PQ106
DTC115EUA_SC70-3

BATT

PL102
10U_LF919AS-100M-P3_5.3A_20%
1
2

PC131
@1000P_0402_50V7K

LX_CHG

PC116
4.7U_0805_25V6-K
2
1

PH

PC115
4.7U_0805_25V6-K
2
1

VDAC

DH_CHG

25

26

VIN_1

+3VL

PR124
1K_0402_5%
1
2

VIN

VIN

PACIN

LM393DG_SO8

PR134
10K_0402_5%

PD103
RLZ4.3B_LL34

2N7002KDW-2N_SOT363-6

PU102A
LM393DG_SO8

PR133
10K_0603_0.1%

PU102B

8
P

PC126
0.047U_0402_16V7K

PR132
100K_0402_5%
2
1

2
FSTCHG#

PR136
60.4K_0402_1%
1
2

PR135
10K_0603_0.1%

<39>

PR127
10K_0402_1%

O
-

PQ112A

PR130
2.15K_0402_1%
1
2

PR128
10K_0402_5%
2
1

1
2

CHGEN#

PC125
0.1U_0603_25V7K

PR129
10K_0402_1%
2
1

1
PR131
133K_0402_1%

PR126
100K_0402_1%
+3VL

ACIN

+3VL
PR125
47_1206_5%

VIN

<39>

PQ108
AO4466L_SO8

2 2

13

Charge Detector

PC111
0.1U_0402_10V7K
1
2
4

PC114
4.7U_0805_25V6-K

HIDRV

BST_CHG

ACOFF

5
6
7
8

CHGEN

PU101
BQ24740RHDR_QFN28_5X5

27

28

PC113
4.7U_0805_25V6-K
2
1

2
ACN

3
ACP

BTST

RLS4148_LL34-2

PC117
0.1U_0603_16V7K

PC134
2
1

1
2

PC105
4.7U_0805_25V6-K

1
2

PC104
4.7U_0805_25V6-K

1
2

PC103
4.7U_0805_25V6-K

PVCC

PC110
1U_0805_25V6K
1
2

4
VCTRL

12

PR105
10K_0402_5%

29

+3VL

VADJ

PR113
140K_0402_1%

PR114
43.2K_0402_1%
1
2

VIN

CHG_B+

PD102

2
1SS355_SOD323-2<39>

TP

AGND
VREF

PR103
47K_0402_5%
1
2

3
PQ109B
2N7002KDW-2N_SOT363-6
1

10

CHG_B+

PR108
10_1206_5%
1
2

IADSLP

BQ24740VREF

8
7
6
5

ACOFF#

3
2
1

PC112
1
2
1U_0603_6.3V6M

11

PD101
ACOFF#

ACDET

7
8

1
PACIN

PC109
@0.1U_0603_25V7K
CHGEN#

LPREF

PC128
1
2

PACIN_1

1
2

PR110
0_0402_5%
1
2

PR111
3K_0402_1%
1
2

@180P_0402_50V8J

2N7002KDW-2N_SOT363-6

PC102
1U_0603_6.3V6M

2
SUSP#

PR109
150K_0402_5%

PQ109A
2

PR140
100K_0402_5%

ACSET

<31,34,39,41,46,47,48,51>

PQ105
DTC115EUA_SC70-3

PC107
@0.01U_0402_16V7K

ACSET
1

AC_SET

PC133
@470P_0402_50V7K
ACDET

PR104
0_0402_5%
1
2

2
PR106
200K_0402_5%

PQ104
DTA144EUA_SC70-3

1
2
3

PL101
HCB2012KF-121T50_0805
2

1
2

PC106
0.1U_0603_16V7K
2
1

1000P_0402_50V7K
1
PC129
470P_0402_50V7K
2
1

0.012_2512_1%
1
4

8
7
6
5

PC108
0.1U_0603_25V7K

<39>

PR102

PQ103
SI4459ADY_SO8
1
2
3

PR101
47K_0402_5%
1
2

PC101
47P_0402_50V8J
PR107
47K_0402_1%
1
2

PQ101
SI4835BDY-T1-E3_SO8
1
2
3

LPMD

8
7
6
5

PC132
@1000P_0402_50V7K

PQ102
FDS6675BZ_SO8

VIN_1

PQ112B

1.24VREF

FSTCHG

2N7002KDW-2N_SOT363-6
4

STD_ADP <39>

PU104
4

ACDET

PC127

1.24VREF

ANODE

NC

2
4

LMV431ACM5X_SOT23-5

Compal Secret Data

Security Classification

Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

Charger

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

CATHODE
NC

22P_0402_50V8J

1
2

100K_0402_1%
PR138

PR137
20K_0402_1%

REF

<39>

Monday, November 09, 2009

D

Sheet

43

of

55

LG_5V

5
6
7
8
3
2
1
5
6
7
8

1
2

PC311
10U_0805_10V6K

1
2

2VREF_51125

PR318
1
2
0_0805_5%

PC313
@22U_0805_6.3V6M

3
2
1

PQ304
AO4712L_SO8

+3_5V PWR_OK <13>

2N7002KDW -2N_SOT363-6

+5VL

VL
PJP304
PJP302

VL

+5VALW P

PR313
100K_0402_5%
PQ307
2
G
SSM3K7002FU_SC70-3

+3VALW P

1
PAD-OPEN 2x2m

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VL

+3VLP

PAD-OPEN 4x4m
PJP303

PJP301

2
+3VALW

(3A,120mils ,Via NO.= 6)

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m

EC_ON

2
PC312
0.1U_0603_25V7K

ENTRIP2

B++

1
4

PC315
680P_0603_50V7K

VL

PR311
191K_0402_1%
2

<42> EN0_TRIP

PC317
0.1U_0402_25V6
2
1

PC318
4.7U_0805_25V6-K
2
1

1
2

PC305
4.7U_0805_25V6-K
2
1

PR316
4.7_1206_5%
2
1

13

PR309
1
2
1M_0402_1%

+5VALWP

19

PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

DRVL1

PC310
150U_D_6.3VM

LX_5V

PC304
2200P_0402_50V7K

UG_5V

20

PQ305B

21

LL1

6ENTRIP1
PQ305A
2N7002KDW -2N_SOT363-6

ENTRIP1

DRVH1

RT8205AGQW

PR308
PC308
2.2_0402_5% 0.1U_0402_10V7K
BST_5V 1
2 1
2

VCLK

DRVL2

VFB1

22

PQ302
AO4466L_SO8

18

12

VREF

23

VBST1

VREG5

LL2

PGOOD

VBST2

VIN

DRVH2

11

VFB2

VREG3

EN0

10

24

B++

PC314
@680P_0603_50V7K

1
2

PC309
220U_6.3VM_R15

PR306
113K_0402_1%
2

PR315
@4.7_1206_5%
2
1

LG_3V

B++

VO1

17

UG_3V

VO2

16

PL302
3.3UH_SIQB74B-4R7PF_5.9A_20%
2
1

BST_3V

TONSEL

1
PR307
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

+3VALWP

P PAD

GND

S TR AO4932 2N SO8
1G 8
1S/2D 7
1S/2D 6
1S/2D 5

SKIPSEL

D1
D1
G2
S2

15

1
2
3
4

PU301

25
2

PC306
10U_0805_6.3V6M

PC303
4.7U_0805_25V6-K

PC301
2200P_0402_50V7K
2
1

PQ301

PR305
100K_0402_1%
1
2

ENTRIP1

PR304
20K_0402_1%
1
2

ENTRIP2

PR303
20K_0402_1%
1
2

+3VLP

2
PC316
0.1U_0402_25V6

PR302
30.9K_0402_1%
1
2

ENTRIP2

PL301
HCB2012KF-121T50_0805

PR301
13.7K_0402_1%
1
2

14

B++

B+

PC302
1U_0603_16V7

2VREF_51125

<39>

100K_0402_5%
PR314

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

3.3VALWP/5VALWP

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
E

44

of

55

1.5V_B+

B+

PL402
HCB1608KF-121T30_0603
2
1

PR404

<31,39,40,41> SYSON

1
PC406
@0.1U_0402_10V7K

14

+5VALW
LG_1.5V

3
2
1

PC408
0.1U_0402_25V6

1
2

2200P_0402_50V7K
PC407

1
2

PC403
4.7U_0805_25V6-K

+5VALW

PR410
@4.7_1206_5%

PQ402
S TR FDS6690AS_NL 1N SO8

PC410
4.7U_0805_10V6K

PC401

DRVL

PC405
4.7U_0805_6.3V6K

TPS51117RGYR_QFN14_3.5x3.5

3
2
1

PC412
@680P_0603_50V7K

330U_D2_2.5VY_R15M

PR402
10K_0603_0.1%

10

PGOOD

11

15.4K_0402_1%

TRIP
V5DRV

PR403

+1.5VP

PL401
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

VFB

LL

LX_1.5V

5
6
7
8

VBST

TP

V5FILT

UG_1.5V

12

PQ401
AON7408L_DFN8-5

1 2

10.2K_0603_0.1%

13

FB_1.5V

DRVH

PR407
0_0402_5%
1
2

PR401

PC411
1U_0603_10V6K

VOUT

+1.5VP

TON

PGND

PR409
316_0402_1%

UG1_1.5V

+5VALW 1

2
0_0402_5%

+5VALW

1
PR408

GND

EN_PSV

PU401
PR406
255K_0402_1%
1
2 2

15

PR405
PC409
2.2_0402_5% 0.1U_0402_10V7K
BST_1.5V 1
2
1
2

+1.5VP

PC402
4.7U_0805_25V6-K

0_0402_5%

PJP401

+1.5VP

+1.5V

(8A,320mils ,Via NO.= 16)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

+1.5VP

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

45

of

55

+VCCP

VCC

PC709
0.22U_0603_16V7K

BOOT

PR710
2.2_0603_5%
1
2

+6269_VCC

5
6
7
8

BST_VCCP

PR709
0_0402_5%

13

14
UG

15

16

1
2
PR707
2 0_0603_5%

PQ701
AO4474L_SO8

4
PVCC

12

LG

11

DL_VCCP

PGND

10

PC710
2.2U_0603_6.3V6K
PL701
0.47UH_FDV0630-R47M-P3_18A_20%
1
2

ISL6269ACRZ-T_QFN16_4X4

FCCM

SE_VCCP 1

2
PR704
6.98K_0402_1%
4

330U_D2_2V_Y

PC701
330U_D2_2V_Y

2
PR701
35.7K_0402_1%

3
2
1

PQ702
AON6718L_PSO8

PC703

2 330U_D2_2V_Y

PC713
680P_0603_50V7K

2
1
PC714
0.01U_0402_16V7K

+VCCP

PR715
49.9K_0402_1%
2

FB_VCCP

PR714
27.4K_0402_1%
2
1

2
PR702
1.58K_0402_1%

2+VCCP
PR716
10_0402_5%

2
PR717
0_0402_5%

<9> VTT_SELECT

5
3

2
1
PC716
6800P_0603_50V7K

PC712
@0.1U_0402_10V7K

PC715
22P_0402_50V8J

+
PC702

COMP

PR713
0_0402_5%

ISEN

EN
VO

FSET

FB

1
PR712
4.7_1206_5%

<31,34,39,41,43,47,48,51> SUSP#

+VCCP
+VCCP

PR711
0_0402_5%
1
2

+5VALW

PC711
2.2U_0603_6.3V6K

2
PR708
2.2_0603_5%

3
2
1

VIN

PHASE

1
+6269_VCC

PGOOD

GND

17

<6> VTTPW RGOOD

PU701

1
DH_VCCP

PR706
@1K_0402_5%

PR705
1K_0402_5%

DH_VCCP1

+3VS

LX_VCCP

2
1
PC706
4.7U_0805_25V6-K

2
1
PC705
4.7U_0805_25V6-K

2
1
PC704
4.7U_0805_25V6-K

VCCP_B+
PC708
2200P_0402_50V7K

PL702
HCB2012KF-121T50_0805
1
2
PC707
0.1U_0402_25V6

B+

PC717

PR703
1.96K_0402_1%

VTT_SELECT= Low, 1.1V

VTT_SELECT= High, 1.05V

VTT_SENSE <9>

@0.1U_0402_10V7K

Compal Secret Data

Security Classification
Issued Date

2008/09/15

Deciphered Date

2009/09/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

1.05V_VCCP

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

D

Sheet

46

of

55

+1.5V

VCNTL

NC

+5VALW
+5VALW

GND

2
2

PC609
@0.1U_0402_10V7K

EN

VOUT

FB

TP

+1.8VSP

PR605
0_0402_5%

VOUT

PC608
10U_0805_10V6K

PC610
22U_0805_6.3V6M

GND

SUSP#

VIN

<31,34,39,41,43,46,48,51> SUSP#

PC606
@0.1U_0402_10V7K

@0_0402_5%

POK

1
PC605
10U_0805_6.3V6M

2
2
PR604
1

PR606
15K_0402_1%
2

APL5930KAI-TRG_SO8

PC611
150P_0402_50V8J

PR603
@0_0402_5%

2
G

PC617
@0.1U_0402_10V7K

2
1

1
PR613
0_0402_5%

<6> 1.5VSCPU_DRAM_PWRGD

PQ602
SSM3K7002FU_SC70-3

2
G

+0.75VSP

PR602
1K_0402_1%

2
1
PC604
0.1U_0402_16V7K

1
D

PQ601
SSM3K7002FU_SC70-3

PU602

G2992F1U_SO8
PR614
10K_0402_1%

PC607
1U_0603_10V6K

TP

+3VS
PC603
1U_0603_10V6K

NC

VOUT

NC

VREF

VCNTL

PR601
1K_0402_1%

+3VALW

VIN

1
2

PC601
10U_0805_10V6K

PC602
@10U_0805_10V6K

PU601
1

<36,41><41>
SYSON# SUSP

PR607
12K_0402_1%
C

+3VS

PR608
10K_0402_5%

1.1VS_POK <28>
PJP601
+0.75VSP

+0.75VS

(2A,80mils ,Via NO.= 4)

+5VALW

PAD-OPEN 3x3m
1

+1.5VS

(1.5A,60mils ,Via NO.= 3)

PU603
SUSP#

PJP603
1

+1.1VSDGPU

(3A,120mils ,Via NO.= 6)

2
PR612
@0_0402_5%

POK

<14,23,40,41,51> DGPU_PWR_EN

VIN

VOUT

VOUT

FB

TP

PC613
10U_0805_10V6K
<BOM Structure>

+1.1V_PCIE
PC615
22U_0805_6.3V6M

1
2

PR610
15K_0402_1%

PC616
@47P_0402_50V8J

APL5930KAI-TRG_SO8

PC614
@0.1U_0402_10V7K

EN

2
1

PR609
0_0402_5%

PAD-OPEN 3x3m

GND

+1.1V_PCIE

+1.8VS

2
PAD-OPEN 3x3m

PC612
1U_0603_10V6K
<BOM Structure>

VCNTL

+1.8VSP

PJP602

PR611
39.2K_0402_1%

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

0.75VP/1.8VSP/1.1V_PCIE

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

47

of

55

PR504

PL502

1.05V_B+

HCB1608KF-121T30_0603
1
2

PC505
@0.1U_0402_10V7K

1
2

PC503
4.7U_0805_25V6-K

PC502
4.7U_0805_25V6-K

3
2
1
2

13K_0402_1%
PQ502

+5VALW

PR510
@4.7_1206_5%

FDMC8296_POW ER33-8-5
PC510
4.7U_0805_10V6K

1
PC504
4.7U_0805_6.3V6K

TPS51117RGYR_QFN14_3.5x3.5

PC511
@680P_0603_50V7K

3
2
1

PR512
10_0402_5%

PC501
220U_B2_2.5VM_R25M

LG_1.05V

PR503

DRVL

+5VALW

V5DRV

10

11

PC507
2200P_0402_50V7K

14

12

+1.05VSP

PL501
2.2UH_PCMC063T-2R2MN_6A_20%
1
2

PGOOD

VBST

TP

1
EN_PSV

VFB

PR502
10.2K_0402_1%

LX_1.05V

LL
TRIP

B+

PQ501
AON7408L_DFN8-5

UG1_1.05V

PC509
1U_0603_10V6K

+1.05VSP1

V5FILT

1
PR501
1
2 FB_1.05V
4.12K_0402_1%

VOUT

UG_1.05V

PR509
316_0402_1%

13

2
0_0402_5%

PGND

+5VALW 1

DRVH

PR507
0_0402_5%
1
2

1
PR508

+1.05VSP
+5VALW

TON

GND

PU501
PR506
255K_0402_1%
1
2 2

15

PR505
PC508
2.2_0402_5% 0.1U_0402_10V7K
BST_1.05V 1
2
1
2

PC506
0.1U_0402_25V6
2
1

0_0402_5%

<31,34,39,41,43,46,47,51> SUSP#

+1.05VSP

+1.05VS

PR511
0_0402_5%
PJP501

+1.05VSP

Close PCH

+1.05VS

(6A,320mils ,Via NO.= 16)

PAD-OPEN 4x4m
3

Compal Secret Data

Security Classification
Issued Date

2008/09/15

Deciphered Date

2009/09/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

1.05VSP

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

D

Sheet

48

of

55

PR228 @1K_0402_5%
1
2

+VCCP

PR229
<9>

+VCC_CORE
V2N

PC212
0.1U_0402_25V6
2
1

10K_0402_1%

PR225
1_0402_5%

ISEN2
VSUM+

ISL62883HRZ-T_QFN40_5X5
1

PR238
1

1_0402_5%
2
+5VALW

PC223
0.22U_0603_25V7K

1
2

0.22U_0603_10V7K

0.22U_0603_10V7K
PC226
2
1

PR242
10.5K_0402_1%

CPU_B+

VSSSENSE

BOOST_CPU1

VSUM-

PC225
2
1

ISEN1

PC222
1U_0603_10V6K
2
1

ISEN2

<9>

PQ201
AO4406AL 1N SO8
PR243
0_0603_5%
2
1

UGATE_CPU1
PR244
2.2_0603_5%
2
1

VSUM+

PC229
0.22U_0603_10V7K
1
2

PC228
0.1U_0402_25V6
2
1

PR240
412K_0402_1%

IMVP_IMON

PC204
4.7U_0805_25V6-K
2
1

PR241

0_0402_5%
2

5
6
7
8

0_0402_5%
2
CPU_B+

PR239

PR237
3.01K_0402_1%

1
2
PC220
10P_0402_50V8J

PC203
4.7U_0805_25V6-K
2
1

390P_0402_50V7K
1 PR236 2
1
2
562_0402_1%
PC219

0_0402_5%
PR234

PC201
4.7U_0805_25V6-K
2
1

AGND

PC227
2200P_0402_50V7K
2
1

41

11
12
13
14
15
16
17
18
19
20

1
2

PC216
22P_0402_50V8J

PC217
1000P_0402_50V7K

+5VALW

3
2
1

1
PR235
8.06K_0402_1%
1

VSUM-

PC224
0.22U_0603_25V7K

30
29
28
27
26
25
24
23
22
21

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

1U_0603_10V6K

1
2
3
4
5
6
7
8
9
10

PC218
2
1

PR233 0_0402_5%

PC215
1U_0603_10V6K
1
2

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

<6> H_PROCHOT#

PU201

40
39
38
37
36
35
34
33
32
31

PR232
2
68_0402_5%

+VCCP

1
PC221
150P_0402_50V8J

2
PR231 147K_0402_1%

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

0_0402_5%
1
2
PR230
2
1
1K_0402_1%

H_PSI#

PR224
2

PR226
1.91K_0402_1%

VGATE

PR223
3.65K_0603_1%
2
1

LGATE_CPU2

PR221
4.7_1206_5%

PC202
4.7U_0805_25V6-K
2
1

<13,19>

PR227
0_0402_5%
1

PL202

LF2

CLK_EN#

0.36UH +-20% MPO104F-R36H1 30A

PQ204
TPCA8036-H_SOP-ADV8-5

PR222
1.91K_0402_1%
1

PC208
4.7U_0805_25V6-K
2
1

PR218
0_0603_5%
2
1

PHASE_CPU2

3
2
1

CLK_EN#

<19>

PC209
@100U_25V_M

1 PR210 2
1K_0402_1%

PC213
0.22U_0603_10V7K
1
2

UGATE_CPU2

2
1
1K_0402_1% PR219 0_0402_5%
1
2

PR215
2.2_0603_5%
2
1

BOOST_CPU2

2 PR220 1
@1K_0402_1%
+3VS

<9> H_DPRSLPVR

B+

PC214
680P_0603_50V7K
2
1

+VCCP

PC207
4.7U_0805_25V6-K
2
1

5
6
7
8

PR217
G

GFX_B+

3
2
1

0_0402_5%
1
2

PR211
VR_ON

PC206
4.7U_0805_25V6-K
2
1

1PR207
2
@1K_0402_1%

1PR206
2
@1K_0402_1%

1 PR204 2
@1K_0402_1%

1PR205
1K_0402_1%

1PR202
2
1K_0402_1%

H_VID6

H_VID6
<39>

1 PR209
1K_0402_1%

<9>

H_VID5

H_VID5

PL203
HCB2012KF-121T50_0805
2
1
PL204
HCB2012KF-121T50_0805
2
1

PQ202
AO4406AL 1N SO8

H_VID4

1 PR208
@1K_0402_1%

<9>

1PR203
2
@1K_0402_1%

H_VID4

<9>

H_VID2
H_VID3

1PR216
1K_0402_1%

H_VID3

H_VID2

<9>

1 PR214
1K_0402_1%

<9>

H_VID0

CPU_B+

H_VID1

H_VID1

H_VID0

<9>

1 PR213
@1K_0402_1%

<9>

1 PR212
1K_0402_1%

1 PR201 2
@1K_0402_1%

+VCCP

PC210
100U_25V_M

PC205
4.7U_0805_25V6-K
2
1

PC211
2200P_0402_50V7K
2
1

0.36UH +-20% MPO104F-R36H1 30A

PC235
680P_0603_50V7K
2
1

1
10KB_0603_5%_ERTJ1VR103J

21

1
1

PR251
1_0402_5%

VSUMB

ISEN1
VSUM+

VSUM-

Compal Secret Data

Security Classification

2007/05/29

Issued Date

Deciphered Date

2008/05/29

Title
Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:
6

Compal Electronics, Inc.

+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
7

+VCC_CORE
V1N

@100_0402_1%

PR256

@1200P_0402_50V7K

PH201

10K_0402_1%

LGATE_CPU1

PR250
2

PQ203
TPCA8036-H_SOP-ADV8-5

3
2
1
PC238
1

PR247
4.7_1206_5%

PR255
11K_0402_1%
2
1

PR253
1.3K_0402_1%
1
2

LF1

PR248
3.65K_0603_1%
2

PR246
2.61K_0402_1%
2
1

0.047U_0603_16V7K

1
2
PC232

1
2
PC231

PC230
0.022U_0402_16V7K
2
1

PC234

1
1

PHASE_CPU1

PC239
0.1U_0402_16V7K

<9> VSSSENSE

0_0402_5%
2

PR252
1

PC236
1000P_0402_50V7K

PC237
330P_0402_50V7K

PC233
330P_0402_50V7K

0.01U_0402_25V7K

0_0402_5%

PR249

VCCSENSE

<9>

0.22U_0603_10V7K

PL201
PR245
82.5_0402_1%

Monday, November 09, 2009

Sheet

49
1

of

55

GFX_B+

PC809
0.22U_0402_6.3V6K

PC807
1U_0603_6.3V6M

PR833
0_0402_5%
2
1
GFXVR_IMON

<9>

VSS_AXG_SENSE

5
6
7
8

ISUM+
ISUM-

1
2

PC816
2.2U_0603_6.3V6K

VID2

AON6718L 1N DFN

.56UH +-20% ETQP4LR56 W FC 21A

PR811
3.65K_0805_1%

21

VID1

20

PR810
2.2_1206_5%

PR809
1
2 +5VALW
4
0_0603_5%

3
2
1

VID0

18 DL_GFX
19

17

VCCP

+GFX_CORE

PL801

16 LX_GFX

PR812
0_0402_5%

PH801

2 1
PR815
PC817
2.61K_0402_1%
680P_0603_50V7K

22

VID4

3
2
1

PR807
0_0603_5%
1
2 DH_GFX1

15 DH_GFX

13

12

11

10

14
BOOT

IMON

VIN

VDD
VID5

VID3
23

1
PR817
8.06K_0402_1%

PC811
0.22U_0603_16V7K

PQ802

24

2
10KB_0603_5%_ERTJ1VR103J

PR818
1
2
11K_0402_1%
PC820
.1U_0402_16V7K
1
2

1
1
1
1
1
1
1
1
1

PR821
PR822
PR824
PR826
PR827
PR828
PR830
PR831
PR832

GFXVR_VID_0 <9>
GFXVR_VID_1 <9>
GFXVR_VID_2 <9>
GFXVR_VID_3 <9>
GFXVR_VID_4 <9>
GFXVR_VID_5 <9>
GFXVR_VID_6 <9>
GFXVR_EN <9>
GFXVR_DPRSLPVR <9>

PR823
@100_0402_1%

2
2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

GFXVR_CLKEN#

1
2
PC821
0.1U_0603_16V7K
PR825
3.01K_0402_1%
PR829
82.5_0402_1%
1
2
1
2

GFXVR_PW RGD

ISUM+

8
RTN

CLK_EN#

25

PR816
17.8K_0402_1%

PQ801
AO4474L_SO8

PC822
0.01U_0402_16V7K

PC823
@180P 50V J NPO 0402

1 2

PGOOD

+GFX_CORE

2
1
PR819
@1.91K_0402_1%

2
PC818
150P_0402_50V8J

RBIAS

2
1

PC814
100P_0402_50V8J
PC819
22P_0402_50V8J
1
2

1 3

VSSP
LGATE

VID6

VW

26

COMP

VR_ON

2 1

UGATE
PU801
ISL62881HRZ-T_QFN28_4X4 PHASE

28

PR808
47K_0402_1%

FB

1
PR820
@10K_0402_1%

PC815
1000P_0402_50V7K

VSEN

PR814
825K_0402_1%

DPRSLPVR

ISUM

AGND

PC812
330P_0402_50V7K

PR813
10.2K +-1% 0402

PR805
2.2_0603_5%

PC813
330P_0402_50V7K

27

PR806
+GFX_CORE 10_0402_5%
1
2

29

<9> VCC_AXG_SENSE

BST_GFX 1

1
2
PC810
1000P_0402_50V7K

<9> VSS_AXG_SENSE

PR804
10_0402_5%
1
2

2
1
PR803
22.6K_0402_1%
2
1

1 1

PR801
1
+5VALW 2
1_0603_5%

PC808
0.22U_0603_25V7K

PR802
0_0603_5%

1
2

PC806
0.1U_0402_25V6

2
1
PC804
4.7U_0805_25V6-K

2
1
PC803
4.7U_0805_25V6-K

2
1
PC802
4.7U_0805_25V6-K

1
2

GFX_B+

2
1
PC801
4.7U_0805_25V6-K

PL802
HCB2012KF-121T50_0805
1
2
PL803
HCB2012KF-121T50_0805
1
2

B+

PC805
2200P_0402_50V7K

ISUM+
ISUM-

Compal Secret Data

Security Classification
2008/10/31

Issued Date

Deciphered Date

2009/10/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

VCCGFX

Size
Document Number
Custom Calpella DIS LA-4107P
Date:

Monday, November 09, 2009

Rev
Sheet
1

50

of

55

PR922
@0_0402_5%
1
2
PR906
0_0402_5%
1
2

<14,23,40,41,47> DGPU_PWR_EN

PL902

V5DRV

10

+5VALW

2
PR905
14.3K_0402_1%

PC911
4.7U_0805_10V6K

PQ902
FDS6690AS_G_SO8

1
2
+

PR912
@4.7_1206_5%

DL_VGA

+NVVDDP
1

PC913
@680P_0603_50V7K

3
2
1

DGPU_PW ROK <14>

+NVVDDP

PR902
75K_0402_1%

Close VGA

+VGA_CORE

PR915
10_0402_5%

PL901
1UH_PCMC063T-1R0MN_11A_20%
1
2

DRVL

2 DH_VGA_1
PR910
0_0402_5%

11

TRIP

2
5
LX_VGA

3
2
1

DH_VGA

12

5
6
7
8

VBST
PGND

13

LL

PGOOD

14

15
TP

1
EN_PSV

VFB

6
1

DRVH

TPS51117RGYR_QFN14_3.5x3.5

V5FILT

PR913
0_0402_5%

2
PC912

@10P_0402_50V8J
PR914
0_0402_5%

1
2

VOUT

PQ901
AON7408L_DFN8-5

PC902
4.7U_0805_6.3V6K

PC910
1U_0603_10V6K

PR901
15.4K_0402_1%

TON

PC901
330U_D2_2V_Y

+VGA_COREP1
2

GND

PR911
2
1
0_0402_5%

1
2

1+5VALW
2

PR909
255K_0402_1%
1
2

PC907
2200P_0402_50V7K

PU901

B+

PR907
PC909
2.2_0402_5% 0.1U_0402_10V7K

PR908
316_0402_1%

+NVVDDP

2 1

PC904
4.7U_0805_25V6-K

BST_VGA 1

PC903
4.7U_0805_25V6-K

PC906
0.1U_0402_25V6

+5VALW

VGA_B+

PC905
@0.1U_0402_10V7K

HCB1608KF-121T30_0603
1
2

SUSP#

<31,34,39,41,43,46,47,48> SUSP#

+3VS
PR917
15K_0402_1%
2
1

PR903
210K_0402_1%
1
2 3

1
PR919

PC915
PQ904A
0.022U_0402_16V7K
2N7002KDW -2N_SOT363-6

+VGA_CORE

0.9V

1.05V

1.1V

PR904
76.8K_0402_1%
1
2
3

PQ904B
2N7002KDW -2N_SOT363-6

<26> GPU_VID0

GPU_VID1

10K_0402_5%

PR920
15K_0402_1%
2

PQ903B
2N7002KDW -2N_SOT363-6

1
PR918
10K_0402_5%

PC914
0.022U_0402_16V7K

PQ903A
2N7002KDW -2N_SOT363-6

<26> GPU_VID1

GPU_VID0

PR916
10K_0402_5%
1
2

PR921
10K_0402_5%

PJP901
+NVVDDP

+VGA_CORE(11A,489mils

,Via NO.= 22)

Compal Secret Data

Security Classification
PAD-OPEN 4x4m
PJP902

Issued Date

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PAD-OPEN 4x4m
A

2007/05/29

Title

Compal Electronics, Inc.

VGA_CORE

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

D

Sheet

51

of

55

Item

Fixed Issue

(Reason for change)

PLT_RST# need a PD resistor

Remove MUX in CRT DDC circuit

Remove MUX in LVDS ENAVDD circuit

LCD panel will fail in OPP SKU

Remove MUX in LVDS I2C circuit

PAGE

of SG design
of SG design

Modify List

Date

Phase

14

Add R185 PD for PLT_RST#

08/6

PV

20

Change to MOS design

08/6

PV

21

Change to MOS design

08/6

PV

21

Add one 0 ohm resistor (R1238) for OPP SKU

08/6

PV

22

Change to MOS design

08/6

PV

OPP SKU: M93 and VRAM may have leakage in S3 mode

41

Change the power plan to +1.5VS of JP303

08/6

PV

8111VB power on timing issue

32

Add R1083 and C1319 to fine tune the power on timing

08/10

PV

Blade 2.0 need Board ID

39

Use EC GPIO48 for ID pin(Add R1239, R1240)

08/12

PV

EC GPIO17 will be used for debug card

39

LAN_POWER_OFF signal change to EC GPXID4(Pin 115)

08/12

PV

10

Cap. sensor board need to change the power source.

40

Change the power source of Cap. sensor baord to +3VS

08/13

PV

11

Lid switch need to change the power source.

40

Change the power source of Lid switch to +3VALW and R526 PU to +3VALW.

08/13

PV

12

Change +1.8VS to +1.8VSDGPU Transfer design

for cost down

41

Change the power MOS(U49) to 2301 PMOS(Q109).

08/13

PV

13

BIOS team doesn't need XDP connector

Remove the XDP connector

08/13

PV

14

Change +5VS to +5VSDGPU Transfer design

for cost down

41

Use 0 ohm to contact +5VS and +5VSDGPU

08/13

PV

08/13

PV

of SG design

15

PCH_DDR_RST need use PCH GPIO46 to control

PCH_DDR_RST MOS gate control signal change

from EC to PCH GPIO46

16

Remove the 27MHz crystal of VGA

26

Use clock gen 27MHz source and stuff R216

08/14

PV

17

Q104 need change to low Vgs type

Change the Q104 to BSS138 P/N:SB501380020

08/18

PV

18

Cost down plan

Change the C995,C996 330u to ESR=9m ohm

08/14

PV

19

Cost down plan

Change the C64 from 330u to 220u

08/14

PV

20

Cost down plan

Change the C61,C62,C67,C68,C69,C76,C82 from 22u to 10u

08/14

PV

21

Cost down plan

Change the C200 330u to ESR=9m ohm

08/14

PV

22

Cost down plan

Un-stuff C204,C228 and C229

08/14

PV

23

Docking no sound when play music

34

Need to stuff R910

08/14

PV

24

Audio new Mapping

34

Exchange the port A and port F

08/14

PV

25

We won't have DIM_LED function

41

Un-stuff Q99,Q101 and add two 0 ohm(R1244,R1245) resistors for LED power source.

08/14

PV

26

ESD issue

34

Add R1247,C1442,C1443 and change the C983~C986, C1444~C1446 to 0.1u

08/18

PV

27

Black light issue(will see the garbage when boot)

22

Change the black light enable schematic design.

08/18

PV

28

CPU leakage issue

Change the design for Intel's power leakage issue when go into S3 mode

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

08/19

Title

PV

Compal Electronics, Inc.

PIR-HW

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

52

of

55

Item

Fixed Issue

(Reason for change)

PAGE

Modify List

Date

Phase

29

INT.MIC ESD issue

35

Add D58 and D62 for ESD issue

08/18

PV

30

EXT.MIC ESD issue

35

Reserve D63 for Ext. MIC

08/18

PV

31

Reserve PU resistors to +3VL for ESB BUS

39

Reserve R1253,R1254 for ESB bus

08/21

PV

32

Make sure power sequence is correct

6,47

Use 1.5VSCPU_DRAM_PWRGD to enable 0.75VS power

09/11

PV2

33

Add ME_EN# for PCH GPIO33

11

Add inverter circuit for ME_EN signal

09/11

PV2

34

+3VS_VGA will have leakage when switch to

IGPU mode

12

Change Q4 pin2 and pin5 to +3VS_VGA

09/11

PV2

35

Need contact SUS_PWR_DN_ACK between EC and PCH

13

Use PCH GPIO30 and EC pin76 for SUS_PWR_DN_ACK

09/11

PV2

36

Need add VGA ID pin for M93 and M93 LP

14

Use PCH GPIO57 for VGA ID pin

09/11

PV2

37

Change 27MHz clock source of VGA to Y7

19,26

non-stuff R216

09/11

PV2

38

Q37 dual package will have floating isse

22

Change Q37 to single package

09/11

PV2

39

Fix 8103 BOM isse

32

Add R1259 for 8103EL LAN chip

09/11

PV2

40

Fix EXT. MIC reference voltage issue

34

Change the reference voltage to +AVDD_CODEC

09/11

PV2

41

Remove EC_BEEP function

34

Delete EC_BEEP function

09/11

PV2

42

Remove Analog MIC detect function

Delete ANA_MIC_DET signal from EC and codec

09/11

PV2

43

EMI need to add chock for ESATA/USB port

37

Add L66 for ESATA/USB port

09/11

PV2

44

HM55 PCH will disable USB port6 and port7

37

Change Finger printer from USB port7 to USB port 11

09/11

PV2

45

HM55 PCH will disable USB port6 and port7

37

Change Bluetooth from USB port 6 to USB port 12

09/11

PV2

45

Remove EC_BEEP function

39

Change Pin 26 from EC_BEEP to ME_EN

09/11

PV2

46

Fix PV phase Board ID issue

39

Exchange TP_BTN# and Board_ID pin

09/11

PV2

47

Cypress Cap. sensor board need use +3VL power

40

Change Cap. sensor board power to +3VL

09/11

PV2

48

Adjust +3VS / +1.5VS power sequence

41

Change C676,C770 from 0.1u to 0.022u

09/12

PV2

49

PLT_RST# don't need PD resistor

14

Un-stuff R185

09/20

MV

50

Follow Intel to adjust +0.75VS discharge timing

41

Change R593 from 470ohm to 22ohm

09/20

MV

51

Follow Intel to adjust +1.5VS discharge timing

41

Change R590 from 470ohm to 220ohm

09/20

MV

52

Follow Intel Check list 2.0

15

Un-stuff C187 and C192

09/20

MV

53

EDID signal need to add PU resistor

22

Add R1261 for EDID DATA

09/20

MV

54

VCCADAC dosen't need LC filter when DIS only

15

Change L45 to 0 ohm resistor for OPP SKU

10/01

MV

55

GFX core power transient fail

Change

35,39

C996 to 330u 7m ohm

10/21
Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

MV

Compal Electronics, Inc.

PIR-HW

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
E

53

of

55

Item

Fixed Issue

(Reason for change)

PAGE

Modify List

Date

Phase

56

Add M93 / M93LP / Park / Park LP ID pin

14

Use PCH GPIO28 and GPIO57 for VGA ID pin

10/21

MV

57

RTC timing fast / slow issue

19

Change C259, C260 to 22P

10/21

MV

58

ESB CLK can't pass EMI test.

40

Change R1151 to 300 ohm bead and add C1449

10/21

MV

59

Intel PCH CLK jitter issue

12

Reserve Y2 for this issue.

10/23

MV

60

ATE test jig issue(M/B will shutdown when no CPU)

39

Add R1265 for ATE jig test

10/23

MV

61

ATE test jig issue

(need to turn on +VGA_CORE when no CPU)

41

Add R1266 and reserve Q115 for ATE jig test

10/29

MV

62

Ext. MIC record noise issue

34

Reserve LDO circuit for this issue.

11/03

MV

63

Intel CPU GFX overshoot issue

09

Follow Intel suggestion to change the R43 to 249 ohm

11/05

MV

64

+1.8VSDGPU power up/down timing issue

41

Change R916 to 1K and R926 to 10K then add C1454 to fine tune timing

11/05

MV

65

+1.5VSDGPU / +1.5VS power quality issue

41

Change U50 and U58 to low RDSON NMOS

11/05

MV

Compal Secret Data

Security Classification
2007/08/28

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

PIR-HW

Size

Document Number

Rev
1.0

Calpella DIS LA-4107P

Date:

Monday, November 09, 2009

Sheet
1

54

of

55

Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
1

Date Request Issue Description

Owner

44

PWR-3.3VALWP/5VALWP

8/12

PWR

49

PWR-CPU_CORE

8/13

PWR

Note

Solution Description

all cap no more than 0805

OCP & IMON ajustment and
Fixed LL to match INTEL Spec

Add PC318,PC305 from 1206 to 0805 and parallel with PC318

Change PR253 from 1.1K to 1.3K,Change PR242 from 8.25K to 10.5K
Change PR237 from 2.43K to 3.01K

DB to PV1

DB to PV1

49

PWR-CPU_CORE

8/17

PWR

RF Solution

47

PWR-0.75VP/1.8VSP

8/20

PWR

Cost Down plan

Change PU602 from APL5915 to APL5930

DB to PV1

43

PWR-Charger

8/20

PWR

Smart Charger

Change PR113 from 143K to 140K, Change PC117 from 1u to 0.1u, Add PR114

DB to PV1

49

PWR-CPU_CORE

8/20

PWR

Avoide DFX interfere

Delete PC209 and add PC210

DB to PV1

8/24

PWR

Follow HW Suggestion Pull-up

resistor connect to 3VS

Add PR705 connect to 3VS, remove PR706

DB to PV1

46

PWR-1.05V_VCCP

45

PWR-1.5VP

8/24

PWR

PU401 second source solution

PR403 from 13.7K to 15.4K

DB to PV1

46

PWR-1.05V_VCCP

8/24

PWR

PU701 second source solution

PR703 from 8.06K to 6.98K

DB to PV1

10

49

PWR-CPU-CORE

8/28

PWR

Improve transient response

Add PC230

DB to PV1

PWR

Cost down plan

Change PC701 PC702 PC703 from 330u 6m ohm

to 330u 9m ohm

DB to PV1

46

12

46

PWR-1.05V_VCCP

9/3

PWR

Improve VCCP Ripple

Del PC717

DB to PV1

13

50

GFX_CORE

9/11

PWR

Let GFX IMON measure easily

Add PR833 connect to GFRXVR_IMON and PU801 pin 13

PV1 to PV2

PWR

For HW requirement add

1.5VSCPU_DRAM_PWRGD

Add 1.5VSCPU_DRAM_PWRGD add PR613 connect to PQ601 pin 2 and Delet PR604

47

PWR-0.75VP/1.8VSP

9/2

11

14

PWR-1.05V_VCCP

9/11

DB to PV1

Change PQ201 PQ202 from AO4474L to

AO4406AL,PR215 PR244 from 0 to 2.2

Title

PV1 to PV2

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

PIR-PWR

Size Document Number

Custom
Date:

Rev
1.0

Calpella_UMA_LA4106P

Monday, November 09, 2009

Sheet
E

55

of

55