First National Conference On "RECENT TRENDS IN POWER ELECTRONICS AND INDUSTRIAL DRIVES" PEID-2011

First National Conference on RECENT TRENDS IN POWER ELECTRONICS AND INDUSTRIAL DRIVES PEID-2011
March 04-05, 2011
Organized By DEPARTMENT OF ELECTRICAL& ELECTRONICS ENGINEERING
INFO INSTITUTE OF ENGINEERING COIMBATORE
All rights reserved
Copyright 2011 Info Institute of Engineering, Coimbatore

For copiying, reprint or republication permission, write to Convener, PEID 2011, INFO Institute of Engineering, Kovilpalayam, Coimbatore, TamilNadu
Additional Copies of the Publication can be obtained from The Convener, PEID 2011 INFO Institute of Engineering, Sathy Road, Kovilpalayam Coimbatore- 641 107 Coimbatore District TamilNadu
Department of Electrical & Electronics Engineering
Coimbatore District, Tamil Nadu
Info Institute of Engineering, Coimbatore 641 107
INFO INSTITUTE OF ENGINEERING MESSAGE

Dr.S.Karuna Chairperson, IIE
I am pleased to know that the department of Electrical & Electronics Engineering of INFO institute of Engineering is organizing the 1st National conference on Recent Advances in Power Electronics and Industrial Drives in our institution. Power electronics, the young science in engineering has found tremendous applications in heavy electrical industries. Many academicians and researchers have turned their attention towards research in power electronics. The facts and conclusions thus derived must be shared by the technocrats to convert technology into products. This national conference is destined to translate research into practice I appreciate the sincere efforts put in by our students and the valuable guidance given by our faculty members to make this national conference happen. Various sessions and paper presentations related to the branches in power electronics will provide an awesome opportunity to imbibe knowledge, and interaction with expertise in the field and is sure to expand the horizon and get a broader view of this new emerging engineering discipline for the participants. Our Indian government with a national mission is keen in providing the country with capability to become a dominant player in Power Electronics at the international level. I am happy that INFO would enhance the mission by holding the first national conference in Power electronics. I thank the sponsors for their valuable contribution. I wish the programme all success.
Dr.S.Karuna
INFO INSTITUTE OF ENGINEERING COIMBATORE MESSAGE Dr.Chitra Manohar Secretary, IIE

The Department of EEE has made Info proud by organizing a National Seminar aiming to disseminate and share advancements in the field of Power Electronics and Industrial Drives. The conference represents our ability to respond to new trends and technical areas in a rapid but systematic manner. The success of the programme is well predicted by the high quality papers received and the eminent resource persons who are eager to judge and guide. This is the right moment to congratulate all my rightly deserving teaching and non teaching staff members for their exuberant work and applaud the volunteers for their enthusiasm and energy. Special Thanks to all our advisory organizations like L&T, NIOT, and NIT and sponsors, Council of Scientific and Industrial Research (CSIR), New Delhi and Vi-Microsystems, Coimbatore, for their continuing support. I wish this technical meet resonates professional vibrations and brings the college to the fore which in turn would result in salutary social opulence.
Dr.Chitra Manohar
PREFACE
Power Electronics is an Engineering discipline where electronics and power semiconductor devices are used to control power drives. Many researchers in R & D organizations and educational institutions have devoted their attention on Power Electronics. The research findings have to be shared by the technocrats for harmonious growth of technology. The national Conferences and symposia are common forums for disseminating knowledge in the chosen field. With such an idea this conference is organized. The department of Electrical and Electronics Engineering, Info Institute of Engineering, Coimbatore, Tamilnadu, organizes the First National Conference on RECENT TRENDS IN POWER ELECTRONICS AND INDUSTRIAL DRIVES on 04-05 March 2010. This conference is targeted towards researchers, professionals and educators, who would be sharing their innovative ideas, and their research findings. Nearly as many as 200 papers were received from different states like Tamil Nadu, Karnataka, Uttar Pradesh, Kerala and Andhra Pradesh. Power Electronics has branched into Semiconductor Devices, Solid State DC Drives, Solid State AC Drives, Applied Electronics, Power Quality, Control Engineering, Energy Conversion and Flexible AC Transmission Systems. Papers have been received in every one of these branches. After review by experts from academia and industry, 114 papers have been selected for presentation. We express our heartfelt thanks to the management of Info institute of Engineering, Patrons Dr.V.Palanisamy, Principal, IIE, Dr. Chitra Manohar Secretary IIE , for the motivation and guidance in organizing this conference and in bringing out this proceedings. We wish to express our sincere thanks to the Chief guests, Chair persons and Technical Experts for being cordial and giving us scope to interact more technically. We are very much thankful to the Technical Programme Committee members for the technical guidance in conducting the conference. Our special thanks are due to the technical reviewers for meticulously selecting the contributed papers. We are indebted to all the organizing committee members and the student volunteers who have worked very hard to compile the materials for the proceedings of PEID2011.
Editors
Coimbatore- 641 107 Tamil Nadu
ABOUT THE COLLEGE

Info Institute of Engineering (IIE) is the fruit of dedicated efforts put in by the DHARBHARI CHARITABLE TRUST and is governed by a team of well known Industrialists, Professionals and Academicians to establish a Centre of Excellence in Engineering and Technology. IIE was established in the year 2007 and has been approved by All India Council of Technical Education (AICTE),New Delhi and is affiliated to Anna University of Technology, Coimbatore. The college is certified with ISO 9001:2000. IIE is a college with a difference. The motto of the college is to enable the students not only to make a living but also to help them live a quality life by developing futuristic skills. The college campus consists of more than 1,35,000 sq.ft.The college located in Kovilpalayam (Coimbatore to Sathyamangalam Main Road), is 17 kms from Coimbatore railway station, 15 kms from central bus stand and 13 kms from the airport and has plenty of bus services in addition to the one provided by the college. The college has a sprawling campus area of 30 acres of unpolluted, serene and quiet land which provides an ideal learning ambience. The spacious and the earth hugging buildings punctuated with landscaped courtyards and pathways are designed to emphasize the business ethics and character of an excellent center for learning. The campus hosts well planned academic blocks, computer centers, lecture halls, libraries, laboratories, conference halls, hostel. IIE has the feel of a friendly, hamlet while offering all the benefits of a citadel of learning.
Quality Policy
To be a centre of excellence in technical education and deliver high profile technicians to satisfy the needs of industries by disseminating vibrant knowledge through specific measurable achievable and time specified goals.
Vision
To develop the institution at par with the international standard and to equip the students with knowledge and skill in tune with the current technological developments with due emphasis on human values and virtues.
Mission
To plan and implement innovative teaching and learning process. To create a congenial atmosphere for the students to stay, study and do research. To tie up with the companies for better industry interaction enabling the students to gain practical knowledge. To appoint highly experienced faculties and make them do dedicated work by meeting their basic needs and other requirements. To have collaboration with Foreign Universities for exchange of knowledge. To invite faculties from reputed Universities in India and abroad The institute offers the following courses on completion of which the students are awarded with Bachelors Degree in Engineering from Anna University of Technology, Coimbatore.
BACHELOR OF ENGINEERING (B.E.) 4 years Mechanical Engineering Electronics & Communication Engineering Electrical & Electronics Engineering Computer Science Engineering
BACHELOR OF TECHNOLOGY (B.Tech.) 4 years Information Technology
MASTER OF COMPUTER APPLICATION (M.C.A.) 3 years MASTER OF BUSINESS ADMINISTRATION (M.B.A)- 2 Years
FIRST NATIONAL CONFERENCE

ON
RECENT TRENDS IN POWER ELECTRONICS AND INDUSTRIAL DRIVES
PEID-2011
Chief Patron
Dr S Karuna Chairperson, IIE
Patrons
Dr V Palanisamy Principal Dr Chitra Manohar Secretary
Convener
Dr A Nirmal Kumar Prof.&Head Department of EEE Mr T Rajesh (Department of EEE)
Co convener
Organizing Secretaries
Ms R Vidhya Ms R Bagyalakshmi (Department of EEE)
Joint Secretaries
Ms K Kalaivani Mr A Anicks Salamon (Department of EEE)
Advisory Board Members PEID 2011

Shri.Radha Raman Vice President Larsen & Tubro,Chennai. Shri.Mohan Narayanan Founder and CEO, KUBOS Consultancy Services, Pvt.Ltd.Chennai,India. Shri. K V K Menon Chief Advisor, NAT-Bangalore. Dr. M A Atmanand Director, NIOT,Chennai. Dr. M R Vikraman Principal, NSS College Of Engineering, Palakkad. Dr. V P Mohan Das Chairman ECE Department, Amrita Institute Of Technology, Coimbatore. Dr. Shree Ram Kumar EEE Department, NIT,Calicut. Dr. K Geetha EEE Department, NSS College Of Engineering, Palakkad. Dr. V Suresh Kumar Dr. V Saravanan EEE Department, Thiagarajar College Of Engineering, Madurai.
Organizing Committee
PEID 2011
Convener
Dr.A.NIRMALKUMAR
Printing, Designing & Proceedings

Staff In-Charges Mr.T.RAJESH Mr. A ANICKS SALOMON Student volunteers S.SENTHIL KUMAR H.A.MOHAMMED ISHAK S.FREDRICK SAMUEL G.NIRMAL
Overall Co-ordination
Staff In-Charge Mr.T.RAJESH
Audio & Video Photography

Staff In-Charges Ms.R BAGYALAKSHMI Ms. K P ANITHA Mr.VIJAY Mr.VIVEK Student volunteers AKSHAY SHARMA G.NIRMAL
Finance
Staff In-Charges Mr.T.RAJESH Student volunteers V.M.RAMAKRISHNAN
Catering
Staff In-Charges Mr. A ANICKS SALOMON Ms. KALAIVANI Student volunteers B.S.THARVEAS MOHIADEEN R.ANANDRAJ K.HARI V.KARTHIKEYAN D.RAVIBABU M.AJMAL A.KAVIN R.V.NIRMAL RAJ P.PRASANTH LUMAN S.KAVIN KUMAR
Editorial Committee
Staff In-Charges Dr.A.NIRMALKUMAR Mr.T.RAJESH
Accommodation
Staff In-Charges Ms. K P ANITHA
Student volunteers S.NISHA T.RAMYA G.MANOCHITRA
Student volunteer K.VIJAYALAKSHMI R.BALAHEMALATHA R.ANANDHI V.M.RAMAKRISHNAN S.MANIRATHNAM R.V.NIRMAL RAJ
Correspondence & Dispatch Staff In-Charges Ms T. RAJESH Ms B PREETHA Student volunteers V.M.RAMAKRISHNAN B.YOGAMEENAKSHI G.MANOCHITRA T.RAMYA
Registration
Staff In-Charges Ms. KALAIVANI Ms R VIDHYA Ms B PREETHA Student volunteers SWAROOP SOMASUNDARAM G.SIDDARTHAN P.SARAVANAKUMAR T.S.ANU S.RESHMI A.V.R.PRANITHA J.DON GURU SHALOM N.SATHYANARAYANAN
Inauguration
Staff In-Charges Mr. A ANICKS SALOMON Ms. K P ANITHA Student volunteers S.NISHA T.RAMYA V.M.RAMAKRISHNAN
Reception
Staff In-Charges Ms B HARINI Ms B PREETHA Student volunteers G.MANOCHITRA R.BALAHEMALATHA G.NIRMAL S.KAVIN KUMAR
Decoration
Staff In-Charges Mr. A ANICKS SALOMON Ms. K P ANITHA Student volunteers M.BALASUBRAMANIAN D.RAVIBABU M.AJMAL K.VIJAYALAKSHMI J.MAADHU INIYA S.SIVASAKTHI A.KAVIN R.V.NIRMAL RAJ P.PRASANTH LUMAN
Moc
Staff In-Charge Ms R VIDHYA Student volunteers U.PANDHALARAJA G.SARANYA DEVI B.PRANESH S.SNEHA DURGA KEVINA LAWRENCE CHETTIYAR JOY M.GOWTHAM
Transport
Staff In-Charges Mr. A ANICKS SALOMON Ms. KALAIVANI Student volunteers P.SUKDEV M.AJMAL
Hospitality & Refreshment Staff In-Charges Ms B HARINI Ms B PREETHA Student volunteers M.A.VISHNUPRIYA C.VIJAYALAKSHMI B.YOGAMEENAKSHI S.AMUTHA L.E.ESWARLAL
Help Desk
Staff In-Charge Ms. S. Dhanalakshmi Student volunteers S.SENTHIL KUMAR H.A.MOHAMMED ISHAK M.BALASUBRAMANIAN J.MAADHU INIYA S.SIVASAKTHI K.VIJAYALAKSHMI N.MOHANKUMAR M.KUMAR
Sessions
Staff In-Charges Ms.R BAGYALAKSHMI Student volunteers C.SAROJ PRIYADHARSHINI S.DEEPIKA M.MALATHI V.PREETHA
Session Incharges
04. 03. 2011 Session 1 A Friday 02.00- 5.15 pm 04. 03. 2011 Session 1 B Friday 02.00- 5.15 pm 04. 03. 2011 Session 1 C Friday 02.00- 5.15 pm 05.03.2011 Session 2 A Saturday 09.45-01.00 pm 05.03.2011 Session 2 B Saturday 09.45-01.00 pm 05.03.2011 Session 2 C Saturday 09.45-01.00 pm Session 2 D 05.03.2011 Saturday 02.00- 5.15 pm Session 2 E 05.03.2011 Saturday 02.00- 5.15 pm Session 2 F 05.03.2011 Saturday 02.00- 5.15 pm Seminar Hall 3
PQ & App. to PS - III
Seminar Hall 1
Power Converter I
Ms R Vidhya
Seminar Hall 2
Power Electronics in Machine Control
Mr A Anicks
Seminar Hall 3
PQ & App. to PS - I
Ms K Kalaivani
Seminar Hall 1
Power Converter I
Ms Preetha
Seminar Hall 2
PQ & App. to PS - II
Ms B Harini
Seminar Hall 3
Applied Electronics I
Ms K P Anitha
Seminar Hall 1
Applied Electronics II
Ms R Vidhya
Seminar Hall 2
Engg. Applications
Mr A Anicks
Ms K Kalaivani
Overall Coordination : Ms R Bagyalakshmi
INVITED CHAIR PERSONS

Session Chair Person Co-Chair Person
1A
Mr. Sakthivel Professor Dept. of EEE KSR College of Engineering Mr.K.Ramesh Professor Dept. of EEE KSR College of Engineering Mr.Satish Kumar Professor Dept. of EEE KSR College of Engineering Mr.Thiruvenkadam Professor Dept. of EEE Dr.Mahalingam College of Engineering & Technology
Ms R Vidhya Assistant Professor Dept. of EEE INFO Institute of Engineering Mr A Anicks Assistant Professor Dept. of EEE INFO Institute of Engineering Ms K Kalaivani Assistant Professor Dept. of EEE INFO Institute of Engineering
1B
1C
2A
Ms R Vidhya Assistant Professor Dept. of EEE INFO Institute of Engineering
2B
Mr.V.Kumarchinnayan Professor and Head Dept. of EEE Jansons Institute of Engineering
Ms.Bagyalakshmi Assistant Professor Dept. of EEE INFO Institute of Engineering
2C
Mr.VijayBaskar Professor Anna University of Technology
Mr.Aravind Assistant Professor Dept. of EEE INFO Institute of Engineering
2D
Mr.Pongiyannan Profesor Department of EEE Bannari Amman Institute of Technology
Ms.Sasipriya Professor Dept. Of ECE INFO Institute of Engineering
2E
Mr.Vijayakumar Professor Dept. of EEE Karpagam College of Engineering
Mr.Anicks Assistant Professor Dept. of EEE INFO Institute of Engineering Ms K Kalaivani Assistant Professor Dept. of EEE INFO Institute of Engineering
2F
Mr.Veerakumar Professor Dept. of EEE Bannari Amman Institute of Technology
CONFERENCE TOPICS
Power Generation, Transmission, Power Quality, Stability and FACTS Application of Power Electronics in the area of Energy Conservation and Automotive applications. Power Market and Power System Economics Artificial Intelligence in Power System, Neurofuzzy and GA based applications. Power Conversion and Energy Management Energy Conservation and Optimization in Process Industries HVDC Transmission and Electric Drives Power System Protection, Operation and Control and SCADA/PLC System. Digital Control of Industrial Process and Industrial Automation. Alternative Energy Sources of Power Generation. Renewable and Non-Renewable Energy Sources. Value Engineering growth and its prospects in Indian Scenario. Remote Sensing, Telemetry, Instrumentation, Signal processing and Nano-Technology
Recent Advances in Power Electronics and Industrial Drives PEID 2011

March 04-05, 2011
PROGRAMME SCHEDULE
Time
Seminal Hall 1 DAY 1: FRIDAY MARCH 04, 2011

Registration Inaugural Function Tea Break Keynote Address Lunch Break
Seminar Hall I Session IA Power Converters - I Seminar Hall II Session IB Power Electronics in Machine Control Seminar Hall III Session IC Power Quality & Application to Power Systems-I
09.15 am to 10.15 am 10.15 am to 11.50 am 11.50 am to 12.05 noon 12.05-01.00 pm 01.00 pm to 02.00 pm
Time
Session IA, 1B, 1C 02.00 pm to 5:15 pm
(3.30 pm- 3.45 pm -Tea Break)
Day 2:
Time
Session 2A, 2B, 2C 09.45 am to 01.00 pm
(11.15 am to 11.30 am-Tea Break)
SATURDAY MARCH 05, 2011

Seminar Hall II Session 2B Power Quality & Application to Power Systems -II Lunch Break Session 2D Applied Electronics-II Session 2E Engineering Applications Session 2F Power Quality & Application to Power Systems -III Seminar Hall III Session 2C Applied Electronics-I
Seminar Hall I Session 2A Power Converters - II
01.00 pm to 2.00 pm Session 2D, 2E, 2F 02.00 pm-5.15 pm

(3.30 pm- 3.45 pm -Tea Break)
PEID 2011 SCHEDULE
Schedule for Paper Presentation

Session 1A Power Converters I March 04, 2011 (02:00- 05.15 pm)
A 9 Level Cascaded Multilevel Inverter Using Transformer Connections ----------------------------------(1) K.Mahendran, P.Karuppusamy A Bidirectional DC-DC Converter For Renewable Energy Applications ----------------------------------------(7) T.K.Santhosh, K.Yamuna A Double-Ended Zero Voltage Switching Full-Bridge Zeta Converter-----------------------------------------------(13) R.Leelavathy ,S.Sugumar A Neuro Fuzzy Based MPPT Controller with DC-DC Converter----------------------------------------------------(19) P.Suresh Muthukumar ,K.Manikandan A Novel Isolated Bidirectional Full-Bridge DcDc Converter With A Fly back Snubber --------------------(24) Kata Naresh ,J.LakshmanaPerumal A soft-switching dc-dc converter with high Voltage gain ----------------------------------------------------------------(30) M. Indira priyadarshini, S. Komala chitra, P. Moorthy Analysis of Matrix Converter with Direct Driven Permanent Magnet Generator-----------------------------(35) K.Lalitha , R. Bharanikumar , A. Nirmal Kumar Design and Real Time Implementation of Integrated Fuzzy Logic Controller for a High Speed PMDC Motor-----------------------------------------------------------------(41) S.Sivasakthi ,K.Vijayalakshmi,J.Maadhu iniya Design and Analysis of Soft Switching Boost converter for Photovoltaic Applications-----------------------------(45) B.Saravanakumar, P.Sivaraman Design And Analysis Of Zero Voltage Switching DC-DC Converter With Synchronous Rectifier------------------(51) E.Sathishkumar, B.Shanthibhushan A Nona-Switch Inverter Employing Space Vector Modulation for Independent Control of Two Motors-(56) P.Arthi,N.Leena
Paper Code
1A.001
Paper Code
1B.001
Session 1B Power Electronics in Machine Control March 04, 2011 (02:00- 05.15 pm)
Design and Implementation of Front-End Converter for Switched Reluctance Motor Drive------------------------(61) A.Pradeep, J.Karpagam, E.Kannapiran Direct Torque Control Of Induction Motor Drive Using Matrix Converters-------------------------------------------(67) M.Suresh, J.Karpagam, Dr.A.Nirmal Kumar Dynamic Model Analysis of Induction Motor----------(73) Steffi Kuriakose, S.Veerakumar FPGA Based AC Motor Control for Closed Loop Application (Comparison, Consideration & Implementation) --------------------------------------------(80) G.N.Nandish,Chethan D Raj Impedance Source Inverter for Wind Turbine Driven Permanent Magnet Synchronous Generator-------------(87) V Kandhasamy,T.Muthukumar Multilevel Inverter fed Induction Motor Drive with DTC control---------------------------------------------------------(92) S.Kaviya , P.Karuppusamy Neural Network Based Torque Ripple Minimiztion of BLDC Motor------------------------------------------------(98) M. Raja Nandakumar, S. Nellaiyappan, R. Shanmuga sundaram Neuro Fuzzy Based Speed Control Of Dc Motor Using Wavelet Transform Comparison With PID- Particle Swarm Optimization Strategy---------------------------(105) Sourabh Kumar Jain, Hemant Amhia Novel Voltage Controller for Stand Alone Induction Generator using Modified Sinusoidal PWM VSI---(112) Sujitha C, Premalatha K Pspice Approach for Space Vector Pulse Width Modulation for Induction Motor Drive-----------------(117) M.Sasikumar S.VeeraKumar, Dr.A.Nirmal Kumar Sensor less Control of Brushless DC Motor Using Modified Back-EMF Detection--------------------------(123) S. Nellaiyappan, M. Raja Nanda Kumar, R. Shanmuga Sundaram Simulation of Three Phase Matrix Converter Fed Induction Motor Using Space Vector Modulation----(127) Isvaria.A,J.Karpagam,Dr.A.Nirmal Kumar Maximum Power Point Tracking Controller for Wind Turbine Driven Permanent Magnet Generator for ZSource Inverter---------------------------------------------(135) M.Manimekala, R.Bharanikumar
1A.002
1B.002
1A.003
1B.003
1A.004
1B.004
1A.005
1B.005
1A.006
1B.006
1A.007
1B.007
1A.008
1B.008
1A.009
1B.009
1A.010
1B.010
1A.011
1B.011
1B.012
1B.013
PEID 2011 SCHEDULE
Paper Code
1C.001
Session 1C Power Quality & Application to Power System - I March 04, 2011 (02:00pm- 05.15 pm)
An Intelligent Electrical Power System To Perform Multi Tasks Using Zigbee---------------------------------------(141) Anu T S, Arthi Sahaya Rones , Mohana Jothi S, Nallasivam N Autonomous Hybrid Renewable Energy System for Smart Grid Application----------------------------------(145) J.Vasanthakumar,V.Sharmila Deve Carrier Based Z-Source Inverter for Uninterruptible Power Supplies--------------------------------------------(150) K. Chitra ,R. Senthilkumar Consideration and Implementation of Photovoltaic Power supply for Low power drives----------------------------(157) Magal Chaithra, Megha Arora Control of Power in a Transmission System Using DFACTS Devices-------------------------------------------(162) Mereya Baby,R.Thilepa Design and Application for PV Generation System Using a Soft-Switching Boost Converter with SARC-------(168) Balamurugan.T, S.Arunkumar Design and Implementation of Four Wire Inverter for UPS Applications-----------------------------------------(174) T. Alex Stanley Raja, R. Senthil Kumar, Dr.Jovitha Jerome Design and Implementation of FPGA Based Resonant Inverter For UPS Application---------------------(181) K.Seetharaman, R.Senthikumar Digital Simulation Of Multi-Level Inverter Based Dynamic Voltage Restorer------------------------------(188) N S Sakthivel Murugan Dynamic Stability Of Power System Using Advanced Intelligent Controller-------------------------------------(193) D.Sabapath , S.Periyanayagi ,M. Valarmathi Design And Simulation Of UPQC To Improve Power Quality And Transfer Wind Energy To Grid---------(199) G.T.Ganesh kumar, G. Srinivasan, P.Moorthy Energy Conservation and Optimization in Process Industries---------------------------------------------------(205) Ayyappan.S , Saravanan.T Interline Dynamic Voltage Restorer An Economical Way to improve Power Quality-------------------------(207) N. Naveen Kumar , S. Kavitha An Adaptive Hysteresis Band Current Controller Based Active Power Filter For Harmonic Suppression And Reactive Power Compensation--------------------------(213) T Rajesh V.M Ramakrishnan R. Balahemalatha S.Nisha
Paper Code
2A.001
Session 2A Power Converters II March 05, 2011 (09:45am- 01.00pm)

High-Efficient Multilevel Half-Bridge Converter----(223) R.Anugraha ,G.Vijayakumari
1C.002
2A.002
Implementation of a High-Efficiency Full-Bridge SingleStage Converter With Reduced Auxiliary Components------------------------------------------------------------------(228) R. Sathiya priya, S. Lakshmi High efficient single phase PFC converter-------------(233) K.Preetha Implementation of Matrix Converter for Controlling Input Voltage Variations----------------------------------------(239) B Balabharathi ,S Chinnaiya Implementation of Resonant Inverter with Inbuilt Boost Converter---------------------------------------------------(246) M. Gayathri,J.Baskaran,P.Tamizharasi Implementation of Space Vector Modulation for Voltage Source Inverter --------------------------------------------(252) T.A Liphi ,R. Senthil Kumar Neuro-Fuzzy Controller for Non-Linear Buck and QuasiResonant Buck Converter--------------------------------(256) A.Rameshkumar, Dr.S.Arumugam Study on Transient Stability of a Power System Using Series Compensator---------------------------------------(265) Mayank Gupta , KK Mishra Unity-Power-Factor Operation Based On Boost Active Clamp Topology------------------------------------------ (270) S.Bharath, R.Vibin ZVS based high-efficient half-bridge converter-------(276) S.Subramanian ,T.Suganthi Modeling and Simulation of 3 phase Induction Motor under dynamic load conditions--------------------------(282) Snehaprabha T V , Suresh Kumar P , Dr. Sanjay L
1C.003
2A.003
1C.004
2A.004
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2A.005
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2A.006
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2A.007
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2A.009
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1C.011
2A.011
1C.012
1C.013
1C.014
PEID 2011 SCHEDULE
Paper Code
Session 2B Power Quality & Application to Power System-II March 05, 2011 (09:45- 01.00pm)
Hydrogen clean fuel for production of energy for Sustainable development--------------------------------(287) K.Vinoth Kumar , Kavya Venugoplan , Nimmy Joseph Implementation of multilevel inverter topology for PV cell application--------------------------------------------(293) V.Srimaheswaran, J.Karpagam, R.Uthirasamy and Dr.A.Nirmal kumar Implementation of Simple MPPT Algorithm for PV Cell and SEPIC Converter--------------------------(299) K.P.Santhi , P.Sivaraman , Dr.A.Nirmal Kumar Intercell Transformer Based Converter for Renewable Energy Application---------------------------------------(305) R.Malathy , J.Baskaran ,C.Sharmeela Mitigation of Back-Flashovers for 110-kV Lines at Multi-Circuit Overhead Line Towers------------------(310) A.Brighty Deborahl,M.Shanmugapriya, B.Subhanandhini Modeling and FEM Analysis of Surface Mounted Permanent Magnet Generator for Wind Energy Conversion System---------------------------------------(319) R. Ashok Kumar, R. Bharanikumar Modified of 11 Level Cascaded H-Bridge Dc To Ac Grid Tied Inverter Interface With Solar Photo Voltaic Cell-------------------------------------------------------------------(324) Dr.S.Senthilkumar,M.Sathishkumar Novel Single Phase Grid Connected Inverter for Photovoltaic Modules------------------------------------(330) Santhosh.C Akila.R Optimized Power System Design with Help of Evolutionary Computing---------------------------------(334) P.Harikrishnan, N.S.Suresh Power Conversion Stage Reduction Using Z-Source Inverter with Different PWM Control Schemes for Wind Energy Conversion System-----------------------------(340) B.Indhumaty, R. Bharanikumar, A. Nirmal Kumar Power control using UPFC system--------------------(346) N.Muralidharan, Sudhi.M.M Power Quality Monitoring and Control----------------(352) K.Nathiya, P.Divyapriya
Paper Code
Session 2C Applied Electronics I March 05, 2011 (09:45am-01:00pm)
2B.001
2C.001
A New Mechanism of Track Design for an all Terrain Mobile Robot and its Applications----------------------(369) R.Elamurugu Alias Gokul , M.Dhivya Air Pollution Monitoring System Using Zigbee------(375) D.Kalanithi ,K.N.Vijeyakumar
2B.002
2C.002
2B.003
2C.003
An Efficient Throughput Algorithm For Multichannel Wireless Mesh Networks---------------------------------(380) K.Mohanapriya , V.G.Pratheep Analysis of Non Invasive Pulse Oximetry With Single Light Source Using Fourier Series And Soft Computing Techniques------------------------------------------------- (384) R.Mouleeshuwarapprabu , P.Hari Krishnan Design of ALUs Using Adaptive Clock Stretching----(389) Bavithra.T , Sakthivel.P
2B.004
2C.004
2B.005
2C.005
2B.006
2C.006
Design of Parallel Mac Architecture Based On Modified Booth Algorithm--------------------------------------------(400) D.Kowsalyadevi , K.Ayyar Design Of Wimax Transceiver Module Using Rs & Viteribi------------------------------------------------------(406) Vennilapriya.B, M.Srinivasan Digital Subtraction Angiography In Heart and Brain Diagnostics Using Labview------------------------------(410) R.Naveeth Kumar, P.Hari Krishnan Enhancement of Optic Cup To Disc Ratio Detection In Glaucoma Diagnosis--------------------------------------(414) D. Sasirekha , A. Murthi A Low Power Double-Edge Triggered Direct Data Clocked Pair Shared Flip-Flop-------------------------- (420) B.Kousalya Low Power High Performance Dual Match Line For Mobile Devices------------------------------------------- (427) S.Umaiyal, S.Deepa
A Low Power Design SRAM Using Self-Controllable Voltage Level (Svl) Technique---------------------------------------------(434) S.Chinnu Kanchan, S.A.Aswathi, B.Deepan Raj S.Balakrishnan
2B.007
2C.007
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2C.008
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2C.009
2B.010
2C.010
2B.011
2C.011
2B.012
2C.012
2B.013
Reduction Of Harmonics In Integrated Power Factor Correction Stage With High Efficiency Dc-Dc Converter---------------------------------------------------------------(358) V.Karthika, J.Lakshmanaperumal Power Quality Enhancement In Distribution Systems Using USSC-----------------------------------------------(364) T.Rajesh , T.Ramya, G.Manochitra
2B.014
PEID 2011 SCHEDULE
Paper Code
2D.001
Session 2D Applied Electronics II March 05, 2011 (02:00- 05:15 pm)

Image Segmentation by Using Fuzzy Measures------(439) S.Deiva Santhalyn Mercy, P.Hari Krishnan
Paper Code
2E.001
Session 2E Engineering Applications March 05, 2011 (02:00- 05.15 pm)

Adaptive Neuro Fuzzy Control of Flexible Joint Robot Manipulator------------------------------------------------(503) P. Hari Krishnan, A. Johnson Antony Data Driven Quality Prediction In A Refining Process Using Advanced Optimization Technique-------------(508) P.Hari Krishnan , V G Hari Hara Sudhan Model Based Predictive Control For Membrane Bioreactor In Sewage Water Treatment----------------(514) P.Hari Krishnan , D.Deena Robotic Surveillance For Patient Care In Hospitals--(520) D.Sudarvizhi,Aamani Janga,Aleena Mary Cherian
2D.002
Low-Power D-BCT Decoder For Wi-Max Using Neural Networks---------------------------------------------------(444) Gayathiri.S , S.Saravanan Optimized Threshold In Image Segmentation Using Fuzzy Measures-------------------------------------------(452) Nishamary.P , S.Saravanan Robust De-Noising With Extraction of P-Wave ,T-Wave, R-Peak And QRS Complex In Normal Electrocardiogram and Analysis With The Abnormal Electrocardiogram Using Wavelet Transforms------------------------------(458) R.Vinoth Kumar , P.Hari Krishnan Runtime Partial Reconfiguration of FIR Filter-------(465) M. Mubarak Ali, R. Arun Software Power Estimation for Microcontroller Instruction Set---------------------------------------------(468) M.Mohamed Asan Basiri , N.Kumaresan Zig Bee based Monitoring of Leg Ulcers--------------(473) M.Dhivya , A.Sugantha priyan Low Power Design Based On Variable Input Delay CMOS Logic----------------------------------------------(478) Kamali.B ,P.Rajasekaran Signal Processing With Sensor Measurements-------(484) R.Senthil Kumar , S.Saravanan , Vijay Sridharr.V.Sandip, S. Saikumar EEG Analysis of Hearing Impaired Children---------(490) R.Dhivya , S.Thiruvenkadam
2E.002
2D.003
2E.003
2D.004
2E.004
2D.005
2E.005
Application of Intelligent Systems in Model Order Reduction---------------------------------------------------(525) S.Priya, K.Ramesh
2D.006
A Automation In Textile Looms Using Digital Signal 2E.006 Processor---------------------------------------------------------(531) S. Arunmozhi, J.Amutha 2E.007 2E.008 Nano Generators-------------------------------------------(534) S.Saravanakumar,G.Yadav An Embedded System for Underwater Imaging Application-------------------------------------------------(541) Deepak N, Dr.Dhilsha Rajappan, M Valarmathi Multi Purpose Identification Card Using Embedded System------------------------------------------------------ (546) A.Jagadeesan, P.Boorani, V.Sowmiya , K.Karthiga Smart Purchase In Supermarkets Using RFID System------------------------------------------------------------------- (550)
A.Jagadeesan, G.Vikashini, T.S.Yuvashree, K.Selvi, S.Sathyapriya
2D.007 2D.008
2D.009
2E.009
2D.010
2E.010
2D.011
Transmission Reduction Algorithm For Wireless Sensor Networks--------------------------------------------------------------(494) Deepa.K , Sathish kumar.M Wavelet Based Multilevel Image Restoration--------(499) S.Karthika, J.Amudha
2 E.011
Automation of Boiler In Diesel Power Plant Using Scada( 554 ) K.Geetha, Megha Murali, Nimitha M, Remyamol, Sidhin K.S, Titto Thomas
2D.012
2 E.012
Energy Efficient Management in Home Networks Using Network Protocol Agent----------------------------------(558) S.Hariprasad , N.Kumaresan Autonomous Aircraft----------------------------------- (564)
K.Geetha, Sreejesh, Sreejith, Soumya, Shobita, Nideesh Kumar and Nitin K Salim D.Josephine Selvarani Rut, P.Hari Krishnan
2E.013
2E.014
Automation on PLC Furnace System-------------------(570)
PEID 2011 SCHEDULE
Paper Code
Session 2F Power Quality & Application to Power System III

March 05, 2011 (02:00- 05.15 pm)
Three Port Series Resonant DC-DC Converters To Interface Renewable Energy Sources With Bidirectional Load And Energy Storage Ports------------------------(575) N.Hemalatha, P. J. Vijayakumari P.Moorthy, K.Rajeswaran Two Leg Voltage Source Converter For Voltage And Frequency Control In Standalone Wind Power Generation-------------------------------------------------(581) K.Gurumoorthi , K.Premalatha Voltage Profile Improvement In Distribution System With Distributed Generation----------------------------(587) Dr.N.Shanmugavadivoo ,M.Mahin Abubakkar Conservation of Energy Losses in Snubber through Energy Recovery Method--------------------------------(593) M.Thenthamizh , R.Thangam, J.Baskaran
Session 2F Power Quality & Application to Power System III

March 05, 2011 (02:00- 05.15 pm)
2F.008 Design and implementation of a hybrid regenerative power system combining gridtie and uninterruptible power supply functions of three phase system--------(616) D. Rajalakshmi , N.Vikranth
2F.001
2F.002
2F.009
Comparison of Modified Z Source Inverter and Voltage Source Inverter for PV Cell Application--------------(623)
Kohila.J, P.Sivaraman,, Dr.A.Nirmal Kumar
2F.003
2F.010
Fault Detection and Diagnosis for CLBs and Interconnect Resources in FPGA---------------------------------------(628)
Maya T Govind, S.Thiruvenkadam
2F.004
2F.011
An Integrated Four Port DC/DC Soft Switching Boost Converter with SARC for Renewable Energy Applications-----------------------------------------------(633) N.Dhivya Devi , R.Radika,J.Baskar Solar Air Conditioner Using Nitrogen Gas as Coolant------------------------------------------------------------------(640) Amrutharaj.M, Camelia Sengupta, Reshma Maria George
2F.005
Selective Harmonic Elimination (SHE) in Switching Voltage Waveforms of Power Converters Using Passive filters--------------------------------------------------------(598) Beena . S
2F.012
2F.006
Novel Circuit Configuration for Reactive Power Compensation in Induction Generator-----------------(601) G.Suresh,K.Malarvihzi Application of Wavelet Multi resolution Analysis For Classification And Location Of Faults On Transmission Lines--------------------------------------------------------(610) I Andrews Juben Ratchanyaraj
2F.013
Analysis of Power Converter Used in Wind Energy System ---------------------------------------------------(644) A.Edwin Isaac Raj, S.Ganesan A Soft-Switching Current Driven Full Bridge Pwm Dc/Dc Converter With Snubber Circuit ---------(651) P.Yuvaraj
2F.007
2F.014
PEID 2011 SCHEDULE
Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore
A 9 Level Cascaded Multilevel Inverter Using Transformer Connections

K.Mahendran, P.Karuppusamy Department of Electrical and Electronics Engineering Bannari Amman Institute of Technology, Sathyamangalam, Erode. mahae1987@gmail.com
Abstract: The research on multilevel inverter in these days for various applications goes on rapidly due to its efficient operation. The project proposes an advanced cascaded multilevel inverter which varies from the conventional one from the number of input dc sources used. The proposed nine level multilevel inverter configurations utilize a single dc source whereas in the conventional one it varies based on the number of levels. The single phase transformer is replaced by the three phase linear transformer to reduce the transformer number. The circuit simulation is mode using MATLAB/Simulink software and the performance analysis is made based on the factors like THD, efficiency, cost effectiveness, etc. Keywords--Cascaded multilevel inverter, harmonics, switching Phase angle control, three-phase transformers.
switching frequency, their efficiency is high (>98%) because of the minimum switching frequency, they are suitable for medium to high power applications, multilevel waveform naturally limits the problem of large voltage transients. The selection of the best multilevel topology for each application is often not clear and is subject to various engineering tradeoffs. The different multilevel topologies are, Diodeclamped multilevel inverter, Capacitor-clamped multilevel inverter and Cascaded multilevel inverter. II. DIODE CLAMPED MULTILEVEL INVERTER The first practical multilevel topology is the neutral point clamped PWM technology first introduced by Nabe, et al, in 1980. For m-level inverter, dc bus voltage is splits into m levels by (m-1) series connected bulk capacitors. Here, diodes clamp the switch voltage to half the level of the dc bus voltage, which is an added advantage of this type. The advantages of the diode clamped multilevel inverter topology are: When the number of levels is high enough, the harmonic content is low enough to avoid the need for filters, inverter efficiency is high. The disadvantages of the diode clamped multilevel inverter topology are: excessive clamping diodes are required when levels are high, the issue of maintaining the charge balance of the capacitors is still an open issue for NPC topologies with more than three levels. III. FLYING CAPACITOR MULTILEVEL INVERTER This topology was first proposed in 1992 and is considered to be the serious alternative to the diode clamped topology. In addition to improving the waveform quality, these multilevel inverters substantially reduce voltage stress on the devices. However in this type of inverters the required voltage blocking capabilities of the clamping diodes at higher levels is high. So an alternative multilevel structure where the voltage across an open switch is constrained by clamping diodes has been proposed by Meynard. These inverters are commonly known as flying capacitor. This makes the topology attractive even for the dc/dc conversion. At the present time it seems that this topology has few advantages like: Large amount of storage capacitors can provide capabilities during power outages, Like diode
I.INTRODUCTION Numerous industrial applications have started utilizing high power applications in recent years. Some medium voltage motor drives and utility applications require medium voltage and mega watt power level for a medium voltage grid; it is troublesome to connect directly a single switch. As a result, multilevel power converter (both rectifiers and inverters), has been introduced as an alternative in high power and medium voltage situations. The concept of multilevel inverters has been introduced since 1975. The term multilevel starts with the three level inverters. Multilevel inverters include an array of power semiconductors and capacitor voltage sources, the output of which generates voltages with stepped waveforms with less distortion, less switching frequency, higher efficiency, lower voltage devices and better electro-magnetic compatibility. A multilevel inverter not only archives high power ratings, but also enables the use of renewable energy sources. Renewable energy sources such as photo voltaic, wind and fuel cells can be easily interfaced to a multilevel inverter (converter) system for a high power application. The multilevel power converters can be referred as voltage synthesizers in which high output voltage is synthesized from many discrete smaller voltages levels. The advantage of multilevel converters when compared to other converters can be listed as follows: they can generate output voltages with extremely low distortion and lower (dv/dt), they draw input current with very low distortion, they can operate with a lower
2
is determined by the input voltage and turn ratio of the transformer. Usually, a traditional cascaded H-bridge converter employs a multipulse isolation transformer to obtain the input dc source. When the traditional cascaded H-bridge converter needs to isolate from the ac output, it requires a three-phase transformer between the inverter and the ac outputs. On the other hand, the proposed inverter has an advantage of galvanic isolation between the source and the output voltages, which comes from being combined with transformers. VI. THREE PHASE CASCADED H-BRIDGE MULTILEVEL INVERTER Fig. 2 shows a circuit configuration of the proposed multilevel inverter for three-phase applications. It consists of one single dc input source and several low-frequency threephase transformers. By using the three-phase transformers, the number of transformers and the volume of system can be reduced. As a result, the price of the system is deservedly down.
clamped inverters, when the number of levels is high enough, the harmonic content is low enough to avoid the need for filters, Both real and reactive power flow can be controlled. Some of the disadvantages of flying capacitor topology are: Excessive number of storage capacitors is required, the inverter control can be very complicated. IV. CASCADED MULTILEVEL INVERTER This topology employs a cascade of low voltage Hbridges each with independent and isolated dc sources. The phase output voltage is synthesized by the sum of series of H-bridges plus one. One major advantage of this approach is that the number of the output can be further increased without addition of any new components, requiring only the dc sources with different voltage levels. The advantages of the cascaded multilevel H-bridge converter are the following: The series structure allows a scalable, modularized circuit layout and packaging due to the identical structure of each H-bridge, no extra clamping diodes or voltage balancing capacitors is necessary. The main disadvantage of this topology is that it needs separate dc sources for real power conversions, thereby limiting its applications.
Fig 2 Circuit Configuration of Three Phase Multilevel Inverter Fig 1 Cascaded multilevel inverter with independent DC source
V. SINGLE PHASE CASCADED MULTILEVEL INVERTER Four H-bridge modules are connected to the same dc input source in parallel, and each secondary of the four transformers is connected in series. In this configuration, the output voltage becomes the sum of the terminal voltages of each H-bridge module. The amplitude of the output voltage
Each primary terminal of the transformer is connected to an H-bridge module so as to synthesize Vdc, zero, and Vdc. Every secondary of the transformer is connected in series to pile the output level up. Moreover, each phase terminal is delta connected to restrain the third harmonic component. In this configuration, each phase can be expressed independently, and we call each phase multilevel inverter as isolated H-bridge cascaded multilevel inverter. Therefore,
3
generation of M-level outputs. A cascaded H-bridge inverter needs [(M 1)/2] 3 4 number of switches and [(M 1)/2] 3 number of independent dc sources.
the relationship between the input and the output voltages of the three-phase transformer is given as
VAK 2 -1 -1 Vak T VBK = . -1 2 -1 . Vbk 3 -1 -1 2 Vck VCK
(1)
V AS= V Ai
i=1 k
where T is the transformation ratio (n2/n1) between the primary and the secondary of the transformer. If the input voltage is balanced in three phases, the sum of each phase voltage becomes zero
V BS= V Bi
i=1 k
(5)
V ak+V bk+V ck = 0
From (1) and (2), the output voltage is expressed as
V CS= V Ci
i=1
(2)
V AK V ak V BK = T . V bk V CK V ck
Generally, the conventional multilevel inverters use a circulating switch pattern in order to maintain the same ratio in switch utilization.
Table: 1 Component Comparison of Nine Level Conventional Multilevel Inverter Topologies with the Proposed One.
(3)
From (3), we can notice that each phase output voltage of the transformer is given by the product of each phase input voltage and turn ratio of the transformer. However, in the proposed circuit configuration, it is often unbalanced in three phases because the primary of the transformer is connected to an H-bridge cell generating Vdc, zero, and Vdc. It means that the output voltage is balanced at Vak = VDC, Vbk = VDC, and Vck = 0; however, when Vak, Vbk, and Vck are all VDC, the output voltage is unbalanced. Therefore, the proposed circuit relies on (1) instead of (3). Equation (1) has been expressed by the magnetic concept. For example, a formed flux at the primary of phase a will be equally influenced on phases b and c. Assuming that the quantity of the formed flux is two, the flux of both phases b and c becomes 1. By this concept, we can include the unbalanced relationship to (1). As shown in Fig. 4, the output voltage of the proposed multilevel inverter is synthesized by the series-connected secondary of the transformer outputs. Hence, line voltages VAB, VBC, and VCA can be given by
Component
Diode clamped
Flying capacit ors

36 0 210 1 1
Convent ional Cascade d Hbridge

72 0 18 18 1
Propose d Cascade d Hbridge

36 0 1 1 4
Switch Diode Capacitor Input DC source Output transformer
36 396 4 1 1
VAB VAS VA1+VA2+....VAk VBC = VBS = VB1+VB2+....VBk VCA VCS VC1+VC2+....VCk

The aforementioned equation can be rewritten as
(4)
We can find that a diode-clamped multilevel inverter needs (M 1).(M 2).3 number of diodes to generate M-level outputs. In the case of a flying capacitor, it requires [(M 1)(M 2) 3]/2 + (M 1) number of capacitors for the
Therefore, they employ switches which are equivalent in the voltage and current ratings. Assuming that the magnitude of the output voltages and output power are equivalent, the voltage ratings of each switch are determined by the number of series-connected switches. Consequently, we can say that the proposed method is more advantageous in switch cost and system size compared with the conventional approaches because the proposed method can reduce the number of switches. In addition, usually, these traditional multilevel inverters employ a three-phase low-frequency transformer at the output terminal for a high-power grid connection. In this point, the proposed circuit topology has a valuable merit. Considering that the output voltage is synthesized by an accumulation of each transformer output, it does not require an additional transformer for galvanic isolation. Although the proposed scheme needs three three-phase transformers, the cost and size will be slightly increased because the capacity of the transformer is 1/3 of the transformer which is applied to the conventional method.
VII. SIMULATION RESULTS The conventional and the proposed multilevel inverter are designed and simulated using MATLAB/Simulink tool. The PWM scheme employed to control the inverter is the single phase cascaded multilevel inverter is analyzed based on different loading conditions. Fig 4 represents the output voltage of the single phase cascaded multilevel inverter when running a pure resistive load and RL load of about 1kW. This can be eliminated by using proper harmonic filter circuit. Fig 4 (b) represents the output voltage with RL load without any filter circuit. And fig 5 (a) (b) holds the harmonic spectra of the output voltage at R and RL load respectively.
(a)
(b) Fig 5 Harmonic Spectrum of the Single Phase Cascaded Multilevel Inverter Output Voltage at (a) Pure Resistive Load (b) RL Load
Fig .4. Simulation Model for single phase Advanced Cascaded Multilevel Inverter
The performance of the three phase cascaded multilevel inverter with single dc input is analyzed under different loading conditions. The output voltage and current obtained when driving a pure resistive load is given in fig 6.
(a)
(a)
(b)
Fig 4 Output Voltage of the Proposed Single Phase Cascaded Multilevel Inverter with (a) Pure Resistive Load (b) RL Load- 1kw
(b) Fig 6 (a) Three Phase Output Voltage at Pure Resistive Load (b) Three Phase Output Current at Pure Resistive Load
The corresponding harmonic spectrum of the three phase cascaded multilevel inverter at R load with respect to voltage and current is given in fig 7.
(b) Fig 8 (a) Output Voltage at RL Load of 1kW (b) Output Current at RL Load of 1kW
(a)
The corresponding harmonic spectrum and % of THD in the output voltage and current when driving an RL load of 1kW is depicted in fig 9.
(b) Fig 7 Harmonic Spectrum of Three Phase Cascaded Multilevel Inverter at R load (a) Output Voltage Harmonics (b) Output Current Harmonics
(a)
The output voltage and current obtained when driving a RL load is given in fig 8.
Fig 9 (a) Output voltage THD when Driving RL Load of 1kW (b) Output Current THD when Driving RL Load of 1kW (a)
6
[9] B. P. McGrath, T. A. Meynard, and G. Gateau, Optimal Modulation of Flying Capacitor and Stacked Multicell Converters Using a State Machine Decoder, in Proc. IEEE PESC, Jun. 1216, 2005, pp. 16111677. [10] Jeyraj Selvaraj and Nasrudin Rahim A, Multilevel Inverter for Grid-Connected PV System Employing Digital PI Controller, IEEE Transactions on Power Electronics, Vol.56, No.1, pp 149-158, Jan 2009.
VII.CONCLUSION The proposed nine level cascaded multilevel inverter is simulated in MATLAB/Simulink software using single dc source. The THD value both on current and voltage parameters are reduced comparatively with the conventional multi level inverter topology. Also the reduction in number of dc source also adds advantage to the system. Consequently, the efficiency of the system improves relatively with the conventional multilevel inverter configuration.
REFERENCES
[1] J. Rodriguez, J. S. Lai, and F. Z. Peng, Multilevel Inverters: A survey of Topologies, Controls, and Applications, IEEE Transaction an Industrial Electronics, vol 49, no. 4, pp. 724738, August 2002. [2] K. A. Corzine, M. W. Wielebski, F. Z. Peng, and J. Wang, Control of cascaded multi-level inverters, Electronics Machine Drives Conference Proceedings, vol 3, pp. 15491555, June 2003. [3] F. S. Kang, S. J. Park, S. E. Cho, C. U. Kim, and T. Ise, Multilevel PWM Inverters Suitable for the use of Stand-Alone Photovoltaic Power systems, IEEE Transactions Energy Converters, vol 20, no. 4, pp. 906915, December 2005. [4] M. Calais, V. G. Agelidis, L. J. Borle, and M. S. Dymond, A Transformer Less Five Level Cascaded Inverter Based Single Phase Photovoltaic System, IEEE Power Electronics Spectrum Conference Proceedings, pp. 11731178, November 2000. [5] F. S. Kang, S. J. Park, M. H. Lee, and C. U. Kim, An Efficient Multilevel Synthesis Approach and its Application to a 27-Level Inverter, IEEE Transactions Industrial Electronics, vol 52, no. 6, pp. 16001606, December 2005. [6] D. Soto, R. Pena, L. Reyes, and M. Vasquez, A Novel Cascaded Multilevel Converter with a Single Non-Isolated DC Link, IEEE PESC Proceedings, vol. 4, pp. 16271632, January 2003. [7] Sung Geun Song, Feel Soon Kang, and Sung-Jun Park, Cascaded Multilevel Inverter Employing Three-Phase Transformers and Single DC Input IEEE Transactions on Industrial Electronics, vol 56, no. 6, June 2009. [8] Farid Khoucha, Soumia Mouna Lagoun, Khoudir Marouani, and Mohamed El Hachemi Benbouzid, Hybrid Cascaded H-Bridge Multilevel-Inverter Induction-Motor-Drive Direct Torque Control for Automotive Applications, IEEE Transactions On Industrial Electronics, Vol. 57, MARCH 2010.
BIOGRAPHIES
K.Mahendran received his B.E degree in Electrical & Electronics Engineering from Anna University Chennai in the year 2009. Currently he is pursuing his master degree in Bannari Amman Institute of Technology affiliated to Anna University of Technology, Coimbatore. His field of interest includes Power Converters and Renewable Energy Resources. P.Karruppusamy received his B.E degree in Electrical & Electronics Engineering and M.E Power Electronics and Drives from Anna University, Chennai. Currently he is pursuing his PhDin Anna University of Technology, Coimbatore. His field of interest includes Power Electronics and Electrical Machines.
A Bidirectional DC-DC Converter For Renewable Energy Applications

T.K.SANTHOSH
PG scholar K.S.R. College of Engineering Tiruchengode. tksanthosh.kct@gmail.com
K.YAMUNA
Asst.Professor, EEE Department. K.S.R. College of Engineering Tiruchengode. yamuna_kris@yahoo.co.in with low losses and with minimum use of capacitors need to be developed. This paper presents a novel ZVS-ZCS bi-directional DCDC converter. The new converter is based on a dual halfbridge topology with an auxiliary circuit in primary side. It has the advantages like low EMI, low switching stresses, low switching losses compared with ZVS bi-directional DC-DC converter. The ZCS topology removes the turn-off current tail of the main switch. The ZCS operation is obtained by both forcing the primary current towards zero and delaying its raise, or by resetting the primary current before the corresponding switch turned off. The ZVS-ZCS bi-directional DC-DC converter has been simulated and developed for rectification and inversion operations in both buck and boost. The operating modes of the proposed converter are described in the following section. The obtained results shows that the proposed converter can be a good solution for fuel cell vehicle systems, where voltage boosts and efficiency are key issues. The simulations were conducted with the switching frequencies of 10 KHz. The current waveforms at the DC-AC stages are observed to be conformity with the theoretical estimates. II POWER STAGE DESCRIPTION AND OPERATION
Abstract This paper propose a bidirectional dual half bridge converter for renewable energy applications. A bidirectional DCDC converter provides boost operation in the forward mode and buck operation in the reverse mode. A typical application of this converter is found in a hybrid vehicle which operates on a fuel cell or solar source. The proposed concept incorporates both zero voltage switching and zero current switching. The operating modes are separately simulated using MATLAB and results were obtained. This converter is suitable for low and medium power applications. Keywords-component; ZVS,ZCS,MATLAB,DC-DC converter .
I.
INTRODUCTION
In recent years, the area of bidirectional DC-DC converters is improving the fuel cell economy, automobile companies are developing alternative battery operated vehicles. In addition, a major change in the electrical system of the vehicles is on the horizon by going for a 40 to 300V DC from 12/24V DC systems. The main reasons for switching over to 12V/24V to 300V are to meet the increased electrical demands of cell vehicles, to lower the current drawn from the battery, and to implement additional safety and comfort features, also to reduce the mechanical and hydraulic components, and to improve the design flexibility of the vehicles. In hybrid/fuel cell vehicles, the main goals are to have a high efficient, small size, rugged and low cost bidirectional DC-DC converter. In hybrid/fuel cell vehicles, a power conditioning unit such as novel bidirectional DC-DC converter to match the fuel cell voltage with the battery pack may also required. In certain conditions, a fast response required to supply load, converter to give bidirectional power to that vehicle system without any disturbance. It is able to operate at adverse environmental conditions. The power semiconductor devices (MOSFET, IGBT, etc) and packaging of the individual units and the system integration play a major role in hybrid/fuel cell vehicles. The proposed converter system should be efficient to improve the range of performance of the battery operated vehicles. In addition to the power semiconductor devices, controllers, there are several other components such as inductors, capacitors, isolation transformer form a major portion of the proposed system. The soft switching converters have the advantage of lower switching losses and higher operating voltage. Hence the proposed soft switching techniques ZVS/ZCS were needed. The proposed system with two integrated function is that DC/AC and AC/DC conversion,
A. power stage description The proposed bi-directional DC- DC converter for fuel cell and battery applications is shown in Fig. 2. In the ZVS bidirectional DC -DC converter[1] low-voltage side half bridge with MOSFETS and high voltage side half bridge with IGBTs were developed. Whereas in the proposed ZVS-ZCS bidirectional DC-DC converter, dual half-bridges are developed using MOSFETs with an auxiliary circuit in the low voltage side. The auxiliary circuit used in this converter has been adapted from [6] and it can also be used in full-bridge topologies, but this will be the scope of future work. In proposed ZVS -ZCS bidirectional DC-DC converter the auxiliary circuit is composed of one resonant inductor La, one auxiliary switch Sa, and also diode D a, so that the zero current switching (ZCS) in main switches S1& S2 can be obtained. Switch Sa is turned on under zero current switching (ZCS) condition. When power flows from the low voltage side to high voltage side, the circuit works in ZCS condition to turned off and ZVS condition to turned on of a main switches S1, S2.
in boost mode. Inof Engineering, Coimbatore INFO Institute the other direction of power flow, the circuit operates in ZVS condition (buck mode). The transformer is used to provide isolation and voltage matching. The leakage inductance of the transformer is utilized as an interface and energy transfer element between two half-bridges. The two voltage source half-bridges each generates a square wave voltage applied to the primary and secondary of the transformer, respectively. The major draw back of this converter is TDR penalty because auxiliary circuit used in primary side. The TDR of the [1] ZVS bidirectional DC-DC converter is calculated as TDR = 2Vdc. Iac. (2 devices) = 4 Po, where Po is the output power. The TDR of the proposed ZVS- ZCS bidirectional DC-DC converter is calculated as TDRP = 2Vdc. Iac. (3 devices) = 6 Po, Where Po is again the output power. The TDR has been increased for the proposed converter and the ZVS bidirectional DC-DC converter is not same output power. The main advantage of proposed circuit is the current stresses are reduced for the low voltage side main switches S1, S2 and high efficiency is achieved due to ZCS condition.
Fig.2.Proposed ZVS-ZCS bidirectional DC-DC converter
Proceedings of PEID-2011
Mode I: ir = (v1+v4) / Ls + ir (0) Mode II: ir = (v1-v3) ( -1) / Ls + ir (1) Mode III: ir = 0 Mode IV: ir = - (v2+v3) ( -) / Ls + ir () Mode V: ir = - (v2+v4) ( --) / Ls + ir (+1) Mode VI: ir = 0 The current initial conditions can be solved using the boundary conditions of ir(0) = ir()=0 ir(1) = -ir(+1) Further, the output power can be found to be
(1) (2) (3) (4) (5) (6)
(7) (8)
Fig.1. ZVS bidirectional DC-DC converter
B. Description of operating stages Fig. 2. illustrates the proposed converter topology . ZCS is achieved by auxiliary circuit used in one half-bridge, operating the two half-bridges with a phase shift. The circuit operation that is significant for the development of the state space model. Fig. 2 is the proposed circuit. Fig. 3 presents the voltage and current waveforms of the transformer during one switching period. In fuel cell applications, when power flows from the low voltage side to high voltage side, the circuit works in boost mode to keep the high voltage at a desired high value before fuel cell can generate power. In other direction of power flow, the circuit works in buck mode to absorb regenerated energy. Based on the waveforms in Fig. 3, there are six operation modes in one switching cycle, and the transformer current ir of each mode can be calculated as follows:
Ts is the period of switching frequency, Vdc is the input voltage in boost mode. The output power can be regulated by phase shift angle 1, duty cycle and switching frequency . If duty cycle assumed to 50% then the output power equation can be simplified as 2 Po= x0 / Ts = Vdc / Ls [(2- ) 1/ )] (9) Because of the asymmetry property of dual half-bridges, the operation principles of boost mode and buck mode are not the same, polarity of the phase shift angle is also not same. 1. Boost mode: The interval of Fig. 3. describes the various stages of operation during switching period in boost mode. The converter operation is repetitive in the switching cycle. One complete cycle is divided into six steps. To aid in understanding each step, a set of corresponding annotated circuit diagrams is given in Fig. 4(a,b,c,d,e,f) with a brief description.
Fig. 4(c). third stage(3 to )
Fig.3.Transformer voltages and primary current
First stage (0 to 1): switch S1 starts to conduct. Due to the resonant capacitor Cr1 , the voltage across S1 is becomes zero. During this stage C1, C4 are charged, C2, C3 are discharged.
Fourth stage (2 to 2): when S2 is turned on, C 2 & C3 are charged, C3 & C4 discharged. This stage finishes when S is turned-on.
Fig. 4(d) fourth stage( to4)
Fig. 4(a) first stage(0 to 1)
Second stage (1 to): S1 is still turn on state. During this stage C1, C4 are charged, energy stored in C2, C3 are transferred to the load. When ir reaches at 3, Sa is gated to turn off S1. This stage finishes when S1 is turned off.
Fifth stage (2 to 3): At this stage S2 is still in turn on state. During this stage C2, C3 are charged, energy stored in C1, C4 are transferred to the load. When ir reaches at 3, Sa is turned on to turn-off the S2. This stage finishes when S2 is turned off.
Fig .4(b) second stage(1 to 3)
Third stage ( to 2): at this stage Sa is turn on, remaining switches are in off state. During this stage energy stored in C1,C4 are transferred to the load. C3, C2 are charged.
Fig . 4(e) fifth stage( 3 to 5)
Sixth stage (3 to 5): at this stage Sa is turned on, remaining switches S1&S2 are in off state. During this stage energy stored in C2, C3 transferred to the load. C1, C4 are charged.
10
v
= i
r
(1
)/ C
( i
/ C
(17)
= [ (v 3 + v 4 v s P 1) / R S + C 0 d (v 3 + v 4 ) / dt )](1 P 2 ) / CS + [i r (v 3 + v 4 v s ) / R s C 0 d (v 3 + v 4 )dt ]P 2 / Cs (18)

3
= [( i r + (v 3 + v 4 v s ) / R S + C 0 d (v 3 + v 4 ) / dt )](1 P 2 ) / CS + [ (v 3 + v 4 v s ) / R s C 0 d (v 3 + v 4 )dt ]P 2 / Cs (19) Where Cp= C1=C2 and Cs= C3=C4.

4
These equations describe all the operation modes of one switching cycle in Fig. 3.The next step is to calculate the integration of fast variable ir in [0, 1] ,[ 1,
Fig.4(f) sixth stage( 3 to 5)
2. Buck mode: Because of the auxiliary circuit in one half-bridge the two sides are asymmetrical, the operation principles in buck mode are similar to those in boost mode except mode III & mode VI. Due to the reversed power-flow direction, the phase of the VS2 is leading than VP1. The inductor current LS is reversed. The buck mode only operates under ZVS condition. This mode of operation can be divided into four steps. In this mode the switches in S3 &S4 are turned on and turned off at zero voltage due to the resonant capacitors Cr3, Cr4.Body diodes of the switches S1& S2 acts as rectification. Mode I: ir = (v3+v4) / Ls + ir (0) Mode II: ir = (v3-v2) ( -1) / Ls + ir (1) Mode III: ir = - (v1+v4) ( -) / Ls + ir () Mode IV: ir = (- v2+v4) ( --) / Ls + ir (+1) (10) (11) (12) (13)
[3,2] ,respectively based on (1)(2)(3)(4)(5)(6). Then substitute the above results and switch functions P1and P 2 in to (14)(15)(16)(17)(18)(19) to calculate the move averages of the slow variables shown in (20)
t + Ts
],[,2],[2,3,],
avg = (
t t + Ts
i 1 dt ) / Ts ; i a avg = (
i
t + Ts
dt ) / Ts
v avg = ( v dt ) / Ts ; v avg = (
1 1 2
i dt ) / Ts
2
(20)
t t + Ts
3 3 1
t t + Ts
v avg = ( v dt ) / Ts ; i avg = (
t
i ) / Ts
1
The state space model of proposed converter with ZCS condition is derived. We shall now demonstrate the normal operation of the ZVSZCS bidirectional DC-DC converter through simulation using MATLAB/Simulink. The simulation results are shown in Fig. 5,6,7and Fig. 8.
III. STATE SPACE MATHEMATICAL MODEL The state variables of the proposed converter [1] are chosen to be the inductor currents i1, i2, transformer current ir and the capacitor voltages v1, v2, v3 and v4 [1] that state variables vary slowly with time, also does i1,i2 if enough large inductance and small inductances are selected, while the state variable ir varies quickly with time. To analyze the behavior of the fast variable ir, the other slow state variables can be treated as dc constants. From section II, we know that the converter is operated as dual active half-bridges and there are six operation modes during one switching cycle. With the help of switching functions, the state equation of the slow state variables is described by
dc b 1 dc
(14)
= [v i1R P (v1 + v 2)] / L = 1/ La[vb

1r
Rb
Sa (v1 v2)]
11 p
(15) (16)
Fig .5. Transformer primary and secondary side voltages in boost mode
P (i / C ) +
P (i / C )
11
The simulations revealed modes of operation where the primary side switches operate under ZVS, ZCS conditions. The simulation results were shown in Fig. 3, 5(a,b).During the forward operating mode the battery voltage is initially inverted to a pulsating DC, stepped up using a transformer and then converted to drive the load.
IV SIMULATION RESULTS The detailed circuit model is built using Matlab/Simulink. Simulation of forward and reverse operating modes are done separately. The simulated results are compared with ZVSbidirectional DC-DC converter to show the performance of proposed converter. 1. Boost mode: The following parameters are selected according to a 400W for fuel cell and battery applications. Vb =12V, Rb=1, D = 45%, fs=10 kHz, Ls= 380 H, La= 4.96H, CP1= CS1= 20mF, C0= 150mF, RL= 0.5.Vo= 80V
Fig.8. Simulation resulst of reverse operating mode.
Fig.6. Simulation circuit
2. Buck mode: Similarly, the buck mode can also be simulated using same parameters as boost mode. Simulations of the proposed converter waveforms are presented in Fig.8. In the reverse operating mode the load act as source. The power regenerated is initially given to the half bridge. The half bridge convert the DC to pulsating waveform which is suitable for the transformer to step down. Then it is converted and fed to the source. The simulations revealed modes of operation where the primary side switches operate under ZVS condition.
V CONCLUSION A dual half bridge ZVS-ZCS bidirectional DC-DC converter has been presented in this paper. The operation, state space mathematical model and simulation results were illustrated. The purpose of separating the operating modes is for better analysis. However in the actual circuit, a single circuit handles both the operating modes. Due to the simultaneous boost conversion and inversion provided by the low voltage side half bridge, current stresses on the switching devices and transformer are reduced by switching an auxiliary switch in primary side. The advantages of the proposed circuit are reduced current stress, high efficiency, which is achieved due to the ZCS operation.
Fig.7. Simulation results for forward operating mode
increment due to the auxiliary circuit components and decreased output power. This proposed converter for medium power applications like fuel cell and battery, with high power density. Excellent dynamic performance is obtained because of the auxiliary circuit used in the half bridge. REFERENCES
[1] Fang Z.Peng,Hui Li,Gui-Jia,Jack S.Lawler, A new ZVS bidirectional dc-dc converters for fuel cell and battery application, IEEE Trans. Power Electro., vol. 19,No. 1,Jan 2004,pp 54-65. [2] H.L.Chan, K.Cheng, and D.Sutanto, An extended load range ZCS-ZVS bidirectional phase shift dc-dc converter, in proc. 8th Int.conf.Power Electron. Variable speed drives, 2000, pp 74-79. [3] Manu Jain, M.Daniele, and Praveen K.Jain, A bidirectional dcdc converter topology for low power application, IEEE Trans. Power Electro.,vol. 15, No.4,July 2000,pp 595-606 [4] Fang Z.Peng,Hui Li, modeling of a new ZVS bidirectional dc-dc converter, IEEE Trans. Power Electron, vol. 40, No. 1, Jan 2004, pp 272-283. [5] H.Chung et al., A ZCS bidirectional flyback dc-dc converter, IEEE Trans. Power Electron, vol. 19,No. 6, Nov 2004, pp 14261434. [6] R.Mendes Finzi Neto,F.Lessa Tofoli, and Luis carlos de Freitas, A High power-factor half-bridge doubler boost converter without commutation losses, IEEE Trans.Power Electron, vol. 52, No. 5, Oct 2005, pp 1278-1285. [7] L.C.Freitas, D. F. Cruz, and V.J. Farias, A novel ZCS-ZVS PWM dc-dc converter for high switching frequency: analysis,simulation and experimental results, in proc.IEEE APEC93,San Diego,CA,1993, pp 693-699. [8] F.Carichhi, F.Crescimbini, F.G.Capponi, and L.Solero, Study of bidirectional buck-boost converter topologies for application in electrical vehicle motor drives, in proc. IEEE applied power electronics specialists conf. Expo, 1998, pp. 287-293. [9] S.Hamada et al., A novel zero-voltage and zero-current switching PWM dc-dc converter with reduced conduction losses, IEEE Trans. Power electron., vol. 17, pp. 413-419, May 2002. [10] Z.R.Martinez and B.Ray, Bidirectional dc/dc power conversion using constant frequency multi-resonant topology, in Proc. APEC94, 1994, pp. 991-997.\ [11] D.Makasimovic, S.Cuk, A general approach to synthesis and analysis of quasi-resonant converters, IEEE Trans.Power Electron., vol. 6,No. 1,Jan 1991, pp. 127-140. [12] R. L. Lin, Fred C.Lee,Novel zero-current switching-zerovoltage switching converters, in proc. IEEE PESC96, pp. 438-442. [13] R. W. DeDonker, D. M. Divan, and M.H.Kheraluwala, A Three-phase soft-switched high power density dc-dc converter for high power applications, IEEE Trans. Ind.Applicat.,vol. 27,pp.. 6373,Jan./Feb.1991.
Proceedings of PEID-2011 The drawbacks of this Coimbatore INFO Institute of Engineering, proposed converter is cost is
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14
A Double-Ended ZeroVoltage Switching Full-Bridge Zeta Converter

R.Leelavathy1 S.Sugumar2 1 PG student, 2Assistant Professor, Dept of EEE, Madha Engineering College, Kundrathur, Chennai-69 E-mail ID:leelaraj87@gmail.com Mobile no:9677680657
ABSTRACT A new double-ended type zero-voltage switching (ZVS) full-bridge zeta (FBZ) converter employing a double-ended rectifier (DER) is proposed. The proposed DER for the FBZ converter provides a bidirectional powering path in the rectifier. As a result, the improved voltage waveform of the rectifier reduces the output filter size and voltage stresses on rectifier components. Moreover, it offers a wide ZVS range. In addition, to minimize the secondary snubber loss, a simple lossless snubber is adopted. The operational principles and characteristics of the proposed converter are to be analyzed and verified experimentally. Index Terms Double ended rectifier (DER), fullbridge zeta(FBZ) converter, single-ended rectifier (SER), zero-voltage switching (ZVS).
I. INTRODUCTION
A Zeta converter performs a non-inverting buckboost function similar to that of a SEPIC, which is an acronym for Single-Ended Primary Inductance Converter. The Zeta topology uses two inductors, four switches and a capacitor to isolate the output from the input. However, Zeta conversion requires a P-Channel MOSFET as the primary s witch, while SEPIC conversion uses an N-Channel MOSFET To Minimize the size and weight of pulse width modulation (PWM) converters, a high switching frequency is generally required. However, the hard switching of power switch results in high switching loss and high electromagnetic interference (EMI) noise. Therefore, various types of soft switching dc/dc converters have been proposed. Among them, fullbridge-type converters are very attractive due to the reduced voltage/current stress, reasonable number of components and zero-voltage switching (ZVS) without auxiliary circuits. The conventional ZVS half-bridge zeta (HBZ)
Fig.1 converter, which is derived from zeta converter, is one of the attractive circuits mentioned before with a wide ZVS range and a linear dc conversion ratio. However, it features a single-ended-type converter where the power delivery of the rectifier is unidirectional, as shown in Fig. 1. That is, the power is transferred from the primary to the output only in the conducting state of switch Q as can be seen in the voltage waveform of rectifier V . Figs. 2 and 3 show circuit diagrams and voltage Waveforms of a usual single-ended rectifier (SER) and a double-ended rectifier (DER), i.e., bridge rectifier, respectively. In general, the unidirectional power delivery of SER needs more transformer secondary turns to achieve the same dc conversion
15
across the secondary diodes makes this problem more severe, and a large amount of power should be dissipated in the snubber to prevent the additional stress. Moreover, the SER impresses a higher ac voltage on the output filter than the DER, resulting in a larger output filter size. In order to solve aforementioned drawbacks of the conventional singleended HBZ (SHBZ) converter caused by the SER, this paper proposes the double ended FBZ (DFBZ) converter employing the DER.
Fig. 2. SER. (a) Circuit diagram. (b) Voltage waveforms
As shown in Fig. 4, the structure of proposed DFBZ converter is similar to that of the conventional SHBZ converter except for one additional capacitor and a diode of the rectifier to provide the bidirectional powering path. By adopting the proposed DER, the DFBZ converter reduces the voltage stress on rectifier components and the output filter size while maintaining a wide ZVS range. In addition, to minimize the secondary snubber loss, a simple lossless snubber which does not have any magnetic components is employed.
II CHARACTERISTICS
A. DC Conversion Ratio
Fig. 3. DER. (a) Circuit diagram. (b) Voltage waveforms
ratio; thus, the higher voltage is impressed on the rectifier devices than the DER where the power delivery of the rectifier is bidirectional. Especially in high-output-voltage applications such as a plasma display panel (PDP) sustaining power module (SPM) where the output voltage is over 170 V, a high voltage stress increases the cost of the device, and degrades its performance. In addition, a high voltage ringing
To obtain the dc conversion ratio considering the resonant effect between CB , CS1 , CS2 , and Llkg , it is assumed that the resonant period is large enough, i.e., VB and VCs are constant. The voltage-second balance across LM and LO can be expressed by equations respectively D(VS VB) =(1 D)npVCs D(2VCs +1np(VS VB )VO ) =(1 D)(VO VCs)
Fig. 4. Proposed DHBZ converter
16
on diodes, and thus a snubber is required to prevent the additional voltage stress. The general method is to utilize a resistorcapacitordiode (RCD) snubber across the rectifier; however, the considerable loss degrades the overall efficiency and it becomes more severe in high-output-voltage applications.
Fig.5 Dc conversion ratio Fig. 5 presents the dc conversion ratio according to the variation of Q, with np = 2. As Q decreases, the dc conversion ratio
IV. SIMULATION USING ORCAD SOFTWARE

It is an electronic design software. It has the design character of different components. Device ratings can be seen. Printed circuit board format is seen. Digital simulation is carried out.
PSPICE
Q= LlkgTsRO C. Device Stress The current stresses on secondary diodes DS1 and DS2 can be expressed as IDS 1, 2 (max)= {2/(1 D)}Io . The voltage stress on switch is VS because of the half-bridge structure VDS 1 , 2 (max) = VO/2D. D. Output Filter Tthe ac content of Vrec is much smaller in the DHBZ converter compared with peak-to-peak filter inductor current ripple, one-half of the filter inductance in the SHBZ converter is used in the DHBZ converter. Consequently, due to the improved waveform of Vrec, the output filter size of the DHBZ converter can be significantly reduced.
Electronic circuit design requires accurate methods for evaluating circuits performance. Because of the enormous complexity of modern integrated circuits, computer-aided circuit analysis is essential and can provide information about circuit performance that is almost impossible to obtain with laboratory prototype measurements. SPICE is a general-purpose circuit program that stimulates electronic circuits. SPICE can perform various analyses of electronic circuits. The operating points (or the quiescent) points of transistors, a time domain response, a small signal frequency response, and so on. SPICE contains models for common circuit elements, active as well as passive, and is widely used both in industries and universities. The acronym SPICE stands for stimulation program with integrated circuit emphasis. Until recently PSPICE was available only on the mainframe computers. In addition to the initial cost of the computer system, such a machine can be expensive and inconvenient for classroom use. SPICE, therefore, widens the scope for the integration of computer-aided analysis into electronic circuits courses at the undergraduate level. In 1984,microsim introduced the pspice simulator, which is similar to the Berkeley SPICE and runs on an IBM-PC or compatible. Pspice, therefore, widens the scope for the integration of computer aided circuit analysis into electronic circuits at the undergraduate level..
III. LOSSLESS SNUBBER

In general, isolated converters employing an output inductor suffers from a voltage ringing across the rectifier since the leakage inductance of the transformer and junction capacitance of rectifier diodes are interacted after the rectifier current commutation.This ringing increases the voltage stress
17
Proposed circuit diagram for boosting current
Proposed circuit diagram for boosting voltage
VOLTAGE DOUBLLER
CURRENT DOUBLLER
R6 1 .01
L4 2 5u
D5 M5 V6 IRF840
V
C4 30n
V6 M5 V8 IRF840 IRF840 .0001 V10 45 R7 1 1k 20UH L3 2 1 TX2 L24 10mH M7 R5
1
V+
M7 R5 V8 IRF840 .0001 R7 1 1k 20UH L3 2 1 TX2 L24 10mH
D5 1N5814
1N5814
V10 45
C7 220u
I
R4 800k
M8 M6 V9 V7 IRF840 IRF840 2
R8 20k
M8 M6 V9 V7 IRF840 IRF840
D6
2
D6 1N5814
C6 30n
V-
1N5814
2
2 L5
0
5u
Output voltage waveform
i/p 45v o/p 110v

1A 5
Output current waveform
i/p 4Amps o/p 9Amps
Voltage
10 0V
Ampere
8V 0
1A 0
6V 0
5 A
4V 0
0 A
2V 0
0 V 0 s
1u 0s 5s u (7d VD:,) VM:) (5K0
1u 5s
2u 0s
2u 5s
3u 0s
Tm ie
3u 5s
4u 0s
4u 5s
5u 0s
5u 5s
6u 0s
-A 5 0 s
Time(sec)
5s u -(7 I 1) I C ) (V 0
1u 0s
1u 5s
2u 0s
2u 5s
3u 0s
3u 5s
4u 0s
4u 5s
5u 0s
Tm ie
Time(sec)
18
[7] S. Korotkov, V. Meleshin, R. Miftahutdinov, and S. Fraidln, Softswitchedasymmetrical half-bridge DC/DC converter: Steady-state analysis:An analysis of switching processes, in Proc. TELESCON. [8] T. M. Chen and C. L. Chen, Analysis and design of asymmetrical halfbridge flyback converter, Proc. Inst. Electr. Eng. Electr. Power Appl.,vol. 149. [9] W. Chen, P. Xu, and F. C. Lee, The optimization of asymmetric halfbridge converter, in Proc. IEEE APEC. [10] H. S. Choi, Design consideration of half-bridge LLC resonant converter,J. Power Electron., vol. 7. [11] X. Xie, J. Zhang, C. Zhao, Z. Zhao, and Z. Qian, Analysisand optimization of LLC resonant converter with a novel over-currentprotection circuit, IEEE Trans. Power Electron., vol. 22. [12] K. Yoshida, T. Isbii, and B. Handa, A novel zero voltage switchinghalf bridge converter, in Proc. INTELEC.
V. CONCLUSION
A Double-ended ZVS Full bridge Zeta converter have been simulated using Orcad/Pspice. The following conclusions can be made from the analysis: A new DFBZ converter, which has a bidirectional powering path in the rectifier, is proposed. The proposed converter has a low voltage stresses on rectifier devices that make it suitable for high-output-voltage applications, and its improved rectifier voltage waveform reduces the output filter size compared with the conventional SHBZ converter. Moreover, it basically has a wide ZVS range due to the characteristic of the FBZ converter. In addition, the lossless snubber is adopted to minimize the secondary snubber loss. Therefore, the DFBZ converter is promised for high-output-voltage applications such as a PDPSPM with high efficiency.
VI. REFERENCES
[1] L. H. Mweene, C. A. Wright, and M. F. Schlecht, A 1 kW 500 kHz front-end converter for a distributed power supply system, IEEE Trans Power Electron., vol. 6. [2] Y. Jang and M. M. Javanovic, A new PWMZVS full-bridge converter,IEEE Trans. Power Electron., vol. 22. [3] S. S. Lee, S. W. Choi, and G. W. Moon, Highefficiency active-clampforward converter with transient current build-up (TCB) ZVS technique,IEEE Trans. Ind. Electron., vol. 54. [4] Y. K. Lo, T. S. Kao, and J. Y. Lin, Analysis and design of an interleavedactive-clamping forward converter, IEEE Trans. Ind. Electron., vol. 54. [5] Q. Li and P. Wolf, An analysis of the ZVS twoinductor boost converterunder variable frequency operation, IEEE Trans. Power Electron.. [6] P. Imbertson and N. Mohan, Asymmetrical duty cycle permits zeroswitching loss in PWM circuits with no conduction loss penalty, IEEETrans. Ind. Appl., vol. 29
19
A Neuro Fuzzy Based MPPT Controller with DC-DC Converter

1
P.SURESH MUTHUKUMAR
K.MANIKANDAN
1. P.SURESH MUTHUKUMAR, II M.E Roever Engg College, Perambalur. Suresh_muthukumar@gmail.com
2. K. MANIKANDAN, Asst.professor, Roever Engg College, Perambalur.
Abstract: The global electrical energy consumption is steadily rising and therefore there is a need to increase power generation capacity. The conventional energy capacity increase can be based on renewable energy. Solar energy remains a largely unexploited renewable energy source due to low conversion efficiency of photovoltaic modules. The efficient way of harvesting solar energy plays a vital role in power generation. Some of the conversion methods of photovoltaic modules include, Modified Perturb and Observation ( P&O) method, Incremental conductance method, Parasitic capacitance method, Constant voltage method and Scaling Fuzzy logic Control which were accounting for various setbacks such as low tracking responses, complexity, instability and high cost . The Neuro-Fuzzy based MPPT control algorithm with DC-DC converter can achieve a high performance tracking of Maximum Power from the Photovoltaic system. This method combines the learning abilities of Artificial Neural Network and the ability of Fuzzy Logic to handle imprecise data. It is therefore able to handle non-linear and time varying problems, hence making it suitable for this work. The Simulink Model of the proposed scheme employing Neural Network and Fuzzy Logic controller has been built using MATLAB. It is expected that this method
will be able to accurately track the maximum power point and will ensure efficient use of PV systems and thereby leading to reduced cost of electricity. Index Terms maximum power point tracking (MPPT), MATLAB software, neuro fuzzy logic control based MPPT controller, dc-dc converter. I-INTRODUCTION Renewable energy sources play a massive role in electric power generation. Some of the renewable energy sources include solar energy, wind energy, and geothermal energy. Solar energy is clean, maintenance free, and an abundant resource of nature. So it is suitable to be a green energy source. The solar energy is directly converted into electrical energy by solar photovoltaic module. The solar system uses the solar module as a source of electrical power supply. Photovoltaic systems or solar system has low conversion efficiency and therefore controlling of maximum power point tracking of solar module is essential. This can be achieved by using MPPT controller. The solar system in this controller is composed of solar panel and DC/DC Converter and MPPT controller. The nonlinear nature of PV system in addition to the fact that the maximum power operating point varies with the insolation level and temperature complicates the tracing control of
20
maximum power point. When a PV array is directly connected to a load, the systems operating point will be at the intersection of the I-V curve of the PV array and the load line. Maximum power point tracking is based on load line adjustment under varying atmospheric and load conditions by searching for an optimal equivalent output resistance of the PV module. Many tracking control strategies have been proposed such as Perturb and Observe, incremental conductance, parasitic capacitance, constant voltage and Fuzzy logic controller. These strategies have a number of disadvantages which include high cost, complexity, instability and sluggishness in output power tracking under changing temperature and insolation conditions. This setbacks can be sort out using this project which comprises of Neuro Fuzzy based MPPT algorithm. The role of Neuro Fuzzy MPPT is to acquire as much power as possible from the PV system while overcoming the challenges experienced by already existing methods. II-BLOCK DIAGRAM
Photovoltaic cells are devices that absorb sunlight and convert that solar energy into electrical energy. A photovoltaic module consists of a number of interconnected solar cells encapsulated into a single unit. It comprises of many solar cells wired in series and in parallel. The output of a solar array is characterized by a performance curve of voltage versus current, called the I-V curve. The PV module is simulated in MATLAB-SIMULINK software. The figure shows the IV-PV curve of the simulated solar array. The inputs to the system are ambient temperature T and radiation G while the outputs are array voltage Vpv and array current Iph.
Fig.2 IV - PV curve of solar array 2.1.3 MPPT CONTROLLER MPPTs are used to correct the variations in the I-V characteristics of the solar cells. The IV curve will move and deform depending upon such things as temperature and illumination. For the array to be able to put out the maximum possible amount of power, either the operating voltage or current needs to be controlled. Since the maximum power point quickly moves as lighting conditions and temperature change, a device is needed that finds the maximum power point and converts that voltage to a voltage equal to the system voltage. Cost is a major factor when deciding to utilize solar energy as a source. As one
Fig. 1.General Block Diagram of a NEURO FUZZY BASED MPPT 2.1. BLOCK DIAGRAM DESCRIPTION 2.1.2 PV MODULE
21
might expect, a purchaser would want to extract the maximum power per dollar spent on an array. Solar arrays do present an interesting problem in the transfer of energy to a load, however. Since the solar array has a unique I-V relationship similar to a silicon diode, the maximum power point must be tracked to extract the most energy possible. Connection of an arbitrary load to a solar array does not guarantee operation at the maximum power point. As an example, if an array has a maximum power point at a source voltage of 100V (with current being constant) a 24V load will absorb energy, but it will not be at the optimal rate (maximum power). A means of controlling the source voltage or current is needed to guarantee operation at the maximum power point. 2.1.4 DC-DC Converter The conversion of fixed dc voltage to an adjustable dc output voltage, through the use of semiconductor devices, can be carried out by the use of dc to dc converters. III-CIRCUIT DESCRIPTION The PV Module used here consists of an array of 3X3 solar cells encapsulated in a single unit and it is a standalone PV system. When the light intensity falls on the PV array, it generates varying voltage and current. When the irradiance is more there will be a rise in the voltage and current levels and vice versa. The output voltage and current from the solar array is fed to the DC-DC converter (which initially makes the DC-DC converter to switch on) and Neuro Fuzzy MPPT controller. The DC/DC converter output is taken and fed back again to the Neuro Fuzzy controller forming a closed loop system. Here the neuro fuzzy MPPT controller computes the error signal and the change in error signal which in turn is fed to the MOSFET switch of the DC-DC converter to regulate the output. The Neuro Fuzzy controller uses the learning abilities of Neural
Network which is used to train the values and Fuzzy logic to handle imprecise and ambiguous data in linear and time varying problems. Fuzzy logic uses linguistic rule base. The Neuro Fuzzy MPPT controller uses this measurement to control the DC/DC power converter duty cycle which is then applied
through a PWM modulator to control the switching and hence the power output of the converter. The power output of the converter can be obtained for Buck mode, Boost mode and Buck-Boost mode.
Fig.3.Circuit Diagram for Neuro Fuzzy based MPPT controller with DC-DC Controller. 3.1 Neuro Fuzzy Based MPPT Controller In this study, the neuro fuzzy interference system was used to formulate the MPPT algorithm. This neuro fuzzy algorithm combines the learning abilities of artificial neural network and the ability of fuzzy logic to handle imprecise and ambiguous data in linear and time varying problems. The fuzzy logic systems used here are rule-based. The first step involves formulation of the rules from human experts or domain knowledge. The next step is
22
to combine these rules into a single system. Here the controller integrates the fuzzy logic for tuning the converter duty cycle. IV-SIMULATION CIRCUITS
Fig. 6. Simulated circuit of solar cell.
Fig 4. Simulated circuit of A neuro fuzzy based MPPT controller.
Fig. 7. Simulated circuit of solar panel 4.1. Simulation waveforms:
Fig.8 Buck-Boost Mode Fig 5. Simulated circuit of neuro fuzzy block
23
Fuzzy current control algorithm is implemented to keep the current injected into the grid sinusoidal and to have high dynamic performance with rapidly changing atmospheric conditions. The overall proposed system is verified through simulation. The proposed work will lead to successful implementation of MPPT for a solar array. The parameters obtained from PV system can be processed for different operations such as Buck mode, Boost mode, and Buck boost mode. Fig. 9 Buck Mode VI-REFERENCES 1. Hua C, Shen C. Comparative study of peak power tracking techniques for solar storage system. IEEE Appl. Power Electron Conf Exposition 1998; 2:679-83 2. Hussein KH, Muta I, Hoshino T, Osakada M. Maximum photovoltaic power tracking: an algorithm for rapidly changing atmospheric conditions. IEEE Proc Generation transmission Distribution 1995;142(1): 59-64. 3. Brambilla A. New approach to photovoltaic arrays maximum power point tracking. Proc 30th IEEE Power Electron Specialists Conf 1998;2:632-7. 4. Hohm DP, Ropp ME. Comparative study of maximum power pointtracking algorithm using an experimental, programmable, maximum power point tracking test bed. Proc 28th IEEE Photovoitaic Specialist Conf2000;28:1699702. 5. Swiegers W, Enslin J. An integrated maximum power point tracker for photovoltaic panels. Proc IEEE Int. Symp Ind Electron 1998;1: 40-4. 6. Won CY, Kim DH, Kim SC, Kim WS, Kim HS. A new maximum power point tracker of photovoltaic arrays using fuzzy controller. Proc Annual IEEE Power Electron Specialists Conf 1994;396-403.
Fig. 10 Boost Mode. V-CONCLUSION This project aimed at determining the efficient way of tracking the maximum power point from a PV system by using Neuro-Fuzzy based MPPT controller. The simulation of the power conversion system has been evaluated using Matlab/Simulink and Fuzzy Toolbox. The Simulink model of the proposed scheme employing fuzzy logic controller has been built using MATLAB. A DC-to-DC buck boost converter photovoltaic (PV) converter topology for Solar array based PV systems with a novel pulse width-modulated (PWM) control scheme is implemented. A Neuro
24
A NOVEL ISOLATED BIDIRECTIONAL FULL-BRIDGE DCDC CONVERTER WITH A FLYBACK SNUBBER

Kata Naresh*, Prof.J.LakshmanaPerumal,** P.G.Student, **Head Of the Department of EEE, Department of Electrical & Electronics Engineering, Government College of Engineering, Salem-11. E-mail: knaresh.230@gmail.com
*
ABSTRACTA novel isolated bidirectional fullbridge dcdc converter with high conversion ratio, high output power, and soft start-up capability is proposed in this paper. The use of a capacitor, a diode, and a flyback converter can clamp the voltage spike caused by the current difference between the current-fed inductor and leakage inductance of the isolation transformer, and can reduce the current flowing through the active switches at the current-fed side. Operational principle of the proposed converter is first described, and then, the design equation is derived. Index Terms Flyback converter, isolated fullbridge bidirectional converter, soft start-up.
I.
INTRODUCTION
In renewable dc-supply systems, batteries are usually required to back-up power for electronic equipment. Their voltage levels are typically much lower than the dc-bus voltage. Bidirectional converters for charging/discharging the batteries are therefore required. For high-power applications, bridge-type bidirectional converters have become an important research topic over the past decade. For raising power level, a dual full-bridge configuration is usually adopted, and its low side and high side are typically configured with boost type and buck-type topologies, respectively. The major concerns of these studies include reducing switching loss, reducing voltage and current stresses, and reducing conduction loss due to circulation current. A more severe issue is due to leakage inductance of the isolation transformer, which will result in high voltage spike during switching transition. Additionally, the current Freewheeling due to the leakage inductance will increase conduction loss and reduce effective duty cycle. An alternative approach is to precharge the leakage inductance to raise its current level up to that of the current-fed inductor, which can reduce their current difference and, in turn, reduce voltage spike. However, since the current level varies with load condition, it is hard to tune the switching timing diagram to match these two currents. Thus, a passive or an active clamp circuit is still needed. An active commutation principle was to control the current of leakage inductance; however, clamping circuits are additionally required. Passive and active clamping circuits have been proposed to
suppress the voltage spikes due to the current difference between the current-fed inductor and leakage inductance of the isolation transformer. The simplest approach is employing an RCD passive snubber to clamp the voltage, and the energy absorbed in the clamping capacitor is dissipated on the resistor, thus resulting in lower efficiency. A buck converter was employed to replace an RCD passive snubber, but it still needs complex clamping circuits. A simple active clamping circuit was proposed, which suits for bidirectional converters. However, its resonant current increases the current stress on switches significantly. In, Wang et al. proposed a topology to achieve soft-starting capability, but it is not suitable for step-down operation. This paper introduces a flybacksnubber to recycle the absorbed energy in the clamping capacitor. The flybacksnubber can be operated independently to regulate the voltage of the clamping capacitor; therefore, it can clamp the voltage to a desired level just slightly higher than the voltage across the low-side transformer winding. Since the current does not circulate through the full-bridge switches, their current stresses can be reduced dramatically under heavyload condition, thus improving system reliability significantly. Additionally, during start-up, the flybacksnubber can be controlled to precharge the high-side capacitor, improving feasibility significantly. A bidirectional converter with lowside voltage of 48 V, high-side voltage of 360 V, and power rating of 1.5 kW has been designed and implemented, from which experimental results have verified the discussed performance.
II. CONFIGURATION AND OPERATION

The proposed isolated bi-directional dc-dc converter with a flyback snubber is shown in Fig. 1. The converter is operated with two modes: buck mode and boost mode. Fig. 1 consists of a currentfed switch bridge, a flyback snubber at the lowvoltage side, and a voltage-fed bridge at the highvoltage side. Inductor Lm performs output filtering when power flows from the high-voltage side to the batteries, which is denoted as a buck mode. On the other hand, it works in boost mode when power is transferred from the batteries to the high-voltage side. Furthermore, clamp branch capacitor CC and diode DC are used to absorb the current difference
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between current-fed inductor Lm and leakage inductance Lll and Llh of isolation transformer Tx during switching commutation.
to charge the high-voltage-side capacitor to avoid over current. The clamp branch and the flyback snubber are activated during both start-up and regular boost operation modes. A nonphase-shift PWM is used to control the circuit to achieve smooth transition from start-up to regular boost operation mode. Referring to Fig. 1, the average power PC transferred to CC can be determined as follows:
Fig 1: Basic circuit of full-bridge dc-dc converter with flyback snubber The flyback snubber can be independently controlled to regulate VC to the desired value which is just slightly higher than VAB. Thus, the voltage stress of switches M1 ~ M4 can be limited to a low level. The major merits of the proposed converter configuration include no spike current circulating through the power switches and clamping the voltage across switches M1 ~ M4, improving system reliability significantly. Note that high spike current can result in charge migration, over current density and extra magnetic force which will deteriorate in MOSFET carrier density, channel width and wire bonding and, in turn, increase its conduction resistance. A bi-directional dc-dc converter has two types of conversions: step-up conversion (boost mode) and step-down conversion (buck mode). In boost mode, switches M1 ~ M4 are controlled, and the body diodes of switches M5 ~ M8 are used as a rectifier. In buck mode, switches M5 ~ M8 are controlled, and the body diodes of switches M1 ~ M4 operate as a rectifier. To simplify the steady-state analysis, several assumptions are made as follows: All components are ideal. The transformer is treated as an ideal transformer associated with leakage inductance. Inductor Lm is large enough to keep the current iL constant over a switching period. Clamping capacitor CC is much larger than parasitic capacitance of switches M1 ~ M8.
......1 Where
VC(R) stands for a regulated VC voltage, which is close to (VHV (NP /NS )), fs is the switching frequency, and Lm _Leq. Power PC will be transferred to the high-side voltage source through the flyback snubber, and the snubber will regulate clamping capacitor voltage VC to VC(R) within one switching cycle Ts (=1/fs ). Note that the flyback snubber does not operate over the interval of inductance current ip increasing toward iL. The processed power PC by the flyback snubber is typically around 5% of the full-load power for lowvoltage applications. With the flyback snubber, the energy absorbed in CC will not flow through switches M1 - M4, which can reduce their current stress dramatically when Leq is significant. Theoretically, it can reduce the current stress from 2iL to iL . The peak voltage VC(P ) of VC will impose on M1 - M4and it can be determined as follows:
........2 where iL(M) is the maximum inductor current of iL , which is related to the maximum load condition. Additionally, for reducing conduction loss, the high-side switches M5 M8 are operated with synchronous switching. Reliable operation and high efficiency of the proposed converter are verified on a prototype designed for alternative energy applications. The operation waveforms of step-up conversion are shown in Fig. 2.Adetailed description of a half-switching cycle operation is shown as follows.
A. Boost Conversion
In boost mode, switches M1 ~ M4 are operated like a boost converter, where switch pairs (M1 , M2 ) and (M3 , M4 ) are turned ON to store energy in Lm. At the high-voltage side, the body diodes of switches M5 ~ M8 will conduct to transfer power to VHV . When switch pair (M1 , M2) or (M3 , M4 ) is switched to (M1 , M4) or (M2 , M3 ), the current difference iC (= iL ip ) will charge capacitor CC , and then, raise ip up to iL . The clamp branch is mainly used to limit the transient voltage imposed on the current-fed side switches. Moreover, the flyback converter can be controlled
26
Mode 1: [t0 t < t1 ]: In this mode, all of the four switches M1 - M4 are turned ON. Inductor Lm is charged by VLV , inductor current iL increases linearly at a slope of VLV /Lm, and the primary winding of the transformer is short-circuited. The equivalent circuit is shown in Fig. 2(a). Mode 2: [t1 t < t2]: At t1 , M1 and M4 remain conducting, while M2 and M3 are turned OFF. Clamping diode Dc conducts until the current difference (iL(t2)ip(t2)) drops to zero at t = t2 . Moreover, the body diodes of switch pair (M5 , M8) are conducting to transfer power. During this interval, the current difference (iL(t)ip(t)) flows into clamping capacitor CC . The equivalent circuit is shown in Fig. 2(b). Mode 3: [t2 t < t3]: At t2 , clamping diode Dc stops conducting, and the flyback snubber starts to operate. At this time, clamping capacitor Cc is discharging, and flyback inductor is storing energy. Switches M1 and M4 still stay in the ON state, while M2 and M3 remain OFF. The body diodes of switch pair (M5, M8 ) remain ON to transfer power. The equivalent circuit is shown in Fig. 2(c). Mode 4: [t3 t < t4]: At t3 , the energy stored in flyback inductor is transferred to the high-voltage side. Over this interval, the flyback snubber will operate independently to regulate VC to VC(R) . On the other hand, switches M1 and M4 and diodes D5 and D8 are still conducting to transfer power from VLV to VHV . The equivalent circuit is shown in Fig. 2(d). Mode 5: [t4 t < t5]: At t4 , capacitor voltage VC has been regulated to VC (R) , and the snubber is idle.Over this interval, the main power stage is still transferring power from VLV to VHV . It stops at t5 and completes a half-switching cycle operation. The equivalent circuit is shown in Fig. 2(e).
Fig. 2. Operation modes of step-up conversion. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5.
B. Buck Conversion In the analysis, leakage inductance of the transformer at the low-voltage side is reflected to the high-voltage side, in which equivalent inductance L eq equals (Llh + Lll (N2 p _ z2s )). This circuit is known as a phase-shift full-bridge converter. In the step-down conversion, switches M5M8 are operated like a buck converter, in which switch pairs (M5 , M8 ) and (M6 , M7 ) are alternately turned ON to transfer power from VHV to VLV .Switches M1M4 are operated with synchronous switching to reduce conduction loss. For alleviating leakage inductance effect on voltage spike, switchesM5M8 are operated with phase-shift manner. Although, there is no need to absorb the
27
capacitance Cc has to satisfy the following inequality:
current difference between iL and ip , capacitor CC can help to clamp the voltage ringing due to Leq equals (Llh + Lll (N2 p _ z2s ))and parasitic capacitance of M1M4 . Mode 1: [t0 t < t1]: In this mode, M5 and M8 are turned ON, while M6 and M7 are in the OFF state. The high-side voltage VHV is immediately exerted on the transformer, and the whole voltage, in fact, is exerted on the equivalent inductance Leq and causes the current to rise with the slope of VHV/Leq . With the transformer current increasing linearly toward the load current level at t1 , the switch pair (M1 , M4 ) are conducting to transfer power, and the voltage across the transformer terminals on the current-fed side changes immediately to reflect the voltage from the voltage-fed side, i.e., (VHV (Np/Ns)). Mode 2: [t1 t < t2]: At t1, M8 remains conducting, while M5 is turned OFF. The body diode of M6 then starts to conduct the freewheeling leakage current. The transformer current reaches the load-current level at t1, and VAB rise to the reflected voltage (VHV (Np/Ns)). Clamping diode Dc starts to conduct the resonant current of Leq and the clamp capacitor CC . This process ends at t2 when the resonance goes through a half resonant cycle and is blocked by the clamping diode Dc . Mode 3: [t2 t < t3]: At t2 , with the body diode of switch M6 conducting, M6 can be turned ON with zero-voltage switching (ZVS). Mode 4: [t3 t < t4]: At t3 ,M6 remains conducting, whileM8 is turned OFF. The body diode of M7 then starts to conduct the freewheeling leakage current. Mode 5: [t4 t < t5]: At t4 , with the body diode of switch M7 conducting, M7 can be turned ON with ZVS. Over this interval, the active switches change to the other pair of diagonal switches, and the voltage on the transformer reverses its polarity to balance flux. It stops at t5 and completes a halfswitching cycle operation.
.. 4 C. Flyback Converter In the interval of t1 t t2 , the high transient voltage occurs inevitably in boost mode, which could be suppressed by the clamp branch (Dc , Cc ). The energy stored in capacitor Cc is transferred to the high-voltage side via a flyback converter. The regulated voltage level of the flyback converter is set between 110%120% of the steady-state voltage at the low-voltage side. Power rating of the flyback converter can be expressed as follows: . 5 where Vc,h is the maximum voltage of Vc , Vc,l is the minimum voltage of Vc , and fs is the switching frequency. D. Start-Up Operation High inrush current with the isolated boost converter is the start-up problem before the highside voltage is established. The initial high-side voltage VHV should not be lower than VLV (NS /NP ) to avoid inrush current. The proposed flyback snubber can be controlled to precharge the highside capacitor. The operation principle is very similar to the active clamp flyback converter. Before the boost mode, the flyback converter starts to operate. Since the power rating of the flyback snubber is much lower than that of the main power stage, inductor Lm is operated in discontinuous condition mode. The start-up process usually lasts for a short period.
IV. SIMULATION RESULTS USING III. DESIGN CONSIDERATIONS

A. Boost Converter The proposed boost converter will be operated at 48v(dc) input voltage and got the 360v(dc) output voltage.
MATLAB
A. Low-Voltage Side Switch pairs (M1 ,M4 ) and (M2 ,M3) are turned ON alternately under any load condition. Its minimum conduction time is
3 B. Clamping Capacitor For absorbing the energy stored in the leakage inductance and to limit the capacitor voltage to a specified minimal value Vc,l ,
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Fig: Current waveforms across the terminals AB Fig. Triggering gate pulses and CD B. Buck Converter
Fig: Input voltage waveform
Fig: Triggering gate pulses
Fig: Output voltage waveform Fig: Output voltage waveform across the terminal CD
Fig: Voltage waveforms at the terminals AB, switch4 and charge capacitor CC Fig: Output current waveform across the terminal CD
29
Trans. Power Electron., vol. 24, no. 12, pp. 2756 2768, Dec. 2009. [8] F. Barone, A lightweight inverter for off-grid and grid-connected systems, in Proc. Photovoltaic Spec. Conf., 1994, vol. 1, pp. 917920. [9] T. Reimann, S. Szeponik, and G. Berger, A novel control principle of bi-directional DC-DC power conversion, in Proc. Power Electron. Spec. Conf., 1997, vol. 2, pp. 978984. [10] K.Wang, C. Y. Lin, L. Zhu, D. Qu, F. C. Lee, and J. S. Lai, Bi-directional DC to DC converters for fuel cell systems, in Proc. Power Electron. Transp., 1998, pp. 4751.
V. CONCLUSIONS
This Paper Presents a Novel Isolated Bidirectional Full-Bridge DC-DC Converter With A Flyback Snubber for high-power applications. The flyback snubber can alleviate the voltage spike caused by the current difference between the current-fed inductor and leakage inductance of the isolation transformer, and can reduce the current flowing through the active switches at the currentfed side by half of the rated current. Since the current does not circulate through the fullbridge switches, their current stresses can be reduced dramatically under heavy-load condition, thus improving system reliability significantly. The flyback snubber can be also controlled to achieve a soft start-up feature. It has been successful in suppressing inrush current which is usually found in a boost-mode start-up transition.
VI. REFERENCES
[1] H.Bai andC.Mi, Eliminate reactive power and increase system efficiency of isolated bidirectional dual-active-bridge DC-DC converters using novel dual-phase-shift control, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 29052914, Dec. 2008. [2] B. Bai, C. Mi, and S. Gargies, The short-timescale transient processes in high-voltage and highpower isolated bidirectional DC-DC converters, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 26482656, Nov. 2008. [3] C. Zhao, S. D. Round, and J.W.Kolar, An isolated three-port bidirectional DC-DC converter with decoupled power flow management, IEEE Trans. Power Electron., vol. 23, no. 5, pp. 2443 2453, Sep. 2008. [4] R. Huang and S. K. Mazumder, A softswitching scheme for an isolated DC/DC converter with pulsating DC output for a three-phase highfrequency- link PWM converter, IEEE Trans. Power Electron., vol. 24, no. 10, pp. 22762288, Oct. 2009. [5] H. Xiao and S. Xie, A ZVS bidirectional dc-dc converter with phasedshift plus PWM control scheme, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 813823, Mar. 2008. [6] G. Ma, W. Qu, and Y. Liu, A zero-voltageswitching bidirectional DC-DC converter with state analysis and soft-switching-oriented design consideration, IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 21742184, Jun. 2009. [7] F. Krismer and J. W. Kolar, Accurate smallsignal model for the digital control of an automotive bidirectional dual active bridge, IEEE
30
A SOFT-SWITCHING DC-DC CONVERTER WITH HIGH VOLTAGE GAIN

Ms. M. Indira priyadarshini1, Mrs. S. Komala chitra2, Mr. P. Moorthy3
1
Final year- ME Power Electronics & Drives, Madha Engineering College, Chennai-600 069 2 Assitant Professor Dept of EEE, Madha Engineering College, Chennai-600 069 3 Head of Department of EEE, Madha Engineering College, Chennai-600 069 Email-m_indirapriyadarshini@yahoo.co.in
Abstract- This Paper Presents a Soft-Switching DC/DC Converter with High Voltage Gain. The soft switching characteristic of the proposed converter reduces switching loss of active power switches and raises the conversion efficiency. The reverse recovery problem of output rectifiers is also alleviated by controlling the current changing rates of diodes with the use of leakage inductance of a coupled inductor. Zero voltage switching is used for the switches in boost mode operation during turn on and turns off condition to reduce the switching losses during the transition and improves the overall efficiency. The efficiency of the proposed soft switching dcdc converter is verified by experimental results and the feasibility of the proposed circuits can be verified by PSPICE simulation.
Vin 24
V+
D2 MUR150 L4 1 74u D1 MUR150 V1 = 0 V2 = 10 TD = 6us TR = 0.1n TF = 0.1n PW = 4us PER = 10u 1 LB 154u R2 V1 = 0 V2 = 10 TD = 0 TR = 0.1n TF = 0.1n PW = 6us PER = 10u V1 1 M1 IRF540 105u 10 L3 2 2 V2 M2 IRF540 TX1 2
C1 1u
V+
C2 1u C5 47u R 648
C3 1u
V-
C4 1u
Index TermsBoost converter, high voltage gain, soft switching.

V-
I. INTRODUCTION Nowadays, the demand for dc/dc converters with high voltage gain has increased. The energy shortage and the atmosphere pollution have led to more researches on the renewable and green energy sources such as the solar arrays and the fuel cell. A DCDC converter with a high step-up voltage gain is used for many applications. Theoretically, a dcdc boost converter can achieve a high step up voltage gain with an extremely high duty ratio. However, in practice, the step-up voltage gain is limited due to the effect of power switches, rectifier diodes, and the equivalent series resistance (ESR) of inductors and capacitors. Moreover, the extremely high duty-ratio operation will result in a serious reverse-recovery problem. Linear regulators can output a lower, but not a higher, voltage from the input. They are very inefficient if the voltage drop is large and the current high as they dissipate as heat power equal to the product of the output current and the voltage
Fig. 1. Circuit Diagram of Soft Switching Dc/Dc Converter with High Voltage Gain drop; consequently they are not normally used for large-drop high-current applications. For a continuous input current, current-fed step-up converters were proposed. They provide high voltage gain and consequently they are not normally used for large-drop high-current applications. For a continuous input current, current-fed step-up converters were proposed. They provide high voltage gain and galvanic isolation. However, the additional snubbers are required to reduce the voltage stresses of switches. A dcdc fly back converter is a very simple structure with a high stepup voltage gain and an electrical isolation, but the active switch of this converter will suffer a high voltage stress due to the leakage inductance of the transformer.
31
Some of the transformers less dcdc converters, which include the cascade boost type, the quadratic boost type, the voltage-lift type, the capacitor-diode voltage multiplier type, and the boost type integrating with switched-capacitor technique. However, these types are all complex and have a higher cost. Conventional dcdc boost converters are unable to provide high step-up voltage gains due to the effect of power switches, rectifier diodes, and the equivalent series resistance of inductors and capacitors. In order to increase the efficiency and power conversion density, a softswitching technique is required in dc/dc converters. To increase the voltage gain, the output of the coupled inductor cell is laid on the top of the output of the CCM boost cell. Therefore, the high voltage gain is obtained without high turn ratio of the coupled inductor, and the voltage stresses of the switches are confined to the output voltage of the CCM boost cell. A zero-voltage-switching (ZVS) operation of the power switches reduces the switching loss during the switching transition and improves the overall efficiency.
boost converter cell. This cell consists of switches S1 and S2.The gate signal to these switches are generated by the control circuit. The output of the boost converter is the stepped up pulsating dc voltage. This voltage is applied to the coupled inductor which induces voltage at its secondary. The induced voltage is fed to the voltage doublers. This doubles the input voltage and load is connected to get the output voltage. b. Control circuit The gate signal to the switches of boost converter cell are generated by the micro controller PIC 12F508.The input to this controller is 5V.The signal from the controller is fed to the buffer which acts as a current amplifier. Its input is also 5V.Darlington pair isolator has input of 12V .Its function is to isolate high current signal from buffer and low rating switches. B.POWER CIRCUIT ANALYSIS A soft-switching dc/dc converter with high voltage gain, which is shown in the above fig., is proposed. A CCM boost cell provides a continuous input current. Fig. 1 shows the circuit diagram of the proposed soft switching dc/dc converter with high voltage gain. Its key waveforms are shown in Fig. 2. The switches S1 and S2 are operated asymmetrically and the duty ratio D is based on the switch S1 .D1 and D2 are intrinsic body diodes of S1 and S2. Capacitors C1 and C2 are the parasitic output capacitances of S1 and S2. The proposed converter contains a CCM boost cell. It consists of LB, S1, S2, Co1, and Co2. The CCM boost cell provides a continuous input current. When the switch S1 is turned on, the Boost inductor current iLB increases linearly from its minimum value ILB2 to its maximum value ILB1. When the switch S1 is turned off and the switch S2 is turned on, the current iLB decreases linearly from ILB1 to ILB2. To obtain ZVS of S1 and S2 and high voltage gain, a coupled Inductor Lc is inserted. The coupled inductor Lc is modeled as the magnetizing inductance Lm, the leakage inductance Lk, and the ideal transformer that has a turn ratio of 1: n (n = N2/N1).The voltage doublers consists of diodes D1, D2 and the output capacitors Co3, Co4, and the secondary winding N2 of the coupled inductor Lc is on the top of the output stage of the boost cell to increase voltage gain. The coupled inductor current IL varies from its minimum value IL1 to its maximum value IL2. The operation of the proposed converter in one switching period Ts can be divided into six modes. Fig. 3 shows the operating modes.
II PROPOSED CONVERTER A. BLOCK DIAGRAM The soft-switching dc/dc converter can be divided into two circuits. (a) Power circuit (b) Control circuit
DC VOLTAGE
BOOST CONVERTER
COUPLE INDUCTOR
VOLTAGE DOUBLER
DARLINGTON PAIR ISOLATOR
12V
LOAD
BUFFER
5V
PIC12F508
5V
Fig. 2. Block Diagram of Soft-switching dc/dc converter a. Power circuit This block consists of boost converter, coupled inductor, voltage doublers and load. Primarily, the DC input voltage is given to the
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Mode 1
Mode 2
Mode 3
Mode 4
Mode 5 Fig. 3. Operating modes Before t0, the switch S2 and diode D4 are conducting. Mode 1: At t0, the switch S2 is turned off. Then, the
Mode 6 boost inductor current iLB and the coupled inductor current IL starts to charge C2 and discharge C1. Therefore, the voltage vS1across S1 starts to fall and
33
the voltage vS2 across S2 starts to rise. The transition interval Tt1 of switches can be considered as since the output capacitances C1 and C2 of the switches are very small, the transition interval Tt1 is very short and it can be neglected. Therefore, the inductor currents iLB and iL can be considered to have constant values during mode 1. Mode 2: At t1, the voltage vS1 across the lower switch S1 becomes zero and the lower diode D1 is turn on. Then, the gate signal is applied to the switch S1. Since the current has already flown through the lower diode D1 and the voltage vS1 becomes zero before the switch S1 is turned on, zero-voltage turn-ON of S1 is achieved. Since the voltage across the boost inductor LB is Vin, the boost inductor current increases linearly from ILB2 . Mode 3: At t2, the secondary current i2 changes its direction. The diode current iD4 decreases to zero and the diode D4 is turned off. Then, diode D3 is turned on and its current increases linearly. Since the current changing rate of D4 is controlled by the leakage inductance of the coupled inductor, its reverse-recovery problem is alleviated. Mode4: At t3, the lower switch S1 is turned off. Then, the boost inductor current iLB and the coupled inductor current iL starts to charge C1 and discharge C2. Therefore, the voltages vS1 and vS2 start to rise and fall in a manner similar to that in mode 1. The transition interval Tt2 of switches can be considered as Tt2 is also negligible. Therefore, the inductor currents iLB and iL can be considered to have constant values during Tt2 . Mode 5: At t4 , the voltage vS2 across the upper switch S2 becomes zero and the diode D2 is turned on. Then, the gate signal is applied to the switch S2. Since the current has already flown through the diode D2 and the voltage vS2 becomes zero before the switch S2 is turned on, zero-voltage turn-ON of S2 is achieved. Mode 6: At t5 , the secondary current i2 changes its direction. The diode current iD3 decreases to zero and the diode D3 is turned off. The reverse-recovery problem of D3 is also alleviated due to the leakage inductance of Lc. Then, the diode D4 is turned on and its current increases linearly.
III. SIMULATION Simulation has become a very powerful tool in industry application as well as in academics, nowadays. It is now essential for an electrical engineer to understand the concept of simulation and learn its use in various applications. Simulation is one of the best ways to study the system or circuit behavior without damaging it. The tools for doing the simulation in various fields are available in the market for engineering professionals. Many industries are spending a considerable amount of time and money in doing simulation before manufacturing their product. In most of the research and development (R&D) work, the simulation plays very important role. Without simulation, it is quite impossible to proceed further. It should be noted that in power electronics, computer simulation and a proof of concept hardware prototype in the laboratory are complimentary to each other. However, computer simulation should not be looked upon as a substitute for a hardware prototype. In many cases, testing a real world system can be prohibitively expensive or out rightly impossible. Seeing how the generator of a power plant is going to be damaged in a real system is an example of an expensive exercise to conduct in reality. But by damaging the generator into a simulated fault condition, generator safety engineers can quickly evaluate potential designs and reduce the level of risk for it to sacrifice. A. SIMULATION TOOLS Simulation of power electronic converters and can be done, either by (I) circuit oriented simulator (e.g. PSPICE, PSIM, TINA, electronics workbench, etc), or by (2) mathematical model based equation solvers using high level languages (e.g., C++, VISUALBASIC, etc.), or high level language based packages (MATLAB, MATHEMATICA, etc). In this we can use the circuit-oriented simulators (Pspice) also few software simulation tools are listed which are widely accepted by the engineering society, particularly by the electrical engineers. The simulation tools are in use in industries as well as academic institution. B. EXPERIMENTAL RESULTS The prototype soft-switching dc/dc converter with high voltage gain is implemented with specifications of n = 5, Vin = 24 V, Vo = 360 V, LB = 154 H, Lk = 74 H, Co1 = Co2 = Co3 = Co4 = 1
34
REFERENCES [1] F. Blaabjerg, Z. Chen, and S. B. Kjaer, Power electronics as efficient interface in dispersed power generation systems, IEEE Trans. Power Electron., vol. 19, no. 5, pp. 11841194, Sep. 2004. [2] R. J. Wai, W. H. Wang, and C. Y. Lin, Highperformance stand-alone photovoltaic generation system, IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 240250, Jan. 2008. [3] C. Wang and M. H. Nehrir, Power management of a standalone wind/photovoltaic/fuel cell energy system, IEEE Trans. Energy Convers., vol. 23, no. 3, pp. 957967, Sep. 2008. [4] R. J. Wai and W. H. Wang, Grid-connected photovoltaic generation system, IEEETrans. CircuitsSyst. I, Reg. Papers, vol. 55, no. 3, pp. 953 964, Apr. 2008. [5] R. J.Wai, C. Y. Lin, R. Y. Duan, and Y. R. Chang, High-efficiency power conversion system for kilowatt-level distributed generation unit with low input voltage, IEEE Trans. Ind. Electron., vol. 55, no. 10, pp. 37023714, Oct. 2008. [6] K. Kobayashi, H. Matsuo, and Y. Sekine, Novel solar-cell power supply system using a multiple-input DCDC converter, IEEE Trans. Ind. Electron., vol. 53, no. 1, pp. 281286, Feb. 2006. [7] S. K. Mazumder, R. K. Burra, and K. Acharya, A ripple-mitigating and energy-efficient fuel cell power-conditioning system, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 14371452, Jul. 2007. [8] C. Wang, Y. Kang, B. Lu, J. Sun, M. Xu, W. Dong, F. C. Lee, and W.C. Tipton, A high powerdensity, high efficiency front-end converter for capacitor charging application, in Proc. IEEE APEC, Mar. 2005, vol. 2, pp. 12581264. [9] Z. Qun and F. C. Lee, High-efficiency, high step-up DCDC converters, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 6573, Jan. 2003. [10] X. Kong and A. M. Khambadkone, Analysis and implementation of ahigh efficiency, interleaved current-fed full bridge converter for fuel cell system, IEEE Trans. Power Electron., vol. 22, no. 2, pp. 543550, Mar 2007 [11] S. Pradhan, S. K. Mazumder, J. Hartvigsen, and M. Hollist, Effects of electrical feedbacks on planar solid-oxide fuel cell, ASME J. Fuel Cell Sci. Technol., vol. 4, no. 2, pp. 154166, May 2007.
F, C05 = 47 F, Lm = 105 H, fs = 100 kHz, and Po = 747.7 mW. Fig. 4 shows PSPICE simulation results. It is clear that the reverse-recovery current is significantly reduced and the reverse-recovery problem is alleviated dramatically by the leakage inductance of the coupled inductor Lc. It exhibits an efficiency of 96.4% at full-load condition. Due to its soft-switching characteristic and alleviated reverserecovery problem, the overall efficiency was improved by around 2% compared with the conventional high step-up boost converter with a coupled inductor.
Fig 5.8 Output Voltage Waveform
IV. CONCLUSION A soft-switching dc/dc converter with high voltage gain has been proposed in this paper. The proposed converter can minimize the voltage stresses of the switching devices and lower the turn ratio of the coupled inductor. It provides a continuous input current, and the ripple components of the input current can be controlled by using the inductance of the CCM boost cell. Soft switching of power switches and the alleviated reverse-recovery problem of the output rectifiers improve the overall efficiency.
35
Analysis of Matrix Converter with Direct Driven Permanent Magnet Generator

K.Lalitha1 , R. Bharanikumar 2 , A. Nirmal Kumar3
1, 2, 3
Department of Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Anna University, Tamil Nadu India E-mail: lalithkannan@gmail.com
ABSTRACT: This paper which mainly focuses on single stage power conversion for a Wind Energy Conversion System (WECS) consists of Wind Turbine, Permanent Magnet Generator (PMG) and Matrix Converter. The traditional power conversion from AC-AC consists of a rectifier, boost chopper and inverter. This three stage conversion which is the main cause for the reduction of overall efficiency.The advantages of Matrix converter is mainly utilized to control the output voltage and output frequency, and size of power converters are small in size and are of low cost. It is a simple and compact AC-AC converter. The proposed wind turbine, PMG with matrix converter is modeled using PSIM. Index Terms - Wind Turbine, PMG, Matrix Converter, Boost chopper, Inverter.
NOMENCLATURE
A Iq , Id - Velocity of the Wind V - Tip Speed Ratio
- Air density - Area swept by the blades - Power Angle - q,d- Axis Current
- Turbine Speed - Pitch Angle - Power Coefficient - Phase Voltages - Phase Resistances - Differential Operator (d/dt) - Flux Linkages in the phases - Load voltage with respect to neutral
Cp
Vabc Rabc
P
abc
V jn
I. INTRODUCTION The demand for electricity increases day by day with the increase in population all over the world .This demand is more on developing countries and also due to the depletion of fossil fuels and the environmental problem caused due to the usage of fossil fuels. Renewable energy sources are distributed in nature. Therefore require distributed infrastructure for energy production. Windmills are distributed in a wide area
where the power is generated at low voltage level. The generator used for WECS are Induction generators, synchronous generators, permanent magnet generators etc. The PMG is made up of permanent magnets that are very stable with very high coercive magnetic field and high specific energy A growing proportion of energy is being met all over the world by electricity. This trend will further be simulated because of increasing availability of clean electricity. This applies especially to developing countries because their industrial progress will be based on modern technological development in power generation. During recent years, due to the increase in fossil fuel prices and the environmental problems caused by the use of conventional fuels, we are reverting back to renewable energy source. Wind is the one of the source of renewable energy. Wind power is converted in to electricity by wind turbine generator. In a typical wind turbine, the wind energy of kinetic energy is converted in to rotational motion by three bladed rotor assembly at the front of the wind turbine. Growing application various technologies are developed in wind energy conversion systems (WECSS). It is the result of the effort to further improve wind turbine energy conversion system based on the permanent magnet generator. The induction type machine has the drawbacks of need for an AC excitation source and low power factor. PMG is choosing so as to eliminate the drawbacks of induction generator [1]. PMG is directly driven by wind turbine which results in elimination of gearing system is called as variable speed wind turbine system. A variable speed configuration system consists of wind turbine, PMG, matrix converter. This matrix converter has less variation in electrical power; obtain maximum power, reduced acoustical noise at lower wind speed, lower mechanical stress [2]. In addition the PMG does not need of DC excitation, robust in construction, compact size, require less maintenance. It is mainly used in remote area where it is directly connected to load not to grid system. These are the advantages by choosing this type of proposed system. In axial type PMG have been used increasingly highenergy magnets for various applications. They have several unique features such as high power density, high efficiency etc. [3]. In axial type PMG have possibility to
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energy is converted in to electrical energy by PMG. This power goes to load through the matrix converter. Since the wind power fluctuates with wind velocity, the generator output voltage and frequency vary continuously. The matrix converter converts AC-AC with controlled output value and produce desire output voltage and frequency. III. THEORETICAL ANALYSIS 3.1 Wind Turbine Model The main classification of wind turbines are vertical axis type and horizontal axis type. Due to the advantages of low cost, high efficiency and ease in design for high power ratings , horizontal axis type are used in modern wind turbines The wind turbine output power is given in the equations as (1), [8, 13]
achieve small pole pitch allows the generator to operate at low speed and either eliminates the need for the gear box or permits use of the single stage, low transfer ratio gears for more compact design. matrix converter firstly introduce in 1976. Recent years most interesting research is going on above matrix converter [4]. It is providing direct AC-AC power conversion. It has following advantages, (i) It has no energy storage element (ii) Possibility of to get unity power factor (iii) Simple and compact design (iv) Regeneration capability (v) Sinusoidal input and output currents The matrix converter is a converter which uses forced commutation for thyristor switches. It can construct by an array of bidirectional controlled switches. These switches in matrix converter theoretically assume 512 (29) different switching state combinations but not all of them can be employed for practical applications. This switching state is basically two rules. [5] The converter is supplied by a voltage source and usually feeds an inductive load, (i) The input phase should never be short Circuited (ii) Output current should not be interrupted (iii) The output phase should not be kept open circuited In practical cases these rules imply one and only bidirectional switch per output phase must be switched on at any instant. By this constraint in three phase to three phase matrix converter switching combination have 27. Different control schemes are to be employed to control the matrix converter. In that paper the PWM method is proposed to get rid of the undesirable effects of the distorted input voltages for matrix converter. Since this technique utilize the more wind energy, improving the output performance of the system and reduce the harmonic effects. II. COMPONENTS OF WIND ELECTRIC SYSTEMS
1 P = R 3V 2 C p 2
(1)
Where the power coefficient Cp is a nonlinear function of wind velocity and blade pitch angle and is highly dependent on the constructive features and characteristics of the turbine. It is represented as a function of the tip speed ratio given by
R t V
(2)
It is obvious to mention that at the optimum tip speed ratio, maximum aerodynamic efficiency is obtained. The torque expression is obtained from equation (1) by dividing turbine speed. It is given in (3),
1 Tt (V , t ) = R 2Ct ( )V 3 2
C p ( )
(3)
Where Ct () is the torque co-efficient of the turbine, given by
Ct ( ) =
165 .
(4)
The power co-efficient Cp is given by
116 Cp() = (0.4*) 50.5e 1 1

Where,
(5)
1 =
1 1 0.035 ( + 0.089 ) 3 +1
(6)
Fig 1. Block diagram of proposed wind electric generator system.
The basic component of wind electric system is wind turbine, PMG, matrix converter shown in Figure 1. Wind energy of kinetic energy is converted in to mechanical energy by wind turbine and mechanical
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r =
P n G m 2
(11)
P pr = n (Tm Te) 2Jg
(12)
(13)
p = r
Torque developed by the turbine Tt released to the input to the generator Tm is expressed as T (14) Tm = t G
Fig 2. Wind Turbine Model
3.2 Permanent Magnet Generator Model Permanent Magnet Generator provides an optimal solution for varying-speed wind turbines, of gearless or single-stage gear configuration [7]. This eliminates the need for separate base frames, gearboxes, couplings, shaft lines, and pre-assembly of the nacelle. The output of the generator can be fed to the power grid directly. A high level of overall efficiency can be achieved, while keeping the mechanical structure of the turbine simple [7].
IV. MATRIX CONVERTER A matrix converter is a most compatible converter without any limits on the output voltage, frequency. It replaces the multiple conversion stages by single stage conversion and the intermediate energy storage element by a single power conversion stage, and uses a matrix converter which consists of bidirectional switches. With a switch connected between each input terminal to each output terminal. A three phase matrix converter requires nine bidirectional switches capable of blocking voltage and conducting current in both directions. There are no such devices currently available, so usually the bidirectional switches, consists of two IGBTs connected in anti parallel [4]. Basic matrix converter with PMG topology is shown in Figure 4.
Fig 3. Equivalent circuit PM
Generator for one phase Generated emf / phase , E= Vt+ Ia (Ra+jXs) = Vt+IaZs
(7)
where Zs= Ra 2 + Xs 2 The rotor reference frames of the voltages are obtained as The rotor reference frames of the voltages are
Vq = RS + Lq p Iq r Ld Id + rm
Fig 4. Basic matrix converter topology.
(8) (9)
Vd = (RS + Ld p)Id +rLqIq
The expression for the electromagnetic (EM) torque in the rotor is given by
3 P Te = n Ld Lq I q I d mI q 2 2
[(
(10)
The relationship between the angular frequency of the stator voltage (r) and the mechanical angular velocity of the rotor (m) is obtained as follows:
It has an array of m x n combination, directly connects m-phase voltage source to an n-phase load. In Figure 4 shows 3 x 3 matrix converter totally 9 switches are used. In Venturini method, the appropriate firing pulses to each of the nine bidirectional switches must be calculated to generate sinusoidal output voltages and variable frequency value. In that paper Vjn, j={a,b,c} are the load voltage with respect neutral point n of the load, and Ij, j={a,b,c} , are the load currents. Matrix Converter input voltage is Vi, i ={A,B,C} MC input current is ii, i ={A,B,C}. The modulation matrix is,
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frequency of the reference signal fr determines the output frequency fo. To generate the SPWM patterns those are used to control the power switches. V. RESULTS
mAa (t ) mBa (t ) mCa (t ) M (t ) = mAb (t ) mBb (t ) mCb (t ) mAc (t ) mBc (t ) mCc (t )
(15)
The sinusoidal input voltages of the matrix converter can be given by,
cos(i t ) cos( t 2 / 3) vi = i cos(i t + 2 / 3)
(16)
The sinusoidal output currents of the matrix converter can be given by,
cos(ot + o ) cos( t + 2 / 3) io = I om o o cos(ot + o + 2 / 3)

Where,
(17)
Fig 5.Simulation Model of Wind Generator System
is the output current phase angle.
In accordance with this each output phase voltage can be expressed by,
Fig 5. Shows the overall simulation model of Wind Electric Conversion System. This model is simulated for various wind velocities, see Fig . 6-to 8
v jN (t ) = [ M (t )][ vi (t )]
(18)
In the same way the input current are also shown by expression in,
[ii (t )] = [ M (t )] [io (t )]
T
(19)
Where,
[ M (t )]
is the transpose matrix of M (t ) Duty

Fig 6. Wind Turbine Speed
cycles of bidirectional switches were calculated according to, 1 2v v 2q (20) tKj = Ts + k2 j + sin(it + k )sin(3i (t ) 3 3vim 9qm
K= {A,B,C}; j={a,b,c}, = 0, 2/3, 4/3. 4.1 Sinusoidal Pulse Width Modulation for a Single Phase Matrix Converter The efficient method of controlling the output voltage of matrix converter is to incorporate PWM control within the converter. Through there are different PWM control techniques, the Sinusoidal Pulse Width Modulation (SPWM) is a well famous shaping technique of output voltage. The gating signals are generated by comparing a sinusoidal reference signal with a triangular carries wave of frequency fc. The
Fig 6 shows the wind turbine speed in rpm for different values of wind velocity. Wind turbine reaches the steady state at t=0.020milliseconds at all wind velocities. Fig 7 shows the Permanent Magnet Generator output voltages for different values of wind velocities. The generated voltage reaches steady state at t=0.020milliseconds
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Fig. 10. Shows matrix converter constant output voltage for different wind velocity value in closed loop operation. V. CONCLUSION The wind turbine directly driven Permanent Magnet Generator is modeled using PSIM tool and analyzed output for various input wind velocities. As the wind velocity varies the output voltage of PMSG also varies. The varying voltage is converted in to fixed voltage, fixed frequency. The constant voltage from the converter is controlled by Sinusoidal Pulse Width Modulation (SPWM) technique. Simulation study on a Wind Generated System employing PSIM model is the core coverage in this paper. VI. REFERENCES
[1] N.Yamamura, M.Ishida, T.Hori, A Simple Wind Power Generating System with Permanent Magnet Type Synchronous Generator, IEEE Conference PED99,pp.849-854. [2] S. M. Barakati, J. D. Aplevich, and M. Kazerani, Controller design for a wind turbine system including a matrix converter, in Proc. IEEE PES Gen. Meet., 2007, pp. 18. [3] M.Sadeghierad, H.Monesf, and A.Darabi, Design Considerations of High Speed Axial Flux Permanent Magnet Generator with Coreless Stator in 8th International Power Engineering Conference (IPEC 2007), pp.1097-1102. [4] Hulusi karaka, Ramazan akkaya Control of Venturini Method Based Matrix Converter in Input Voltage Variations, in Proc. International multiconference of engineers and computer scientists march, 2009.vol-II, Hong Kong. [5] L. Helle, K. B. Larsen, A. H. Jorgensen, S. Munk-Nielsen, and F. Blaabjerg, Evaluation of modulation schemes for three-phase to threephase matrix converters, IEEE Trans. Ind. Electron., vol. 51, no. 1, pp. 158171, Feb. 2004. [6] Kelvin Tan,Syed Islam: Optimum Control Strategies in Energy Conversion of PMSG Wind Turbine System without Mechanical Sensors,IEEE Transactions on Energy Conversion, vol. 19, no. 2, June 2004, pp.392-399 [7] A.B. Raju, K.Chatterjee and B.G. Fernandes, A Simple Power Point Tracker for Grid connected Variable Speed Wind Energy Conversion System with reduced Switch Count Power Converters IEEE Transactions on Power Electronics,2003. pp 456-462.
Fig 7. PMSG Output Voltage
Fig 8. Matrix Converter Output Voltage
Fig 8 shows the matrix converter output voltage for different values of wind velocity. The converter output frequency is 50Hz constant. This is given to SPWM inverter.
Wind velocity vs Output voltage 250 200
Voltage (v)
150 100 50 0 7 9 10 11 12 13 14 15 Wind Velocity m/s
BIOGRAPHIES
Lalitha.K was born in Tamilnadu India, on Jan 19, 1986. She received Diploma in Electrical & Electronics Engineering from Rudhraveni Muthuswmy Polytechnic College, Udumalpet. She received her B.E Degree in Electrical and Electronics Engineering from Erode Sengunthar Engineering College, Perundurai, Anna University. Currently she is pursuing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, affiliated to Anna University of technology,Coimbatore. Her field of interest includes PMG, Power converters and Reactive power. Bharanikumar.R was born in Tamilnadu, India, on May 30, 1977. He received the B.E degree in Electrical and Electronics Engineering from Bharathiar University, in 1998. He received his M.E Power Electronics and Drives from College of Engineering Guindy Anna University in 2002. He has 9 yrs of teaching experience. Currently he is working as Asst. Professor in EEE department, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India Currently he is
Fig 9. Wind Speed Vs output voltage
When the wind Velocity varies the output voltage of PMG varied. Fig 9. Shows the different wind Velocity and their corresponding output voltage.
Fig 10. Constant output voltage
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doing research in the field of power converter for special machines; vector controlled based synchronous machine drives, converters for wind energy conversion systems. A.Nirmal Kumar was born in the year 1951. He completed his PG and UG in Electrical Engineering from Kerala and Calicut University respectively. He completed PhD in Power Electronics in the year 1992 from P.S.G. College of Technology, Coimbatore under Bharathiar University. He was with N.S.S. College of Engineering for nearly 28 years in various posts before joining Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India in the year 2004. He is a recipient of Institution of Engineers Gold Medal in the year 1989. His current research areas include Power converters for Wind Energy Conversion System and Controller for Induction motor drives.
1
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Design and Real Time Implementation of Integrated Fuzzy Logic Controller for a High Speed PMDC Motor
1
Maadhu iniya.J, 2Sivasakthi.S,3Vidhya.R ,4Vijayalakshmi.K

Dept of EEE, Info Institute of Engineering, Kovilpalayam, Coimbatore-641107, Tamil Nadu, India. 1 iniyainfoeee@gmail.com 2 Sakthi.iie@gmail.com 3 vidsmile@yahoo.com 4 Vijieee.viji7@gmail.com
ABSTRACT: This paper presents the design and implementation of an integrated fuzzy logic controller (IFLC) for a high-speed permanent magnet DC (PMDC) motor speed control system. The proposed strategy is intended to improve the performance of the conventional controller by use of IFLC. The system is studied for step input with and without load (magnetic) conditions and for various standard input test commands such as square, triangular, sinusoidal, and ramp. The experimental implementation demonstrates that IFLC is particularly effective in speed control of PMDC motor under the abovementioned conditions. The graphical results of the proposed controller are presented and are compared with conventional controllers. Keywords: Integrated fuzzy logic controller, high speed control, PMDC motor, analog interface card.
input commands include triangular and sinusoidal, the nonlinear input includes step and square, and semi-linear input i.e., ramp. In this paper, the real time implementation of IFLC for high-speed PMDC motor is discussed. Heuristic knowledge is applied to define fuzzy membership functions and rules. The membership functions and rules are modified after initially barrowing the knowledge from PID controller developed from simple linear model. The process of fuzzification is done based on min-max (MOM) method. The defuzzification is done using centre of gravity (COG) method.
II. NEED
The PMDC motor is one of the most widely used prime movers in industry today. PMDC motors used in many applications such as steel rolling mills, electric tracking systems, textile mills -including weaving and spinning, robotic manipulators, defense etc., require precise speed controllers to perform these tasks. The major problems in applying the conventional control algorithms in a speed controller are the effects of non-linearity in a DC motor. The nonlinear characteristics of a DC motor such as saturation and friction could degrade the performance of conventional controllers. Many advanced model-based control methods such as variable structure control and model reference adaptive control have been developed to reduce these effects. However, the performance of these methods depends on the accuracy of system models and parameters. Generally, an accurate nonlinear model of an actual DC motor is difficult to find, and parameter values obtained from system
I.
INTRODUCTION
The proposed system aims at implementing integrated fuzzy logic controller, which is a combination of both fuzzy logic and PID controllers (PIDC), on a PC with a new highresolution, high-speed 16-bit analog interface card (AIC) designed for parallel port of PC. This approach is novice and makes the hardware portable. The performance of the proposed controller is studied at high speed of 5000 rpm and for various linear and nonlinear input test signals. The linear
2
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identification may be only approximated values. Emerging intelligent techniques have been developed and extensively used to improve or to replace conventional control techniques, because these techniques do not require a precise model. One of the intelligent techniques, fuzzy logic developed by Lotfi A. Zadeh ,is applied for controller design in many applications. A fuzzy logic controller (FLC) was proved analytically to be equivalent to a nonlinear PI controller, when a nonlinear defuzzification method is used. A. Literature survey Lee, Chun Chen, 1990, "Fuzzy logic in control systems: Fuzzy logic controller" - Part I, II. IEEE Transactions on Systems, Man and Cybernetics, 20, 2. Zadeh, Lotfi A., 1965, "Fuzzy setsInformation Control", 8, 338-353. C. Conventional Methods III. SYSTEM ANALYSIS Importance of integrated fuzzy logic controller and conventional methods used for speed control are discussed A. Fuzzy logic controller Fuzzy controllers are very simple conceptually. They consist of an input stage, a processing stage, and an output stage. The input stage maps sensor or other inputs, such as switches, thumbwheels, and so on, to the appropriate membership functions and truth values. The processing stage invokes each appropriate rule and generates a result for each, then combines the results of the rules. Finally, the output stage converts the combined result back into a specific control output value.The most common shape of membership functions is triangular, although trapezoidal and bell curves are also used, but the shape is generally less important than the number of curves and their placement. From three to seven curves are generally appropriate to cover the required range of an input value, or the "universe of discourse" in fuzzy jargon.The processing stage is based on a collection of logic rules in the form of IF-THEN statements, where the IF part is called the "antecedent" and the THEN part is called the "consequent". Typical fuzzy control systems have dozens of rules. B. Integrated fuzzy logic controller The basic IFLC configuration is shown in Fig. 1, where FLC is used in a supplementary role to enhance the conventional PIDC. When the control conditions change, FLCs are easy to realize and the system behavior can be easily redesigned by modifying the fuzzy logic rules. One does not have to redesign the existing control system hardware in order to acquire satisfactory response during the change of load conditions and appearance of disturbances These are some of the more common methods of speed control method: 1) Ward Leonard control: A Ward Leonard drive is a high-power amplifier in the multi-kilowatt range, built from rotating electrical machinery. A Ward Leonard drive unit consists of a motor and generator with shafts coupled together. The motor, which turns at a constant speed, may be AC or DC powered. The generator is a DC generator, with field windings and armature windings. The input to the amplifier is applied to the field windings, and the output comes from the armature windings. The amplifier output is usually connected to a second motor, which moves the load, such as an elevator. With this arrangement, small changes in current applied to the input, and thus the generator field, result in large changes in the output, allowing smooth speed control. Armature voltage control only controls the motor speed from zero to motor base speed. If higher motor speeds are needed the motor field current can be lowered, however by doing this the available torque at the motor armature will be reduced.
2) Armature-voltage DC Motor Control:
In this method, shunt-field current is maintained constant from a separate source while the voltage applied to the armature is varied. Dc motors feature a speed, which is proportional to the counter emf. This is equal to the applied voltage minus the armature circuit IR drop. At rated current, the torque remains constant regardless of the dc motor speed (since the magnetic flux is constant) and, therefore, the dc motor has constant torque capability over its speed range.
3
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and transmits output control signals through the AIC. The proposed real-time control algorithms such as PID, FL, and IFL controllers and other control schemes are implemented on this platform.
IV. PROPOSED SYSTEM The block diagram of the proposed system is shown in figure no- 02and figure no-03
V.
RESULTS AND DISCUSSIONS
The experimental results of PMDC motor are discussed here for a desired speed (of 5000 RPM), for load (magnetic) conditions, and for various standard input test commands such as step, square, triangular, sinusoidal, and ramp.
Figure 02: Block diagram of IFLC based PMDC motor speed control system.
A. For Desired speed: Fig. 04 shows the step response of PMDC motor for PID, FL, and IFL controllers for a desired speed of 5000 rpm.
Figure03: Blockdiagram of analog interface card.
The block diagram of experimental PMDC motor control system is illustrated in Fig. 5. We have used PMDC motor unit from LUNAR Motors Pvt. Ltd. India. The motor details are presented in Table I. The system consists of PMDC motor, speed sensor, analog interface card, personal computer, and driver. An indigenous 16-bit analog interface card (AIC), designed by the authors [20], is used as the interface for implementation of digital controller. The card is designed for multi purposes i.e., it can be used both for measurement, and control. The card mainly consists of a high- speed four channel 16-bit serial A/D converter -AD974 from Analog Devices [21], and a 16-bit serial D/A converter -MAX542 from Maxim [22]. The D/A converter is operated in bipolar mode in order to drive the motor in both clockwise and anti-clock wise directions. The control output from PC is a digital data, which is converted into equivalent analog voltage by D/A converter. The D/A converter is provided with onboard four channels using analog multiplexer -CD4051 to control multiple parameters. The card is interfaced to PC through parallel port. The AIC is shown in Fig. 6. The photograph of AIC is shown in Fig. 7. In the present study a PC -Intel Pentium-IV processor with 1.7GHz clock frequency, 128MB RAM, 40GB HDD, one parallel port, and two serial ports is employed for controlling the speed of a PMDC motor. The PC receives input signals
Figure 04: Comparison of PIDC, FLC, and IFLC for step input
B.Square input: A square input command is applied to all the controllers. Fig. 05 shows the response of PMDC motor for PID, FL, and IFL controllers for square input command. The rise time of IFLC is observed to be better than the FLC, and PIDC. It is clear from the plot that IFLCs trail is close to the input command than the other two.
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We are highly obliged and express our sense of gratitude to Mr. T. RAJESH M.E., Ms. M. VIDHYA M.Tech., for their valuable support and help. REFERENCES Liptak, B. G., 1995 "Instrument Engineers' Handbook" Process Control. Butterworth Heinemann Ltd., Oxford. Zadeh, Lotfi A., 1965, "Fuzzsets.Information Control", 8, 338-353. Zheng, Li, 1992, "A practical guide to tune of PI like fuzzy controllers", IEEE Int. Conf. on Fuzzy Systems. Mamdani, E. H. and Assilian, S., 1975, "An experiment in linguistic synthesis with a fuzzy logic controller", Int. J Man Machine Studies, 7, 1-13. Lee, Chun Chen, 1990, "Fuzzy logic in control systems: Fuzzy logic controller" - Part I, II. IEEE Transactions on Systems, Man and Cybernetics 20, 2.
C.Triangular and Sinusoidal Triangular and sinusoidal input commands are applied to all the controllers. Fig. 06 shows the response of PMDC motor for PID, FL, and IFL controllers for triangular and sinusoidal input commands respectively. In both the cases it is found that PIDC and IFLCs trails are closer to the input command than the FLC.
[1] [2] [3] [4]
[5]
Figure05: Comparison of PIDC, FLC, and IFLC for square input.
[6] Guillemin, P., 1996, "Fuzzy logic applied to motor control", IEEE Trans. Ind. Applications, 32, 51-56.
Figure 06: Responses of PIDC, FLC, and IFLC for (a) triangular input, (b) sine input
VI. FUTURE ENHANCEMENTS Our next work is to is to implement the speed control of motor using zigbee technique to overcome the complexities in fuzzy logic. VII .CONCLUSION By studying the response of PID, FL, and IFL controllers for various inputs, it is concluded that for non-linear inputs (step and square) the FL and IFL controllers perform better than the conventional PID controller. Whereas for linear inputs (triangular and sine) PID and IFL controllers are better than FLC. PIDC response is best for linear portion of the wave where as it has poor response for non-linear portion of the wave (changing from max to zero). But for both the cases IFL responds quicker than the other controller as it contains both the controllers.
ACKNOWLEDGMENT We express our preformed gratitude to Dr.A. NIRMAL KUMAR, Head of the Electrical and Electronics Engineering department his unique innovative plans, dynamic guidance with constant encouragement and motivation, which triggered us to great extent in completion.
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Design and Analysis of Soft Switching Boost converter for Photovoltaic Applications
B.Saravanakumar *, P.Sivaraman #
*PG Scholar, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India.
# Senior Lecturer, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India.
{sivaramanpsr@gmail.com, saravaaa.official@gmail.com}
Abstract In this paper, a high efficiency soft switching boost converter is proposed for photovoltaic system. A softswitching boost converter using a simple auxiliary resonant circuit, which is composed of an auxiliary switch, a diode, a resonant inductor, and a resonant capacitor, is adopted in this paper .Using this simple auxiliary circuit it is possible to reduce the switching losses device stress and improve the efficiency of photo voltaic system considerably. Size of this L and C is very small as it is operated in the very high resonant frequency. Each of the switches in the proposed circuit performs ZV (Zero Voltage) or ZC (Zero Current) switching. This paper also presents an easy and accurate modeling of photovoltaic arrays to obtain the array model using information from datasheet. MPPT controller using improved P&O algorithm is implemented for tracking the maximum power .The photovoltaic model, MPPT controller and soft switching boost converter are simulated altogether to confirm the theoretical analysis. 1. INTRODUCTION PV (Photovoltaic) generation has constraints on the amount of sunlight, temperature, and other environmental conditions. Moreover, the energy conversion efficiency of PV generation is fairly low. In order to supplement for these weaknesses, there are many researches going on to increase the efficiencies of the solar cell and the electric power conversion device On the other hand, in cases of converters doing hard switching at a high frequency, the switching loss increases in proportion to the switching frequency. Thus, in order to reduce switching losses, the soft switching technology, which uses resonance by inductor and capacitor, has been actively researched [1-6].the size of the inductor and capacitor used are very small since they are operated at higher resonant frequency. This paper proposes a soft switching boost converter to improve the efficiency of the boost converter, which is an energy conversion device, to raise the low output voltage of solar array. Under the condition of zero-voltage and zerocurrent by inductor and capacitor resonance, soft switching can cut down the stress and loss produced at the switch. In this paper, the detailed explanation of the soft switching boost converter, PV module, and MPPT
controller with improved P&O algorithm are offered. After that simulations are performed to confirm the aforementioned operational explanation under the condition of 30 kHz switching frequency and PV input voltage using a PSIM simulation tool. And then we adduce some simulated results to ascertain the validity of the proposed circuit. 2. MODELING OF PV DEVICES 2.1. Ideal PV Cell Fig. 1 shows the equivalent circuit of the ideal PV cell. The basic equation from the theory of semiconductors [7] that mathematically describes the IV characteristic of the ideal PV cell
Fig. 1. Equivalent Circuit of a Solar Cell.
I I PV ,cell I d
(1)
I d I o,cell [exp(
is
qV ) 1] aKT
(2)
I I PV ,cell I o,cell [exp(
qV ) 1] aKT
(3)
where Ipv, cell is the current generated by the incident light (it is directly proportional to the Sun irradiation), Id is the Shockley diode equation, I0,cell is the reverse saturation or leakage current of the diode, q is the electron charge (1.60217646 1019 C), k is the Boltzmann constant (1.3806503 1023 J/K), T (in Kelvin) is the temperature of the pn junction, and a is the diode ideality constant
46
Fig 2 IV Characteristic Curves for ions 2.2. Modeling the PV Array The basic equation (3) of the elementary PV cell does not represent the IV characteristic of a practical PV array. Practical arrays are composed of several connected PV cells and the observation of the characteristics at the terminals of the PV array requires the inclusion of additional parameters to the basic equation [3]
Fig 3. PV array model circuit with a Controlled current source, equivalent resistors, and the equation of the model current (Im ).
3. THE IMPROVED P&O ALGORITHM The modified P&O algorithm was presented [14] [17]. it can be defined as improved based on the basic P&O algorithms which fails to track maximum power quickly .figure 4 shows the flowchart of control algorithm. an additional control loop is proposed in this modified version .if there is a large change in array output current,it can be supposed that this is due to sudden change in insolation which is caused by fast moving clouds
I I PV I o [exp(
V Rs I qV ) 1] Vt a Rp
(4)
where Ipv and I0 are the photovoltaic (PV) and saturation currents, respectively, of the array and Vt = NskT/q is the thermal voltage of the array with Ns cells connected in series The diode saturation current I0 and its dependence on the temperature may be expressed by as shown [8], [9], [10] [12] below equation (5):
qE 1 1 T 3n I o I o,n ( 3 ) exp[ g ( )] T ak Tn T
(5)
where Eg is the band gap energy of the semiconductor (Eg = 1.12 eV for the polycrystalline Si at 25 C [13], [10]), and I0,n is the nominal saturation current: I0,n = Isc,n exp(Voc,n/aVt,n ) 1 (6) with Vt,n being the thermal voltage of Ns series-connected cells at the nominal temperature Tn. The light-generated current of the PV cell depends linearly on the solar irradiation and is also influenced by the temperature where Ipv,n (in amperes) is the lightgenerated current at the nominal condition (usually 25 C and 1000 W/m2 ), T =T Tn (T and Tn being the actual and nominal temperatures [in Kelvin], respectively), G (watts per square meters) is the irradiation on the device surface, and Gn is the nominal irradiation.
I pv =(I pv ,n k1dt )
G Gn
(6)
The value of the model current Im is calculated by the computational block that has V , I, I0 , and Ipv as inputs. I0 is obtained from (5) or (7) and Ivp is obtained from (4). This computational block may be implemented in any circuit simulator able to evaluate math functions
Fig 4 Flowcharts for Perturb and Observe Algorithm
47
4.1 MODES OF OPERATION 4. SOFT-SWITCHING BOOST CONVERTER FOR PV GENERATION SYSTEM 4.1. 1 INTERVAL 1 (T0 T < T1) Switch s1 and s2 are all off state, current cannot flow Through switch s1 and s2. The main inductor current iL1 Flows through the output diode D out. The resonant Capacitor voltage is equal to the output voltage. VL(t)=VsVo (7)
iL (t ) iL (to )
iDo(t)=iL(t) Fig 5 Block diagram for Soft Switching Boost Converter iLr(t)=0 Vcr(t)=Vo.
vo vs t L
(8) (9) (10) ` (11)
4.1.2 INTERVAL 2 (T1 T < T2) Switch s1 and s2 are turned on with zero current condition simultaneously: current starts to flow in the resonant inductor Lr. The current flowing into the load through the output diode D out gradually decreases, whereas the current flowing into the resonant inductor Lr increases. At the time period t2, the current flowing in inductor L1 and the current in resonant inductor Lr become equal. At this point, the current flowing to the load through output diode D out becomes zero.
Fig.6 Theoretical Waveforms
iLr(t1)=0VLr(t)=Vo
(12) (13)
ilr (t )
iL(t2)=iLr(t2) iDo(t2)=0.
Vo t Lr
(14) (15)
Fig 7
Circuit Diagram of Soft Switching Boost Converter
4.1.3 INTERVAL 3 (T2 T < T3) The current that flowed to the load through output diode Do no longer flows, since t2 and the resonant capacitor Cr, and the resonant inductor Lr start a resonance The current flowing to the resonant inductor is a combination of the main inductor current and the resonant capacitor current The amount of resonant current is expressed as iL(t)=Imin (16)
The Fig .5 and Fig .6 shows the proposed soft switching boost Converter and its respective waveforms. The proposed converter capable of minimizing the switching losses. A switch, two diodes, and the inductor and capacitor are added in the proposed circuit compared with the conventional boost converter. The two switches are controlled on and off simultaneously. Also, the switching loss is reduced by soft switching utilizing the resonance between inductor and capacitor.
iLr (t ) I min
vo sin r Zr
(17)
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4.1.5 INTERVAL 6 (T5 T < T6) Interval 6 begins when the resonant capacitor equals the output voltage, and the output diode is turned on under the zero voltage condition. During this interval, the main inductor current iL and the resonant inductor current iLr flow to the output through the output diode Do iDo(t)=iL(t)+iLr(t). (30) (31) (32)
During this resonant period, the resonant capacitor Cr is discharged from Vo to zero. This is expressed as (4.12). Resonant When the voltage of the resonant capacitor equals zero,the interval 3 is over vCr(t)=Vocosrt vCr(t2)=Vo vCr(t3)=0 (18) (19)
4.1.4 INTERVAL 4 (T3 T < T4) After the resonant period in interval 3, when the voltage of the resonant capacitor equals zero, interval 4 begins. In this interval, the freewheeling diodes of D1 and D2 are turned on, and the current of the resonant inductor is the maximum value. The resonant inductor current flows to the freewheeling diodes S1LrD2 and S2LrD1 along the freewheeling path iLr(t)=iL(t)+iD1(t)+iD2(t) iLr(t3)=iLr(t4)=ILr,max. (20) (21)
iLr(t5)=(Imax+ILr,max)cosr(t5t4)Imax vCr(t)=Vo.
At that time, two of the inductor currents are linearly decreased, and the energy of the resonant inductor is completely transferred to the load. Then, the interval 6 is over iLr(t6)=0. 5. SIMULATED RESULTS This paper simulated the adopted soft-switching boost converter and the PV module modeling of 2500 W using the PSIM software. Fig. 8 shows the simulated model circuit of PV cell .The output characteristic waveform of the PV module, MPPT controller using Improved P&O algorithm is shown in Fig 9 and fig 10 respectively. At 1.5S, this converter starts estimating the maximum power point.. At this time, the simulated PV module reaches the maximum power of 2403 W, and the corresponding output voltage and current of simulated PV module are 157.3 V and 15.172 A respectively. Fig. 11 shows the simulated circuit of soft switching boost converter with MPPT controller and PV array as input. PV array model and MPPT controller are used as a subsystem. The MPPT controller varies the duty cycle of the boost converter through PWM technique to obtain constant output irrespective of different incident solar radiation. The fig 17 shows waveforms for the soft switching boost converter. The switch current, switch voltages, resonant inductor current, Main Inductor current, and resonant capacitor voltage are shown in the order. The main switch and auxiliary switches are turned on in ZCS condition and turned off during ZVS condition. The next table shows the comparisons of boost converter, boost converter with PI controller with constant DC source and soft switching Boost converter with MPPT controller and without MPPT controller with PV source. It is inferred that Soft Switching boost control increases the efficiency of boost converter from 82.4% to 99%. It is also inferred that MPPT controller increase the efficiency from 50 % to 91.3%. (33)
During this time, the main inductor voltage equals the input voltage, and the current accumulating energy increases linearly vL(t)=Vs (22)
iL (t ) I min
vo t. L
(23)
4.1.6 INTERVAL 5 (T4 T < T5) In interval 5, all of switches are turned off under the zero voltage condition by the resonant capacitor. During this interval, the initial conditions of the resonant inductor current and resonant capacitor voltage are as follows: iLr(t4)=ILr,max vCr(t4)=0 (24) (25)
When all of the switches are turned off, the resonant capacitor Cr is charged to the output voltage by two of the inductor currents. Until the resonant capacitor has been charged to Vo, the output diode is in the OFF state. iL(t)=Imax iLr(t)=Imax(Imax+ILr,max)cosrt vCr(t)=Zr(Imax+ILr,max)sinrt vCr(t5)=Vo. (26) (27) (28) (29)
49
Fig 8 Simulated Circuit for PV Array Fig 12 Waveforms Of A) Switch Current B) Switch Voltages C) Resonant Inductor Current D)Main Inductor Current E)Resonant Voltage TABLE I Comparisons for Boost Converter
Fig 9 Simulated Output of PV Array at 298K ,1000 W/M2
Fig 10 Circuit for MPPT Controller with Improved P&O Algorithm
6. CONCLUSIONS In this thesis, we proposed a soft-switching boost converter, which involved an added SARC in the conventional boost converter. This soft-switching boost converter is easy to control because the two switches are controlled by the same PWM signal. All of the switching devices in this Converter achieved ZCS and ZVS by the resonant inductor and capacitor at turn/off. Therefore, the switching losses were reduced dramatically. This thesis has also analyzed the operational principles of the adopted converter and applied them to the improved P&O algorithm, which is a kind of MPPT method. Moreover, this converter was verified by the simulation and validated results. This soft-switching boost converter can be applied to a stand-alone and a grid-connected system using a PV power conditioning system
Fig 11 Circuit for Overall Soft Switching Boost Converter
50
[16]D. Sera, R. Teodorescu, and P. Rodriguez, PV panel model based on datasheet values, in Proc. IEEE Int. Symp. Ind. Electron. (ISIE), 2007,pp. 23922396. [17]Y.-C. Kuo, T.-J. Liang, and J.-F. Chen, Novel maximum-power-point tracking controller for photovoltaic energy conversion system, IEEE Trans. Ind. Electron., vol. 48, no. 3, pp. 594601, Jun. 2001.
7. REFERENCES [1] H. Bodur and A. Faruk Bakan, A new ZCT-ZVTPWM DCDC converter, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 676684,May 2004. [2] J.-H. Kim, D.-Y. Yung, S.-H. Park, C.-Y.Won, Y.-C. Jung, and S.-W. Lee,High efficiency soft-switching boost converter using a single switch,J. Power Electron., vol. 9, no. 6, pp. 929939, Nov. 2009. [3] J.-P. Lee, B.-D. Min, T.-J. Kim, D.-W. Yoo, and J.-Y. Yoo, Design and control of novel topology for photovoltaic dc/dc converter with high efficiency under wide load ranges, J. Power Electron., vol. 9, no. 2,pp. 300307, Mar. 2009. [4] J.-J. Lee, J.-M. Kwon, E.-H. Kim, and B.-H. Kwon, Dual series resonant active clamp converter, IEEE Trans. Ind. Electron., vol. 55, no. 2 ,pp. 699710, Feb. 2008. [5] X. Wu, J. Zhang, X. Ye, and Z. Qian, Analysis and derivations for a family ZVS converter based on a new active clamp ZVS cell, IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 773781, Feb. 2008. [6] S.-S. Lee and G.-W. Moon, Full ZVS range transient current buildup half bridge converter with different ZVS operations to load variation, IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 25572559, Jun. 2008. [7]H. S. Rauschenbusch, Solar Cell Array Design Handbook. NewYork:Van Nostrand Reinhold, 1980. [8] W. De Soto, S. A. Klein, and W. A. Beckman, Improvement and validation of a model for photovoltaic array performance, Solar Energy, vol. 80,no. 1, pp. 7888, Jan. 2006. [9] Q. Kou, S. A. Klein, and W. A. Beckman, A method for estimating the long-term performance of direct-coupled PV pumping systems, Solar Energy, vol. 64, no. 13, pp. 3340, Sep. 1998. [10] A. Driesse, S. Harrison, and P. Jain, Evaluating the effectiveness of maximum power point tracking methods in photovoltaic power systems using array performance models, in Proc. IEEE Power Electron. Spec.Conf. (PESC), 2007, pp. 145151. [11] R. A. Messenger and J.Ventre, Photovoltaic Systems Engineering., FL: CRC Press, 2004. [12] F. Nakanishi, T. Ikegami, K. Ebihara, S. Kuriyama, and Y. Shiota, Modeling and operation of a 10 kW photovoltaic power generator using equivalent electric circuit method, in Proc. Conf. Record 28th IEEE Photovoltaic Spec. Conf., Sep. 2000, pp. 17031706. [13] J. Crispim, M. Carreira, and R. Castro, Validation of photovoltaic electrical models against manufacturers data and experimental results, in Proc. Int. Conf. Power Eng., Energy Elect. Drives, POWERENG, 2007,pp. 556561. [14] K. H. Hussein, I. Muta, T. Hoshino, and M. Osakada, Maximum photovoltaic power tracking: An algorithm for rapidly changing atmospheric conditions, in Proc. IEE Proc.-Generation, Transmiss. Distrib., Jan.1995, vol. 142, pp. 5964. [15]G. Walker, Evaluating MPPT converter topologies using a matlab PV model, J. Elect. Electron. Eng., Australia, vol. 21, no. 1, pp. 4555, 2001.
Saravanakumar.B received the B.E degree in electrical and Electronics Engineering from Prathyusha Engineering College, Chennai Tamil Nadu, in 2008. Currently he is doing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, Sathyamangalam, and Tamil Nadu. His area of interest includes power converters, PV energy conversion and electric drives
P.Sivaraman.received the BE degree in electrical and electronics engineering from Bharathiyar University, Coimbatore ,Tamilnadu, in 2002 and the M.Tech. Degree from the School of Electrical and Electronics Engineering SASTRA University, Thanjur, Tamilnadu,in 2004. Now he is pursuing PhD in Anna University of Technology Coimbatore. From 2004 onwards he was working with the Bannari Amman Institute of Technology, Sathyamangalam,Erode,Tamilnadu, where his current research interest include power converter for photovoltaic application and distributed power generation for rural area applications.
51
DESIGN AND ANALYSIS OF ZERO VOLTAGE SWITCHING DC-DC CONVERTER WITH SYNCHRONOUS RECTIFIER
1
E.SATHISHKUMAR, 2B.SHANTHIBHUSHAN
Power Electronics and Drives, School of Electrical Sciences, Karunya University, Kovai E-MAIL ID:
2
esrwings@gmail.com shanthibhushanb@yahoo.co.in
Abstract Active resonant tank (ART) cells are proposed in this paper to achieve zero-voltage-switching (ZVS) and eliminate body diode conduction in dcdc converters with synchronous rectifiers (SRs). In low-output-voltage dcdc converters, SRs are widely utilized to reduce rectifier conduction loss and improve converter efficiency. However, during switches transition, SRs parasitic body diodes unavoidably carry load current, which decreases conversion efficiency because voltage drop across body diodes is much higher than that across SRs. Moreover, body diodes reverse recovery leads to increased switching losses and electromagnetic interference. With the proposed cells of an ART, the body diode conduction of the SR is eliminated during the switching transition from a SR to an active switch, and thus body diode reverse-recovery- related switching and ringing losses are saved. An ART cell consists of a resonant tank and an auxiliary switch. A resonant tank cell is charged in a resonant manner and energy is stored in the capacitor of the tank. Prior to a switching transition from a SR to an active switch, the energy stored in the tank capacitor is released and converted to inductor current, which forces the SR current changes direction to avoid conduction of the body diode and related reverse recovery when the SR turns off. Moreover, at the help of energy released from the ART, the active switchs junction capacitance is discharged, which allows the active switch turns on at ZVS. Since energy commutation occurs only during switching transition, conduction loss in the ART cell is limited. Moreover, the auxiliary switch turns off at ZVS and the SR operates at ZVS. The concept of ART cells is generally introduced and detailed analysis is presented based on a synchronous buck converter. Experimental results show the proposed ART cell improves conversion efficiency due to the reduced switching loss, body diodes conduction, and reverserecovery losses. Keywords Buck, converter, dcdc, resonant tank, reverse recovery, synchronous rectifier (SR), topology, zero voltage switching (ZVS).
1. INTRODUCTION With demanding powering requirements of fast transient response and high power density, converters switching frequencies keep increasing resulting in increased switching loss. Recently, soft-switching techniques draw a lot of attention in reducing switching loss and electromagnetic interference (EMI) noises. Among them, particularly, zero
voltage switching (ZVS) techniques are desirable for metal oxide semiconductor field effect transistor (MOSFET)-type switches. ZVS multi resonant converters (MRCs) technique utilizes all major parasitic of the power stages and all semiconductor devices in MRC operate with ZVS, which substantially reduces the switching losses and noise. Quasiresonant converters (QRCs) were introduced to overcome the disadvantages of conventional pulse width modulation (PWM) converters operating at high switching frequency by achieving ZVS for the active switch and zero current switching (ZCS) for the rectifier diode. However, the switches in both QRCs and MRCs have to withstand high voltage stress or high current stress which restricts the applications of those resonant converters. By reducing the filter inductance in the conventional PWM converters, ZVS quasi-square-wave (QSW) technique offers ZVS for both the active and passive switches without increasing the switches voltage stress. However QSW converters suffer high current stress in components, as a result, conduction losses are greatly increased, and active switches turn off at high currents. In a similar concept of QSW is presented with a cell in parallel with the active switch or rectifier diode. The cell consists of a small inductor in series with a large capacitor and the cells high inductor current ripple is utilized to achieve ZVS turn-on for the active switch. However, the current ripple in the cells inductor is more than twice the one in the filter inductor, and the associated conduction and turn-off loss increase is significant. To facilitate ZVS while preserving the advantages of the PWM technique, hybrid topologies incorporate PWM technique and resonant converters in order to minimize circulating energy and corresponding conduction loss and switching loss. Adding an auxiliary switch across the resonant converter in a ZVSQRC derives ZVS-PWM converter, which can be considered as hybrid circuits of ZVSQRCs and PWM converters wherein ZVS is achieved for the power switch and the converter operates at a constant switching frequency. However, the power switch suffers from a high voltage stress that is proportional to the load range. Compared with ZVSPWM converter, zero-voltage-transition PWM (ZVTPWM) converters are more desirable since soft switching is achieved without increasing switch voltage and
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The description of block diagram as follows, 2.1. BUCK CONVERTER A buck converter is a step-down DC to DC converter. Its design is similar to the step-up boost converter, and like the boost converter it is a switched-mode power supply that uses two switches (a transistor and a diode), an inductor and a capacitor. The simplest way to reduce a DC voltage is to use a voltage divider circuit, but voltage dividers waste energy, since they operate by bleeding off excess power as heat; also, output voltage isn't regulated (varies with input voltage). Buck converters, on the other hand, can be remarkably efficient (easily up to 95% for integrated circuits) and self-regulating, making them useful for tasks such as converting the 12-24V typical battery voltage in a laptop down to the few volts needed by the processor. 2.2. TRANSFORMER A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductorsthe transformer's coils. A varying current in the first or primary winding creates a varying magnetic flux in the transformer's core, and thus a varying magnetic field through the secondary winding. This varying magnetic field induces a varying electromotive force (EMF) or "voltage" in the secondary winding. This effect is called induction. Step down transformer as evidenced by the high turn count of the primary winding and the low turn count of the secondary 2.3. RECTIFIER A rectifier is an electrical device that converts alternating current (AC) to direct current (DC), a process known as rectification. Rectifiers have many uses including as components of power supplies and as detectors of radio signals. Rectifiers may be made of solid state diodes, vacuum tube diodes, mercury arc valves, and other components.
current stress.By adding an auxiliary shunt network to discharge switch junction capacitance and shift the rectifier diode current, ZVS is achieved for switch and reverse 2 recovery of rectifier diode is attenuated. This paper presents a ZVS hybrid topology that consists of an active resonant tank (ART) and a dc-dc converter with a synchronous rectifier (SR). The ART cell is inserted into a conventional dcdc converter to achieve ZVS for both the power switch and the SRs. The proposed topology is essentially unique compared to other existed hybrid ZVS dc -dc topologies, because the added ART cell is specifically operating with a SR in dcdc converters. The proposed ART cell allows converters to utilize SRs for higher voltage since reverse recovery of body diodes is completely eliminated. In recent years, synchronous rectification technique has been widely used in low-voltage applications, while moving towards applications with higher voltage level, because high voltage MOSFET on-resistance is increasingly reduced such that voltage drop across them is competitive with that of fast recovery diodes. However, the reverse recovery problem of MOSFET body diodes is a barrier to SRs applications with higher voltage. For example, SRs with 200 V and higher voltage ratings are hardly found in applications, because SR body diodes reverse recovery is more severe with increased voltage ratings which significantly increase switches and body diodes switching loss. Moreover, the reverse-recovery-related EMI noise may lead to malfunction of converters. In techniques are presented for reducing rectifier reverse recovery related losses in high-voltage boost converters, which can be applied to applications with SRs replacing diodes. But these techniques only provide a passive solution since reverse recovery of diodes is attenuated instead of eliminated. 2. BLOCK DIAGRAM
3 3. CIRCUIT DIAGRAM T The modes of operation are described as follows, Mode 1 : The resonant capacitor was pre-charged and the filter inductor freewheels through the SR. This mode starts with turn-on of the switch, where the inductor current charges at resonant manner, the associated voltage and current. The mode ends with the capacitor voltage discharged to zero, and the resonant current reaching maximum value
Fig1.Block diagram representation.
53
Fig2.Buck converter with ART cell
Mode 2 : With the resonant capacitor voltage reach zero, the diode in the cell carries current, and the inductor is trapped in the short-circuit loop. Assuming the inductor current value ,the SR current is reversed. As a matter of fact, inductor freewheels through the ART cell during this mode. Mode 3 : SR turns off, the inductor current previously flowing through the SR charges the junction capacitance and discharge until the switch s body diode conducts in Mode 4. Mode 4 : When the junction capacitance voltage across the switch is discharged to zero ,body diode conducts to carry current. During this mode through the body diode of the switch S1 , the resonant inductor current resets towards a steady-state value. Mode 5 : The switch turns on at ZVS. The resonant inductor current continues to decrease with the slew rate. When the resonant inductor current decreases to output filter inductor current ,the current in the switch reverses the direction and becomes positive. After that, the current keep increasing and the resonant inductor current decreases with the same slew rate. Mode 6 : When the switch current increases to the filter inductor current , the resonant inductor current reverses the direction and becomes negative, then the diode is blocked, and the resonant capacitor is involved in a resonance. The ART tank is charged in a resonant manner. Mode 7 : The ART cells switch S turns off at ZVS and the carried resonant current shifts to its body diode and the resonance continues. The sinusoidal resonant current rises to the peak and then decreases towards zero. The resonance ceases with the capacitor voltage reaches the peak and the inductor current reaches zero.
Fig3.Waveforms for synchronous buck converter with ART cell.
Mode 8 : The voltage across the resonant capacitor reaches 2Vin , and the resonant inductor current becomes zero. After that, the circuit goes into damped ringing caused by the involvement of the switch junction capacitor. When body diode of switch S was conducting in mode 7, the junction capacitor of switch was not charged, at the beginning of mode 8, the body diode stops conducting and the junction capacitor of switch is charged towards a steady-state voltage level . This forms a resonant circuit composed of the input voltage , resonant inductor , resonant capacitor and the junction capacitor of the switch Considering the capacitance value of the capacitor is much greater than that of the junction capacitor ,the resonant inductor and the junction capacitor determine the resonant manner. Mode 9 : The ringing is damped by the equivalent resistance along the path of the resonant loop. The ART cell is naturally inactive and separated from the converter .In this mode, the output filter is charged and the input power is delivered to the output. Mode 10 : The switch s1 turns off, the filter inductor charges the junction capacitance and discharges Mode 11 : When the junction capacitance voltage reaches zero, the SR body diode conducts carrying the output inductor current, which provide ZVS turn-on condition for the SR. Mode 12 : During the body-diode conduction interval, the SR turns on at ZVS, and the converter enters into inductor freewheeling mode. With the turn-on of the switch S,the converter goes back to Mode 1.
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4 4.2. BUCK CONVERTER OUTPUT CURRENT
4. SIMULATION
4. 4.3. GATE TO SOURCE VOLTAGE AND DRAIN TO SOURCE VOLTAGE OF SWITCH S1
Fig4.Simulation diagram
4.1. BUCK CONVERTER OUTPUT VOLTAGE
4. 4.4. GATE TO SOURCE VOLTAGE AND DRAIN TO SOURCE VOLTAGE OF SWITCH S
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[7] G. Chen, D. Xu, B. Feng, and Y.Wang, A family of compound active clamping DC-DC converters, in Proc. IEEE Appl. Power Electron. Conf., 2002, pp. 850856. G. Hua and F. C. Lee, A new class of ZVS-PWM converters,Proc. High Freq. Power Conv. Conf., 1991, pp. 244 251. G. Hua, C. S. Liu, Y. Jiang, and F. C. Lee, Novel zero-voltagetransition PWM converters, IEEE Trans. Power Electron., vol. 9, no. 2, pp. 213219, Mar. 1994. Zhang, X. Xie, X. Wu, G. Wu, and Z. Qian, A novel zerocurrent transition full bridge DC/DC converter, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 354360, Mar. 2006. J. Abu-Mahout and I. Batarseh, Unified steady-state analysis of soft switching DC-DC converters, IEEE Trans. Power Electron., vol. 17, no. 5, pp. 684691, Sep. 2002. P.-L. Wong, B. Yang, P. Xu, and F. C. Lee, Quasi-square-wave rectification for front-end DC/DC converters, in Proc. IEEE 31st Annu. Power Electron. Spec. Conf. (PESC00), Jun. 2000, vol. 2, pp. 10531057. M. M. Jovanovic, R. Farrington, and F. C. Lee, Comparison of half bridge off-line, ZCS-QRC and ZVS-MRC, IEEE Trans. Aerosp. Electron. Syst., vol. 26, no. 2, pp. 326336, Mar. 1990. C. M. da Cunha Duarte and I. Barbi, A new family of ZVS PWM active clamping dc to dc boost converters: Analysis, design, and experimentation, IEEE Trans. Power Electron., vol. 12, no. 5, pp. 684691, Sep. 1997. X. Wu, J. Zhang, X. Ye, and Z. Qian, Analysis and design for a new ZVS DC-DC converter with active clamping, IEEE Trans. Power electron., vol. 21, no. 6, pp. 15721579, Nov. 2006.
5. CONCLUSION Concept of the ART cell applying for the non isolated topologies is introduced.High frequency synchronous buck converter is introduces as an example wherein an ART cell is connected in parallel with the SR to achieve the zero voltage for the active switch and eliminating the reverse recovery of the body diode. To achieve the zero voltage switching in DCDC converter and eliminate the body diode conduction losses.Improve the converter efficiency .High efficiency at high switching frequency is achieved due to the reduced switching losses and reduced reverse recovery loss compared to the hard switching synchronous ordinary buck converter.
[8]
[9]
[10]
[11]
[12]
[13]
[13]
Fig.5 Efficiency comparision
[14]
Experimental results are very close to theoretical results. The efficiency of ART converter is 2% more than ordinary buck converter REFERENCES
[1] T. Zheng, D. Y. Chen, and F. C. Lee, Variation of quasi resonant DC/DC converter topologies, in Proc. IEEE Power 1] K. H. Liu and F. C. Lee, Zero-voltage switching technique in dc-dc converters, in Proc. IEEE Power Electron. Spec. Conf., 1986, pp.5870. Electron. Spec. Conf., 1986, pp. 381392. C. P. Henze, H. C. Martin, and D. W. Parsley, Zero-voltageswitching in high frequency power converters using pulse width modulation, in Proc. IEEE Appl. Power Electron. Conf., 1988, \ pp. 3340.
[2]
[3]
V. Vorperian, Quasi-square wave converter: Topologies and analysis, IEEE Trans. Power Electron., vol. PE-3, no. 2, pp. 183191, Apr. 1988. K. Harada and H. Sakamoto, Non-resonant converter for megahertz switching, in Proc. IEEE Power Electron. Spec. Conf., 1989, pp. 889894. T. Mizoguchi, T. Ohgai, and T. Ninomiya, A family of singleswitch ZVS-CV DC-to-DC converters, in Proc. IEEE Power Electron. Spec. Conf., 1994, pp. 13921398. M. M. Jovanovic, A technique for reducing rectifier reverserecovery related losses in high-voltage high-power boost converter, in Proc. IEEE Appl. Power Electron. Conf., 1997, pp. 10001007.
[4]
[5]
[6]
56
A Nona-Switch Inverter Employing Space Vector Modulation for Independent Control of Two Motors
Arthi.P arthi.parthipan@gmail.com Leena.N lee_eee@yahoo.co.in
Abstract- The permanent-magnet synchronous machine drive has emerged as a top competitor for a full range of motion control applications. Several applications demand independent control of two PM motors. This was early done either by providing separate inverters to control each motor or by the connecting the two motors in parallel and driving them using a single inverter. Both the above mentioned methods suffer from several disadvantages in terms of cost, complexity and independent control. This paper proposes an inverter with reduced switch count for independent control of two motors. The inverter has nine switches and a specific SVM switching pattern is used to reduce the cost of power devices, thermal heat effect, and to reduce the number of semiconductor switching,. This feature will be advantageous for high-power inverter applications where cost and efficiency are key decision factors. Index Terms-Nine-switch inverter, pulse width modulation (PWM), voltage-source inverter (VSI).
failure. This has already been implemented in direct and indirect matrix converters. Instead of passive components active semiconductor switches and their drive circuitries can also be reduced as quoted in converters where B4 and five leg inverter were proposed. A further saving in switches can be achieved compared to the above two topologies by adopting a nine switch inverter with two sets of three phase interfacing terminals. The validity of the proposed inverter is verified by simulation. II. NINE SWITCH CONVERTER TOPOLOGY A. Basic concept The respective circuit layouts of the back-to-back converter and the nine switch inverter are shown in Fig.1 and Fig.2 with the switches properly labeled to show how the latter is derived from the former. In Fig.1, it may be noted that the back to back converter has 12 switches. Merging of the switches in the second and third rows of Fig.1 results in the nine-switch converter of Fig.2. It can be thus thought of as a combination of two three phase inverters with three common switches.
I. INTRODUCTION Inverters are used to create single or polyphase AC voltages from a DC supply. A very large number of inverters are used for adjustable speed motor drives. The permanent-magnet synchronous machine (PMSM) drive has emerged as a top competitor for a full range of motion control applications like widely and other highpower applications like vehicular propulsion and industrial drives due to high efficiency, low torque ripple, superior dynamic performance. There are two methods to control dual induction motors. The first method is to provide separate inverters for each of the motors. However this needs large and expensive apparatus thus increasing the cost and complexity of the system. The second method is to connect the two motors in parallel and driven by the same inverter. This method does not allow independent control due to the difference in the rotor angles of the motors. These deficiencies can be overcome using a dual output inverter which can also be used as an ac/ac converter. Another key factor while designing power converters is to reduce the number of active and passive components thus lowering the overall cost. In relation to voltage- source inverter, reduction in passive components mainly aimed at minimizing or removing the electrolytic capacitor which is costly and also causes premature
57
When one of the outputs has an active or short zero (0 0 0) vector, the other output has long zero (1 1 1) vector.
Fig. 3. Carrier-based PWM method for nine-switch inverter.
In Fig.2, the upper part is named Inv1, and the lower part is named Inv2. Inv1 consists of switches designated SA, SB, SC, SAU, SBV and SCW. Inv2 consists of switches designated SAU, SBV, SCW, SU, SV and SW. Thus the switches SAU, SBV and SCW are shared by Inv1 and Inv2. B. Carrier-Based PWM Method The carrier-based PWM control method for nineswitch inverter is shown in Fig. 3. There are two reference signals (upper and lower) for each phase. The upper and lower reference signals are related to upper and lower outputs respectively. The gate signal for upper switch of a leg is generated by comparing the carrier signal and upper reference signal of the related phase (VrefUJ). Similarly, the gate signal for lower switch is generated from the carrier signal and lower reference signal of the related phase (VrefLJ). The gate signal for mid switch is generated by the logical XOR of the gate signals for upper and lower switches. With this method, always two switches are ON in each leg. Fig. 4 shows carrier-based PWM method switching vectors. There are six vectors in each switching cycle for both outputs: two non zero vectors, one zero vector (0 0 0), two non zero vectors and one zero vector (1 1 1) {two activeshort zero (0 0 0)two activelong zero (1 1 1)}. In an active vector, output load is connected to the dc input source, while in a zero vector, the output load is short-circuited.
Fig. 4. Carrier-based PWM method switching vector.
III. SVM FOR NINE-SWITCH INVERTER In regard to Fig. 3, each leg can be in three different semiconductors ON-OFF position. These position can be called {1}, {0}, and {1}, as is illustrated in Table I. In Table I, J refers to leg A, B, or C and U, M, L refers to upper, mid, and lower semiconductor, respectively. The combination of switching vector of both outputs in Fig. 4creates a specific sequence as shown in Fig. 5. These sequences used to design SVM method. There are 12 vectors in each switching cycle: {two upper active (VAU)zero (VZ )two upper active (VAU )zero (VZ )two lower active (VAL)zero(VZ )two lower active (VAL)zero (VZ )}. The switching vectors are listed in Table II. The vectors V1V6 are upper active vectors. In these vectors, the upper output is in active
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state; and the lower output is in zero state. There is an inverse logic in lower active vectors (V7V12). In zero vectors (V13V15), both outputs are in zero state. Table II does not include all possible variations of switching states {1}, {0}, and {1}. Since a vector including {1} and {0} connects both loads to the dc source at the same time, the loads lose their independence and they cannot have independent frequencies. This is the reason for avoiding a vector that includes combinations of {1} and {0}.In none of the switching vectors as listed in Table II, both outputs are not in an active state at the same time. However, in vectors including both {1} and {0} such as {1, 1, 0}, both outputs are in active state. These vectors are ignored because there are not all combinations of active vectors for both outputs. For example, if upper output be in active vector (1 1 0), lower output can be in vectors (0 0 0), (1 0 0), (0 1 0), or (1 1 0) as shown in Fig. 6. However, vectors (0 1 1), (0 0 1), and (1 0 1) are not available for lower output. Therefore, outputs cannot be controlled independently.
To determine the proper active vectors, two space vector diagrams are proposed as shown in Fig. 7. The diagrams (a) and (b) are used to determine the upper and lower active vectors, respectively. The SVM active vectors are determined with regard to location of upper reference signal ( VrefU ) in the diagram (a) and lower reference signal ( VrefL ) in the diagram (b). The reference signals for the upper and lower outputs are defined as
where fU , fL are the frequencies, and U , L are the phases. All zero vectors V13, V14, and V15 can be used for zero states. The type of zero vectors can be selected
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vectors (V2, V4, V6, V7, V9, and V11) in a switching sequence. In an even active vector, two legs are in state {1}, while in an odd active vector only one leg is in state {1}. If even active vectors are placed next to V13, number of switching will be reduced even more (see Fig. 8).There are other possible switch generation methods too, e.g., a switching method, to reduce THD. To minimize THD, active vectors for each output should be centrally placed within the switching period [11]. Fig. 9 shows a switching vector sequence that shifts active vector into center of switching period, hence reducing THD. In this sequence, zero vectors are inserted between active vectors. In Fig. 9, V14 is inserted between upper active vectors and V15 is inserted between lower active vectors.
based on control goals and optimizations such as minimum number of semiconductor switching. The switching time intervals of vectors are calculated as
where T1, T2 are the time interval of upper active vectors, T3, T4 are time of lower active vectors, To is time of zero vectors and T is switching period.mU andmL are upper and lower modulation indices, respectively, and defined by
The sum of active vector time intervals must be less or equals to T. Thus, the following constrain must be satisfied
Fig. 8. SVM with reduced number of semiconductor switching
Equation (12) clearly indicates that in the proposed SVM scheme, sum of modulation indices increases about 15%a very important feature to provide higher torque for a given input dc-voltage. In the case of washing machines, the above capability translates to higher machine capacity (in terms of cloth load) at high spin speed (e.g., 1800 r/min)an important product feature in marketplace. A switching vector sequence for the proposed SVM is shown in Fig. 8. This switching sequence is developed to reduce the number of semiconductor switching. The zero vectors are placed just between two upper and lower active vectors. In upper active vectors, legs are in state {1} or {0} and in lower active vectors, legs are in state {1} or{1}. If V13 zero vector is placed between the active vectors, minimum number of switching is required. While if V14 or V15 zero vectors are used, number of switching nis increased. There are two odd active vectors (V1, V3, V5, V8, V10, and V12) and two even active
Fig. 9. SVM with reduced THD
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REFERENCES
[1] T. Kominami and Y. Fujimoto, A novel nine-switch inverter for independentcontrol of two three-phase loads, in Proc. IEEE Ind. Appl. Soc.Annu. Conf. (IAS), 2007, pp. 23462350. [2] C. Liu, B. Wu, N. Zargari, and D. Xu, A novel three-phase threeleg AC/AC converter using nine IGBTs, IEEE Trans. Power Electron., vol. 24, no. 5, pp. 11511160, May 2009. [3] K. Oka, Y. Nozawa, R. Omata, K. Suzuki, A. Furuya, and K. Matsuse,Characteristic comparison between five-leg inverter and nineswitch inverter,in Proc. Power Convers. Conf., Nagoya, 2007, pp. 279283. [4] F. Z. Peng, Z-source inverter, IEEE Trans. Ind. Appl., vol. 39, no. 2,pp. 504510, Mar./Apr. 2003. [5] Y. Huang, M. Shen, and F. Z. Peng, A Z-source inverter for residential photovoltaic systems, IEEE Trans. Power Electron., vol. 21, no. 6,pp. 17761782, Nov. 2006. [6] S. M. Dehghan, M. Mohamadian, and A. Yazdian, A new variable speedwind energy conversion system using permanent magnet synchronousgenerator and Z-source inverter, IEEE Trans. Energy Convers., vol. 24,no. 2, Sep. 2009. [7] P. C. Loh, S. W. Lim, F. Gao, and F. Blaabjerg, Three-level Zsourceinverters using a single LC impedance network, IEEE Trans. PowerElectron., vol. 22, no. 2, pp. 706711, Mar. 2007. [8] P. C. Loh, F. Gao, and F. Blaabjerg, Topological and modulation designof three-level Z-source inverters, IEEE Trans. Power Electron., vol. 23,no. 5, pp. 22682277, Sep. 2008. [9] P. C. Loh, D. M. Vilathgamuwa, Y. S. Lai, and G. T. Chua, Pulsewith modulation of Z-source inverters, IEEE Trans. Power Electron., vol. 20,no. 6, pp. 13461355, Nov. 2005. [10] Tsutomu Kominami and Yasutaka Fujimoto, Proposal of a NineSwitch Inverter That Can Independently Control Two PM Motors, IEEJ Industry Applications Society Conference, pp. 187-190, 2006, (in Japanese) [11] Kazuo Oka and Kouki Matsuse, A Nine-Switch Inverter for Driving Two AC Motors Independently, IEEJ Trans. on Electrical and Electronic Engineering, 2007. [12] F. A. B. Batista and I. Barbi, Space vector modulation applied to threephase three-switch two-level unidirectional PWMrectifier, IEEE Trans. Power Electron., vol. 22, no. 6, pp. 22452252, Nov. 2007. [13] C. Liu, B. Wu, N. R. Zargari, and D. Xu, A novel nine-switch PWM rectifier-inverter topology for three-phase UPS applications, in Proc. IEEE-EPE2007, pp. 110.
IV. .SIMULATIONS RESULTS The proposed SVMs are simulated for nine-switch inverter. Simulation parameters are listed in Table VII. The nine-switch inverter with input dc source of 150 V and resistive loads with LC filters connected to the output is simulated and implemented with reduced number of switching It was seen that both outputs have expected frequencies. The load currents were found to have nearly sinusoidal waveforms.
TABLE I
SIMULATION PARAMETERS
Parameter Switching frequency fu fl Rload Lf Cf mU mL

V.
Value
3kH 25Hz 50Hz 5.6ohm 1mH 20uF 0.35 0.55 CONCLUSION
In this paper, the SVM of nine-switch inverter was proposed. Switching sequence of the proposed SVM is composed of the upper active vectors, the lower active vectors and the zero vectors. The upper and lower active vectors are determined via two space vector diagram. The total harmonic distortion was found to be less for space vector modulation compared to carrier PWM technique. Hence, the nine-switch inverter has better harmonic performance. The proposed SVM increases sum of modulation indices up to 15%, an important feature in providing higher torque for a given input dc-voltage.
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Design and Implementation of Front-End Converter for Switched Reluctance Motor Drive
A.Pradeep, J.Karpagam, and E.Kannapiran,
circuits [3] to reduce switching loss and stress; (iv) commutation instant tuning to improve torque generating capability [8,11];(v) reduction of mechanical vibration and acoustic noise [12-14]; (vi) current profiling control [13]; (vii) speed control [4,9]; (viii) position servo driving control ; (ix) front-end converters [1,2] and switch-mode rectifiers , which are placed between the power source and the SRM converter to boost the DC-link voltage and charge the battery reversely with good line power quality. II. FRONT-END CONVERTER WITH DC INPUT The main purpose of a DC-DC converter is to supply a regulated DC output voltage to a variable load resistance from an unstable DC input voltage. DC-DC converters are commonly used in applications requiring regulated DC power, such as computers, medical instrumentation and communication devices. DC-DC converters are also used to provide a stable variable DC voltage for DC motor speed control applications. There are three types of DC-DC converters in use today, linear converters, switched capacitor converters (also known as charge pumps), and switched converters. Linear converters can only generate lower output voltage from the higher input voltage. Their conversion efficiency is never greater than Vout / Vin. In practice most linear converters operate with typical conversion efficiencies of only 30%. Basic switched DC-DC converter is shown in Fig.1
Abstract This paper presents the method to improve the performance of switched reluctance motor by operating with front-end converter and high demagnetization voltage. The front-end converter operated as a DC/DC boost converter. The boost converter is wellregulated and dynamically boosted voltage with dc link. The boost converter needs two bidirectional switches of motoring and regenerative operation for switched reluctance motor. The paper analysis the boosted output voltage, current with particular emphasis on the harmonic content, input voltage utilization and variable speed performance of the motor. Sinusoidal wave modulation signals in PWM generation have been used to demonstrate the effect of the modulating signal on the input voltage utilization and output harmonic content. Torque output of switched reluctance machines can be increased with high demagnetization voltage, especially for high speed. Performance of the switched reluctance motor drive in terms of increased torque and power output can be improved. Simulation results for a boost converter and switched reluctance motor power converter are presented. The results are obtained through PSIM simulation model. The voltage, THD is measured and speed is measured through open loop system. Keywords Switched Reluctance Motor, voltage boosting, front-end converter, high demagnetization voltage.
I. INTRODUCTION Switched reluctance motor (SRM) [6] has many advantages, such as rigid structure, wide speed range, suitable for high-speed operation, high acceleration capability, and high power density. Furthermore, the SRM converter circuit is simple [6,7,13] and free from arm feedthrough short. However, the SRM still has many disadvantages, such as nonlinear torque dynamics, high torque ripple, and high mechanical vibration and acoustic noise, etc. Consequently, the torque generating capability is reduced. Till now, more researches have been conducted to improve the performance of a SRM, such as: (i) converter circuits and their switching controls [1-5]; (ii) DC-link voltage boosting circuits [6,10], they can effectively increase winding current rising rate at high speed; (iii) soft switching
A.Pradeep, PG scholar, Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: cruisepradeep@gmail.com J.Karpagam, Assistant Professor, EEE Department Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: sujisumi@rediffmail.com E.Kannapiran, Senior Lecturer, EEE Department Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: kannakalam@yahoo.co.in
Fig.1. Basic Switched DC-DC Converter
A. DC/DC Boost Converter A boost converter topology is obtained by rearranging the components of a buck converter. During the time the switch is closed energy is transferred to the inductor while the diode is preventing the capacitor to discharge through the switch. When the switch opens current through the inductor continues to flow in the same direction as during the previous cycle. This forward biases the diode and both the input voltage source and the inductor are transferring energy to the load. Hence, a voltage boost
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occurs across the load, which causes the output voltage to be higher than the input voltage. The capacitor must be large enough to keep the output voltage approximately constant.
Fig.3. b) Regenerative Braking Operation
Fig.2. Two Quadrant Boost Converter
The layout of the bidirectional dc-dc converter is accomplished by connecting in antiparallel a dc-dc step-up stage and a dc-dc step-down stage. For motoring operations of the motor drive the converter step-up stage is used to step up the battery voltage and control the inverter input voltage in order to minimize the ripple of the motor current waveform. B. Modes of Operation Thereby, the M1 and M2 are never operated at the same time, being the switch M2 always off during motoring operation, whereas the switch M1 is kept off continuously whenever the regenerative braking operation is commanded. For the transition from M1 switching operation to M2 switching operation a delay blanking time between the gating signals of the two switches is used, in order to avoid a "shoot through" or cross-conduction current through both the converter output capacitor and the two switches. For motoring operations the switch M1 is operated at constant switching frequency and variable duty-cycle, in order to step up the battery voltage at a voltage level which is slightly greater than the peak value of the motor phase-tophase EMF. Fig.3.a) shows the circuit states which occur along one time period of the converter switching frequency. When the switch M1 is on, the battery supplies energy to the inductor L. When the switch M1 is off, the output capacitor C receives energy from the inductor as well as from the battery. Thereby, the voltage Vdc at the output capacitor terminals can be regulated accordingly with the motor speed by adjusting the duty-cycle of the switch M1. Whenever either the reference value for the motoring current is set to zero, the switch M1 is turned off and kept in this state till the braking command is removed and a reference value greater than zero is commanded for the motoring current.
After a fixed blanking time interval the switch M2 is turned on to allow the reversal of the power flow. Thereafter, the switch M2 is operated at constant switching frequency and variable duty-cycle in order to keep at the desired value the braking current flowing in the battery. Fig.3.b) shows the converter modes of conduction related to the regenerative braking operation. When the switch M2 is on, the battery receives energy from the capacitor C as well as from the machine, which operates as a generator. By turning off the switch M2 the battery is isolated from such an energy supply, and thereby the control of the average value of the braking current flowing in the battery can be accomplished by regulating the duty cycle of the switch M2. Such a control of the braking current reduces stressing of the battery due to the regenerative braking operation. III. SWITCHED RELUCTANCE MOTOR DRIVE A schematic representation of the lamination pattern of two phase, three phase and four phase switched reluctance motors is shown in Figure 3.1. In each of the motors shown in Figure 3.1 a coil is wound around each stator pole and is connected, usually in series with the coil on the diametrically opposite stator pole to form a phase winding. The reluctance of the flux path between the two diametrically opposite stator poles varies as a pair of rotor poles rotates into and out of alignment. Since inductance is inversely proportional to reluctance, the inductance of a phase winding is a maximum when the rotor is in the aligned position and a minimum when the rotor is in the non- aligned position. A pulse of positive torque is produced if current flows in a phase winding as the inductance of that phase winding is increasing. A negative torque contribution is avoided if the current is reduced to zero before the inductance starts to decrease again. The rotor speed can be varied by changing the frequency of the phase current pulses while retaining synchronism with the rotor position.
Fig.3. a) Motoring Operation a) 2 Phase b) 3 Phase c) 4 Phase
Fig .4. Schematic of Switched Reluctance Laminations all with Two Poles per Phase
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voltage across the phase winding during this time is equal to the sum of the on-state voltages of the two semiconductor devices. This voltage is very small compared to the supply voltage and so the current in the phase winding decays very slowly.
Fig.5. Single Phase Equivalent Circuit of SRM
An elementary equivalent circuit for the SRM can be derived neglecting the mutual inductance between the phases as follows. The applied voltage to a phase is equal to the sum of the resistive voltage drop and the rate of the flux linkages and is given as:
Fig.6. Power Converter for Four Phase Motor with Asymmetric Half Bridge
where Rs is the resistance per phase, and the flux linkage per phase given by:
where L is the inductance dependent on the rotor position and phase current. Then, the phase voltage is:
The final mode of operation is a negative voltage loop. Both the switching devices are turned off. The current is forced to flow through both the freewheel diodes. The current in the phase winding decreases rapidly as energy is returned from the motor to the supply. The asymmetric half-bridge thus offers three very flexible modes for current control. The zero voltage loop is very important in minimising the current ripple at any given switching frequency. B. SRM Power Converter Operation In SRM converter, two switches and two diodes are used for per phase windings of the SRM as shown in Fig.7.
In this equation, the three terms on the right-hand side represent the resistive voltage drop, inductive voltage drop and induced emf, respectively. The induced emf, e, is expressed as:
A. Power Converter Unlike induction motors or d.c motors the reluctance motor cannot run directly from an a.c or d.c supply. A certain amount of control and power electronics must be present. The power converter is the electronic commutator, controlling the phase currents to produce continuous motion. The purpose of the power converter circuit is to provide some means of increasing and decreasing the supply of current to the phase winding. Many different power converter circuits have been proposed for the switched reluctance motor. By far the most common power converter for the switched drive is the asymmetric halfbridge, shown in Fig.6. a four phase motor. Each asymmetric half-bridge has three main modes of operation. The first, a positive voltage loop, occurs when both switching devices associated with a phase winding are turned on. The supply voltage is connected across the phase winding and the current in the phase winding increases rapidly, supplying energy to the motor. The second mode of operation is a zero voltage loop. This occurs if either of the two switching devices is turned off while current is flowing in a phase winding. In this case the current continues to flow through one switching device and one diode. The
Fig.7. Single Phase Converter Operation
When both the switches M1 and M2 are ON, then the winding is in energizing mode. When both the switches M1 and M2 are OFF, then the winding is in de-energized mode. When any one of the switches is ON and another switch is OFF, then the winding is in current regulation mode.
Fig.8. Modes of Operation for the Classical Converter (a) Energization (b) Zero Loop (c) De-Energization
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The Fig.11 shows PSIM simulated model of power converter for SRM drive. The input dc voltage for power converter is boosted by using DC/DC boost converter. The ac voltage source is connected to power converter for initially charge the stator coil in switched reluctance motor.
IV. CONVERTER FOR CONTROLLED DEMAGNETIZATION VOLTAGE The main reason for using a higher demagnetization voltage is to reduce the phase current to zero in as short duration as possible after the aligned position. This leads to higher positive torque, since the current turn-off can be initiated closer to the aligned position, and lower negative torque, since the current decays faster in the negative torque zone(after the aligned position). Thus at a particular speed, the maximum average torque can be increased. Using similar reasoning for the same value of desired torque, the rms motor current will be lower with higher demagnetization voltage. The need for high demagnetization voltage is only at high speeds, hence only the single pulse mode of operation needs to be considered. For a given speed, input dc voltage, Vdc and demagnetization voltage, Vdm the average torque depends on the ON and OFF angles for each phase. The maximum torque obtainable, based on the values of on and off, then depends on the maximum current allowable for the power converter. Thus, for specified peak converter current, Imax, on and off can be derived for calculating maximum possible torque. For each value of on considered, off is chosen such that the maximum possible average torque is obtained.
Fig.11. PSIM Simulation Model of Power Converter Circuit for SRM
The Fig.12 shows PSIM simulated model with high demagnetization voltage. The demagnetization inductor (Ldm), capacitor (Cdm), diode (Ddm) and switch (Sdm) acts as a buck-boost converter end of the power converter. The demagnetization voltage is added by using demagnetization capacitor that is fed back to the source for useful utilization in SRM drive.
Fig.9. SRM Converter for High Demagnetization Voltage Fig.12. PSIM Simulation Model for power Converter with High Demagnetization Voltage
V. SIMULATION MODEL The Fig.10 shows MATLAB/SIMULINK model for switched reluctance motor drive. The SRM drive model is simulated with DC/DC boost converter and high demagnetization voltage in open loop system. The sinusoidal PWM is applied for the gate to IGBT. The front end converter is simulated in PSIM and it is coupled with SRM drive by using Sim coupler which is modeled in MATLAB.
VI. SIMULATION RESULTS & DISCUSSION The Switched Reluctance Motor is simulated with DC/DC boost converter and high demagnetization voltage using PSIM software.
Fig.13. Sinusoidal Pulse Width Modulation for Boost Converter
The Fig.13 shows input pulses for DC/DC boost converter. The sinusoidal PWM technique is used for generating pulse with a switching frequency of 12.5 kHz.
Fig.10. Overall MATLAB Simulation Model for SRM Drive
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Fig.14. Output Voltage for Boost Converter without Filter
Fig.17. Phase B Voltage for Converter with High Demagnetization Voltage
The Fig.14 shows output voltage for DC/DC boost converter in open loop system. The input voltage is 48 V and the boosted voltage is around 64 V. It shows more ripples in output. The duty ratio is 0.25 for front end converter.
The Fig.17 shows single phase output voltage for SRM drive with high demagnetization voltage. The increased high demagnetization voltage fed back to the source for useful utilization in SRM drive and increases efficiency.
Fig.18. Output Current for SRM Fig.15. Output Voltage for Boost Converter with Filter
The Fig.15 shows output voltage for DC/DC boost converter with filter circuit. The output voltage is increased due to LC filter circuit and also reduced ripples in output. The output voltage is constant at a value of 70 V.
The Fig.18 shows output current for SRM drive. The output current initially increased and reaches to steady state for all three phase current at a value of 5.5 Amps.
Fig.19. Output Speed for SRM
Fig.16. Output Phase Voltage for Power Converter
The Fig.19 shows output speed for SRM drive. Thus at a particular speed the maximum average torque is increased by operating with high demagnetization voltage. VII. CONCLUSION The performance of Switched Reluctance Motor is improved with front-end converter and high
The Fig.16 shows output phase voltages for four phase SRM drive. Each phase voltage is measured across the phase coil. The phase voltage is increased with the boosted voltage from DC/DC boost converter and sinusoidal PWM for the gate to IGBT. The average output voltage per phase is 102 V.
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[13] King-Jet Tseng, Shuyu Cao and Jijiu Wang, A New Hybrid C-dump and Buck-Fronted Converter for Switched Reluctance Motors, IEEE Transactions on Industrial Electronics., Vol. 47, No. 6, pp 12281236, 2002. [14] T. Gopalarathnam and H. A. Toliyat, A High Power Factor Converter Topology for Switched Reluctance Motor Drives, IEEE Industry Applications Conference, Vol. 3, pp. 1647- 1652, 2002.
demagnetization voltage. The two quadrant front-end converter operated as a DC/DC boost converter for dynamically boosted voltage. It is connected between power source and SRM to boost voltage for charging the battery with good line power quality. To operate with boost converter for SRM drive, efficiency is increased and torque ripple is reduced. The high demagnetization voltage for motoring operation is illustrated in the form of increased torque at high speeds. At high speeds, torque output of SRM is increased with high demagnetization voltage, which enables faster reduction of phase current to zero after aligned position. Based on general requirements the classic converter is presented in this thesis has high efficiency because of demagnetization voltage fed back to the source for useful utilization.
BIOGRAPHY
REFERENCES
[1] H. J. Chang and C. M. Liaw Development of a Front-End Converter for Switched-Reluctance Motor Drive, IEEE Transactions on Industrial Applications, Vol. 42, No. 06, pp 18-23, 2006. K. I. Hwu and C. M. Liaw, DC-link Voltage Boosting and Switching Control for Switched Reluctance Motor Drives, in Proceedings of IEE Power Electronics Applications, Vol. 147, No. 5, pp 337-344, August 2000. Jaehyuck Kim, and R. Krishnan Novel Two-Switch Based Switched Reluctance Motor Drive for Low-Cost Applications IEEE Transactions on Industrial Applications,Vol.197, No.7, pp 22182225, 2007. Jain, A.K. Mohan, N. "SRM Power Converter for Operation with High Demagnetization Voltage", IEEE Transactions on Industry Applications, Vol. 41, No. 6, pp 1224 1231, September 2005. G. Venkatesan, R. Arumugam, Modeling and Simulation of a Novel Switched Reluctance Motor Drive System with Power Factor Improvement American Journal of Applied Sciences, Vol. 3, No. 1, pp 1649-1654, 2006. T. J. E. Miller Switched Reluctance Motors and Their Control, Clarendon Press, Oxford, 1993. A. M. Hava, V. Blasko and T. A. Lipo, A Modified C-dump Converter for Variable Reluctance Machines, IEEE Transactions on Industrial Applications, Vol. 28, No. 5, pp 1017-1022, 1992. Y. G. Dessouky, B. W. Williams and J. E. Fletcher, A Novel Power Converter with Voltage-Boosting Capacitors for a Four-Phase SRM Drive, IEEE Transactions on Industrial Applications, Vol. 45, No. 5, pp 815-823, 1998. F Soares, P. J. Costa Branco, Simulation of a 6/4 Switched Reluctance Motor Based on Matlab/Simulink Environment IEEE Transactions on Aerospace and Electronic Systems, Vol. 37, No. 3, pp 567-655, 2001.
Pradeep A. was born in Tamilnadu, India. He received B.E degree in Electrical and Electronics Engineering from Kumaraguru College of Technology, in 2007. Currently he is doing M.E Power Electronics and Drives in from Bannari Amman Institute of Technology, Sathyamangalam. His area of interest includes power electronics, AC & DC Drives, Protection & Switchgear and converters & Inverters.
[2]
[3]
[4]
J.Karpagam, She completed her Masters degree in the specialization of Power Electronics and Drives from Anna University Chennai, India. Presently she is working as Assistant Professor in the department of Electrical and Electronics Engineering at Bannari Amman Institute of Technology Tamilnadu, India and she is in this profession since 1999. Currently she is pursuing her Ph.D. in the area of multilevel converters applications to AC Drives under Anna University Coimbatore. Her area of interest includes Power Electronics, DSP applications to Power Electronics and Wind Power Generation, Solid State Drives, Power Converters, AC & DC drives. So far she has published around 15 papers in national level and International conferences.
[5]
[6] [7]
Kannapiran E. He completed his Masters degree in the specialization of Power Electronics and Drives from Anna University Chennai, India. Presently he is working as Lecturer in the department of Electrical and Electronics Engineering at Bannari Amman Institute of Technology Tamilnadu, India .His area of interest is AC & DC Drives, Embedded systems, neural network and computer networks. He has two years experience in system administration. So far he has published around 5 papers in national level conferences.
[8]
[9]
[10] R. Krishnan and N.Peter Staley, Design of a Single-Switch PerPhase Converter for Switched Reluctance Motor Drives, IEEE Transactions on Industrial Electronics, Vol. 37, No. 6, pp 469-476, 1990. [11] R. Krishnan, S. Y. Park, and K. S. Ha, Theory and Operation of a Four-Quadrant Switched Reluctance Motor Drive with a Single Controllable Switch-The Lowest Cost Brushless Motor Drive, IEEE Transactions on Industrial Applications, Vol.41, No.4, pp 1047-55, Aug 2005. [12] A. K. Jain, Two Phase Modelling Experimental Characterization and Power Converter with Fast Demagnetization for Switched Reluctance Motor Drives, Ph.D. Thesis, University of Minnesota, 2003.
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DIRECT TORQUE CONTROL OF INDUCTION MOTOR DRIVE USING MATRIX CONVERTERS

M.Suresh, J.Karpagam, Dr.A.Nirmal Kumar
Abstract This paper presents the direct torque control of induction motor drive using matrix converters. DTC is a high performance motor control scheme with fast torque and flux responses. However, the main disadvantage of conventional DTC is electromagnetic torque ripple. In this paper, direct torque control for Induction Motors using Matrix Converters is analysed and points out the problem of the electromagnetic torque ripple which is one of the most important drawbacks of the Direct Torque Control. Besides, the matrix converter is a single-stage ac-ac power conversion device without dc-link energy storage elements. Matrix converter (MC) may become a good alternative to voltage-source inverter (VSI). This work combines the advantages of the matrix converter with those of the DTC technique, generating the required voltage vectors under unity input power factor operation. Simulation results demonstrates the effectiveness of the torque control. KeywordsDirect Torque control, vector control, Matrix Converters, space vector modulation
phase Matrix Converters (MC) have emerged to become a good alternative to the well known Voltage Source Inverter (VSI)[2,10] due to its advantages over voltage source inverters. In this paper, a new control technique for matrix converters which generates, under unity input power factor conditions, the voltage vectors needed to implement the DTC for induction motors is investigated. Simulation results, which demonstrate the effectiveness of the proposed scheme, are presented. The results obtained states a good torque response and minimized torque ripples. II.DIRECT TORQUE CONTROL THEORY The principle of Direct Torque Control (DTC) is to directly select voltage vectors according to the difference between reference and actual value of torque and flux linkage. Torque and flux errors are compared in hysteresis comparators. Depending on the comparators, a voltage vector is selected from a table. Advantages [6] of the DTC are ; low complexity, no pulse width modulation is needed, no coordinate transformations needed. Instead one of the six VSI voltage vectors is applied during the whole sample period. All calculations are done in a stationary reference frame which does not involve the explicit knowledge of rotor position. Still, for a synchronous motor, rotor position must be known at start-up. The DTC hence require low computational power when implemented digitally. The system possess good dynamic performance but shows quite poor performance in steady-state since the crude voltage selection criteria give rise to high ripple levels in stator current, flux linkage and torque. Its simplicity makes it possible to execute every computational cycle in a short time period and use a high sample frequency. For every doubling in sample frequency, the ripple will approximately halve. The problem is that the power switches used in the inverter impose a limit for the maximum sample frequency. In general, a scalar control technique called Volts/hertz control being among the simplest control methods. It is used where exact torque and flux control is not essential but where speed control is desirable, like when several motors are driven in parallel by a single inverter. Vector control is used where high performance torque and flux control is needed. Vector control can be implemented by using FOC or DTC technique. DTC technique is simple, robust and offer good dynamic performance. FOC technique gives the best performance in terms of ripples level but requires more processor power and are more complicated to implement.
I. INTRODUCTION For many years, induction machine[6,8] have provided the most common form of electromechanical drive for industrial, commercial and domestic applications that can operate at essentially constant speed. Induction machines have simpler and more rugged structure, higher maintainability and economy than DC motors. They are also robust and immune to heavy loading. In the mid 1980s, a new advanced control technique, known as direct torque and flux control (DTFC or DTC) or direct self-control (DSC) [6] was introduced for voltage-fed PWM inverter drives. However, some research is still being done to adapt DTC to new motors and converters and also to reduce the torque ripple [1, 4] which is one of its main drawbacks. DTC, as the name indicates, is the direct control of torque and flux of a drive by the selection, through a look-up table, of the inverter voltage space vectors. The main advantage of DTC is its structure simplicity, since no coordinate transformations and no PWM generation are needed. However, torque and flux modulus values and the sector of the flux are needed. Not only it is a very simple and robust signal processing scheme but also a very quick and precise torque control response is achieved. Recently, three
M.Suresh, PG scholar, EEE Department, Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: infostosuresh@gmail.com J.Karpagam, Assistant Professor, EEE Department, Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: sujisumi@rediffmail.com Dr. A. Nirmal Kumar, Professor and Head, EEE Department, Info Institute of Engineering, Coimbatore.
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On substituting yields, in and further simplification which
III. DIRECT TORQUE CONTROL PRINCIPLE In the direct torque control principles, it has been proven that the change of torque can be controlled by keeping the amplitude of the stator flux linkage constant and increasing the rotating speed of the stator flux linkage as fast as possible [6]. The amplitude and rotating speed of the stator flux linkage can be controlled by selecting the proper stator voltage vectors. Direct torque control (DTC) is one method used in variable frequency drives to control the torque (and thus finally the speed) of three-phase AC electric motors. This involves calculating an estimate of the motor's magnetic flux and torque based on the measured voltage and current of the motor. The torque expression can be expressed in the vector form as,
(9) that is, the magnitude of torque is,
(10) where is the angle between the fluxes.
If the rotor flux remains constant and the stator flux is changed incrementally by the stator voltage and the angle is , the incremental corresponding change of torque expression is given as
(1) where
(11) (2) and (3) IV. MATRIX CONVERTER Nowadays Matrix Converters are being alternative for Voltage Source Inverters, which converts AC-AC supply without any intermediate dc link. The Matrix Converter is an advanced circuit topology capable of converting AC-AC, providing generation of load voltage with arbitrary amplitude and frequency, bidirectional power flow, sinusoidal input/output waveforms, and operation with unity input power factor. Furthermore, since no inductive or capacitive elements are required, matrix converter allows a very compact design. A Matrix Converter is an AC-AC converter, with m x n bidirectional switches, which connects an m-phase voltage source to an n-phase load. From a practical point of view, the three-phase matrix converters having 3x3 switches connects a three phase voltage source to a three-phase load, e.g. a motor. In the MC shown in fig.1, a switch Sij, i={A,B,C}, j={a,b,c} can connect phase i of the input to phase j of the load. With a suitable switching strategy, arbitrary voltages VjN at arbitrary frequency can be synthesized. Switches are characterized by the following equation: Sij = 0 , (7) The corresponding equation of is if Sij is open and
In this equation,
is to be replaced by the rotor flux
In the complex form, and the functions of currents as
can be expressed as
(4) (5) Eliminating from equation , we get
(6) where
Sij = 1 , if Sij is closed. The induction motor drive fed by matrix converter is superior to the induction motors fed by the conventional inverters because of the lack of bulky direct current (dc)-link capacitors with limited lifetime, bidirectional power flow capability, sinusoidal input/output currents and adjustable input power factor.
(8)
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Fig.2 shows the space vectors for the Matrix Converters. The magnitude and direction of the active vectors depends upon the instantaneous line-to-neutral voltages and line currents as shown in Table 2. The direction of each of these vectors remains constant. On the contrary, the magnitude of the six rotating vectors remains constant and corresponds to the maximum value of the input line-to-neutral voltage vector and the input line current vector, while its direction depends on the angles of the line-to neutral input voltage vector i and the input line current vector. Fig.3 shows the vector rotations of Matrix Converters, which is used for the vector selection.
Fig. 1.Three Phase Matrix Converters
A mathematical model of the MC can be derived as follows: Applying Kirchhoffs voltage law, (12) can be easily obtained.
(12) Applying Kirchhoffs current law, it can be found that

Fig.3. Rotation of Space Vectors
Table.1 Switching Table for Matrix Converters
(13) where the output voltages and output currents are being synthesised by the input voltages and input currents respectively. V. SPACE VECTORS OF MATRIX CONVERTER It can be noted that the three-phase MC allows any output phase to be connected to any input phase. Thus, 27 switching configuration are possible. Applying Clarks transformation to the 27 possible switching configuration, it can be easily found that a MC can generate 18 active, voltage and current space vectors, three zero vectors and six rotating vectors[13]. Table 1 shows the 27 switching states of the three phase MC. The first 18 states (1, 2, 3, 4, 5, 6, 7, 8, 9) corresponds to the active vectors. 0a, 0b and 0c are the corresponding zero vectors states. And the last six states (shadowed rows) are the rotating vectors. Representation of the output line-to-neutral voltages and input line currents space active vectors are shown in fig.2
VI. DTC USING MATRIX CONVERTERS
Fig.2. Space Vectors of Matrix Converters
Matrix Converters generates a higher number of output voltage vectors with respect to a VSI, the introduction of a third variable, such as the average value of the sine of the
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in terms of stator voltages and currents measured from the motor, which generates the flux and torque errors that properly selects the voltage vectors in order to drive the motor. A Matrix Converter is being used to run the motor, from which the faster torque response can be achieved.
displacement angle between the input line current vector and the input line to neutral voltage vector, can be used to keep under control of the input power factor. The flux, torque estimations require the and the average value of sine knowledge of voltages and currents at the input and output side of the MC. Assuming that Vo is the output voltage vector selected by the basic DTC control algorithm, from table 1, it is obvious that one of the switching states 1, 2 or 3 must be selected. Since the magnitude and direction of these voltage vectors depends on the input line-to-neutral voltage vector, only those having the same direction of Vi and the maximum magnitude will be taken into consideration.
Table 2. Switching table for DTC using Matrix Converters
Fig .5. Stator Flux of Induction Motor
Fig.5 shows the variation of stator flux waveforms, where the stator flux is sinusoidal in nature, whose amplitude is about 0.7 wb/m2.
VII. SIMULATION RESULTS AND DISCUSSION Fig.4 shows the overall MATLAB/Simulink diagram for the Direct Torque Control of Matrix Converter fed Induction Motor drive.
Fig. 6. Voltage Sectors of Matrix Converter
Fig .6 shows the voltage sector waveforms of the Matrix Converter, in which the proper voltage sectors are being selected from the look up table in order to drive the Induction motor.
Fig.4. Overall Simulation Model of Matrix Converter fed Induction Motor Drive
Fig .7. Stator Voltage of Induction Motor
In order to control the speed of an induction motor, an reference value of flux and torque is being chosen initially and it is being compared with that of the torque and the flux,
Fig.7 shows the stator voltage waveforms which is used to drive the induction motor, whose amplitude is about 300V,which is sufficient to drive the motor.
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Fig .8. Stator Current of Induction Motor
Fig. 11. Torque of Induction Motor
Fig.8 shows the variation of stator current with respect to time where the initial starting current is about 25 A and then gradually decreases to about 15 A , which avoids the heating of windings.
Fig.11 shows the variation of torque with respect to time. When the speed starts increasing, the torque gradually decreases to about 40 Nm. VII.CONCLUSION In this paper, the matrix converter fed induction motor drive implemented by DTC is simulated. Based on the principles of the matrix converter and direct torque control, combined control strategy is presented, which can implement the real-time space vector modulation of converter and induction motor stator flux linkage oriented direct torque control. The equations show that the change of torque can be controlled by keeping the amplitude of the stator flux linkage constant and increasing the rotating speed of the stator flux linkage as fast as possible. The amplitude and rotating speed of the stator flux linkage can be controlled by selecting the proper stator voltage vectors. The torque and flux linkage reference are kept constant at the same level in order to reduce the torque ripples. The simulated results shows that induction motor drive fed by the matrix converters using direct torque control technique has reduced torque ripples and faster torque response.
REFERENCES [1] Casdei.D, Serra.G, Tani.A, The Use of Matrix Converters in Direct Torque Control of Induction Machines, IEEE Transactions on Industrial Transactions, Vol 48, No.6, pp 1057-1064, Dec 2001. P. Wheeler, J. Rodriguez, J. Clare, L. Embringham, and A. Weinstein, Matrix Converters: A Technology review, IEEE Trans. on Industrial Electronics, Vol. 49, No. 2, pp. 276-288, April 2002. D. Casadei, G.Grandi, G.Serra, A. Tani, Switching Strategies in Direct Torque Control of Induction Machines, Proceedings in International Conference on Electrical Engineering, Paris, pp. 204209, 5-8 September 1994. M. Depenbrok, Direct Self-Control (DSC) of Inverter-Fed Induction Machine, IEEE Trans. on Power Electronics, Vol. 3, pp. 420-429, Oct. 1988. Takahashi, T. Noguchi, A New Quick-Response and High Efficiency Control Strategy of an Induction motor, IEEE Trans. on Industrial Automation and Electronics, Vol. IA-22, No. 5, pp. 820-827 Sept./Oct. 1986. Bimal K.Bose, Modern Power Electronics and Electric Drives Englewood Cliffs, 2nd Edition, New Jersey, Prentice Hall, 1986.
Fig .9. Rotor Flux of Induction Motor
Fig.9 shows the variation of rotor flux with respect to time, in which the rotor flux amplitude is about 0.7 wb/m2 and it is also sinusoidal as that of stator fluxes.
[2]
[3]
[4]
Fig .10. Speed of Induction Motor
[5]
Fig.10 shows the variation of speed with respect to time. At the time of starting, the speed gradually increases and then maintains the constant speed of about 1900rpm.
[6]

[7] Zhong.Ll, Rahman.M, Hu.W, Lim.K Analysis of Direct Torque Control in Permanent Magnet Synchronous Motor Drives, IEEE Trans on Power Electronics, Vol. 12, No. 3, May 1997. C.Ortega, P.Wheeler, Sensorless Induction Motor Drives Fed by a Matrix Converter, IEEE Proceedings on Industry Applications Conference, Fourtieth IAS Annual Meeting, Vol.4, 2-6 Oct. 2005 . Lascu.C, Boldea. I, Blaabjerg.F ,A Modified Direct Torque Control for Induction Motor Sensorless Drive,IEEE Trans on Automation and Electronics , Vol. 36, No. 1, pp. 122-130, Jan.-Feb 2000.
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[8]
[9]
[10] Hong Hee Lee , Hoang M.Nguyen, Tae Won Chun, Implementation of Direct Torque Control method using Matrix Converter fed Induction Motor, Journal of Power Electronics, Vol.8, No.1, pp. 74-80, January 2008.
BIOGRAPHY
M.Suresh was born on 1988 in Tamilnadu, India. He received his B.E degree in Electrical and Electronics Engineering from Muthayammal Engineering College, Rasipuram, Affiliated to Anna University, Chennai in the year 2005. Currently, he is doing his Masters degree in Power Electronics and Drives in Bannari Amman Institute of Technology, Sathyamangalam, Affiliated to Anna University, Coimbatore. His area of interests includes Digital systems and Design, Sensorless control of Induction motor Drives. J.Karpagam, She completed her Masters degree in the specialization of Power Electronics and Drives from Anna University Chennai, India. Presently she is working as Assistant Professor in the department of Electrical and Electronics Engineering at Bannari Amman Institute of Technology Tamilnadu, India and she is in this profession since 1999. Currently she is pursuing her Ph.D. in the area of multilevel converters applications to AC Drives under Anna University Coimbatore. Her area of interest includes Power Electronics, DSP applications to Power Electronics and Wind Power Generation, Solid State Drives, Power Converters, AC & DC drives. So far she has published around ten papers in national level and international conferences. Dr.A.Nirmal Kumar was born in the year 1951. He completed his PG and UG in Electrical Engineering from Kerala and Calicut University respectively. He completed PhD in Power Electronics in the year 1992 from P.S.G. College of Technology, Coimbatore under Bharathiyar University. He was in teaching profession for the past 35 years. Currently he is the Professor and Head, Department of EEE at Info Institute of Engineering, Coimbatore. He is a recipient of Institution of Engineers Gold Medal in the year 1989. His current research areas include Power Converters for Wind Energy Conversion System, Solid State Drives, Electrical Machines and Controller for Induction motor drives
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Dynamic Model Analysis of Induction Motor

Asst professor, Dept of Electrical and Electronics Engineering, Bannari Amman Institute of Technology Steffi.kuriakose@gmail.com
Steffi Kuriakose, P.G Student, S.Veerakumar,M.E.,
Abstract - Dynamic or transient condition occur in electric drive system, when the operating point changes from one steady state condition to another following a change introduced in system variable. Ordinary voltage source inverter fed induction motor has poor response in the transient conditions. Pulse width modulation techniques are the most efficient method for controlling the output voltage of the inverter. The flux and torque output of an ac motor is directly controlled by the current input to the motor. For high dynamic controlled drive applications hysteresis band current control is initially preferred due to its fast dynamics, easy for implementation and accurate control.In hysteresis-band current control the actual current tracks the command current within a hysteresis band. The main aim of this paper is to generate pulses using Hysteresis PWM technique for voltage source inverter to improve transient response of induction motor.
input voltage is supplied and a controlled ac output voltage is obtained by adjusting the on and off periods of the inverter switching device. PWM inverter offers better harmonic control of the output than six-step inverter.The commonly used PWM techniques for voltage source in are Sinusoidal PWM, Space Vector PWM and Hysteresis band Current Control PWM. The flux and torque output of an ac motor is directly controlled by the current input to the motor. For high dynamic controlled drive applications hysteresis band current control is initially preferred due to its fast dynamics, easy for implementation and accurate control.This approach is very popular because of simple implementation, fast transient response, direct limiting of device peak current and practical insensitivity to dc link voltage ripple. In hysteresis-band current control the actual current tracks the command current within a hysteresis band. The main aim of this paper is to generate pulses using Hysteresis PWM technique for voltage source inverter.The simulation model is developed using PSpice 9.2.
Index Terms- Induction motor, Pulse width modulation (PWM), Hysteresis current control (HCC), PSpice 9.2.
1. INTRODUCTION
Dynamic or transient condition occur in electric drive system, when the operating point changes from one steady state condition to another following a change introduced in system variable. These variables may be mechanical such as speed torque etc or electrical such as voltage current etc. These conditions generally exist during starting, braking and speed reversal of the drive. The drive may also have transient behaviour if there are sudden changes of load, supply voltage or frequency. Ordinary voltage source inverter fed induction motor has poor response in the transient conditions. It also has high harmonic content. Pulse width modulation techniques are the most efficient method for controlling the output voltage of the inverter. In this method a fixed dc
2. HYSTERESIS CURRENT CONTROL PWM

Hysteresis current control is a method of controlling a voltage source inverter so that an output current is generated which follows a reference current wave form. Hysteresis current control is the easiest control method to implement.In hysteresis-band current control the actual current tracks the command current within a hysteresis band. In this approach a sine reference current wave is compared to the actual phase current wave. As the current exceeds a prescribed hysteresis band, the upper switch in the half-bridge is turned off and the lower switch is turned on. As the current goes below the hysteresis band, the opposite switching takes place.
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Consider a single phase half bridge configuration
Here a envelope is introduced in the reference current. It is called the Hysteresis Band such that the current ripple is not allow to go above or below the band. Current ripple is confined to a Hysteresis band, so that the average variation of current is nearly sinusoidal. In this technique, reference load current signals are generated and the inverter switches are controlled so that the actual inverter phase currents match these within tolerable error limits. The scheme requires current sensors to sense actual phase currents. For a three-phase load, sensing two phase-
Fig 3.1 Single phase half bridge inverter
Fig 3.2 Pulse for S1 and S2 Fig 2.1.Principle of Hysteresis current control PWM
When S1 ON current will flow through iL. When S2 is ON Vdc/2 and Ec oppose current so it falls. When S1 is ON
currents suffices as the third phase current can be obtained by algebraic manipulation of the other two. The actual currents are compared with the corresponding reference currents to generate the required switching action. To increase the magnitude of current leaving the inverter pole the high side switch of the particular pole is turned on. Conversely the low side switch is turned on to decrease the magnitude of load current. Turning of high side switch causes input dc voltage to support the load phase current. The load phase current flows against the input dc voltage when low side switch is ON. The control actions for individual legs are generally independent of each other but the rate at which current changes in one leg may get affected by the switching state of the other legs. The control required is simple and the load current is directly controlled, hence the name CCPWM.
dil (dc /2) E I V P I I C V dt L T ONT ON

TO N (V d c I / 2 ) . EC L
(1) (2)
When S2 is ON
(V d c T o ff T o ff .L (V
d c
/ 2 ) L I / 2 )
E
(3)
T
Switching by,
Tn o
Tf f o
is
(4)
3. SWITCHING FREQUENCY OF HCC

Switching Frequency of HCC depends on Hysteresis Band and on load whether it is inductive or with back emf.. Select width of hysteresis band to optimally balance harmonic ripple and inverter switching loss.Current control tracking is easy at low speed but at high speeds, when counter EMF is high, current tracking can be more difficult.
frequency
F is inversely proportional to Hysteresis Band. When frequency decreases current ripple decreases. With a fixed tolerance band , the
(Vdc / 2)2 E c2 (Vdc / 2). L.
1 T
(5)
given
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compared to the commanding currents, and the error signals are operated by the current controller to generate the firing pulses, which activate the inverter power switches in a manner that reduces the current error.
switching frequency depends on the output load voltage,Ec. For three phase operation Ec varies sinusoidally EC Emax Sint When EC =0, frequency, maximum switching
f max is
V dc / 4 L . I
M is the Modulation
f m ax f m
Index.
E f fm 1 ( C 2) V dc / 2 V EC M . dc .Sint Where 2
an average value.
m 2 m2 f f m 1 Cos 2t , ie f varies around 2 2
Fig 4.5 Current controlled Voltage source inverter
Fig 3.4.Thre e phase inverter
or variable speed application, we have to decide the hysteresis band either for maximum switching frequency or for average value. In a star connected load sum of phase currents, ia ib ic 0 The phase which has maximum back emf will have minimum switching frequency. The current variation in a phase with minimum switching frequency will be decided by the other two phases. The phase which has the minimum switching frequency will experience current overshoot ie current ripple will go beyond the hysteresis limit.
F
Fig 4.6 Switching current wave form
Here ia is the peak-to-peak current ripple and T is the cycle period, t1 and t2 are the times at which the inverter output voltage is switched between +VB and -VB respectively. The time in which the line current will increase by ia can be found from t ( t1+ t2) as 1 gives the inverter t L aVaRia) i ( f t switching frequency.
4. IMPLEMENTATION OF HYSTERESIS BAND PWM

The function of the current controllers is to force the load current to follow as closely as possible the reference current. The operation of the current-controlled voltage-source inverter (VSI) is given below. In this diagram, a balanced threephase RL load is connected to the three-phase transistor inverter. The sensing currents are
The purpose of the current controller is to control the load current by forcing it to follow a reference one. This is achieved by the switching action of the inverter to keep the current within the hysteresis band. A simplified diagram of a typical three-phase hysteresis current controller is shown below, while SW is off. The load currents are sensed and compared with the respective command currents using three independent hysteresis comparators having a hysteresis band, H.
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The output signals of the comparators are used to activate the inverter power switches. The advantage of the controller lies in its simplicity and its providing of excellent dynamic performance. Thus, it is most extensively used. Based on the band, there are two types of current controllers. 1. Sinusoidal-band hysteresis current controller. 2. Fixed-band hysteresis current controller. In a sinusoidal band controller, the hysteresis band varies sinusoidally over a fundamental period. The mathematical model for this scheme is given as
Fig 4.7 Hysteresis current controller scheme
Fig 4.8 Waveforms of hysteresis current controller Sinusoidal band and Fixed band
iref I maxSin t iup (I max H )Sin t

In the fixed-band scheme, the hysteresis band is fixed over the fundamental period. The ripple content of the current can be reduced in fixed-band. The mathematical model for the fixed band scheme is given as
Fig 4.9 Control block diagram for Hysteresis-band PWM
ilo (I max H )Sin t
The error in the control loop is input to a Schmitt trigger circuit. The width of the hysteresis band HB is given by
HB V
R2 R1 R 2
i ref Im ax S in t iu p iref H ilo iref H

Where (13)
* Lower switch on: (i -i) <-HB * Upper switch on: (i -i) >HB
5. ADVANTAGE OF HCC PWM

This approach is very popular because of Simple implementation, Fast transient response, Direct limiting of device peak current Practical insensitivity to dc link voltage ripples (small filter capacitor).
iup is the upper band,
H is the hysteresis band limit.
ilo is the lower band and
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The upper band and lower band is set in the hysteresis comparator. When the actual current touches the upper band lower device is turned on and when it touches the lower band upper device is turned off. In this way gating signals are generated to the voltage source inverter. The output of the voltage source inverter is fed to the induction motor drive.
6.1THREE PHASE DIODE RECTIFIER OUTPUT

Table 5.1 Comparison of current controllers.
However, PWM frequency is not constant which leads to non-optimal harmonic ripple in machine current. It can create sub harmonics and it has distributed harmonic spectrum. Also, significant phase lag at high frequency is a drawback of this method for high-performance drives. The necessity of fast current sensors may be seen as a drawback but current sensor costs are coming down and most inverter circuits employ current sensors, any way, for protection against over-current. Another draw back of the scheme may be associated with the hysteresis controller, if used. The switching frequency of such controllers becomes dependent on load parameters and may not remain optimum for the given load.
Fig 6.1 Output of Three phase Diode Rectifier
6. SIMULATION RESULTS
Fig 6.2 Output of Three phase Diode Rectifier with filter
6.2 HYSTERESIS PULSE GENERATED FOR SWITCH 1(PHASE A)
Fig 6.1 Block diagram of Hysteresis current control PWM
The Fig 1.2 shows the block diagram of Hysteresis current control PWM which is used to generate PWM pulses. Here the actual current is compared with the reference current and is given to Hysteresis comparator.
6.3. Hysteresis pulse generated for switch 1(phase a)
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8. REFERENCES
[1] P.A.Dahono (2009) New hysteresis current controller for single-phase full bridge inverter . IET Power Electron.,2009. [2] P. N. Tekwani, R. S. Kanchan, K. Gopakumar (2007) Novel current error space phasor based Hysteresis Controller using Parabolic Bands for control of Switching Frequency Variations .. IEEE Trans on Indus Electr October 2007. [3] B.J.Kang, C.M.Liaw(2001)Robust hysteresis current- controlled PWM scheme with fixed switching frequency. IEEE Proc- Electr. Power. November 2001 4] R . Ramchand , K. Siva Kumar(2010)Improved switching frequency variation control of hysteresis controlled VSI- fed IM drives using current error space vector. IET power electron ., 2010. [5] Vinay M , Mistry S ,P. Waikar (1997) A Multi Axis Space Phasor Based Current Hysteresis Controller for PWM Inverters. 1997 IEEE. [6] Sidney R. Bowes & Derrick Holliday (2007) Optimal Regular Sampled PWM Inverter Control Technique. IEEE Trans on Indus Electr, JUNE 2007. [7] Bong-Hwan Kwon, Byung-Duk Min (1998) An Improved Space-Vector-Based Hysteresis Current Controller ., IEEE Trans on Indus Electr, OCTOBER 1998. [8] A.N. Tiwari, P. Agrawal (2003) Modified hysteresis controlled PWM rectifier. IEE
6.3. LINE VOLTAGES OF HCC PWM INVERTER
Fig 6.3 Output line voltage for phase A and phase B (Vab)
6.4 OUTPUT VOLTAGE WAVE FORM OF HCC PWM FED INDUCTION MOTOR
Fig 6.4 Output voltage wave form of Hysteresis Current Control PWM fed Induction Motor
Proc. -Electr. Power , July 2003.
7. CONCLUSION
Hysteresis current control is the easiest control method to implement.In hysteresis-band current control the actual current tracks the command current within a hysteresis band. This approach is very popular because of Simple implementation, Fast transient response, Direct limiting of device peak current and Practical insensitivity to dc link voltage ripples. Here PWM pulses are generated for voltage source inverter using Hysteresis current control technique. The simulation model is developed using PSpice 9.2. By using a current control method like hysteresis PWM technique we can improve the dynamic response of induction motor.
[9] Musbah J. Aqel, Walid Emar (2008) Modeling and Simulation of a Modified BangBang Hysteresis Control Technique for a Three Phase PWM Converter European Journal of Scientific Research ISSN (2008) [10]LucaDalessandro,Simon D.RoundCenterPoint Voltage Balancing of Hysteresis Current Controlled Three-Level PWM Rectifiers,. IEEE Trans on Power Electronics, SEPTEMBER 2008. BIOGRAPHY
S.Veerakumar was born in the year 1983. He completed is PG and UG in Electrical Engineering form VIT Deemed university, Vellore and Kongu Engineering College, Perundurai. He is currently doing his Ph.D in the area of Industrial Drives at Anna Institute of Technology, Coimbatore.
Steffi Kuriakose was born in the year 1986. She received her B.Tech degree in Electrical and Electronics from M.G University college of Engg Kerala. Currently she is doing M.E Power Electronics and Drives in Bannari Amman Institute of Technology, sathyamangalam. Her areas of interests includes Designing and developing Microcontroller based systems.
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FPGA Based AC Motor Control for Closed Loop Application (Comparison, Consideration & Implementation)
G.N.Nandish and Chethan D Raj M.S.Ramaiah Institute of Technology Bangalore, Karnataka Abstract: In this paper we are presenting an over view of FPGA ( Field Programmable Gate Array ) based control of AC drive for closed loop application , over other control category like DSP, microcontroller etc . FPGA is a programmable logic device which is considered as an efficient hardware for rapid prototyping in which architecture is not fixed, & it can be programmed such a way that, we can develop flexible control architecture for necessary control of an AC drive in either open loop or closed loop. This paper gives necessary consideration & comparison for implementing FPGA as a controller over other control methods. FPGA controller is used to take the digital form of input of different circuit controllable parameter like voltage, current, torque, speed etc generates the necessary command signals which in turn switches the inverter to obtain necessary control. Objective of our presentation is to provide an overview on implementation of FPGA based AC Drive control, under different considerations like cost, speed, flexibility, implementation constraints etc. Introduction: The primary function of any adjustable speed motor drive is to control the speed, torque, acceleration, deceleration and direction of rotation of machine. Unlike constant speed systems, the adjustable drive permits the selection of infinite number of speeds within its operating range. Most multipurpose production machines benefit from adjustable speed control, since frequently their speed must change to optimize the machine process or adapt it to various tasks for improved product quality, production speed or safety. The controller circuit should flexible so that any change in required control is done without replacing the hardware. Hence from the flexibility point, FPGA can be preferred & implemented as a controller for AC drive control application. A Field FPGA an Overview: Programmable Gate Array is a reconfigurable digital integrated circuit that can be programmed to do any type of digital function. The FPGA has logic elements arranged in rows and columns as shown. Each logic element has certain hardware resources, which will be utilized to realize the user logic. The choice of an FPGA device for a given application is based on the size required (number of logic elements), clock speed and number of I/O pins. XILINX & ALTERA are the leading, FPGA manufacturers industries.
Index terms: Introduction, FPGA, proposed Block diagram, PWM inverter & techniques, control algorithm, MATLAB simulation
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The FPGA consists of three major configurable elements as shown in figure 1
download cable connected to a host computer (parallel port of PC) as shown in figure 2. Once they are programmed, they can be disconnected from the computer and will retain their functionality until the power is removed from the chip. The FPGAs can be programmed while they run, because they can be reprogrammable in the order of microseconds.
Figure 1. Configurable Logic Blocks (CLBs) arranged in an array that provides the functional elements and implements most of the logic in a FPGA. Input-output blocks (IOBs) that provide the interface between the package pins and internal signal lines. Programmable interconnects that provide routing path to connect inputs and outputs of CLBs and IOBs to the appropriate network .FPGA supports hardware that is upwards of one million gates, which can be re programmed to upgrade the design & re use the same hardware , which can decrease E-waste to environment . Once they are programmed, they can be disconnected from the computer and will retain their functionality until the power is removed from the chip. The FPGAs can be programmed while they run, because they can be reprogrammable in the order of microseconds. FPGAs are programmed using support software and a
Figure 2 VERILOG & VHDL are hardware description language used to describe electronic circuits and digital systems. In practice it is generally used for simulating, testing, and programming PLDs (programmable logic devices) or FPGA s other similar hardware. We have chosen Verilog over VHDL because it is easier to learn and use for most people because it looks like the C language in syntax. Verilog is a language that includes special features for circuit modeling and simulation. Why FPGA? DSP & Micro-controllers technology offering increasing performance you might wonder how FPGAs could be the next stage in the evolution of motor control. FPGAs has no fixed architecture , hence its architecture can be designed & implemented to match required control process , at any instant , without changing existing hardware.FPGAs give designers the freedom
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to create custom functions completely adapted to their specific application requirements by enabling both hardware and software customization. An FPGA-based motor controller offers completely deterministic performance and enhanced product reliability compared to the serial instruction-execution approaches of MCUs or DSPs. Why it is better option to go for FPGA? , can be understood well from its following advantages. Unlike an ASIC (Application Specific Integrated Circuit) which can perform a single specific function for the lifetime of the chip, an FPGA can be reprogrammed to perform different function in a matter of microseconds. DSP processor/ microcontrollers are sequential machines i.e. tasks are executed sequentially which take longer processing time, whereas FPGA can be configured to perform independent functions simultaneously. DSP processor/ microcontrollers architecture & hardware is fixed, so software is the only option, where designer can change control logic or control characteristic. Whereas in FPGA hardware is flexible & reconfigured. Bit length of the digital word is limited in DSP processor/ microcontrollers but not in FPGA. Control technique cost of FPGA is low compared to DSP processor/ microcontrollers. FPGA can be re-programmed when they are running in real time. FPGA has ability to operate faster, higher processing power, & supports hardware i.e. Upwards of one million gates.
Block Diagram Proposed.
Figure 3 Power supply: AC drive, FPGA chip, ADC, DAC & other instrumentation devices needs sufficient & compactable power for their working and its fulfilled by power supply block. In case of self contained unit power requirements can be fulfilled directly by battery systems. Rectifier & DC Link: if the available power source is AC then, AC power required to run an AC drive, initially converted to DC by rectifier circuit designed for motor applications. Purpose of DC link is to limit the current & to provide pure DC output. ADC/DAC: ADC is used to convert the analog input signals from the AC drive system to digital signals, which are used for further processing by FPGA.DAC is used to output the digital variables in the controller in analog form, which is used to drive switching devices of inverter. Drive circuit Isolation: The Driver circuit isolates FPGA & Inverter circuit & gives the required gate signals to switching devices (IGBT) depending on output of the FPGA, which in turn controls the operation of the AC motor.
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PWM Inverter & Techniques. The basic full bridge MOSFET or IGBT based inverter as shown in figure 3 is used to convert DC to AC. The PWM signals are applied to gate of inverter switch through isolation circuit. In Pulse Width Modulation technique the different types of modulating modes are Sinusoidal PWM, Space Vector PWM etc. Figure 3 Figure 4 FPGA can reduce THD (Total Harmonic Distortion) by 30% to 50% at high modulation index as shown in figure 4, so that less audible noise .Hence FPGA can be selected. Control Algorithm: The sensor in circuit is used to sense the actual parameter (speed, voltage, current). FPGA controller compares actual parameters with set parameters & generates the error signals if any difference exists; error command then changes the amplitude of the sine wave to minimize the difference.
PWM techniques are of two types Analog & Digital Techniques. In analog techniques there is a carrier signal and a modulating signal. These two signals are compared using comparator. The output of this comparator is the desired PWM output. Disadvantages of these analog methods are, that they are prone to noise and they change with voltage and temperature change. They suffer changes due to component variation. They are less flexible as compared to digital methods. Digital methods are the most suited form for designing PWM Generators. They are very flexible and less sensitive to environmental noise. Also they are simple to construct and can be implemented very fast and can be implemented easily using DSP, MCU, FPGAs
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MATLAB experimental setup & result: The following SPWM generation circuit, in which sine wave and triangular wave is compared to generate necessary PWM signals. Same circuit model can be developed in FPGA chip to generate PWM signals. SPWM generation circuit
Following figure shows MATLAB simulated inverter bridge & output voltage waveforms of Inverter Bridge.
Scope 1
Note: a pure sine wave can be obtained by passing the inverter output to low pass filter. Constraint Applying FPGA for electric motor control is an interesting alternative to the recently used digital signal processors. Reconfigurable control hardware cannot be obtained by means of any DSP or microcontrollers. In case of 3 phases AC machines, the PWM generation and closed loop operation using only FPGA, is bit complicated & it requires large capacity FPGA (memory requirement & speed to perform all operation in parallel) hence cost will increase. To reduce such complication, DSP or microcontroller can be used with FPGA as shown in figure 5.
Scope 2 gate pulse for gate Q1, Q2 & Q3, Q4
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Microcontroller or DSP operates in outer loop and provides required control data to FPGA, and FPGA operates in inner loop & provides the required PWM as per control data, to Inverter Bridge, and hence required control can be achieved.
Figure 5 Conclusion FPGA based digital platform is more suitable for the control applications in Power electronic systems. The use of FPGAs in control applications not only increases the performance of the system but also reduces the cost and size of the controller. FPGA platform can also be used for many Applications such as Front-end converters, uninterrupted power supplies, DC-to-DC Converters and phase-controlled rectifiers. As a conclusion, the design of the switching pulses using FPGA technology shall produce better control signal for inverter switches. With the high programming flexibility, the design of the switching pulse can be further altered easily without any further changes on the hardware. For SPWM switching frequency, the number of pulses and the duty cycle generation are Flexible using FPGA & this approach also eliminates the use of more electronic components. Choosing the correct devices for the heart of any system is very difficult and is made
even harder by the emergence of new technologies such as Field Programmable Gate Arrays (FPGA). The only certainties are that the system will invariably have a processing engine of some type, some memory, and logic. We also know with some certainty that choices made in the design phase impact heavily on the total life cycle costs of the end product, so this decision is key to any major project. This decision will be based on time-to-market, costs, cost of change, obsolescence concerns (and the costs associated with this), and cost to service and maintain in the field. FPGAs are a viable alternative to custom microprocessors as they can offer a shorter Time cycle to market, can offer re-usable options, can be used across many platforms/PCBs to reduce inventory costs, and when using them in conjunction with a soft core embedded processor, can solve the Device obsolescence problem. The following table gives clear picture , for selecting FPGA controller over other control methods from different points like cost, speed, reprogram time, reusability etc.
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References: 1. Ying-Yu Tzou, Hau-Jean Hsa,. FPGA realization of Space Vector PWM control IC for three phase PWM converters., IEEE Transaction on Power Electronics, Vol. 12, No. 6, November, 1997, pp. 953-963 . 2. S. Venugopal and G. Narayanan,. FPGA Based Digital Platform for Control of Power Electronic Systems., National Power Electronic Conference, December, 2005. 3. Power electronics by Ned mohan, Udeland, Robbins 4. Rashid M.H., Power Electronics Handbook. Florida, Academic Press, 2001 5. Do-Hyun Jang; Jong-Soo Won; GyuHa Choe "Asymmetrical PWM method for ac chopper with improved input power factor" , IEEE, PESC Conference 1991, Cambridge, Massachusetts, USA, pp. 838845, 1991. 6. Xilinx Inc.,The Programmable Logic Data Book 2000, Xilinx, 2000.
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Impedance Source Inverter for Wind Turbine Driven Permanent Magnet Synchronous Generator
Mr.V Kandhasamy1, Assistant Professor, T.Muthukumar2, PG Scholar, Department of Electrical and Electronics Engineering Kumaraguru College of Technology, Coimbatore, Tamil Nadu muthurajanmec@gmail.com
Abstract- This paper presents a Boost chopper circuit and a Z Source inverter for Wind Energy Conversion System. The main thrust in Wind Energy Conversion System (WECS) is to maintain a constant voltage at the output in spite of variations in wind velocity. The ZSource inverter has been identified to exhibit in steady-state, both voltage buck-and boost-capabilities. It employs a unique impedance network included between the dc power source and converter circuit. All the traditional pulse width modulation (PWM) schemes can be used to control the Z-Source inverter. When the dc voltage is high enough to generate the desired ac output voltage, normal PWM is used. While the dc voltage is not enough to directly generate a desired output voltage, a modified PWM with shoot-through zero states is employed to boost the voltage. The proposed Z-Source inverter with PMG and wind turbine is modeled and simulated using MATLAB/SIMULINK. Key words: Z Source inverter, WECS, PMSG, Wind Turbine, PWM inverter.
A. Traditional Wind Energy Conversion System The basic components of a wind electric system considered in this project are shown in figure 1. Wind Turbine converts wind energy in to rotary mechanical energy. A mechanical interface consists of step up gear and a suitable coupling transmitter, which is connected between wind turbine and Permanent Magnet Synchronous Generator (PMSG). The electric power from generator is connected to local load through power converters, where output with constant voltage and constant frequency can be obtained. The wind turbine converts the kinetic energy of the wind into mechanical energy, which drives the permanent magnet synchronous generator through a gear box. Since the wind is an intermittent source of energy, the output voltage and frequency from generator will vary according to the wind velocities. The variable AC power from the generator is first rectified into DC using diode bridge rectifier. The voltage across the rectifier terminal is regulated for constant voltage by controlling the duty ratio. The constant DC output is inverted and, fed to the load at the required level of voltage and frequency employing a PWM inverter. The duty ratio 6 is used to control the Boost chopper so as to maintain a constant output voltage
I. INTRODUCTION The capital cost of small wind turbine driven electrical power generation system (of rating less then 15kW) is very competitive compared to that of other known non-polluting and renewable energy sources. This paper addresses the issues related to the implementation of Permanent Magnet Synchronous Generators for the stages of power conversion of wind energy. Permanent Magnet Synchronous Generators are preferred over Induction Generators, in view of this improved efficiency and no requirement of reactive excitation current. The permanent magnet does away with the excitation winding for the synchronous machine and offers benefits of price reduction and improved magnetic material characteristics. Variable speed power generation schemes enable operation of the turbine at the maximum power co-efficient point over a wide range of wind speeds, enabling a larger percentage of the energy capture from the wind. To facilitate variable speed operation the Wind Energy System requires variety of power electronics converters.
Wind
PM SG
DIODE RECTIFIER
BOOST CHOPPER
PWM INVERTR
L O A D
CONTROLLER
Figure. 1. Traditional Energy Conversion System
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Drawback The traditional wind energy conversion system employs a Diode Rectifier, a Boost Chopper and a PWM inverter. The boost chopper can boost up the voltage to a certain extent only. If the wind speed is very less this system fails to work properly B. Proposed System
Wind
The boost chopper output voltage is obtained as
Where = Duty ratio of the chopper

L O A D
PM SG
DIODE RECTIFIER
BOOST CHOPPER
Z Source INVERTR
IV. Z SOURCE INVERTER In order to overcome the problems of the traditional V-source and I-source converters, this paper presents an Impedance-source (or impedance-fed) power converter (abbreviated as Z-source converter) and its control method for implementing dc-to-ac, ac-to-dc, ac-to-ac, and dc-to-dc power conversion. figure. 3 shows the general Z-Source converter structure proposed. It employs a unique impedance network (or circuit) to couple the converter main circuit to the power source, load, or another converter, for providing unique features that cannot be observed in the traditional V and I-source converters where a capacitor and inductor are used respectively. The Z-source converter overcomes the above-mentioned conceptual and theoretical barriers and limitations of the traditional V-source converter and I-source converter and provides a novel power conversion concept. In figure. 3, a two-port network that consists of a split inductor L1 and L2 and capacitors C1 and C2 connected in X shape is employed to provide an impedance source (Z-source) coupling the converter (or inverter) to the dc source, load, or another converter. The dc source or load can be either a voltage or a current source for load. Therefore, the dc source can be a battery, diode rectifier, thyristor converter, fuel cell, an inductor, a capacitor, or a combination of those. The inductance L1 and L2 can be provided through a split inductor or two separate inductor.
DIGITAL CONTROLLER
Figure .2. Wind Energy Conversion System with Z Source inverter
The proposed micro controller based control for the Z-Source inverter is expected to exhibit both buck and boost capabilities, for which a unique LC impedance network is introduced between the dc power source and inverter circuit. Thus the efficiency is increased in this system II. RECTIFIER A three-phase diode rectifier converts the AC generated output voltage, which will be varying in magnitude and also in frequency, into DC The average output voltage of the three phase diode rectifier is obtained as follows:
And the average and RMS load current are given by:
III. BOOST CHOPPER The conversion of rectified DC voltage to any specified DC voltage can be carried out employing a DC DC converter or chopper circuit
Figure. 3. General structure of the Z Source inverter
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inverter bridge is in one of the eight non shoot-through switching states
A. Operating Principle To describe the operating principle and control of the Z Source inverter in figure.5, let us briefly examine the Z Source inverter structure. In Fig. 5, the 3-phase Z-source inverter bridge has nine permissible switching states (vectors) unlike the traditional three-phase V-source inverter that has eight. The traditional three-phase V-source inverter has six active vectors when the dc voltage is impressed across the load and two zero vectors when the load terminals are shorted through either the lower or upper three devices, respectively. However, in the 3-phase Z-source inverter bridge has one extra zero state (or vector) when the load terminals are shorted through both the upper and lower devices of any one phase leg (i.e., both devices are gated on), any two phase legs, or all three phase legs. This shootthrough zero state (or vector) is forbidden in the traditional V-source inverter, because it would cause a shoot-through. We call this third zero state (vector) the shoot-through zero state (or vector), which can be generated by seven different ways: shoot through via any one phase leg, combinations of any two phase legs, and all three phase legs. The Z-source network makes the shoot-through zero state possible. This shoot through zero state provides the unique buck-boost feature to the inverter.
Figure. 6. Equivalent circuit of the Z-source inverter viewed from the dc link.
Figure. 7. Equivalent circuit of the Z-source inverter viewed from the dc link when the inverter bridge is in the shoot-through zero state.
The peak dc-link voltage across the inverter bridge is expressed as
Fig. 5. Z-source inverter.
B. Equivalent Circuit Figure.6 shows the equivalent circuit of the Z-Source inverter shown in Fig. 5 when viewed from the dc link. When viewed from the Z-Source network, the inverter bridge is equivalent to a short circuit when the inverter bridge is in the shoot-through zero state, as shown in figure.7, whereas the inverter bridge becomes an equivalent current source as shown in figure. 8 when in one of the six active states. Note that the inverter bridge can be also represented by a current source with zero value (i.e., an open circuit) when it is in one of the two traditional zero states. Therefore, figure. 8 shows the equivalent circuit of the Z-source inverter viewed from the dc link when the
Where To is the shoot through time period in seconds T1 is the non shoot thro' time period or Active state T is the Total time period in seconds
where B is the Boost factor resulting from the shoot through zero state. The dc link voltage vi is the equivalent dc link voltage of the inverter. On the other side the output peak phase voltage from the inverter can be expressed in
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where M is the Modulation Index. Vac is the output line voltage of ZSI. Using equation 6 and 7 we get
+ 4
R 1 2 Y 3 B
5 -
Figure. 10. Rectifier unit
Figure. 8. Equivalent circuit of the Z-source inverter viewed from the dc link when the inverter bridge is in one of the eight non-shoot-through switching states.
B. Boost Chopper Circuit The boost chopper circuit is a high speed on/off semiconductor switch. It is used to step up the voltage as per our requirement and to maintain a fixed DC output. The Boost Chopper circuit is shown in figure. 11.
i -
V. MATLAB SIMULATION The proposed wind energy conversion system with Boost Chopper and Z-source inverter is modeled in MATLAB SIMULINK as shown in figure. 9.
V G ate
2 I
1 ohm s 1 e -6 F
2 5 0 e -6
+O u t 3
v G oto
+In
1 e -3 H
i
R + A B C I +In Y +O ut B In -O ut B B
2
G a te
.0 0 1 o h m s
G oto1
1 e -6 F
+ + m s v v g
aA bB cC
R + Y
R
vi G o to
1 V
Three-Phas Source e
Bus R ectifier
4 -O u t
Boos C t hopper C ontrol C ircuit
ZSource Inverter
Load
In
Figure. 11. Boost Chopper circuit

i
B. Z-source inverter unit

C ontinuous
v
Meas ent urem
C ontrol s tem ys
P ulse V
figure. 9. simulation model of wind energy conversion system with boost chopper ans Z-source inverter
A. Rectifier unit The three phase output voltage which is varying in both magnitude and frequency has to be converted into DC so as to obtain the required DC output from the Boost Chopper. Here we use a diode rectifier to convert the varying AC supply into DC supply and it is given to the Boost Chopper circuit. This rectifier unit is shown in figure. 10.
The Z-source inverter (ZSI) can either act as a boost or buck inverter as per the requirement. ZSI is less affected by electro magnetic interference as the impedance source acts as a filter. Harmonic distortion is low in the case of ZSI. In ZSI misfiring of switches may be acceptable. As capacitor and inductance are used in the DC link, it act as a constant high impedance voltage source. So it overcomes all the disadvantages of V-source inverter and I-source inverter. The output from the Z-source inverter is used to supply the load. The Z-source inverter unit is shown in figure. 12.
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1.6 mH
1 + [p3]
[p1]
g g C C
[p5]
g C
+ v -
4
[vdc]
5 B
3
1.6 mF 1.6 mF
R
[p6]
g
Figure. 14 shows the Z-source inverter output voltage and it can be seen that the peak to peak output voltage is maintained constant at 650V. The same voltage level is maintained for different input voltage from 150V to 400V. VII. CONCLUSION A Wind Energy Conversion System employing a Boost Chopper and a Z-source inverter has been proposed and the corresponding simulated waveforms are verified. From the result obtain above we see that the system works efficiently for various input voltage. Similarly we can come to a conclusion that we get a constant output voltage in spite of the variation in wind speed. This system works efficiently even at very low wind speed.
[p2]
g C
[p4]
g C
1.6 mH
2 -
Figure. 12. Z-source inverter
VI. SIMULATION RESULTS The simulation results of the boost chopper output and Z-source inverter output voltage are shown in the following figures. Simulation is done for various input voltage and the output voltage of the Z-source inverter is found to be constant
VII. REFERENCES
[1]
Monica Chinchilla, Santiago Arnaltes,Juan Carlos Burgos, "Control of Permanent-Magnet Generators Applied to Variable-Speed Wind-Energy Systems connected to the Grid", IEEE Transactions on Energy Conversion, vol 21, no 1, March 2006, pp.130-135.
[2] F. Z. Peng, "Z-Source inverter," IEEE Trans. Ind. Applicat., vol. 39, pp.504-510, Mar. /Apr. 2003. [3] F. Z. Peng, M. Shen, and Z. Qian, "Maximum boost control of the Z-source inverter," IEEE Transaction on Power Electronics. vol.20, no.4, pp833-838 July 2005.
Figure. 13. Boost Chopper Output Voltage
Figure. 13 shows the Boost Chopper output voltage. This output is taken for a input voltage of 150V. It is seen that the Boost Chopper output voltage is maintained constant at 400V. The output voltage is maintained constant at 400V for various input voltage from 150V to 400V.
[4] ShigeoMorimoto,Hideaki Nakayama, Masayuki Sanada, Yoji Takeda:"Sensorless Output Maximization Control for Variable- Speed Wind Generation System using IPMSG", IEEE Transactions on Industrial Applications 2003,pp. 1464-1471. [5] Tomonobu Senjyu, Sathoshi Tamaki, Naomitusu Urasaki, Katsumi Uezato Toshihisa Funabashi, Hideki Fujita "Wind Velocity and PositionSensorless Operation for PMSG Wing Generator", Proceedings of IEEE Power Electronics Conference. Pp787-791, 2006. [6] A.B. Raju, K.Chatterjee and B.G. Femandes, "A Simple Power Point Tracker for Grid connected Variable Speed Wind Energy Conversion System with reduced Switch Count Power Converters", IEEE conference on Power Electronic specillists,2003. pp 456-462.
Figure. 14. Z-source inverter output voltage
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Multilevel Inverter fed Induction Motor Drive with DTC control

S.Kaviya , Student Member, IEEE * , P.Karuppusamy #
*PG Scholar, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, Tamil nadu, India.
# Lecturer, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, Tamil nadu, India.
E.mail- kaviyaeee@gmail.com
AbstractThis paper presents Torque Control of Induction Motor Drive using the five level Cascaded Multilevel Inverter for automotive applications. The five level multilevel inverter is used to reduce the harmonics. The total harmonic distortion is very low compared to that of classical inverter. The poor quality of voltage and current of a conventional inverter fed induction machine is due to the presence of harmonics and hence there is significant level of energy losses. It has the advantages of reduction in the torque ripple, control of sinusoidal output voltages and currents, lower switching losses and a highperformance torque and ux regulation. Simulation results for torque control induction motor drive are done using Matlab/Simulink. Index terms: Multilevel inverter, Induction motor, Direct Torque Contol(DTC). NOMENCLATURE
Electromagnetic torque and load torque of the induction machine(N-m). m The instantaneous angular velocity of the motor shaft (rad/sec) J The moment of inertia of the motor load system (kg-m2) L1, L2 ' Stator inductance and Rotor inductance. Lh Magnetizing inductance. P No. poles. 1, ' 2 Stator flux and Rotor flux. sr Angle between stator and rotor flux.
I. INTRODUCTION
T, TL
Multilevel converter technologies are receiving increased attention recently, especially for use in high power applications [1], [2]. This increased attention is probably due to the fact that the output waveforms are much improved over those of the two-level converter technologies, and that the voltage rating of the converter is increased due to the series connection of the devices. Power Electronics is playing an important role in
the torque and speed control of motor drive. Variable speed AC induction motor drives are replacing the conventional DC Drives in industries DC motors have excellent speed and torque response, they have inherent disadvantage of commutator and mechanical brushes, which undergo wear and tear with time. AC induction machines are single excited, mechanically rugged and robust, but speed and torque control of these machines are more complex and involved, compared to DC machines. Induction motors have low starting torque and the motors carry large amplitude of starting currents, star delta starting or pole changing methods were followed (Juan Dixon et al., 2006).The advent of controlled switches the speed and torque control of induction machines have become relatively easier. A voltage source inverter can run the induction by applying three phase square wave voltages to the motor stator winding (Tolbert et al., 1999). A variable frequency square wave voltage can be applied to the motor by controlling the switching frequency of the power semiconductor switches the recent advancement in power electronics has initiated to improve the level of inverter instead increasing the size of filter. The total harmonic distortion of the classical inverter is very high. The performance of the multilevel inverter is better than classical inverter. In other words the total harmonic distortion for multilevel inverter is low. Numerous industrial applications have begun to require higher power apparatus in recent years. Some medium voltage motor drives and utility applications require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly. As a result, a multilevel power converter structure has been introduced as an alternative in high power and medium voltage situations. A multilevel converter not only achieves high power ratings, but also enables the use of renewable energy sources. Renewable energy sources such as photovoltaic, wind, and fuel cells can be easily interfaced to a multilevel converter system for a high power application.
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III. INDUCTION MOTOR DRIVE
II. MULTILEVEL INVERTER TOPOLOGY
The power circuit of the Asymmetric Cascaded HBridge Inverter is illustrated in Fig. 1. The inverter is composed by the series connection of two or more Hbridge inverters fed by independent dc-sources provided by individual secondaries of a transformer or batteries. The use of asymmetric input voltages can reduce, or when properly chosen, eliminate redundant output levels, maximizing the number of different levels generated by the inverter. Therefore this topology can achieve the same output voltage quality with less number of semiconductors. This also reduces volume, costs, losses and improves reliability.
The introduction of variable-speed drive increases the automation and productivity and, in the process, efficiency. Nearly 65 percentage of the total electric energy produced is consumed by electric motors. Decreasing the energy input or increasing the efficiency of the mechanical transmission and process can reduce the energy consumption. Three-phase AC induction motors are widely used in industrial and commercial applications. They are classified either as squirrel cage or wound-rotor motors. These motors are self-starting and use no capacitor, start winding, centrifugal switch or other starting device. The simulation model of the multilevel inverter fed induction motor drive is shown fig. 2
Fig.1 Five level H-bridge multilevel inverter topology
Fig2. Simulation model of multilevel inverter fed induction motor
When cascading three level inverters like Hbridges (output levels: +Vdc, 0 and Vdc). The addition of extra cells permits to locate also the first band of high-order harmonics at higher frequencies, resulting in a twofold reduction effect in the torque ripple. The output voltage of each phase is shown in Equation (1)
VAN =VA1 +VA2
Torque and flux references can be calculated by using the induction motor parameters is shown in the block diagram.
(1)
Commercial versions of the H-bridge multilevel inverter use the phase-shift multilevel pulse width modulation (PWM) method to generate an output waveform with multiple levels [7]. This modulation strategy is easy to implement and operates the power switches with constant switching frequency, but it has higher harmonic content in comparison to other strategies such as phase-disposition PWM and SPM[8].
Fig3. Reference signal calculation block
The induction motor parameters are calculated by the equivalent circuit parameters. It is assumed that the nominal voltage V, power P, slip s, efficiency , power factor cos and the locked rotor current Is are known. The power is the useful electrical power, that is, the
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power consumed in the load resistance R2 (1-s) / s of the equivalent circuit. The efficiency is the electrical efficiency, i.e. the useful electrical power divided by the total power taken by the motor. V I cos = I
2
3 L T= *p* h 1'2*sinsr 2 L1L'2

T -TL =J d m dJ + m dt dt
(4)
R1+ (P/3)/ (1-s)
(2) (3)
2
(5)
R1 = (V cos / I) (1 / (1-s)) Ra = R1 + R X3 Where R = R2/s

2
/ [R2 + (X2 + X3) ]
(4)
The torque of the induction motor can be estimated using the above equations
IV. DTC CONTROL METHOD
Xa= X1+[R2 X3 + X2 X3 (X2 + X3)]/[R2 +(X2 + X3) ](5) R (X3 + X2 Xa) = (X2 + X3) (Ra R1) where R = R2/s
2 2
(6)
X3 =(Ra R1) (X2+X3)/(X2+X3-Xa)+ (X2+X3) (X2+X3-Xa) (7) The presented control method, such as all DTC methods, is based on the control of the magnitude and phase of the stator flux space phasor through the proper choice of the stator voltage space phasor.under the assumption of constant magnitude of stator and rotor fluxes, it is clear that a fast torque change can be achieved with a change of angle between both fluxes. Since the sample time of the controller is smaller than the rotor time constant, the variation in the trajectory of the rotor flux during the sample time interval can be neglected. Hence, the stator flux space phasor is the main quantity influencing torque development. For the modeling of the induction machine, the following assumptions were made. The neutral point is not connected. There are no eddy currents or core losses in the stator and rotor. Only the fundamental wave of the air-gap field is considered for the calculation of the inductances.
Direct torque control (DTC) is one method used in variable frequency drives to control the torque (and thus finally the speed) of three-phase AC electric motors. This involves calculating an estimate of the motor's magnetic flux and torque based on the measured voltage and current of the motor. DTC is an alternative method to flux-oriented control. The basic principle is the selection of the electromagnetic torque and stator flux references by choosing the appropriate inverter state. Several advantages may be considered, namely, nearly sinusoidal stator flux and current waveforms, higher robustness regarding motor parameter variations except the stator winding resistance, higher torque dynamics, and easier flux and speed estimator implementation, since coordinate transformation is not required. However, in the standard version, important torque ripple and high switching losses are obtained due to the use of hysteresis bands and the small number of applicable voltage vectors. Moreover, the converter switching frequency is inherently variable and very dependent on the torque and shaft speed. If continuous operation at low speeds including zero frequency operation is required, a speed or position sensor can be added to the DTC system. With the sensor, high accuracy of the torque and speed control can be maintained in the whole speed range.This produces torque harmonics with variable frequencies and acoustic noise with disturbance intensities that are very dependent on these mechanical variables and particularly grating at low speed. Torque and flux can be changed very fast by changing the references High efficiency & low losses - switching losses are minimized because the transistors are switched only when it is needed to keep torque and flux within their hysteresis bands. The step response has no overshoot No coordinate transforms are needed, all calculations are done in stationary coordinate system
Mathematical equations to calculation torque and flux by using currents shown in the equations below,
1 =L1i1 +L h i'2
2=L h i1 +L'2 i '2
(2) (3)

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The sectors can be identified using space phasors. The nearest stator voltage can be calculated using the sectors as shown in the vector diagram. Vector diagram for the sector 2 is shown in the fig 5. Voltage selection can be made by using sectors and the sign of the reference voltage the look up table shown in Table 1.
TABLE 1. VOLTAGE VECTOR SELECTION LOOKUP TABLE
No separate modulator is needed, the hysteresis control defines the switch control signals directly There are no PI current controllers. Thus no tuning of the control is required The switching frequency of the transistors is not constant. However, by controlling the width of the tolerance bands the average switching frequency can be kept roughly at its reference value. This also keeps the current and torque ripple small. The torque and current ripple are of the same magnitude than with vector controlled drives with the same switching frequency. Flux and current distortion caused by sector changes of the flux position. High dynamic performance, even at zero speed. Variable switching frequency and harmonic content in flux and current waveforms depend on flux and torque hysteresis bands and the operative point.
sector (+,+) 1 2 3 4 5 6 V2 V3 V4 V5 V6 V1
k k Sign(e ,e ) T (+,-) (-,+)
(-,-) V5 V6 V1 V2 V3 V4
V6 V1 V2 V3 V4 V5
V3 V4 V5 V6 V7 V8
V.
SIMULATION RESULTS AND DISCUSSIONS
The simulation of multilevel inverter fed induction motor drive is simulated in Matlab\simulink software. The results for closed loop control with three phase induction motor torque control is discussed in this paper.
Fig4. Vector diagram
Fig6. Line to line voltage of the multilevel inverter fed induction motor drive Fig5. Voltage selection in sector 2
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Fig10. Speed of the Induction Motor Fig7. Line currents
The motor runs nearly a constant speed during the control of the Induction motor fed by a multilevel inverter. The stator current of the induction motor is sinusoidal in nature.
Fig8. THD wave for the multilevel inverter
Fig11. stator current of the induction motor
VI. CONCLUSION
Fig9. Torque waveform of the induction motor
An application of high-performance strategy for induction machines in multilevel inverter can be achieved. A cascaded five level multilevel inverter was modeled. By using the cascaded multilevel inverter torque of the induction motor can be controlled. It overcomes the drawbacks of the traditional voltage source inverter. It has the advantages of reduction in the torque ripple, control of sinusoidal output voltages and currents, lower switching losses and a high-performance torque and ux regulation. The torque ripple can be reduced when compared to voltage source inverter fed induction motor. By using the MATLAB/SIMULINK software the torque control of induction motor can be achieved.
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VII. REFERENCES
[1] L. M. Tolbert and F. Z. Peng, Multilevel converters for large electric drives, in Proc. IEEE APEC98, vol. 2, 1998, pp. 530536. [2] Y. Chen , B. Mwinyiwiwa , Z. Wolanski , and B.-T. OoI , Regulating and equalizing dc capacitance voltages in multilevel statcom, IEEE Transations on Power Delivery, vol. 12, pp. 901907, Apr. 1997.
[3] Farid Khoucha, Soumia Mouna Lagoun, Khoudir Marouani, and Mohamed El Hachemi Benbouzid, Hybrid Cascaded HBridge Multilevel-Inverter Induction-Motor-Drive Direct Torque Control for Automotive Applications, IEEE Transactions On Industrial Electronics, Vol. 57, MARCH 2010. [4] Jos Rodrguez, Jorge Pontt, Samir Kouro, and Pablo Correa Direct Torque Control With Imposed Switching Frequency in an 11-Level Cascaded Inverter IEEE Transactions On Industrial Electronics, Vol. 51, No. 4, August 2004. [5] Miguel F. Escalante, Jean-Claude Vannier,and Amir Arzande,( 2002) Flying Capacitor Multilevel Inverters and DTC Motor Drive Applications IEEE Transactions on Industrial Electronics. [6] Jos Rodriguez, Jorge Pontt, Samir Koura, and Pablo Correa Direct Torque Control With Imposed Switching Frequency in an 11-Level Cascaded Inverter IEEE Transactions on Industrial Electronics.
[7] P. W. Hammond, Drive and power supply with phase shifted carriers,U.S. Patent 6 411 530, Jun. 25, 2000. [8] B. P. McGrath, D. G. Holmes, and T. A. Lipo, Optimised space vector switching sequences for mutilevel inverters, in Proc. IEEE APEC, Anaheim, CA, Mar. 48, 2001, vol. 2, pp. 11231129.
P.Karuppusamy received his B.E degree in Electrical & Electronics Engineering from the affiliated college of Anna University Chennai and M.E Power Electronics and Drives from Government College of Technology Coimbatore affiliated to Anna University Chennai. Currently he is working as a Lecturer in Bannari Amman Institute of Technology, sathyamangalam, Erode, Tamilnadu. Now pursuing his PhD in Anna University of Technology, Coimbatore. His field of interest includes machines and power electronics.
[9] Jos Rodriguez,, Jorge Pontt,, Samir Koura, and Pablo Correa Direct Torque Control With Imposed Switching Frequency in an 11-Level Cascaded Inverter IEEE Transactions On Industrial Electronics. [10] Martin Janben and Andreas Steimel (2002) Direct Self Control With Minimum Torque Ripple and High Dynamics for a Double Three-Level GTO Inverter Drive IEEE Transactions On Industrial Electronics 49:1065-1071. [11]Dwayne Telford, Matthew W.Dunnigan(2003), Adaptive High Bandwidth Current Control for Induction Machines IEEE TRANSACTIONS ON POWER ELECTRONICS 18: 527-538. VIII. BIOGRAPHIES
S.Kaviya received her B.E degree in Electrical & Electronics Engineering from Sasurie College of Engineering affiliated to Anna University Chennai in the year 2008. Currently she is doing M.E degree in Power Electronics and Drives in Bannari Amman Institute of Technology affiliated to Anna University of Technology, Coimbatore. Her field of interest includes drives and power electronics.
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NEURAL NETWORK BASED TORQUE RIPPLE MINIMIZTION OF BLDC MOTOR

1
1
M. Raja Nandakumar, 2S. Nellaiyappan, 3R. Shanmuga sundaram, Member, IEEE
Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, mnandakumar87@gmail.com 2 Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, India, nellaiyappans@gmail.com 3 Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, rss_is@yahoo.com
Abstract This paper presents the implementation of an Artificial Neural Network (ANN) controller scheme for Permanent Magnet Brushless DC (BLDC) motor drive to minimize torque ripple. Artificial neural network has the ability of self-learning and self-regulatory. This paper proposes a technique for torque ripple minimization of BLDC motor using Neural Network controller. In this proposed torque ripple minimization technique, current of the outgoing phase is chopped in a controlled manner to extend the commutation period. Here the comparison of conventional control and non ideal back EMF method with the neural network controller shows that the ANN controller reduces the torque ripples better than conventional control and non ideal back EMF method. Simulation results are presented to validate the effectiveness of the proposed technique. KeywordsArtificial Neural Network (ANN), Brushless dc motor (BLDC), Electromotive force (EMF), Torque Ripple. I. INTRODUCTION Permanent Magnet Brushless DC (BLDC) motors are used in many applications such as servo drives, computer peripherals and electrical vehicles due to their high power output per frame size, high efficiency and easier control. Torque ripple in brushless dc motors is mainly due to the fluctuations of the field distribution and the armature MMF which depends on the motor structure. At high speeds, torque ripple is usually filtered by system inertia. However at low speeds torque ripple produces some effects that may not be tolerable in applications such as positioning and robotics [1]. An idealized brushless DC motor has a trapezoidal back electromotive force (EMF) waveform. Zero torque ripples is produced when the motor is fed by rectangular current. However for practical reasons like non-uniformity of magnetic material and practical design it is not easy to get the desired trapezoidal wave. Therefore torque ripple appears even though rectangular current is fed in conventional control. Since the motor windings are inductive, the current controller does not able to produce the required di/dt in the commutation period. Torque ripple can create undesirable noise and vibration in speed applications, and can cause inaccuracies in motion control [2]. A new method to optimize current waveform based
on d-q frame, which results in minimum torque ripple and maximum efficiency of BLDC motor drives is discussed in [3] and [4]. Torque estimation method is discussed in [5]. A torque control method which required phase terminal voltage is calculated from the torque controller in two phase conducting period and in the commutation period is presented in [6]. The application of Direct Torque Control (DTC) to BLDC motor drives to achieve instantaneous torque control and reduced torque ripple is described in [7]. In this method, a sliding mode observer is used to estimate the non-ideal back EMF waveform. Furthermore, commutation torque ripple minimization techniques are discussed in [8] and [9]. The compensation techniques is based on the strategy that the current slopes of the incoming and the outgoing phases in the commutation period is equalized, this compensation technique neglect the influence of non-ideal back EMF waveforms. In recent years ANN has been applied to a wide range of dynamic system applications. Advantages of ANN controllers over the conventional method is robustness, parallel distributed structure, and ability to learn as well as capability of handles nonlinear situations. These advantages support the ANN in playing a major role in solving uncertainty problems in motor drive systems like stator resistance variation and DC voltage measuring operations in existence of high switching surges which leads to uncertainty in torque and flux estimation which in turn leads to torque ripple and in worst case it may lead to generation of breaking torque. The ANN based speed controller and speed estimator of Permanent Magnet Synchronous Motor drive is presented in [10]. The numerical description of Torque ripples and the control scheme to reduce that torque ripples is shown in [11]. Sensorless control of brushless dc motors at low speed using Neural Network is shown in [12]. The torque model and inverse torque model are developed based on Back Propagation Neural Network of Levenberg-Marquardt algorithm is presented in [13]. This paper proposes a method of minimization of torque ripple of the BLDC motor using ANN. The duty cycle of the pulses used to operate the inverter switches is obtained from the neural network controller during the commutation period. Simulation results shows that compared with conventional control and Non-ideal back EMF method, there is an apparent reduction in torque ripple.
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V 2 Dn 1 eb ec dic dc dt 2L 2L T s
(5)
II. NON IDEAL BACK EMF METHOD A BLDC motor is fed by a three-phase voltage source inverter as shown in Fig.1, where R, L, e, I, V, Vn and V0 represent the armature resistance, inductance, back EMF, terminal voltage, phase current and neutral voltage respectively. The torque equation of a brushless dc motor can be expressed as,
The back emf ec and eb maintained constant during sampling period, after the sampling period T s, the current of phase C can be obtained from (5) as,
Te
ea ia eb ib ec ic m
(1)
ic k 1
where
ic k is the initial value of ic in the kth sampling

Vdc k 1 2Dn k Ts 2L ec k eb k Ts 2L ib k
Vdc k 2Dn k 1 Ts eb k ec k Ts 2L 2L ic k
(6)
period? Similarly the expression for phase B can be obtained from the same deducing process.
ib k 1
(7)
Fig.1 Configuration of BLDC motor fed with VSI In two phase conduction mode of the inverter, there are six combination of stator excitation per cycle and each combination lasts for 60 electrical degrees. It is called as normal conduction period. To produce the maximum torque, commutation should be performed for every 60 electrical degrees. A. Normal Conduction Period During normal conduction period, only two phases excited. Consider the particular combination; phase C and phase B are conducting where current flows through phase C and leaves out phase B. Fig.1 shows switches SW5 and SW6 are conducting. The phase voltage equation during normal conduction period including switching function can be expressed as,
From equation (6) and (7), the torque equation can obtained as,
Te k 1 Te k
Vdc k 2 Dn k 1 ec k eb k Ts 2m k L ec k eb k Ts 2m k L
2
(8)
where
Te k
e i e i is the feedback
b k b k c k c k
m k
torque from last sampling period? If
Te k 1 = Tref , then
the duty cycle of the switches SW5 and SW6 can be obtained as,
When ic = -ib, the voltage between neutrals of the motor and inverter can be expressed as,
Vdc di ic R L c ec Vno 2 dt
(2)
Dn k
Tref Te k m k L ec k eb k T 1 2U dc k 2 Vdc k ec k eb k Ts
(9)
Vno
ec eb
2
Dn k is calculated using dc supply voltage, feedback torque

and actual back-EMFs. B. Commutation Period To produce maximum torque any two switches in inverter is commutated occurred after every 60 electrical degrees. All three phases conduct during the commutation period due to the armature inductance. Consider the particular commutation process, the current transfer from phase C to phase A. This commutation is performed by switching off SW5 and switching on SW1. During this transfer, the current ia called incoming phase current increases through the switch SW1, the current ic called outgoing phase current decreases gradually
(3)
The armature resistance of the BLDC motor is relatively small and it is neglected. Then the derivative current of phase C is expressed as,
Assume duty cycle of SW5 and SW6 is Dn; the sampling period of torque controller is Ts. The above equation (4) can be rearranged as (5) using the state-space averaging technique mentioned in literature [12]
dic Vdc eb ec dt 2 L 2L
(4)
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where
through the anti-parallel diode D2, and the current ib called uncommutated phase current is not involved in the commutation. Three phase voltage equations during the commutation period can be written as,
f ea k , eb k , ec k ea k eb k
Vdc di Ria L a ea Vno 2 dt V di dc Rib L b eb Vno 2 dt
e e e e
2 b k c k 2 c k a k
If (10)
Te k 1 = Tref , then the duty cycle of the switches SW1

f eak ,eb k ,ec k Tref Te k mk L Vdck ea k eb k T s 3 dc k ea k eb k V (17) 2ebk ea k ec k T s + 3 eak eb k
and SW6 can be obtained as follows
The voltage between neutrals of the motor and inverter can be expressed as,
Dck
Vno
The current slope of phase A is expressed as,
Vdc ea eb ec 6 3
(11)
dia 2Vdc eb ec 2ea dt 3L 3L
Dc k is calculated using dc supply voltage, feedback torque

(12) and actual back-EMF. In real case even though the calculated duty cycle reaches 100%, the slope of the incoming phase current may be slower down due to the finite dc bus supply voltage. Since the slope of the outgoing phase current ic is fast, a current dip produces in the un-commutated faze current ib, this leads to commutation torque ripple. C. Considering Finite DC Bus Supply Voltage Even though the calculated duty cycle
Consider the duty cycle of switches SW1 and SW6 is Dc .
The average current slope of phase A is derived as,
Vdc 3Dc 1 eb ec 2 ea dia dt 3L 3L T s
(13)
Solving the above differential (13), the current of phase A can be derived as,
Dc k reaches 100%,
Ts Vdc k 3Dc k 1 eb k ia k ia k 1 3L ec k 2ea k

The phase currents B and C can be obtained with same deducing process.
(14)
the torque feedback cannot follow the torque reference, the slope of the outgoing phase current can be slowed down by again switching on SW5 to compensate the current dip in the un-commutated phase current, so as to minimize the commutation torque ripple.
Ts Vdc k 2 3Dc k eb k ib k 3L ec k 2ea k Vdc k Ts eb k ec k 2ea k Ts ic k 1 (15) 3L 3L ic k ib k 1

By combining the equation (14) and (15), the torque equation can be expressed as,
Vdc di Ria L a ea Vno 2 dt Vdc di Rib L b eb Vno 2 dt
(18)
The voltage between neutrals of the motor and inverter can be expressed as,
Vno
Vdc ea eb ec 6 3
(19)
The current slope of phase A is expressed as,
Vdc k Ts 3Dc k ea k eb k ea k Te k 1 3m k L ec k 2eb k f ea k , eb k , ec k Ts 3m k L
dia Vdc eb ec 2ea dt 3L 3L
(20)
(16)
Consider the duty cycle of switches SW5 is D0 . The
average slope of phase current A can be obtained as,
Te k
101
(21) commutated phase during the commutation period is reduced. Therefore the commutation torque ripple caused by finite dc supply voltage is reduced.
V 2 D0 eb ec 2 ea dia dc dt 3L 3L T s
Phase current of A can be obtained by solving the above differential equation (21) and expressed as,
ia k 1
Ts 3L
eb k ec k 2ea k Vdc k 2 D0 k
ia k
Similarly the other two phase currents are calculated as,
ib k 1 ic k 1
e e 2eb k Ts a k c k 3L Vdc k 1 D0 k e e 2ec k T a k b k s 3L Vdc k 2 D0 k 1
ib k ic k
(22)
Fig.2 Block diagram of BLDC motor control System III. NEURAL NETWORK The proposed ANN controller contains three layers namely input layer, hidden layer and output layer. The inputs of the proposed ANN are the reference torque, three phase back EMFs and speed of the motor. The corresponding output target is duty cycle of inverter switching devices. After the inputs and output are formulated, the next step is to incorporate the hidden layers. The input and output of the ANN controller can be determined from the knowledge of Non ideal back EMF method.
From the above three equations the torque can be derived as,
Te k 1
Vdc k Ts 3Dc k ea k eb k ea k 3m k L ec k 2eb k f ea k , eb k , ec k Ts 3m k L
(23)
Te k
If
Te k 1 = Tref , then the duty cycle of the switch SW5

Tref Te k m k L Vdc k 2ec k ea k eb k Ts 2ea k eb k ec k - 2ec k eb k ea k f ea k , eb k , ec k
(24)
can be obtained as,
D0 k
Vdc k 2ec k eb k ea k
The duty cycle
D0 is used to slow down the slope of the
outgoing phase current ic, therefore the current dip in the un-
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Fig.3 Multilayer feed-forward artificial neural network with one hidden layer. For this present paper, the structure of one hidden layer having eight neurons gives satisfactory results. Once a design of the ANN structure is done, the next step is to train the network, here normal feed forward network is used because it is simple, easy to implement and any number of inputs can be used. IV. SIMULATION RESULTS To verify the feasibility of this method simulation is carried out. Simulation of this paper is done in MATLAB and the output waveforms are shown for conventional control, non-ideal back EMF method and neural network method. The parameters of the BLDC motor are shown in the appendix. A) Conventional Control of BLDC Motor
B) Torque Control by Non-Ideal Back EMF Method
Fig.6 Phase currents in Non-Ideal Back EMF Method [50% load is applied at 0.1sec]
Fig.4 Electromagnetic Torque in conventional method [50% load applied at 0.1sec] Fig.7 Motor speed in Non-Ideal Back EMF Method [50% load is applied at 0.1sec]
Fig.5 Enlarged Electromagnetic Torque waveform
Fig.8 Electromagnetic Torque in Non-Ideal Back EMF Method [50% load is applied at 0.1sec]
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Fig.9 Enlarged Electromagnetic Torque waveform
C) Torque Control by Neural Network Method
Fig.12 Electromagnetic Torque in Neural Network Method [50% load is applied at 0.1sec]
Fig.10 Phase currents in Neural Network Method [50% load is applied at 0.1sec] Fig.13 Enlarged Electromagnetic Torque waveform Fig.4 shows the torque of the motor with 50% of rated torque is applied to the motor at 0.1sec. Fig.5 is the enlarged torque waveform, it is clear that torque ripple of 26.2% rated torque appears in conventional control. Fig.6 shows the three phase current waveforms of BLDC motor with non-ideal back EMF method control when 50% of rated torque is applied to the motor at 0.1sec. Similarly Fig.7 and Fig.8 shows the speed and torque of the motor with 50% of rated torque is applied to the motor at 0.1sec. Fig.9 is the enlarged torque waveform, it is clear that torque ripple of 13.1% rated torque appears in non-ideal back EMF method. Fig.10 shows the three phase current waveforms of BLDC motor with ANN controller when 50% of rated torque is applied to the motor at 0.1sec. Similarly Fig.11 and Fig.12 shows the speed and torque of the motor with 50% of rated torque is applied to the motor at 0.1sec. Fig.13 is the enlarged torque waveform, it is clear that torque ripple of 11.9% rated torque appears in ANN controller method. Therefore by ANN controller method torque ripple has reduced to 11.9% which is less by 14.3% from conventional control and 1.2% from Non-ideal back EMF method.
Fig.11 Motor speed in Neural Network Method [50% load is applied at 0.1sec]
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current sensor, IEEE Trans.Power Electron., vol. 19, no. 2, pp. 312319, Mar. 2004. D. K. Kim, K. W. Lee, and B. I. Kwon, Commutation torque ripple reduction in a position sensorless brushless dc motor drive, IEEE Trans. Power Electron., vol. 21, no. 6, pp. 17621768, Nov. 2006. Prerna Gaur, Bhim singh, A.P.Mittal,Artificial Neural Network based Controller and Speed Estimation of Permanent Magnet Synchronous Motor, proceedings of IEEE conference, 2008 Zhang Xiaodong , Wang Jiang and Li Huiyan, Torque Ripple Minimization in PM Synchronous Motors based on Back stepping Neural Network, Proceedings of the 5'World Congress on Intelligent Control and Automation, June 15-19. 2004, Hangzhou, P.R. China, pp. 4422-4426 Chang-liang xia, wei chen, Sensorless Control Of Brushless Dc Motors At Low Speed Using Neural Networks Proceedings of the Fourth International Conference on Machine Learning and Cybernetics, Guangzhou, 18-21 August 2005. Yan cai, Chao Gao, Torque Ripple Minimization of Switched Reluctance Motor based on BPN Neural Network 2007 Second IEEE Conference on Industrial Electronics and Applications
METHOD Conventional Method Non ideal Back EMF Method Neural Network Method
TORQUE RIPPLE IN % 26.2 13.1 11.9
[9]
V. CONCLUSION A torque control method is proposed in this paper to reduce torque ripple of BLDC motors using non-ideal back EMF waveforms. Thus the ripple in output torque is considerably reduced as compared to the conventional control. This reduced torque ripple makes the motor suitable in applications such as Position Sensing and Robotics. The reduced ripples in torque also help in eliminating undesirable noise and inaccuracies in motion control. APPENDIX PARAMETERS OF THE BLDC MOTOR Rated power 175W Rated voltage 36V Number of poles 4 Rated speed 4000 rpm Connection Star Resistance/phase 0.87 ohm Inductance/phase 1.5 mH REFERENCES [1] J. Y. Hung and Z. Ding, Design of currents to reduce torque ripple in brushless permanent magnet motors, in Proc. IEE, Jul., vol. 140, pp. 260266, no.4, July 1993. [2] J. Y. Hung and Z. Ding, Design of currents to reduce torque ripple in brushless permanent magnet motors, in Proc. IEE, Jul., vol. 140, pp. 260266, no.4, July 1993. [3] S. J. Park, H. W. Park, M. H. Lee, and F. Harashima, A new approach for minimum-torque-ripple maximumefficiency control of BLDC motor, IEEE Trans. Ind. Electron., vol. 47, no. 1, pp. 109114, Feb.2000. [4] H. W. Park, S. J. Park, Y. W. Lee, S. I. Hong, and C. U. Kim, Reference frame approach for torque ripple minimization of bldcm over wide speed range including cogging torque, in Proc. IEEE ISIE, 2001, pp.637642. [5] F. Colamartino, C. Marchand, and A. Razek, Considerations of no sinusoidal field distribution in a permanent magnet synchronous motor control, in Proc. IEE PEVSD, 1994, pp. 508513. [6] S. J. Kang and S. K. Sul, Direct torque control of brushless dc motor with non-ideal trapezoidal backEMF, IEEE Trans. Power Electron., vol. 10, no. 6, pp. 796802, Nov. 1995. [7] Y. Liu, Z. Q. Zhu, and D. Howe, Direct torque control of brushless dc drives with reduced torque ripple, IEEE Trans. Ind. Appl., vol. 41, no. 2, pp. 599608, Mar./Apr. 2005 [8] J. H. Song and I. Choy, Commutation torque ripple reduction in brushless dc motor drives using a single dc
[10]
[11]
[12]
[13]
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NEURO FUZZY BASED SPEED CONTROL OF DC MOTOR USING WAVELET TRANSFORM COMPARISON WITH PID- PARTICAL SWARM OPTIMISATION STRATEGY
*Sourabh Kumar Jain M.E.(control system) Jabalpur Engg. College Jabalpur Prof. Hemant Amhia Department of Electrical Engg Jabalpur Engg college jabalpur
Abstract This paper presents an application of wavelet transform comparison with pid pso and neuro fuzzy control for DC motor speed optimized with swarm collective intelligence. First, the controller is designed according to Fuzzy rules such that the systems are fundamentally robust. Secondly, an adaptive Neuro-Fuzzy controller of the DC motor speed is then designed and simulated; the ANFIS has the advantage of expert knowledge of the Fuzzy inference system and the learning capability of neural networks. Finally, the ANFIS is optimized bySwarm Intelligence. an intelligent controller of DC Motor drive is designed using particle swarm optimization (PSO) methodfor formative the optimal proportionalintegral-derivative (PID) controller Tuning parameters. The DC Motor Scheduling PIDPSO controller is modeled in MATLAB environment. Comparing with fuzzy logic controller using PSO intelligent algorithms, the planned method is more proficient in improving the speed loop response stability, the steady state error is reduced, the rising time is perfected and the disturbances do not affect the performances of driving motor with
no overtaking. controller of DC Motor drive is designed using control strategy based on the multi-resolution decomposition of error signal using Wavelet Transforms method. The proposed approach has superior feature, including easy implementation, stable convergence characteristics and very good computational performances efficiency. Comparing with fuzzy logic controller using multi-resolution decomposition of error signal, the planned method is more proficient in improving the speed loop response stability, The wavelet decomposition, which represents the error signal at different scales, enables us to compensate for these uncertainties in the control design. Wavelets have a tremendous impact on a number of modern disciplines, but they have been mostly used for signal and image analysis. Wavelets possess two properties that make them especially valuable for data analysis: they reveal local properties of the data and they allow multiscale analysis. Their locality is useful for applications that require online response to changes, such as controlling a process. Index TermsDC machines, analytic wavelet transform, direct torque control, speed estimation, short-time Fourier transform. Wavelet Controller (WC ) , neuro fuzzy logic controller, DC Motor drive, neural wavelet networks (NWN),
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Swarm collective intelligence, ANFIS controller using PSO. Particle Swarm Optimization Strategy, Scheduling PIDPSO Controller. 1.INTRODUCTION In spite of the development of power electronics resources, the direct current machine became more and more useful. Nowadays their uses isnt limited in the car Applications (electrics vehicle), in applications of weak power using battery system (motor of toy) or for the electric traction in the multi-machine systems too. The speed of DC motor can be adjusted to a great extent as to provide controllability easy and high performance . The controllers of the speed that are conceived for goal to control the speed of DC motor to execute one variety of tasks, is of several conventional and numeric controller types, the controllers can be: PID Controller, Fuzzy Logic Controller; or the combination between them: Fuzzy-Neural Networks, Fuzzy-Genetic Algorithm, Fuzzy- Ants Colony, Fuzzy-Swarm.than we are using wavelet transform method. . In a similar manner a (WC) decomposes the error signal into its high, low and intermediate frequency components, using the multi-resolution decomposition property of the wavelets discussed in Section 2. Each of these components are scaled by their respective gains, and then added together to generate the control signal u. Unlike a PID controller, which has three tuning parameters (gains) and WC can have two or more parameters based on the level of decomposition of the error signal. The performance of speed estimators depends on the accuracy of the machine model and parameter estimator. Observers for speed estimation have a relatively long delay time
that can limit speed detection during a transient. The short-time Fourier transform (STFT) is a practical tool to measure the frequency variations in time. The timefrequency information is contained in plane boxes called atoms, defined by the spread in time and frequency that contain enough energy density to be useful in signal processing.
Fig. 1. Heisenberg boxes for STFT using the window g(t).
Wavelet analysis is a more general transformation and is also based on internal products of functions. However, in this case the concept of scale replaces the frequency variable of theFourier transform. Although the Heisenberg atom area is not smaller than in the STFT with a Gaussian window, the time or frequency resolution can be conveniently changed using different scales, increasing one variable and decreasing the other (equal area atoms). Wavelet analysis has been applied to reduce torque ripple in DTC drives. There are several conventional
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and numeric controller types intended for controling the DC motor speed at its executing various tasks: PID Controller, Fuzzy Logic Controller; or the combination between them: PID-Particle Swarm Optimization, PID-Neural Networks, PIDGenetic Algorithm, PID-Ants Colony Optimization and the optimal Fuzzy Logic controller using the different strategy. PID controllers are widely used in industrial plants because it is simple and robust. Industrial processes are subjected to variation in parameters and parameter perturbations, which when significant makes the system unstable. So the control engineers are on look for automatic tuning procedures. 2. REALIZATION OF A PID-PSO CONTROLLER TUNING OPTIMAL PARAMETERS Fitness Function The general equation of PID controller is U(t)=kp x e(t)+1/T iz e(t)dt+T d de(t)/dt where: Kp = proportional gain; Ti = integral time; Td= derivative time. The variable e(t) represents the tracking error which is the difference between the desired input value and the actual output. This error signal will be sent to the PID controller and the controller computes both the derivative and the integral of this error signal. The signal U(t) from the controller is now equal to the proportional gain (Kp) times the magnitude of the error plus the integral gain (Ki) times the integral of the error plus the derivative gain (Kd) times the derivative of the error . In PID controller design methods, the most common performance criteria are integrated absolute error (IAE), the integrated of time weight square error (ITSE) and integrated of squared error (ISE) that can be evaluated analytically in the frequency domain . These
three integral performance criteria in the frequency domain have their own advantage and disadvantages. For example, disadvantage of the IAE and ISE criteria is that its minimization can result in a response with relatively small overshoot but a long settling time because the ISE performance criterion weights all errors equally independent of time.
3.MODEL OF DC MOTOR DC machines are characterized by their versatility. By means of various combinations of shunt-, series-, and separately-excited field windings they can be designed to display a wide variety of volt-ampere or speed-torque characteristics for both dynamic and steady-state operation. Because of the ease with which they can be controlled systems of DC machines have been frequently used in many applications requiring a wide range of motor speeds and a precise output motor control, In this paper, the separated excitation DC motor model is chosen according to his good electrical and mechanical performances more than other DC motor models. The DC motor is driven by applied voltage. Figure 1 show the equivalent circuit of DC motor withseparate excitation. 4. WAVELETS AND MULTIRESOLUTION DECOMPOSITION Multi-resolution analysis is a convenient framework for hierarchical representation of functions or signals on different scales. The basic idea of multiresolution analysis is to represent a function as a limit of successive approximations.Each of these successive approximations is a smoother version of the original function with more and more of the finer details added. Wavelets are
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terminating basis vectors used to decompose signals into a set of coefficients.
and sufficiently cover the time-frequency region occupied by a given target. Simultaneously, the
5. WAVELETS NETWORK The origin of wavelet networks can be traced back to the work by Daugman (1988) in which Gabor wavelets were used for image classification. Wavelet networks have become popular after the work by Pati (1991, 1992), Zhang (1992), and Szu (1992). Wavelet networks were introduced as a special feed-forward neural network. Zhang applied wavelet networks to the problem of controlling a robot arm. As mother wavelet, they use the following function
network parameters are updated to preserve the network topology and take advantage of the later process. In the second process, the approximations of instantaneous errors are minimized using an adaptation technique The
based on the LMS algorithms. parameter of the initialized
network is
updated using the steepest gradient-descent method of minimization. Each hidden unit has a square window in the time-frequency plane. The optimization rule is only applied to the hidden units where the selected point falls into their windows. Therefore, the learning cost can be reduced . 6.EXPERIMENTAL RESULTS The dc motor is started without load, using 3.0 Nm as the reference torque and 0.6 Wb as the flux reference. After the acceleration process, the torque is not maintained at its reference value; the DTC algorithm can only adjust the stator flux when the final speed is reached. Fig.3 shows the electric torque during the no-load start up of the induction motor at constant torque and flux ( 0.0 t 1.0 s ). Fig.4 shows the space vector diagram of the stator flux under the same condition. An optical incremental encoder with 1024 ppt is coupled to the motor shaft to perform a direct measure of the angular speed. The DTC algorithm reads the incremental count each 10 ms and calculates
Where a is dilation (i.e. a>0) and b is translation. The wave-net algorithms consist of two processes: the self-construction of networks and the minimization of error. In the first process, the network structures
applied for representation are determined by using wavelet analysis. The network
gradually recruits hidden units to effectively
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the speed. Fig.5 shows that the angular speed obtained by the encoder. Observe that the speed increase is not linear, even though the average torque during this time is constant. This is due to the non-linearity of the mechanical load in the low speed range (static and dynamic friction). In the present work, the intelligent controller based on ANFIS-Swarm optimizationgive a good agreement with the step reference speed. In the Adaptive Neuro-Fuzzy (ANFIS) DC motor control, the optimization of membership functions became very necessary, its important shown in the minimal rising time of speed response, so the membership functions are adjusted in optimal values to give a steady state error speed value equal zero.
Fig.. Instantaneous electromagnetic torque during start up with a DTC drive (constant torque and flux references).
Figure . The optimal membership functions ANFIS with PSO In Fig. shows the current in one phase during the start up. The stator current has some harmonic components related to the inverter operation (variable frequency commutation), and others given by the slot harmonics.
Fig.4. Space vector of the stator flux during start up with a DTC drive (constant torque and flux references).
7.CONCLUSION In this paper, the optimal ANFIS controller is designed using Particle Swarm Optimization algorithms. The speed of a DC Motor drive is controlled by means of three different controllers. By comparison with
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Fuzzy-PSO controller, it shows that this method can improve the dynamic performance of the system in a better way. The wavelet controller is the best which presented satisfactory performances and possesses good robustness (no overshoot, minimal rise time, Steady state error = 0). The major drawback of the fuzzy controller presents an insufficient analytical technique design. That we chose with the use of the Neural Networks andParticle Swarm Optimization for the optimization of this controller in order to control DC motor speed. Finally, the proposed controller (wavelet Controller) gives a very good resultsand possesses good robustness. the wavelet controller gains have a physical relationship with the control system performance characteristics, which makes the tuning very easy. The wavelet decomposition, which represents the error signal at different scales, enables us to compensate for uncertainties in plant in the control design. Implementation of the wavelet controller in hardware is in progress.
4. Ungarala S. and B. R. Bakshi, Multiscale Bayesian Estimation and Data Rectification, Wavelets in Signal and Image Processing, A. Petrosian and F. Meyer, eds., Kluwer Academic Publishers, New York, NY, In print, (2001). 5. G. Ellis and R.D. Lorenz, " Resonant Load Control Methods for Industrial Servo Drives," IEEE Industrial Application Society 2000 Annual Meeting and World Conference on Industrial Applications of Electrical Energy, Oct. 8-12, 2000. 6. G. Ellis, Control System Design Guide (2nd Ed.) Academic Press, 2000. 7. Z. Gao and T. A. Trautzsch A stable self-tuning fuzzy logic control system for industrial temperature regulation, IEEE Industrial Application Society 2000 Annual Meeting, Rome, 2000. 2Donoho, D. and Johnstone, I., Ideal Spatial Adaptation via Wavelet Shrinkage, Biometrika, Vol. 81, December 1994, pp. 425455. 3Coifman, R. and Donoho, D., Translation invariant denoising, Wavelets and Statistics, edited by A. Antoniadis and G. Oppenheim, Lecture Notes in Statistics, Springer-Verlag, Berlin, 1995, pp. 125150. 8Burrus, C. S., Gopinath, R. A., and Guo, H., Introduction to Wavelets and Wavelet Transforms, Prentice-Hall, New Jersey, 1998. 9Mallat, S., A Wavelet Tour of Signal Processing, Academic Press, New York, 1999.
REFERENCES
1. G. Stephanopoulos, O. Karsligil, and M. Dyer Multi-scale aspects in modelpredictive control Journal of Process Control 10(2000) pp 275-282. 2. I. Daubechies, Ten lectures on Wavelets SIAM, CBMS-NSF Regional Conference Series in Applied Mathematics, 1992. 3. S.G.Mallat, A theory of multi-resolution signal decomposition: the wavelet representation, IEEE Transactins on Pattern Analysis and Machine Intelligence (1989) 674-693.
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10 Donoho, D., Smooth Wavelet Decompositions with Blocky Coefficient Kernels, Recent Advances in Wavelet Analysis, edited by L. Schumaker and F. Ward, Academic Press, 1993, pp. 259308 11. Hnao H., Capolino G. A. Mthodologie et application du diagnostic pour les systems lectriques. Article invit dans Revue de l'Electricit et de l'Electronique (REE), (Text in French) 2002, 6, p. 79-86. 12. Raghavan S. Digital control for speed and position of a DC motor. MS Thesis, Texas A&M University, Kingsville, 2005. 13. Allaoua B., Abderrahmani A., Gasbaoui B., Nasri A., The Efficiency of Particle Swarm Optimization Applied on Fuzzy Logic DC Motor Speed Control, SERBIAN JOURNAL OF ELECTRICAL ENGINEERING, Vol. 5, No. 2, Nov. 2008, p. 247 262. 14. Halila A., tude des machines courant continu, MS Thesis, University of LAVAL, (in French), May 2001. 15. Capolino G.A., Cirrincione G., Cirrincione M., Henao H., Grisel R., Digital Signal Processing for Electrical Machines, Invited paper, Proceedings of ACEMP'01 (Aegan International Conference on Electrical Machines and Power Electronics), Kusadasi, Turkey, June 2001, p. 211 219. 16. Lieslehto J., PID controller tuning using Evolutionary programming, American Control Conference, VA June 25-27, 2001. 17. Mitsukura Y., Yamamoto T., Kaneda M., A design of self-tuning PID controllers using a genetic algorithm, in Proc. Amer. Contr. Conf., San Diego, CA, June 1999, p. 1361 1365.
18. Popov A., Farag A., Werner H., Tuning of a PID controller Using a Multi-objective Optimization Technique Applied to A Neutralization Plant, 44th IEEE Conference on Decision and Control, and the European Control Conference 2005.
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Novel Voltage Controller for Stand Alone Induction Generator using Modified Sinusoidal PWM - VSI
Sujitha C Premalatha K
Abstract- This paper proposes a system based on a stand

alone self excited induction generator and presents a constant voltage controller for the stand alone wind energy conversion system using an induction generator. The system uses a modified sinusoidal pulse width modulated voltage source inverter (modified sine PWM VSI). One of the disadvantage of having stand alone wind energy conversion system with self excited induction generator (SEIG) is the poor voltage regulation which takes place due to the change in speed and load condition. To overcome this drawback, a voltage controller is developed which makes the voltage constant when SEIG is subjected to sudden change in load So that it is now possible to operate the SEIG at constant vol.tage in any load condition. The amplitude of the terminal voltage of the SEIG is regulated by adjusting the modulation index of the modified Sine PWM VSI. Here the system requires only the sensing of the dc link voltage. To predict the performance of the developed system, a MATLAB/ SIMULINK - based simulation study is carried out. The simulated results show the good performance of the system under different loading conditions.
Keywords Stand-alone Self Excited induction Generator, Voltage Source Inverter, Modified Sinusoidal PWM, Terminal Voltage . I. INTRODUCTION
Among the different renewable energy systems, wind energy appears as the most promising one, due to both technical and economic factors. Important progress in wind energy conversion technologies has been achieved and more efficient and more powerful wind generators are now available. The selection of the generator depends upon many factors such as type of application, machine characteristics,maintenance, cost etc. Currently induction machines are more popular compared to other machines. However its major disadvantage is the requirement of excitation power. This reactive power can be supplied by a variety of methods [1][3], ranging
Sujitha C, PG Student , Kumaraguru College of Technology, Coimdatore-6 (suji.shark@gmail.com) Premalatha K, Assistant Professor, Kumaraguru college of Technology,Coimbatore-6
from using simple capacitors to that of a VSI inverter with complex power conversion techniques. Another limitation of the SEIG in stand-alone systems is its inability to control the terminal voltage and frequency under change in load and wind speed. To overcome this problem, several methods are proposed in [2][4]. The capacitor excitation [3], [4] is suitable only when there is a constant load at the IG terminal and is driven at constant mechanical speed. However any change in load and rotor speed may result in a loss of excitation. To overcome this problem, discrete blocks of capacitors can be added or removed at the IG terminals either using contactors or power electronic switches in series with the capacitors, depending upon change in speed and load. Another method of providing excitation involves using a saturable reactor [5] connected in each phase of IG. This inductor with stepped air gap gradually saturates with stator current. As a result, its inductance decreases with load. However the overall system is bulky and expensive. In order to improve the performance of the system, use of modern control techniques such as vector control and sliding mode control have been suggested [6 & 7]. Though the use of vector control technique improves the performance of the system, the overall system becomes complex. It should be noted that one of the key issues in standalone system is reliability and simplicity in control structure. The use of these techniques defeats this purpose. The excitation schemes proposed in [6] involve power electronic converters to source the required reactive power to excite the IG. Though the voltage build-up process has been discussed and the results have been presented in these papers, the dynamic behaviour of SEIG is not discussed. Moreover, the overall control structure is complex in nature. Therefore the main objective of this paper is to develop a simple control strategy to overcome the limitations of the existing schemes. The proposed controller is also capable of handling reactive loads and does not require the mechanical speed sensors, ac voltage or current sensors, thereby reducing the overall cost and hardware complexity. This also improves the overall reliability of
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the system. The controller maintains a constant voltage at the IG terminal during the change in load by adjusting the inverter frequency. The amplitude of the terminal voltage of IG is controlled by the modulation index of the VSI. Unlike in most of the systems reported in literature, the proposed system does not require a dump load. Detailed Matlab/Simulink-based simulation studies are carried out to demonstrate the effectiveness of the scheme. Viability of the scheme is confirmed through experimental results using a scaled down laboratory prototype. II. MATHEMATICAL MODELLING OF 3- SELF-EXCITED INDUCTION GENERATOR The d-q axes equivalent circuits of an induction generator (IG) in synchronously rotating reference frame are shown in Fig. 1. The complete dynamic
A. Representation of the d. c. side of the inverter The capacitor voltage equation is governed by:
where Vdc is the voltage across the capacitor and Idc is the current flowing through it, as shown in Fig. 2. The set point of Vdc must be greater than the peak value of the machine line voltage in order to force the desired line currents. Total d. c. current Idc can be expressed in terms of inverter switching function as
(suffix e identifies compensator phase currents) The three switching functions take the value of 1 if the upper switch of the inverter leg is on and it is 0 if the lower switch in the same inverter leg is on. B. Model of the Voltage Source Inverter (VSI) Using the switching function SF1a,b,c the Vao, Vbo and Vco can be obtained as:
equations of IG, taking
The Line-to-Line voltages generated by the inverter can be derived as: Fig . 1. d-q model of IG a) d- axis, b) q- axis saturation into account, in synchronously rotating referenceframe [11], [12] is represented in matrix form as follows :
Equations for electromagnetic torque and mechanical speed of the SEIG are expressed as follows: III. MATHEMATICAL MODELING OF 3- PWM VSI The complete mathematical modeling of the PWM-VSI and the load are explained in the following sections. 2
C. Mathematical model of the Load Equations dealing with generator feeding a (R-L) load in d-q frame are
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induction generator decreases as speed of the prime mover decreases. To maintain a constant voltage at the IG terminal, the controller decreases the inverter frequency. An increase in capacitor voltage indicates that the active power required by the load is reduced due to the removal of load. Under this condition active power generated by the IG is higher than the power required by the load. In order to decrease the active power the controller increases the inverter frequency. V. SIMULATION RESULTS The developed models of the sub-system are integrated and the resulting system is simulated using MATLAB/ SIMULINK. The machine rating and its equivalent circuit parameters used for the study are given in appendix. The simulated results showing the variation of terminal voltage of the generator and the voltage across dc link capacitor during start up are shown in Fig. 4. While, Fig. 5. shows the modified sinusoidal pwm signal. The overall simulation block diagram is given by the Fig .3.
where iLds and iLqs are the d-axis and q-axis components of the load current. IV. PRINCIPLE OF OPERATION OF THE CIRCUIT The proposed overall system block diagram is shown in Fig. 2. A battery on the dc side of inverter is provided for initial excitation. The reactive power required by the IG and load is provided by the voltage source inverter. Therefore the rating this inverter is chosen based on the excitation power of IG and reactive power requirements of the load. During startup, the controller sets the stator frequency lower than the rotor frequency so that the power produced by IG is used to charge the capacitor connected across the dc link to a set reference value. The error between the reference and actual capacitor
Fig.2. Overall system block diagram. voltages is processed by the PI controller. If the measured capacitor voltage is higher than the reference value, the stator frequency is increased by the controller, thereby decreasing the torque and power supplied by IG, and, if the measured capacitor voltage is lower than the reference value the stator frequency is decreased. The output of the PI regulator is fed to the harmonic oscillator to generate the sine and cosine waveforms. These waveforms are multiplied by the modulation index (ma) to get Vr, Vy and Vb as shown in Fig. 2. These sinusoidal waveforms are compared with 1 kHz triangular carrier signal to generate the switching pulses to the IGBT inverter. Any variation in the output power of IG is directly indicated by the variation in the terminal voltage of the generator. A decrease in capacitor voltage below the reference value indicates that the active power drawn by the load is higher than the power generated by IG. This difference in power is supplied by the VSI and hence the dc link voltage falls. Due to step change in load, the input power to the
Fig. 3. Overall simulation block diagram
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Stator inductance(ls) . . . . . . . . . . . . . . . . . 0.4535 (H) Rotor inductance (lr) . . . . . . . . . . . . . . . . . .0.475 (H) Magnetizing inductance(unsaturated) . . . . 0.3H Number of Poles . . . . . . . . . . . . . . . . . . . . .4 Rotor inertia(J) . . . . . . . . . . . . . . . . . . . 0.664 (kg.m2) VIII. REFERENCES
Fig .4. Terminal voltage of the generator and dc link voltage.
Fig.4. Modified sinusoidal PWM signal. The simulation circuit for the generation of the modified sinusoidal pwm signal is given in the fig .6.
[1] E.D.Basset and F.M.Potter, Capacitance excitation of Induction Generators, Transaction on American Institute of Electrical Engineering, vol. 54, no. 1, pp. 540545, 1935. [2] H. C. Rai and A. K. Tandon, Voltage Regulation of SEIG Using Passive Elements, 6thEuropean Conference on Electrical Machines and Drives, vol. 1, no. 1, pp. 240245, 1983. [3] M.B.Brennan and A.Abbondanti, Static Excitation for Induction Generator, IEEE Transactions on Industry Applications, vol. 13, no. 5, pp. 422428, Sept/Oct, 1977. [4] N. H. Malik and A. H. Al-Bahrani, Influence of the Terminal Capacitor on the Performance Characteristics of SEIG, IEE Proceedings of Instituteion of Electrical Engineering,Part C, vol. 137, no. 2, pp. 168 173, March, 1990.
Fig. 6. Simulation block diagram of the controller. VI. CONCLUSION A simple constant voltage controller for stand alone wind energy conversion system using induction generator is proposed. The controller is able to maintain a constant voltage at the terminals of IG during step change in load. The developed controller has a fast dynamic response, robust and reliable. The controller does not require any mechanical speed sensor thereby reducing the cost and complexity of the hardware. The simulation is done using MATLAB/ SIMULINK. VII. APPENDIX Parameters of the Induction Machine at 50 Hz: Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Connection . . . . . . . . . . . . . . . . . . .. . . . . . Rated voltage . . . . . . . . . . . . . . . . . . . . . . . 420 V Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800 RPM Stator resistance(rs) . . . . . . . . . . . . . . . . . . 7.83 () Rotor resistance(rr) . . . . . . . . . . . . . . . . . . 7.55 ()
[5] S. M. Alghuwainew, Steady State Analysis of a Self-Excited Induction Generator by Shunt Saturable Reactor, IEEE Conference on Electrical Machines and Drives, vol. 1, no. 1, pp. 101103, 1997. [6] D. W. Novotny and G. H. Studtmann, Selfexcitation in Inverter Driven Induction machine, IEEE Transactions on Power Apparatus and Systems, vol. 96, no. 4, pp. 11171125, July/Aug, 1977. [7] S. N. Bhadra, K. V. Ratnam, and A. Manjunath, Study of oltage Build up in a Self-Excited, Variable Speed Induction Generator/Static Inverter System With D.C side Capacitor, IEEE Conference on Power Electronics, Drives and Energy System, vol. 2, no. 1, pp. 964970, 1996. [8] T.L.Maguire and A.M.Gole, Apparatus for supplying an isolated dc load from a variable speed Self-Excited Induction Generator, IEEETransactions on Energy Conversion, vol. 8, no. 3, pp. 468475, 1993.
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PSPICE APPROACH FOR SPACE VECTOR PULSE WIDTH MODULATION FOR INDUCTION MOTOR DRIVE
M.Sasikumar S.VeeraKumar, and A.Nirmal Kumar Email id : sasimillinium@gmail.com space vector can be implemented by variable frequency
drives (VFD) to generate three-phase sine waves. The advantages are less harmonic magnitude at the PWM switching frequency due to averaging, less memory requirement compared to sinusoidal PWM, etc. The disadvantages are not full utilization of the DC bus voltage, more calculation required, etc [1]. Implementation of SVMPWM with over modulation can generate a fundamental sine wave of amplitude greater than the DC bus level. The disadvantage is complicated calculation, line-to-line waveforms are not clean and the THD increases, but still less than the THD of the six-step PWM method [2]. 2. SPACE VECTOR PULSE WIDTH MODULATION In many industrial applications, Sinusoidal Pulse Width Modulation (SPWM), also called Sine coded Pulse Width Modulation, is used to control the inverter output voltage. SPWM maintains good performance of the drive in the entire range of operation between zero and 78 percent of the value that would be reached by square-wave operation. A. Generation of the SVPWM switching signals With the three-phase voltage source inverter shown in the figure 1, output voltage is produced by switching only one switch in each leg at any instant of time. There are six possible switching sequences to produce an output voltage.
Abstract The purpose of this project is to present the analysis different PWM inverter and to find the suitable PWM for Induction motor drives. There are so many methods are available in PWM inverter but in this project we discussed about SVPWM Inverter. The most widely used PWM schemes for three-phase VSI carrier based sinusoidal PWM and SVPWM . The most widely used PWM schemes for three-phase voltage source inverters are carrier-based sinusoidal PWM and space vector PWM (SVPWM). There is an increasing trend of using space vector PWM (SVPWM) because of their easier digital realization and better dc bus utilization. This paper focuses on step by step development SVPWM implemented on an Induction motor. The model of a three phase a voltage source inverter is discussed based on space vector representation. Very low values can be reached for the output voltage THD, robust dynamic response, the efficiency of the inverter can be optimized for each load condition and SVPWM enables more efficient use of the DC voltage Controlled induction motor drives without mechanical speed sensors at the motor shaft have the attractions of low cost and high reliability. Simulation model of SVPWM is obtained using PSPICE SCHEMATIC Simulation results are also provided. Key words Space Vector Pulse Width Modulation, Total Harmonic Distortion, Voltage Source Inverter.
1.INTRODUCTION Induction motors (IM) are widely used in low and mid power applications such as computer peripheral equipments, robotics, adjustable speed drives and electric vehicles. The growth in the market of Induction motor drives has demanded the need of simulation tool capable of handling motor drive simulations. Implementations of various PWM techniques have been a major area of research. Latest of them is Space Vector Modulation technique. The concept of operation of linear or non-linear region is based on modulation index that indirectly provides information about the inverter utilization capability. This feature of SVPWM puts on edge over other PWM techniques. The main aim of any PWM technique is to utilize the inverter to its full capacity that is achieved only with six-step operation. In sixstep operation, maximum value of the desired voltage vector is obtained. This control technique is based on the fact that three phase voltage vectors of the induction motor can be
converted into a single rotating vector. Rotation of this
Fig 1: Three-phase voltage source inverter (VSI)
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C. SVPWM Switching Rules To implement the SVPWM algorithm, the following switching rules are implemented: 1. The trajectory of VS should be a circle. 2. Only one switching per state transition. 3. Not more than three switching in one TS. The final state of one sample must be the initial states of the next samples. Table 2: Switching Vectors, Phase Voltages and Output Line to Line Voltages
B. Converter switching states A three-phase bridge inverter, as shown in Figure 1, has 23 =8 permissible switching states. Table 1 gives a summary of the switching states and the corresponding phase-toneutral voltages of an isolated neutral machine [8]. Consider, for example, state 1, when switches Q1, Q6 and Q2 we closed. In this state, phase A is connected to the positive bus and phases B and C are connected to the negative bus. The simple circuit solution indicates that
the inverter has six active states (16) when voltage is impressed across the load, and two zero states (0 and 7). When the machine terminals are shorted through the lower devices or upper devices, respectively. The sets of phase voltages for each switching state can be combined to derive the corresponding space vector. The switching sequence of an inverter is in the order 1-2-3,2-3-4,3-4-5,4-5-6,5-6-1,6-1-2.Each switch conducts over 180 degrees in a period. This indicates the inverter in 180 degrees mode of conduction. Switching from one sequence to another takes place at every 60 degrees [11].
Table 1: Switching sequence
D. INVERTER VOLTAGE VECTORS
Fig 3 The Eight Inverter Voltage Vectors
A different approach to SPWM is based on the space vector representation of voltages in the d, q plane. The d, q components are found by three phase to two phase conversion, where the total power, as well as the impedance, remains unchanged. Figure 2 shows 8 space vectors in according to 8 switching positions of inverter, V* is the phase-to-centre voltage which is obtained by proper selection of adjacent vectors V1 and V2 [9].
Space Vector PWM (SVPWM) refers to a special switching sequence of the upper three Power transistors of a three-phase power inverter. It has been shown to generate less harmonic distortion in the output voltages and or currents applied to the phases of an AC motor and to provide more efficient use of supply voltage compared with sinusoidal modulation technique as shown in Fig. 4
Fig 2: Inverter output voltage space vector.
Fig 4 Locus comparison of maximum linear control voltage in Sine PWM and SVPWM
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3. SIMULATION CIRCUIT
R12 1 D1N5406 D1 D1N5406 VAMPL = 230 V91 VOFF = 0 FREQ = 50 R10 C3 D3 D5 D1N5406 M1 D7 M23 D8 M2 D9 L4 2 R11
To implement the space vector PWM, the voltage equations in the abc reference frame can be transformed into the stationary dq reference frame that consists of the horizontal (d) and vertical (q) axes as depicted in Fig.5.
V10 VOFF = 0 VAMPL = 230 FREQ = 50 V11 VOFF = 0 VAMPL = 230 FREQ = 50 D4 D1N5406 D6 D2 D1N5406 D1N5406 M4 D12
M26 D11
M3 D10
R17
0 0
0
+
U2 OPAMP
C9 V222 5Vdc
OUT
R41
0
R4
R27
U10 U11 OUT OUT + + OPAMP OPAMP R1 R35 R28 R34
R33 R222 U12 U1 OUT + OPAMP 14 1 +IN -IN 1SC CPI COM FOUT VOUT VFC32 5 10 11 7 13
C2
C1
Fig 5The relationship of abc reference frame and stationary dq reference frame
0
R2 C111 R32
1n
0 0
R38 R39 V1
0 0
R333
R02 E3
+ U8A
+ -
0
3 U19A 2 7404 R171 R01 Q2 V2 V3
From this figure, the relation between these two reference frames is below fdq0 = Ksfabc ------------ (1)
V7
1 2 7408 V4 1
0 0 0
0 0
R04 Q22 E4
+ -
+ -
R18 E2
U2A 1 3 2 7408 1 U14A 2 7404 1 3 2 7408 V80 R19 1k R6 E6 Q5 7408 Q2N2222 U34A 1
0
U141A 2 7404 R5
0
Q4
0
V5 Q2N2222
+ -
+ -
0
U35A 1 3 2 1 U1241A 2 7404
0
V12
0 0
V9
+ -
+ -
E R20
0
U5A 1 3 2 7408 V100 V13 U6A 220 Q2N2222 1 U153A 2 7404
1k
0
R7
Q7
E7
+ -
+ -
1 3 2 7408 1
U16A 2 7404 R21
0 0
1k
V6
E1
---------------(2) where fdq0=[fd fq f0]T, fabc=[fa fb fc]T, and f denotes either a voltage or a current variable. E. BASIC SWITCHING VECTORS AND SECTORS As described in Fig. 5, this transformation is equivalent to an orthogonal projection of [a, b,c] onto the two-dimensional perpendicular to the vector [1, 1, 1] (the equivalent d-q plane) in a three-dimensional coordinate system. As a result, six non-zero vectors and two zero vectors are possible. Six nonzero vectors (V1 - V6) shape the axes of a hexagonal as depicted in Fig. 6, and feed electric power to the load. The angle between any adjacent two non-zero vectors is 60 degrees. Meanwhile, two zero vectors (V0 and V7) are at the origin and apply zero voltage to the load. The eight vectors are called the basic space vectors and are denoted by V0, V1, V2, V3, V4, V5, V6, and V7. The same transformation can be applied to the desired output voltage to get the desired reference voltage vector Vref in the d-q plane. The objective of space vector PWM technique is to approximate the reference voltage vector Vref using the eight switching patterns. One simple method of approximation is to generate the average output of the inverter in a small period.
+ -
+ -
0
R9
E Q8
Fig 7 Simulation Circuit
A.
PSPICE CIRCUIT FOR VSI
Fig 8 Pspice Model for VSI
B.
PI CONTROLLER The PSpice simulation model for PI controller
Fig 6 Basic Switching Vectors and Sectors
Fig 9 Pspice Model for PI Controller
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B. SIX PULSE SVPWM GATE PULSE OUTPUT
C.
VOLTAGE TO FREQUENCY CONVERTER (VFC 32)
The PSpice simulation model voltage to frequency converter using (VFC 32)
The three phase six pulse gate signals are shown in Fig 13 the SVPWM gives six pulses and are fed to the inverter gate terminals.
Fig 14 Upper Leg Switching Pulses for Inverter
Fig 10 PSPICE Model for VFC
D.
SPACE VECTOR MODULE
Fig 15 Lower Leg Switching Pulses for Inverter
C.
Fig 11 PSPICE Model for Space Vector Module
OUTPUT WAVEFORM FOR UNCONTROLLED RECTIFIER
E.
+
PSPICE MODEL FOR INDUCTION MOTOR DRIVES

R25 1 R24 1 L38 2 L39 2
The output waveform for three phase uncontrolled rectifier, in this output having more ripples finally we put DC link filter to reduced ripples and also shown filter output.
IN PU T
R26 1
L40 2
1 L41 R27 R48 2 R29
1 L42
61.19K R47 1 L43
R31 2
R46
Fig 12 PSPICE Model for Induction Motor Drives
4. SIMULATIONS RESULTS A. INPUT WAVEFORM D.
Fig 16 Rectifier Output and Filter Output
PI CONTROLLER OUTPUT
The three phase input voltage was shown Fig 12 in which the three phase ac voltage is fed to the rectifier circuit. Its normal phase voltage is 230V. The phase angle between each phases are 120 degree and frequency is 50Hz.
The rectifier output will be sensed by a current sensor after the output will be given to PI Controller. The PI Controller is reduced the steady state error.
Fig 13 Three Phase Input Waveforms
Fig 17 Current Sensor Output
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G. INPUT WAVEFORM FOR IM
Fig 18 PI Controller Output
E.
VOLTAGE TO FREQUENCY OUTPUT

Fig 22 Input Waveform for IM
The voltage to frequency output will be constant. The frequency output will be considered reference voltage.
H.
OUTPUT FOR INDUCTION MOTOR DRIVES
Fig 19 Frequency Output
Fig 23 Line To Line Voltages for IM
F.
OUTPUT FOR VSI
Fig 24 Phase Voltages for IM
I.
TOTAL HARMONICS DISTORTION Fundamental Frequency (50Hz) =132, THD=4.9%
Fig 20 Line To Line (ab, bc, ca) Voltages
The line to line voltage will show above. Here we got peak to peak 230V.
Fig 25 Total Harmonics Distortion Fig 21 Phase (a, b, c) to Neutral Voltages
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BIOGRAPHY
M.Sasikumar was born in the year 1986. He received his B.E degree in Electronics and Communication Engineering from Trichy Engineering college, Trichy in the year 2009. Currently he is doing M.E Power Electronics and Drives in Bannari Amman Institute of Technology, sathyamangalam. His areas of interests includes Control of Electric motor drives and Space Vector concepts.
5.CONCLUSION The project is based upon Space Vector PWM technique, which is used for taking out harmonics and ripples from the input and give out a pure ripple signals as output. This is the most advanced technique, which is being used now; the older version of this project is sinusoidal PWM which has large harmonics and produce heat when compared to Space Vector PWM technique. It finds application in industries the speed control is its main advantage, its used in places where variable speed is required. One of the special uses of this technique is that it can be used as variable frequency drives, which can be got by using v/f method the value of both voltage and frequency can be varied for getting variable speed. Its the latest and newest technique used in every where for its high harmonic and ripple reducing capability and its speed varying ability.
S.Veerakumar was born in the year 1983. He completed is PG and UG in Electrical Engineering form VIT Deemed university, Vellore and Kongu Engineering College, Perundurai. He is currently doing his Ph.D in the area of Industrial Drives at Anna Institute of Technology, Coimbatore.
REFRENCES
[1] D.-C. Lee and G.-M. Lee, A novel over modulation technique for space vector PWM inverters, IEEE Trans. Power Electron., vol. 13, pp. 11441151, Nov. 1998. [2] S. Bolognani and M. Zigliotto, Novel digital continuous control of SVM inverters in the over modulation range, IEEE Trans. Ind. Application, vol. 33, pp. 525530, Mar/Apr. 1997. [3] B.K. Bose, Power Electronics and AC Drives Englewood Cliffs, New Jersey, Prentice Hall, 1986. [4] Di Zhao, V. S. S. Pavan Kumar Hari, Gopalaratnam Narayanan, and Rajapandian Ayyanar, Space-Vector-Based Hybrid Pulse width Modulation Techniques for Reduced Harmonic Distortion and Switching Loss, IEEE Transactions On Power Electronics, VOL. 25, NO. 3, PP.760-774, March 2010. [5] G. Narayanan, D. Zhao, H. K. Krishnamurthy, R. Ayyanar, and V. T. Ranganathan, Space vector based hybrid PWM techniques for reduced current ripple, IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 16141627, Apr. 2008. [6] L. A. C. Lopes and M. F. Naguib, Space vector modulation for low switching frequency current source inverters with reduced low-order noncharacteristic harmonics, IEEE Trans. Power Electron., vol. 24, no. 4, pp. 903910, Apr. 2009. [7] W. Yao, H. Hu, and Z. Lu, Comparisons of space-vector modulation and carrier-based modulation of multilevel inverter, IEEE Trans. Power Electron., vol. 23, no. 1, pp. 4551, Jan. 2008. [8] J. A. Houldsworth and D. A. Grant, The use of harmonic distortion to increase the output voltage of a three-phase PWM inverter, IEEE Trans. Ind. Appl., vol. IA-20, no. 5, pp. 12241228, Sep. 1984. [9] A. Rahiman , Modified SVPWM algorithm for three level VSI with synchronized and symmetrical waveforms, IEEE Trans Industrial Electronics, vol. 54, no. 1, pp. 486-494, Feb. 2007. [10] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and Z. Du, A complete solution to the harmonic elimination problem, IEEE Trans. Power Electron., vol. 19, no. 2, pp. 491499, Mar. 2004. [11] J.-H. Yuma and B.-H. Kwon, An effective software implementation of the space-vector modulation, IEEE Trans. Ind. Electron., vol. 46, pp. 866 868, Aug. 1999.
A.Nirmal Kumar was born in the year 1951. He completed his PG and UG in Electrical Engineering from Kerala and Calicut University respectively. He completed PhD in Power Electronics in the year 1992 from P.S.G. College of Technology, Coimbatore under Bharathiar University. He was with N.S.S. College of Engineering for nearly 28 years in various posts before joining Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India in the year 2004. He is a recipient of Institution of Engineers Gold Medal in the year 1989. His current research areas include Power converters for Wind Energy Conversion System and Controller for Induction motor drives.
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Sensorless Control of Brushless DC Motor Using Modified Back-EMF Detection

1
S. Nellaiyappan, 2M. Raja Nanda Kumar, 3R. Shanmuga Sundaram, Member IEEE
Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, India, nellaiyappans@gmail.com 2 Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, mnandakumar87@gmail.com 3 Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, rss_is@yahoo.com
Abstract This paper proposes a modified Back-EMF Detection

sensorless control scheme for Brushless DC motor drive system. Even though several methods are available for sensorless control, they are found to be unsuitable for closed loop systems controlled by pulse width modulation (PWM) technique. The proposed is well suited for the systems controlled by pulse width modulation technique and can be easily realized through inexpensive PIC microcontrollers. The simulink model of the proposed system is developed using MATLAB to investigate the performance of the proposed sensorless control technique. In the proposed method, a speed dependent time delay unit is developed to produce virtual hall sensor signals. Simulation results are presented to validate the performance of the proposed sensorless control scheme for different reference speeds and load torques.
Keywords Brushless DC motor, Back-EMF Detection, MATLAB/Simulink, Speed Dependent Time Delay. I. INTRODUCTION HE recent improvement in motor control and power electronics technologies leads to the development of Brushless DC Motor(BLDCM). The most important feature of it is the mechanical commutation constituted by commutators and brushes is replaced by electrical commutation circuitry. It solves the problem caused by mechanical commutation and maintains the merits of using a DC motor in varying speed field. BLDC motors are used in many applications like power steering, engine cooling fan, fuel/water pump, heating, ventilating, and air-conditioning (HVAC) blower motors. The rotor position signal of BLDCM is usually provided by hall sensor. The existence of hall sensor has number of drawbacks. They increase the cost and require special arrangement for mounting the hall sensor in the motor. These hall sensors are temperature susceptible and hence limit the motor operation. The reliability is reduced due to extra components and wiring. In this paper, the rotor position is detected via detecting the three phase terminal voltages. This kind of method don't use position sensor, reduce the system cost and the volume of the motor, especially improves the characteristics of the system. Sensor and sensorless are two methods of control of BLDC motors [1],[2],[3]. An approach to position sensorless BLDC motor drive is discussed in [4]. A new Algorithm for sensorless control was proposed in [5]. Two
types of sensorless control techniques of BLDC motors are discussed in [6][7]. The first type is the position sensing using back EMF of the motor [8], and the second type is position estimation using motor parameters. The position estimation scheme usually needs complicated computation, and the cost of the system is relatively high. The back EMF sensing scheme is suitable for many application [7], [9] requires no detailed knowledge of motor parameters. This technique is suitable for motor control using Pulse Width Modulation (PWM). In BLDC motor, only two out of three phases are excited at any time, leaving the third winding floating. The back EMF of the floating winding is measured to establish the switching sequence for commutation of power devices in the three-phase inverter driving the motor [10]. The method for determining the zero-crossing point of back-EMF via terminal voltages is given in [11], [12].A second order Low Pass Filter (LPF) is required to remove the high frequency switching noise signals caused by the use of pulse width modulation (PWM) signals. Due to the use of filter a time delay is produced, thereby deteriorating the torque response and efficiency. The zero-crossing point of back-EMF can be determined from mathematical calculation [13]. In this method, terminal voltages are sampled when PWM is in ON state. It involves lot of complex calculations and need Digital Signal Processor (DSP) to implement it. In this paper, the Time Delay created due to the use of the filter is reduced by designing a Speed Dependent Time Delay Unit. This will overcome the problem of using filter and it can be easily implemented by using low cost micro controllers. The main focus of the paper is to control the speed of Brushless DC motor by using modified Back-EMF Zero Crossing Detection. The Simulation of the proposed system is completed and results are presented. The realization of the proposed method using experimental setup is under progress. II. PROPOSED BACK EMF DETECTION METHOD Consider a 3 phase, Star connected BLDC motor, is driven by a three phase inverter in which the devices are triggered with respect to the rotor position. Fig. 1 shows the terminal voltages of the three phase winding. Va denotes the terminal voltage of the phase A connected to the
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under open loop condition. Once the Back-EMF has become significantly high to detect the zero crossing point the control is switched to closed loop operation. In the experimental setup PIC 16F877A Microcontroller is used to implement the proposed method.
positive dc link rail. Vc indicates the terminal voltage of the phase C connected to the negative dc-link rail. Vb is the terminal voltage of the oating phase C. The back-EMF voltage is detected via the terminal voltage of oating phase. Va
La Vn eb Lb Rb Vb
Vc Fig.1 From Fig.1, the following voltage equations can be written
dI a + Ea + V dt dI Vb = R b I b + L b + Eb + Vn dt dI Vc = R c I c + L c + Ec + Vn dt Va = R a I a + L
(1) (2) (3)
Fig.2 Block Diagram of the proposed method
IV. SIMULATION OF THE PROPOSED METHOD The simulation of the proposed method is performed in MATLAB Environment. The overall simulation block is shown in the Fig. 3. The simulink model consists of speed Controller, PWM Generation, Terminal Voltage Sensing and Zero Crossing Detector and Commutation Control. The virtual hall sensor signal and direction of rotation of the motor are calculated from the Back-EMF signals. The PWM signals given to the inverter switches are proportional to the speed of the motor. The reference and actual speed are compared to obtain the error value. This error is input to PI speed controller and its output is used for PWM generation. The output of the PWM generator block gives pulses proportional to the corresponding speed. These pulses are used to drive the inverter switches. The neutral point voltage Vn is obtained by creating a virtual ground. Low Pass Filter (LPF) is used to remove the ripples created due to use of Pulse Width Modulation (PWM) signals. The Delay Calculation block is used to calculate the time delay between the Zero Crossing instant of Back-EMF signal and the commutation instant. In this proposed method, the drawback created due to the use of filter is eliminated by the use of the delay calculation block.
The motor adopts 120o conducting mode, so only two phases are energized at a time and current in the two phases has the same amplitude but in opposite direction. In floating phase, the current is zero. Adding the above three equations, we get
Va + Vb + Vc = E a + E b + E c + 3Vn
(4)
The sum of the Back-EMF, Ea+Eb+Ec= 0 can be obtained at the instant, when each phase Back-EMF crosses zero. Therefore, at the zero-crossing point of Back-EMF, 1 (5) Vn = ( Va + Vb + Vc ) 3 When phase winding current is zero, its phase Back-EMF is increasing from or decreasing to zero. For example consider phase A, Ea= Va -Vn, when Va= Vn, then Ea= 0. Therefore, neutral point voltage can be obtained from the phase terminal voltages. When the terminal voltage is equal to the neutral voltage, the zero crossing point of the back-emf is detected. III. BLOCK DIAGRAM The Fig.2 shows the block diagram of the sensorless control of the BLDC motor. The terminal voltage is sensed to detect the Zero Crossing point of the Back-EMF. Under very low speeds, Back-EMF is too low to detect. So under such conditions, the controller is programmed to start the motor
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Fig.3 Simulink Model of the Proposed Method action. The Speed response shows that Virtual Hall Sensor Signal is remain synchronised even under loaded condition
phase Voltage A 30 20 10 0 -10 -20 -30 0.05
V. RESULT AND ANALYSIS The proposed method is simulated in the Matlab and the results obtained are shown in the Fig. 4 to Fig. 8. The phase voltage without using filter is shown in Fig. 4. The PWM signal will introduce lot of ripples in the terminal Voltage. This creates difficulty in detecting the zero crossing point of the Back-EMF. So a second order Low Pass Filter (LPF) is used to remove the ripples in the phase voltage. The resultant waveform using filter is shown in the Fig. 5. The cutoff frequency of the filter is carefully designed so that it wont affect the shape of the back-emf signal. The comparison between the generated and real hall sensor signals is shown in the Fig. 6. The result shows that both the waveforms are synchronized and maintains synchronization even under loaded condition. The delay calculation block shown in Fig. 3 is used to adjust the time delay between the zero crossing event of the back-emf and the commutation pulses given to inverter. The 30 time delay between the zero crossing point and commutation instants is not fixed. It is calculated according to the speed of the motor. So it provides better synchronization between real and generated hall sensor signals. The back emf and current are perfectly in-phase with each other. For simplicity, only phase A is shown in the Fig. 7. For proper commutation to take place both current and back-emf should be in-phase. The speed response for the set speed of 3500 rpm is shown in Fig 8. The PI controller provides robust control over wide speed range. The actual speed matches with the reference speed. The load torque of 0.2Nm is applied at 0.3 sec and the PI controller responds quickly and takes the necessary control
V oltage(V )
0.055
0.06
0.065
0.07
0.075 0.08 Time(sec)
0.085
0.09
0.095
0.1
Fig. 4 Phase A voltage without Filter
30 20 10 Voltage(V) 0 -10 -20 -30 0.05
0.055
0.06 0.065
0.07 0.075 0.08 0.085 Time(sec)
0.09 0.095
0.1
Fig. 5 Phase A Voltage with Filter

Real Hall Sensor 2 Voltage(V) 1 0 -1 0.3 0.31 0.32 0.33 0.34 0.35 0.36 Time(sec) Virtual Hall Sensor Signals 0.37 0.38 0.39 0.4
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APPENDIX
2 Voltage(V) 1 0 -1 0.3 0.31 0.32 0.33 0.34 0.35 0.36 Time(sec) 0.37 0.38 0.39 0.4
Fig. 6 Real and Virtual Hall sensor signal

Stator current Ia 5 Current(A)
Motor Parameters Power 175 watts Voltage 36V Current 5A Speed 4000 rpm Torque Constant 0.082 Motor type 3 phase, Star connected Inductance per phase 1.5 mH Resistance per phase 0.87 ohm . REFERENCES
-5 0.38 20 Voltage(V) 10 0 -10 -20 0.38
[1] [2] [3]

0.39 0.4 0.41 0.42 0.43 Time(sec) Stator back emf Ea 0.44 0.45
[4]
[5]
[6]
0.39 0.4 0.41 0.42 Time(sec) 0.43 0.44 0.45
Fig. 7 Current (Ia), & Back-EMF (Ea)

4000 3500 3000 speed(rpm) 2500 2000 1500 1000 500 0 0 0.05 0.1 0.15 0.2 Time(sec) 0.25 0.3 0.35 0.4
[7]
[8]
[9]
[10]
[11]
[12]
Fig. 8 Speed response when load torque of 0.2 Nm is applied at 0.3 sec VI. CONCLUSION The simulation results obtained using the proposed BLDC drive system has proved the simplicity of sensorless speed control of BLDC motor. The implemented Back-EMF sensing method has superior performance and provides control over wide speed range at low cost. The validity of the developed sensorless BLDC drive system using back EMF detection is implemented on a 3-phase, 175 W, 4-pole, BLDC motor. In general, the proposed method is suitable for sensorless BLDC motor control using PWM signals.
[13]
[14]
Boldea and S.A Nasar, Electric Drives, CRC Press, 1999. M. H. Rashid, Power Electronics, Prentice Hall, 1993. R. Krishnan, Electric Motor Drives: Modeling, Analysis and Control Prentice Hall, 2001. S. Ogasawara and H.Akagi, An approach to position sensorless Drive for brushless dc motor. IEEE Trans. J. Industry Application, vol .27, pp. 928-933, Sep/Oct. 1991. N. Ertugrul and P. Acarnley, A new algorithm for sensorless operation of permanent magnet motors, IEEE Trans. J. Industry Application, vol. 39, pp. 126133, Jan./Feb. 1994. Tay Siang Hui, K.P Basu, V. Subbiah, Permanent Magnet Brushless Motor Control Techniques, in Proc. National Power and Energy Conference (PECon), 2003,133-138. R. C. Becerra, T. M. Jahns, and M. Ehsani, Four-quadrant sensorless brushless ECM drive, in Proc. IEEE APEC91 Conf., 1991, pp.202209. Jianwen Shao, Dennis Nolan, Maxime Teissier and. David Swanson, A Novel Microcontroller-Based Sensorless Brushless DC (BLDC) Motor Drive for Automotive Fuel Pumps, IEEE Trans. J. Industry Application, vol.39, No.6, pp.1734-1740, 2003. J. Moreira, Indirect sensing for rotor flux position of permanent magnet ac motors operating in a wide speed range, IEEE Trans. Ind. Application vol. 32, pp. 401407, Nov./Dec. 1996. GE, Control system, method of operating an electronically commutated motor, and laundering apparatus, U.S Patent 654 566, 1987. [11] Y. S. Lai, F. S. Shyu, and Y. S. Chang, Novel sensorless PWMcontrolled BLDCM drives without using position and current sensors, lter and center-tap voltage, Proc. IEEE IECON, pp. 21442149, 2003. Y. S. Lai, F. S. Shyu, and W. H. Rao, Novel back-EMF detection technique of brushless dc motor drives for whole duty-ratio range control, in Proc. IEEE IECON Conf., 2004, pp. 27292732. Y. Kang, S. B. Lee, and J. Yoo, A microcontroller embedded AD converter based low cost sensorless technique for brushless dc motor drives, in Proc. IAS Annu. Meeting, 2005, pp. 21762181. J. Shao, D. Nolan, M. Teissier, and D. Swanson, A novel microcontroller-based sensorless brushless dc (BLDC) motor drive for automotive fuel pumps, IEEE Trans. Ind. Appl., vol. 39, no. 6, pp. 17341740,Dec. 2003.
127
SIMULATION ON THREE PHASE MATRIX CONVERTER FED INDUCTION MOTOR DRIVE USING SPACE VECTOR MODULATION
Isvaria.A#1,J.Karpagam*2,Dr.A.Nirmal Kumar #1 PG Scholar, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India. *2 Assistant Professor, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India. $ Head of the Department, Info Institute of Engineering & Technology, Coimbatore, Tamil Nadu, India. sujisumi@rediffmail.com,isvaria08anand@rediffmail.com
Abstract-This paper presents the simulation of three

phase matrix converter (MC) for a variable speed induction motor drive. The three phase matrix converter needs nine bidirectional switches to convert fixed frequency fixed voltage to variable frequency variable voltage. The paper explains the use of space vector modulation (SVM) technique in matrix converter to obtain good harmonic content and variable speed performance of the motor. The aim of any modulation strategy is to obtain variable output having a maximum fundamental component with minimum harmonics. Space vector modulation is one of the best modulation strategies for adjustable speed AC drive.
Keywords-Three Phase Matrix Converter, Space

Vector Modulation, Three phase Induction Motor, Total Harmonic Distortion.
NOMENCLATURE
MC-Matrix Converter m -Modulation Index rec -Displacement angle of the rectification sequence inv -Displacement angle of the inversion sequence Ts-Sampling Time Period Te-Developed Torque s-per unit slip R1-Stator resistance X1-Rotor inductance R2-Rotor resistance X2-Rotor inductance
essential. The induction motor is usually fed from back-back PWM. In recent years, Matrix Converter has received considerable interest as a viable alternative to the conventional back-back PWM converter. In recent years, the increased attention on energy efficiency has spurred the development of matrix converters. The matrix converter offers an all-silicon solution for AC-AC power conversion. The main circuit of a matrix converter is composed of an filter and bilateral switches. The matrix converter has a number of advantages over the standard converter. Matrix conversion directly converts AC to AC, thus eliminating the need for a large DC filter capacitor. The matrix converter is composed of a set of bidirectional switches, thus permitting both generation and motoring using the same set of switches. Further, the matrix converter permits an optimized power factor and harmonic content of input currents and three-level voltage switching for reduced voltage stress. The more commonly used bidirectional switches in power converters are, two anti-parallel IGBTs each in series with a blocking diode, thus requiring a minimum of four discrete devices, or two anti-parallels reverse blocking IGBTs.
I. INTRODUCTION
Modern industrial processes place stringent requirements on industrial drives to have higher operating efficiency, good dynamic performance, flexible operating characteristics with ease of diagnostics and communication to a central computer. The electrical drive has a wide variety of applications such as machine tools, elevators, mill drives etc., where swift control over the torque of the motor is
Fig.1 Block Diagram of Three Phase Matrix Converter fed Induction Motor Drive
The fig.1 shows the overall block diagram of the three phase Matrix Converter fed induction motor drive. The three phase AC supply is fed to the three phase MC which consists of nine bidirectional switches. The LC filter is installed at the input side to reduce the harmonics and ripple content of the input current. Three phase induction motor acts as the load. SVM is composed of two important
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stages: Rectifying stage modulation and inverting stage modulation. In inverting stage modulation, input current vector is determined by finding the displacement angle between the input current and input voltage. In inverting stage modulation, output voltage vector is determined by finding the displacement angle between the output current and output voltage. By combining input current vectors and output voltage vectors, 36 sectors can be obtained. Switching pattern and duty cycle calculation of each sector is calculated and space vector modulated pulses are generated to the three phase MC.
With space vector modulation control using over modulation, the voltage transfer ratio may be increased to 1.05 at the expense of more harmonics and large filter capacitors.
II. MATRIX CONVERTER

MC has no limit in the output frequency; limitation is only on output amplitude, which is smaller than input amplitude. MC replaces two stage energy conversions to only one stage energy conversion because it contains no energy storage element. It consists of a bidirectional switch capable of blocking voltage and current in both directions, the energy flow can get from source to load and back. In MC it is possible to control the phase angle between the voltages and current on the input, the output phase angle differs from input phase. The matrix converter uses bidirectional fully controlled switches for direct conversion from AC to AC. It is a single stage converter that requires nine switches for three phase to three phase conversion. It is an alternative to the double-sided PWM voltage source rectifier inverter. The circuit diagram of the three-phase to three-phase matrix converter is shown in the figure 2. An ac input LC filter is normally used to eliminate harmonic currents in the input side and the load is sufficiently inductive to maintain the continuity of the output currents. The term MATRIX is due to the fact that it uses exactly one switch for each of the possible connections between the input and the output. The switches should be controlled in such a way that, at any time, one and only one of the three switches connected to an output phase must be closed to prevent short circuiting of the supply lines or interrupting the load current flow in an inductive load. With a given set of input three phase voltages, any desired set of three phase output voltages can be synthesized by adopting a suitable switching strategy. The matrix converter can connect any input phase (A, B, C) to any output phase (a, b, c) at any instant. When connected, the voltages Van, Vbn, Vcn at the output terminals are related to the input voltages VAN, VBN, VCN . Regardless of the switching strategy, there is a physical limit on the achievable output voltage and the maximum voltage transfer ratio is 0.866. The control methods for the matrix converters must have the ability for independent control of the output voltages and input currents.
Fig.2 Schematic Diagram of Three Phase Matrix Converter Being the converter supplied by the voltage source, the input phases should never be short-circuited and owing to the presence of inductive loads, the load currents should not be interrupted. With these constraints, there are 27 permitted switching combinations out of 512 switching combinations. Six combinations of group I, each output phase is connected to a different input phase. In the eighteen combinations of group II, two output phases are short-circuited. In the three combinations of group III, all the output phases are short-circuited. The idea of direct control of MC is based on mathematical expression, which describes conditions between output and input side. For Output Voltage
Va (t ) maA(t )mbA(t )maC (t ) Va (t ) Vb(t ) = maB (t )mbB (t )mcB (t ) Vb (t ) Vc (t ) maC (t )mbC (t )mcC (t ) Vc (t )
For Input current
(1)
ia (t ) maA(t ) mbA(t ) maC (t ) iA(t ) ib (t ) = maB (t ) mbB (t )mcB (t ) iB (t ) ic (t ) maC (t ) mbC (t ) mcC (t ) iC (t )
(2)
III.SPACE VECTOR MODULATION

In general SVM is a digital implementation to generate switching pulses to the MC. SVM is an algorithm similar to the rotation of flux in an induction machine. Performance of MC is improved compared to other modulation techniques. Space Vector Modulation is a mathematical structure formed by a collection of
129
vectors. SVM technique aims to realize the rotating voltage space vector from the six active state voltage vectors and two null state vectors. SVM technique can be considered to be the best solution for achieving the possibility of obtaining the output voltage of highest voltage transfer ratio and to optimize the switching pattern through a suitable use of the zero configurations. Switching losses can be reduced to 15%-35% depending on the output load angle. It is effectively implemented to reduce: Switching losses in the system. Content of reactive power in the system. Harmonic content in the system. Treats the sinusoidal voltage as a constant amplitude vector rotating at constant frequency. This PWM technique approximates the reference voltage V ref by a combination of eight switching patterns. A three phase voltage vector is transformed into a vector in the stationary d-q co-ordinate frame which represents the spatial vector sum of the three phase voltage.
In sampling method and voltage vectors combination, voltage vectors amplitude values are set for a particular time period, where space vector pulses are generated digitally with the help of timer circuits. This can be fed to Matrix Converter for generating output voltages to drive the three phase induction motor. Voltage vectors are combined according to the sector in which it is located. These voltage vectors have certain amplitude where combination of these voltage vectors from a period from 0360 degree would generate space vector modulated pulses to be fed to the Matrix Converter. Table 1 Voltage Vector Configuration of Three Phase Matrix Converter
Fig. 3 General Sector Diagram of Space Vector Modulation The space vector algorithm is based on the representation of the three phase input current and three phase output line voltages on the space vector plane. In MC, each output phase is connected to each input phase depending on the state of the switches. There are totally 512 switching combinations are possible, but applying to the above said rules only 27 switching combinations are possible. There are totally six sectors in the input current and six sectors in the output voltage. So, there are totally 36 sectors of MC operation are possible. Out of 27 switching combinations: There are 18 combinations of stationary vectors. 6 combinations of rotating vectors. 3 combinations of zero vectors. The phase angle of both current and voltage vectors cannot be controlled independently. Duty period of each switch is determined by considering the common switching combinations of both vectors. Duty period of the switches of each switching combination should be calculated to obtain the desired switching frequency. Sum of the switching times must not exceed the switching period.
Based on the SVM pulse generations in MC, there are 18 possible switching states are possible. The switching states are from (+1,-1) to (+9,-9) which have individual switching sequence. For switching state +1, switches 1, 5, 6 are turned on. So, the output voltage vector formed with reference to the upper leg is V1=100. Hence, the voltage vectors formed for corresponding sector of the input current and output voltage is calculated and shown in the above mentioned table of voltage vector configuration of three phase MC. 3.1 RECTIFICATION AND INVERSION STAGE MATHEMATICAL EXPRESSIONS
T = d.Ts = m.sin( rec).sin( inv).Ts (3) 3 3 T = d .T s = m .sin( rec ).sin( inv ).T s (4)
3
T = d .Ts = m.sin i( rec).sin( inv).Ts

T = d .Ts = m.sin( rec).sin( inv).Ts 3
(5)
(6)
m = mc = mv
(7)
T o = T s (T + T
+ T + T
) (8)
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m =
V
s lim
(V d s 2 + V q s 2 ) / V s
= [(3 6 ) / 4 ] .V
li m
(9) (10)
secondary (rotor) winding short-circuited. When the motor operates at slip s, the frequency of rotor currents iss times the frequency of the stator currents, therefore the revolving field produced by the rotor currents revolves with respect to rotor itself at speed. The synchronous speed is in general given by
ir m s
Ns =
The switching pattern for carrying out perfect conversion is generated by corresponding duty cycles. d ,
120 f P
(11)
d , d , d & do are the duty cycles of the rectification

stage in the direct axis and quadrature axis reference frame and the duty cycles of the inversion stage in the direct axis and quadrature axis reference frame and total duty cycle respectively. Inorder to generate the SVM pulses, we have to first detect and determine the position of input phase voltage space vector i . Then, determining the phase angle rec of desired input phase current space vector based on the input phase voltage space vector and setting input displacement angle i will result in the generation of the phase angle inv of output line voltage space vector. Then, we have to calculate switching times T , T , T , T , To and modulation index m. After calculation of switching times, this data should be given to switching pulses. By distributing switching pulses to bidirectional switches, space vector modulated pulses are generated. The five switching states of period T ,T , T ,T , To in each sampling cycle will lead to generation of SVM pulses. The equations involved are shown above from eqn. (3) to eqn. (10).
Mechanical speed of the motor, N=Ns (1-s).The speed of the revolving field of the rotor with respect to stator or space is obtained by combining the rotational speed of rotor field with respect to rotor with mechanical speed of the rotor. Hence speed of rotor revolving field with respect to stationary stator or space= sNs +Ns (1-s) =Ns. Hence from the point of view of the stator, the induction motor still can be considered as static transformer, even when its rotor is rotating and it is possible to represent the performance of an induction motor by a transformer phasor diagram. Actually, the rotor field does not exist alone but combines with the revolving field of stator to produce a resultant field, just as in the transformer, the resultant field is produced by the combination of primary and secondary ampere-turns.
Fig.4 Equivalent Circuit of Three Phase Induction Motor The equivalent circuit of a three phase induction motor is shown in fig.4 where V1 is the applied voltage per phase; R1 and X1 are the stator resistance and leakage reactance per phase respectively; R2 and X2 are rotor resistance and standstill leakage reactance per phase respectively; K is the turn-ratio of secondary to primary; Ro and Xo are the no-load resistance and reactance per phase respectively, with the rotor being driven at synchronous speed. From the fig.4, at s=1, the equivalent circuit becomes the equivalent circuit of a short-circuited two-winding transformer and at s=1, the equivalent circuit becomes the equivalent circuit of an open-circuited transformer. R2 is the actual rotor resistance whereas R2
IV. INDUCTION MOTOR

Induction motors have been used in the past mainly in applications requiring a constant speed because conventional methods of their speed control have either been expensive or highly inefficient. Variable speed applications have been dominated by DC drives. Availability of thyristors, power transistors, IGBT have allowed the development of variable speed induction motor drives. The main drawback of DC motors is the presence of commutator and brushes which require frequent maintenance and make them unsuitable for dirty and explosive environments. On the other hand, squirrel cage are rugged, cheaper, lighter, smaller, more efficient and can operate in dirty and explosive environments. Although, variable speed induction motors are expensive than DC drives, they are used in a number of applications such as fans, blowers, mill run-out tables, cranes, conveyors, tractions etc. because of the advantages of induction motors. Other dominant applications are underground and underwater installations, and explosive and dirty environments. The energy is transferred from primary (stator) to secondary (rotor) winding entirely by induction, therefore, induction motor is essentially a transformer. At standstill, the induction motor is actually a static transformer having its
(1 s ) is the electrical s
analogue of the variable mechanical load. In transformers, the approximate equivalent circuit is obtained by moving the shunt branch across the primary terminals because the no-load current is 2 to 5% of full-load current and per unit leakage reactance is low. The no-load current is 30% to 50% of full-load current in an induction motor and hence per unit leakage reactance is high. If the shunt branch is neglected and or moved towards the stator terminals, considerable error will be reduced. During normal operating
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condition of constant voltage and frequency, the core loss in an induction motor is usually constant. The per phase impedance offered to the stator by the rotating air gap field is given by
Z = R + jX =
(R2 / s + jX 2)( jXo) (R2 / s + j( X 2 + Xo))
(12)
The impedance seen by the stator applied voltage is given by ZT = R1 + jX 1 + Z (13) The stator current is given by
I1 =
V1 ZT R2 s
(14)
The per phase air gap power is given by

2 Pg = I 2
(15) Fig. 5 MATLAB/SIMULINK model of Three Phase MC fed Induction Motor drive The fig.5 shows the MATLAB/SIMULINK model of three phase matrix converter with induction motor load in open loop. The model is simulated for the given value of input voltage. Space Vector Modulated pulses are applied to the gate of IGBTs.
The internal mechanical power developed in rotor is given by

2 Pm = I 2 R 2 (1 s ) s
(16)
The internal torque developed per phase is given by
Te =
Pm
(17) (18)
The synchronous speed is given as follows
r = (1 s ) s
Te = Pm
So, the internal torque equation can be rewritten as
(19)
VI.SIMULATION RESULTS
The three phase MC is modeled using MATLAB/SIMULINK software. The simulated results are discussed below for MC fed induction motor drive.
The shaft power is given by Psh=Pg-Rotor Ohmic losses-Friction and windage losses (20) The output or shaft torque is given by
Tsh =
Psh (1 s ) s
V.SIMULINK MODEL
(21)
Simulations were done using MATLAB 7.6 version. Three Phase Matrix Converter is modeled using MATLAB/SIMULINK software. The model is designed for open loop control with induction motor speed control. SVM pulses are generated digitally for MC through rectification and inversion stage. The switching frequency is taken as 5 kHz. The switches of the matrix converter are constructed using two IGBTs and two diodes are in antiparallel. The snubber circuit is also designed for protection.
Fig. 6 Space Vector Modulated Pulses for Three Phase MC The fig.6 shows the SVM pulses for three phase MC. The constant voltage and frequency supply is given to the MC at an amplitude of 415V (rms), 50Hz. The MC output is found to be 400V (rms), 50 Hz.
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Fig. 7 Input Voltage Waveform of Three Phase MC The fig.7 shows the input voltage waveform of MC. The input voltage is of sinusoidal waveform with a peak amplitude of 230V and peak-peak amplitude of 415V (rms) .The input supply frequency is 50Hz.
Fig. 10 Output Current Waveform of Three Phase MC The fig.10 shows the output current waveform of three phase MC which as an amplitude of 11A with the output frequency of 50Hz.
Fig. 8 Input Current Waveform of Three Phase MC The fig.8 shows the input current waveform of MC. The input current waveform is of sinusoidal waveform with a peak amplitude of 14 A with an input supply frequency of 50Hz.
Fig. 11 Electromagnetic Torque of Three Phase Induction Motor Drive The fig.11 shows the electromagnetic torque of three phase induction motor drive. The torque value of induction motor is found to be 45Nm. Thus, transients prevail in the system and settle down to a final value of 45Nm.
Fig. 9 Output Voltage Waveform of Three Phase MC The fig.9 shows the output voltage waveform of three phase MC. The output voltage waveform is of pulsed sinusoidal waveform with an output frequency of 50Hz.The output voltage amplitude is found to be 400V (RMS).
Fig. 12 Angular Speed of Three Phase Induction Motor Drive
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The fig.12 shows the angular speed of three phase induction motor drive having a rotor angular speed of 147 rad/sec where the nominal speed of rotor is given by 1403.7 rpm.The induction machine runs as induction motor below rated speed.
study the behaviour of the proposed technique. The results also show that the three-phase matrix converter provides output waveforms with better quality at low output frequencies. Using a matrix converter, would eliminate any intermediate power electronic circuitry required for grid connection of a.c.sources. Particular advantages for motors, power drives, actuators etc. operating at low or variable frequency: e.g. marine, propulsion, aerospace, energy generation (wind turbines etc.).
REFERENCES
[1]Lars Helle ,Kim B. Larsen, Frede Blaabjerg, Evaluation of Modulation Schemes for Three-Phase to Three-Phase Matrix Converters, IEEE Transactions on Industrial Electronics,Vol.5, February 2004, pp 765-781. [2]Domenico Casadei, Giovanni Serra, Matrix Converter Modulation Strategies: A New General Approach Based on SpaceVector Representation of the Switch State , IEEE Transactions on Industrial Electronics,Vol.6,No.3, April 2002,pp 1134-1146. [3]Ebubekir Erdem, Yetkin Tatar, Modeling and Simulation of Matrix Converter using Space Vector Control Algorithm IEEE Proceedings on Power Electronics, EUROCON 2005, Vol.8, No.3, July 2005,pp 346-378. [4]Hiashi Hotate, Kouki Matsuse Basic Characteristics of Matrix Converter Controlled by SVM Considering Input Voltage Conditions IEEE Proceedings on Power Electronics-PESC 2007, Vol.5, No.2, February 2007,pp 678-693. [5]J.Rodriguez, E.Silva, F.Blaabjerg, P.Wheeler,J.Clare and J.Pontt, Matrix Converter controlled with the direct transfer function approach: Analysis, Modelling and Simulation International Journal of Electronics,Vol.6,No.3,December 2005,pp 567-580. [6]Ramesh Chand Bansal, Vinod Kumar & Raghuveer RajJoshi Experimental Realization of Matrix Converter Based Induction Motor Drive under Various Abnormal Voltage Conditions, International Journal of Control, Automation and Systems,Vol.7,No.4,October 2008,pp 780-805. [7]Wheeler P.W., Clare J.C., Empringham L., and Weinstein,Matrix Converter: A Technological Review, IEEE Transactions on Industrial Electronics,Vol.3,No.8,April 2002,pp 1120-1134. [8]Laszlo Huber, Dusan Borojevic, Space Vector Modulated Three-Phase to Three-Phase Matrix Converter with Input Power Factor Correction IEEE Transactions on Industry Applications,Vol.8,No.6, December 1995,pp 450-468. [9]Yuping Sun, Fuyuan Xu, Kai Sun, Design of Matrix Converter with Bidirectional Switches IEEE Transactions on Industrial Electronics,Vol.9,No.8,May 2002,pp 956-970. [10]Lixiang Wei, T.A.Lipo, Ho Chan, Matrix Converter Topologies with reduced number of switches IEEE Transactions on Industry Applications,Vol.2,No.5,July 2005, pp 780-796. [11]J.Karpagam, Dr.A.Nirmal Kumar, V.Kumar Chinnaiyan, Comparison of Modulation Techniques of Matrix Converter International Journal of Engineering and Technology,Vol.2,No.2,April 2010,pp 189-195.
Fig. 13 Total Harmonic Distortion of Output Voltage of Three Phase MC The fig.13 shows the total harmonic distortion in output voltage waveform. The modulation index is found to be 0.6. SVM is used to control the output voltage, output current and total harmonic distortion respectively. The THD in output voltage waveform is 22.47%
Fig. 14 Total Harmonic Distortion of Input Current of Three Phase MC The fig.14 shows the total harmonic distortion of input current waveform. The THD in input current waveform is 10.59%.
VII.CONCLUSION
We can conclude that the performance analysis of three phase matrix converter fed induction motor drive has been simulated. Space Vector Modulation is used to control the output voltage, output current, rotor speed and total harmonic distortion respectively. A simulation result gives good performance of the three phase matrix converter drive system. Simulation models in MATLAB are used to
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VIII.BIOGRAPHIES
Isvaria.A was born in Tirupur, Tamil Nadu.She received her B.E. Degree in Electrical and Electronics Engineering from Institute of Road and Transport Technology, Erode, Tamil Nadu.Currently she is pursuing her M.E. degree in Power Electronics and Drives at Bannari Amman Institute of Technology, Sathyamangalam. Her area of interest includes Power Electronics, Electrical Machines and Digital Logic Circuits.
J.Karpagam, She completed her Masters degree in the specialization of Power Electronics and Drives from Anna University Chennai, India. This author became a Member (M) of IEEE. Presently she is working as Assistant Professor in the department of Electrical and Electronics Engineering at Bannari Amman Institute of Technology Tamilnadu, India and she is in this profession since 1999.Currently she is pursuing her Ph.D. in the area of matrix converter applications to AC Drives under Anna University Coimbatore. Her area of interest includes Power Electronics, Power Converters, AC & DC drives, Solid State Drives, DSP applications to Power Electronics and Wind Power Generation. So far she has published around fifteen papers in national level and International conferences.
Dr. A.Nirmal Kumar was born in Kerala, India, on May 22, 1951. He received his B.Sc. (Engg) degree in Electrical Machines from N.S.S. college of Engineering, Palakad. He completed his M.Sc. (Engg) degree in Power Electronics at Calicut University, Kerala and he received his Ph.D. in Power Electronics, Bharathiyar University, Coimbatore. He has total experience of 38 years in teaching and he is currently working as a Professor and Head, EEE Department in Info Institute of Technology, Coimbatore, Tamilnadu. His research interests are Power Converters, Electrical machines, Wind Power Generation and Solid State Drives.
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Maximum Power Point Tracking Controller for Wind Turbine Driven Permanent Magnet Generator for Z-Source Inverter
M.Manimekala, R.Bharanikumar
AbstractThis paper presents Maximum Power Point Control for variable speed wind turbine driven permanent-magnet generator for the three phase z-source inverter. The wind turbine generator is operated such that the rotor speed varies according to wind speed to adjust the duty cycle of power converter and maximizes Wind Energy Conversion System (WECS) efficiency. The maximum power point for each speed value is traced using Maximum Power Point Tracking (MPPT) algorithm. The rotating speed of permanent-magnet generator should be adjusted in the real time to capture maximum wind power. The system includes the windturbine, permanent-magnet generator (PMG), three-phase rectifier, z-source inverter and load. The control parameter is the shoot through of the ZSI. PMG is made to operate at variable speed to achieve good performance. The entire WECS model consists of wind turbine model, PMG model and power converters model. The MATLAB / SIMULINK is used for simulation and the results are compared with laboratory setup. KeywordsPMG, rectifier, z-source inverter, wind turbine, MPPT.
I. INTRODUCTION Consumption of energy based on fossil fuels is considered to be the major factor for global warming and environment degradation. The utilization of naturally occurring renewable energy sources as an alternative energy supply has been assuming more importance of less Power generation utilizing solar rays, geothermal energy, wind force and wave force has became a reality. Research on performance improvement of and cost reduction in such nonconventional energy conversion systems is being accorded the highest priority [8]. Wind power generation has a strong connection to rotating machinery and hence its practical application is most promising. Wind generator control methods have already been proposed to efficiently utilize the wind power which is prone to fluctuation every moment. The induction type machine has the advantages of robustness, low cost and maintenance-free operation. However, they have the drawbacks of low power factor and need for a separate excitation source. Permanent magnet generator is chosen so as to eliminate the drawbacks of induction generator. The power generated varies with load with the peak occurring at certain load. Therefore, MPPT is achieved by varying the shoot through duty ratio of the z-source inverter by using the PWM technique. The validity of the technique for arriving at the maximum power is confirmed in the simulation study. Considerations of the characteristics of the wind mill are not necessary, because the torque is a function of the generator speed and characteristics of the wind mill are reflected in the rotational speed [8]. II. Components of Wind Electric Systems The basic components of a wind electric system analyzed herein are shown in Fig 1. The wind turbine is directly connected to the Permanent Magnet Generator (PMG). The generated power of continuously varying frequency is fed to local load through suitable power converters, to ensure constant voltage and constant frequency. Since the wind power fluctuates with wind velocity, the generator output voltage and frequency vary continuously. The varying AC voltage is rectified into DC in a diode bridge and the dc
A Iq,Id Xq,Xd p Te V
NOMENCLATURE - Air density - Area swept by the blades - q - axis, d -axis current, respectively - Reactance of q -axis , d - axis, respectively - Power Angle - Differential Operator (d/dt) - Electromagnetic Torque produced - Velocity of the Wind - Tip Speed Ratio t - Turbine Speed Tg - Generator Torque - Pitch Angle Cp - Power Coefficient ________________________________________________
M.Manimekala, PG scholar, Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: manimekalajm@gmail.com R.Bharanikumar, Assistant Professor, EEE Department, Bannari Amman Institute of Technology, Sathyamangalam. E-mail id: bharani_rbk@rediffmail.com
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116 Cp ( ) = ( 0.4*) 50.5e 1 1
16.5
voltage is inverted to get the desired AC voltage and frequency employing a PWM inverter. The shoot through duty ratio controls the z-source inverter output voltage. where
(5)
1 =
1 1 0.035 ( + 0.089 ) 3 +1
(6)
B. Permanent Magnet Generator Model Permanent Magnet Generator provides an optimal solution for varying-speed wind turbines, of gearless configuration. This eliminates the need for separate base frames, gearboxes, couplings, shaft lines, and pre-assembly of the nacelle. The output of the generator can be fed to the power grid directly. A high level of overall efficiency can be achieved, while keeping the mechanical structure of the turbine simple.
Fig. 1Block diagram of wind electric generator system
III. THEORETICAL ANALYSIS
A. Wind turbine model There are two types of wind turbines namely vertical axis and horizontal axis types. Horizontal axis wind turbines are preferred due to the advantages of ease in design and lesser cost particularly for higher power ratings. The power captured by the wind turbine is obtained as 1 P = R3V 2C p (1) 2 where the power coefficient Cp is a nonlinear function of wind velocity and blade pitch angle and is highly dependent on the constructive features and characteristics of the turbine. It is represented as a function of the tip speed ratio given by [2] where Zs=
Ra2 + Xs2
Fig. 2 Equivalent circuit of PM generator for one phase
Generated emf / phase ,

E = V t + Ia ( R a + jX s ) = V t + Ia Z s
(7)
Rt V
(2)
The rotor reference frames of the voltages are obtained as

Vq = RS + Lq p Iq r Ld Id + r m
It is important to note that the aerodynamic efficiency is maximum at the optimum tip speed ratio. The torque value obtained by dividing the turbine power by turbine speed is formed obtained as follows:
1 Tt (V , t ) = R 2 Ct ( ) V 3 2
(8) (9)
Vd = ( RS + Ld p) Id + r Lq Iq
The expression for the electromagnetic (EM) torque in the rotor is given by (3)
3 P Te = n Ld Lq I q Id m Iq 2 2
(10)
where Ct () is the torque co-efficient of the turbine, given by

Ct ( ) = C p ( )
C. Rectifier Model
(4)
The power co-efficient Cp is given by [3]
A three-phase diode bridge rectifier converts the AC generated output voltage, which will be varying in magnitude and also in frequency, into DC. The average output voltage of the three phase diode rectifier is obtained [5] as follows:
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(11) E. PWM Inverter Model At any instant of time ,only two phases that have the largest potential difference may conduct, carrying current from the PMG side to the impedance network side. Fig 4 shows the PWM control method for z-source inverter. In each conduction interval, inverter operates in two modes. In mode1, the inverter is operating in the shoot through state. In this mode, the diodes (D1 and D6) are off, and the dc link is separated from the ac line. In mode 2, the inverter is applying one of the six active vectors or two zero vectors, thus acting as a current source viewed from the z-source circuit with diodes (D1 and D6) being on.
Vdc =
3Vm
and the average and RMS load current are given by

Idc = Vdc Rl Vrms Rl
(12) (13)
Irms =
D. Z-source inverter
Fig. 3 Circuit diagram of z-source inverter with diode rectifier
The Fig. 3 shows the complete block diagram of the PMG with diode rectifier and z-source inverter. The inverter has an impedance network on its dc side, which connects the source to the inverter. The impedance network is composed of two inductors and two capacitors. The conventional voltage source inverter have six active vectors and two zero vectors. However the z-source inverter has one extra zero vector(state) for boosting the voltage that is called shootthrough vector. In this state, load terminals are shorted through both the upper and lower devices of any one phase legs, or all three phase legs. The dc link voltage, Vi=2Vc-Vdc Vi=BVdc Where B is the boost factor that is determined by (14) (15)
Fig. 4 PWM control method for z-source inverter
F. Maximum Power Point Tracking
B=
1 T 1-2 0 T
(16)
Where T0 the shoot through time interval is over a switching cycle T. The output peak phase voltage Vac is Vac=MB (Vdc /2) Where M is the modulation index. (17)
Fig. 5 Optimum Power Point tracked.
For variable speed operation, each wind velocity has a maximum power point. Fig.5 shows the optimum power point tracked in the power characteristics curve of wind turbine. To operate the WECS at maximum power point,
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The Fig. 7 shows the MATLAB/SIMULINK model of flux linkage estimator which converts the direct axis and the quadrature axis current in to the equivalent flux linkage.
the controller requires both voltage and current inputs. This increases the number of controller blocks [4], [7]. To improve the efficiency and to reduce the number of controller blocks, the control algorithm is developed with only one input the current input. This controller generates appropriate firing angle to the boost chopper, and as a result, maximum power point is tracked. The optimized current is used as reference so as to obtain the maximum generated output power from the wind turbine generator for various wind velocities. The proposed MPPT control algorithm is represented in Fig 6.
Fig. 7 Flux Linkage Estimation
In the MPPT algorithm as shown in Fig. 5 the values of ia, ib and ic is taken as input and id , iq and m are calculated using the equations (20) and (21)
id = (2 / 3)(ia sin + ib sin( t ) + ic sin( + t ))

iq = (2 / 3)(ia cos + ib cos( t ) + ic cos( + t ))
(20) (21)
The value of flux linkages are obtained by using equations (22) and (23),
d = vds + Rids
q = vqs + Riqs
The optimized speed is given by equation (24),
(22) (23)
m opt =
Fig. 6 MPPT algorithm with current feedback
(( c r 3 k 0 )3 k 2 + k12 )) k12 ( v *
1 ) 3k 2
(24)
From the current reference we are finding out the flux components that are given by equation (18).
vds id s v = R i + p qs qs
ds qs
Tip speed ratio () and power output are obtained from the equations (2) and (1), given in the wind turbine model. For a particular wind velocity, the current operating point is determined by using the power-speed relationship and the
(18)
The flux linkage in the previous matrices is expressed by the following equation
d s id s t cos m = Lq + Ke qs iq s t s in m
(19)
desired operating point is determined by using the optimized value. If current operating point is equal to desired operating point then the duty cycle of chopper is maintained as the same otherwise the duty cycle of chopper
139
is adjusted to make to make both operating points equal and again the process is repeated. IV. SIMULATION RESULTS AND DISSCUSSION
Fig 10 Power-Speed Characteristics of wind turbine with MPPT
Fig. 8 MATLAB model of Wind Energy Conversion System
The Fig 10 shows the Power Speed Characteristics of the wind turbine with maximum power point tracking curve MPPT. From the above curve it reveals that maximum power is tracked for various wind velocities by using the MPPT algorithm. Also the power increases on increasing the wind velocity. For example for a wind velocity of 12m/s the corresponding power is 1612 Watts for 33 Rpm respectively. Similarly for various wind velocities the Power-Speed characteristics are obtained.
Fig. 8 shows the overall simulation model of Wind Energy Conversion System. This model is simulated in MATLAB/SIMULINK for various wind velocities.
Fig .9 Power-Speed Characteristics of wind turbine without MPPT Fig 11 PWM Output Pulse Variation
The Fig 9 shows the Power-Speed Characteristics of wind turbine without MPPT for various wind velocities. The generator power gets increases on increasing the wind speed. Thus in the above shown figure that output power is maximum for wind velocity of 12m/s.
Fig 10 shows the PWM output pulse variation for various wind velocities. If the wind velocity gets varied, correspondingly the PMG and the rectifier voltage get varied. In order to maintain the constant output voltage, the shoot through time period of the Z-Source inverter should be varied.
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REFERENCES
[1] Yaow-Ming Chen,Yuan-Chuan Liu, Shih-Chieh Hung, and ChungSheng Cheng, Multi-Input Inverter for Grid-Connected Hybrid PV/Wind Power System , IEEE transactions on Power Electronics, vol. 22, no. 3, May 2007, pp. 1070- 1077. [2] Monica Chinchilla, Santiago Arnaltes,Juan Carlos Burgos, Control of Permanent-Magnet Generators Applied to Variable-Speed WindEnergy Systems connected to the Grid, IEEE Transactions on Energy Conversion, vol. 21, no 1, March 2006, pp.130-135 [3] P. Anandavel, K. Rajambal and C. Chellamuthu, Power optimization in a Grid-connected wind energy conversion system, IEEE Conf. PEDS 2005, pp.1617-1621. [4] ShigeoMorimoto, Hideaki Nakayama, Masayuki Sanada, Yoji Takeda,Sensorless Output Maximization Control for Variable Speed Wind Generation System using IPMSG, IEEE Transactions on Industry Applications vol. 41, no. 1, Jan/Feb 2005, pp.60-67. [5] Kelvin Tan,Syed Islam: Optimum Control Strategies in Energy Conversion of PMSG Wind Turbine System without Mechanical Sensors,IEEE Transactions on Energy Conversion, vol. 19, no. 2, June 2004, pp.392-399. [6] A.B. Raju, K.Chatterjee and B.G. Fernandes, A Simple Power Point Tracker for Grid connected Variable Speed Wind Energy Conversion System with reduced Switch Count Power Converters, IEEE Power Electronics Specialist Conference, 2003. pp 456-462. [7] Jia Yaoqin, Yang Zhongqing, Cao Binggang, A New Maximum Power Point Tracking Control Scheme for Wind Generation, 07803-7459-2/02/$17.00 2002 IEEE, pp144 -148. [8] Kenji Amei Yukichi, Igkayasu Takahisa Ohji Masaaki Sakui, A Maximum Power Control of Wind Generator System using a Permanent Magnet Synchronous Generator and a Boost Chopper Circuit, PCC-Osaka 2002, pp.1477- 1452. [9] N.Yamamura, M.Ishida, T.Hori: A Simple Wind Power Generating System with Permanent Magnet Type Synchronous Generator, IEEEConf. PEDS99, pp.849- 854. [10] F.Z.Peng, Z-Source Inverter, IEEE Transactions on Industry Applications, vol. 39,no2, pp. 504-510.,March/April 2003.
Fig 12 PMG output voltage for Vw=12m/s
Fig 11 shows the PMG output waveforms. The peak to peak voltage is 73V for 12m/s. PMG output voltage get increases on increasing the wind speed.
Fig .13 ZSI output voltage for Vw=12m/s
Fig 12 shows the output voltages of Z-Source Inverter for wind velocity of 12m/s. The output voltage of the overall WECS, for the wind velocity of 12m/s is at 415V which is controlled by the MPPT controller. V. CONCLUSION The variable-speed wind energy conversion system using a permanent magnet generator has been discussed in this paper and the optimal control strategy of PMG maximizing the generated power was proposed. The optimum current value that maximizes output power is determined and used as reference for MPPT algorithm. Also MPPT control is achieved without a wind speed sensor. The control algorithm is made simple from other existing algorithms by this current reference. The system configuration is also simple, but the operation of wind turbine generator is optimized. Simulation study on a Wind Energy Conversion System employing MATLAB/SIMULINK SIMULINK model is the core coverage in this paper.
BIOGRAPHIES
MANIMEKALA.M was born in Tamilnadu India, on April 11, 1987. She received her B.E Degree in Electrical and Electronics Engineering from Institute of Road and Transport Technology, Erode, Anna University. She currently doing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, affiliated to Anna University. Her field of interest includes Power converters for wind energy conversion systems.
Bharanikumar.R was born in Tamilnadu, India, on May 30, 1977. He received the B.E degree in Electrical and Electronics Engineering from Bharathiyar University, in 1998. He received his M.E Power Electronics and Drives from College of Engineering Guindy Anna University in 2002. He has 9 yrs of teaching experience. Currently he is working as Asst. Professor in EEE department, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India. Currently he is doing research in the field of power converter for wind energy conversion system, vector controller for synchronous machine drives
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AN INTELLIGENT ELECTRICAL POWER SYSTEM TO PERFORM MULTI TASKS USING ZIGBEE

1
Anu T S, 2Arthi Sahaya Rones V, 3Mohana Jothi S, 4Nallasivam N

Dept of EEE, Info Institute of Engineering, Kovilpalayam, Coimbatore-641107, Tamil Nadu, India.
1
anukrishnats@gmail.com 2 sahaya04@gmail.com 3 smohanajothi@gmail.com 4 Sanath201@gmail.com Abstract The goal of An Intelligent Electrical Power System to Perform Multi-Tasks Using Zigbee is to improve the operation of the existing power system by continuously monitoring the load flow from the supply side to the consumer side, thereby providing multiple information such as the amount of power consumed, load power factor, faults in the transmission and distribution line. From the obtained data, power lost due to theft can be found and automatic electricity billing is provided to the consumers. Further the communication between the suppliers and consumers is also established. Keywords Zigbee, Power optimisation, Power theft, Automatic EB billing, Load monitoring.
I. INTRODUCTION The proposed system An Intelligent Electrical Power System to Perform Multitasks Using Zigbee aims at preventing power theft and continuous load monitoring, provides a better communication between the customers and the Electric power suppliers. In this system the load consumed by the users are monitored and electrical billing is done automatically. II. NEED T&D losses have been a concern for the Indian electricity sector since these have been very high when compared with other developed countries. . The present T&D losses including unaccounted energy are about 30% (As per MoP, however this figure is optimistically low) and there is need to reduce these losses through efficient management and the best operation & maintenance practices of the transmission and distribution. When we talk about T&D losses it also includes the theft of electricity, although it is the part of commercial loss but there is no way to segregate theft from the T&D losses. Metering efficiency including defective meters covers all aspects of correct metering of electricity consumed. This theoretically is defined as the ratio of metered consumer to the total number of consumers. As far as looses on account of metering are concerned these include the losses due to
incorrect metering. Defective metering may be on account of defects in meters, defect in CT/PT in case of HT consumers, CT in case of LT consumers. Since assessment of defective meters on regular basis is most important to calculate the losses on account of defective meter and the distribution licensee owing to its huge network is not able to calculate exact number of defective meters/defective metering. Although in some of the states the metering of small and medium power consumers having load more than 25KW is based on indoor and outdoor meters, indoor being the main meter and outdoor being the check meter. The consumption of these two meters must match for the proper metering. This has to some extent reduced the loss on account of defective metering but again due to negligence of the employee of the distribution licensee still the energy is not being matched, further the consumption on the basis of Meter Reading Instrument is not being watched by not analysing the MRI reports this further results in the commercial losses for not billing the energy consumed due to CT, PT circuit open or short. Obviously the losses on account of defective metering is not an easy task to calculate. The distribution licensee needs to first of all find the number of defective meters in its area, then he also needs to find out the number of consumers unmetered, the actual consumption of all these un-metered consumers, the energy billed against these defective plus unmetered consumers. Since all these data are not available or even if available are least authentic so we can say at present there is no way to effectively calculate the commercial loss on account of defective meters or on account of poor metering efficiency. A. Literature Survey ZigBee Alliance, ZigBee Document 075356r14ZB: Smart Energy Profile Specification, San Ramon,CA,USA, May 2008. TAHBOUB, R.,AND LAZARFWAMRU, V., NOVEL APPROACH FOR REMOTE ENERGY METER READING USING MOBILE AGENTS, IN THE PROCEEDINGS OF THIRD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY

AND NEW GENERATIONS VEGAS, NEVADA, USA.
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(ITNG 2006), APRIL 2006, LAS C. Impact of Power Theft INDIAN Power companies are losing . around 30,000 Cr or $6 billion + a year due to Transmission and Distribution losses courtesy outdated network, power theft, and poor billing practices as per the recent news published at Times of India. The per unit cost of electricity in India is highest in the world. According to news the per unit cost has increase by 15.5% per unit, which has raised the cost to 4.50 per unit for the year 2009-10, courtesy outdated grid. The mid-term review panel reviewed the performance of 20 major states; The total distribution expenses increased to 2.03 lakh crore and is likely to go up 2.25 lakh crore this year. MTR criticized the distribution utility for their poor power procurement planning. D. Conventional Methods These are some of the more common methods of identifying electricity theft: 1) Financial Rewards: Utility companies encourage consumers to report electricity theft, sometimes offering big rewards for information leading to conviction of anyone stealing electricity. Unfortunately, most cases are never identified in the apartment industry due to lack of timely information. 2) Periodic Checks: Electricity theft frequently takes place after service has been disconnected. Some utility companies periodically check disconnected meters if the customer has not contacted them to reconnect service. This labor-intensive, manual process has little chance of success given that the apartment industry averages 70% turnover of tenants annually. 3) Meter Readers: Utility meter readers typically suspect that electricity theft is taking place when they find a broken meter tag or other signs of tampering. But as more utility companies outsource the meter reading function to third parties, training meter readers to detect theft is becoming more difficult and less efficient. In addition, third party meter readers do not read disconnected meters. E. Drawbacks Metering done by the electricity boards are single point devices with a specific function of metering. The problem the utilities face is not in getting the correct meter reading, they already have the correct meter reading data. Problem lies outside of metering, where the distribution network as a whole presents phase balancing problems, overload problems, loss related problems none of which have anything to do with
Walid Ahmed Alaa F. Sheta Optimization of Electric Power Distribution Using Hybrid Simulated Annealing Approach, American Journal of Applied Sciences 5 (5): 559564, 2008. III. SYSTEM ANALYSIS Imapacts on power theft in India and the conventional methods used to overcome power theft are discussed. A. Power Theft is Dangerous Electricity theft, an ongoing problem for all electricity providers, is punishable by jail time, a fine or both in the India. Most cases of electricity theft occur when violators physically alter the internal mechanism of their electric meters, causing the electricity to bypass the meter and not be recorded. As a result, violators are not charged for the total number of kilowatt-hours actually used, causing lost revenue for the electricity providers. In addition, tampering with live electricity inside a meter is dangerous and could result in a fire, shock or even death to the perpetrator. Utility staff could also be injured when later repairing the meter. B. Energy profile in India The generation (excluding wind) was 448.38 billion units353.66 BUs thermal, 82.71 BUs hydro and 12.01 BUs nuclear. (Update: Generation capacity in 2010)
TABLE I DATA RELATED TO GENERATION CAPACITY
S.NO
1 2 3 4 5 6
Generation capacity Installed Capacity As on in MW November 30, 2007 Coal 73492.38 Diesel 1201.75 Gas 14581.71 Total 89275.84 Wind and 10175.03 Renewable Energy Nuclear 4120.00 Hydro 34680.76 Grand Total 138257.63
As on November 30, 2010 89778.38 1199.75 17624.85 108602.98 16786.98 4560.00 37367.60 167317.36
It is estimated that India would need a total installed capacity of 212000 MW by 2012 (Eleventh National Power Survey). The Central Electricity Authority has estimated the need for creating additional capacity of 1,00,000 MW by 2012. A capacity addition of 41,110 MW comprising 14,393 MW hydro, 25,417 MW thermal and 1,300 MW nuclear power has been fixed for the Tenth Five Year Plan. An additional capacity of 3,100 MW is expected to come from renewable sources of energy. The contribution of State sector and private sector during Tenth Plan has been fixed at 11,157 MW and 7,121 MW respectively. This is approximately 45 per cent of total capacity addition envisaged.
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conditioning unit. SCU converts the AC signals into DC converts the magnitude of sensed signals into suitable magnitude for microcontroller. Since microcontroller work only in digital data conditioned signal are given to Analog to digital converter. Power factor measuring unit gets signal from current sensor and voltage sensor and measures the power factor. Microcontroller receives signals from ADC and Power factor measuring unit and it is programmed to analyses the data. Microcontroller sends the load status to the Zigbee transceiver. Zigbee transmits the data. Zigbee transceiver in an EB section receives the signal from load section transmitter. Received data is given to the computer through RS232. RS232 is an interfacing unit between computer and microcontroller. In a computer customized program is developed for monitoring and control of the load. When a load exceeds the limit or the power factor is poor the operator from EB office can give the load disconnecting signal using computer. Mean time it calculates the cost for the energy consumed. This data is also transmitted to the consumer side using zigbee. Control signal from computer is given to the zigbee transceiver. Zigbee in a load section receives the signal from EB section transmitter and sends it to the microcontroller. Microcontroller analyses the data and controls load controller. Load controller controls the load. And it is programmed to displays the cost of energy consumed in Liquid crystal Display unit. Power supply supplies essential power to all units. V. MERITS The following are the various merits of the proposed system: Automated Alerts and Notifications to Consumers Continuous load monitoring No waiting for future data analysis to identify theft that happened in the past. Instantly Detect trouble points that reduce Power Quality or can cause outages. Totally granular Demand Side Management without expensive Home Area Network devices that need individual switching of appliances for demand control. Entire H/W and S/W from a single provider & no need for maintaining separate servers and buying expensive software systems
any metering system or any SCADA solution they have implemented. Hence the problem stays on.
IV. PROPOSED SYSTEM The block diagram of the proposed system is shown in figure no- 01 and 02. It consists of two sections namely EB section and LOAD section
Fig. 01 EB Section
Fig. 02 Load Section
Load section consists of variable load, current senor, potential senor, SCU, ADC, microcontroller, load controller, Zigbee transceiver, power factor measuring unit and power supply. EB section consists of computer, RS232, Zigbee transceiver and power supply. Current sensor in load section senses current consumed by the load. Voltage sensor senses voltage consumed by the load. These two signals are given to Signal
VI. SIMULATION RESULTS The simulation results for the power optimization are shown in fig.03 and 04. Fig 03 corresponds to the normal operating conditions and Fig 04 corresponds to the power failure conditions. x axis corresponds to the amplitude of the source voltage in volts. x1 and x2 corresponds to the amplitude of the load current and the auxiliary load current in mA. Y axis corresponds to the time in ms.
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VII. FUTURE ENHANCEMENT Our next work is to implement the above said intelligent electrical power system using GSM and interpreting artificial intelligence to overcome the manual difficulties in providing control action to the consumers VII. CONCLUSION Therefore with the help of this project power consumption is minimized, power factor is maintained in good condition. One more advantage is no need of power cut consumer can utilize their power within their limit without any interruption. no man power or manual error in billing. ACKNOWLEDGMENT We express our preformed gratitude to Dr.A. NIRMAL KUMAR, Head of the Electrical and Electronics Engineering department his unique innovative plans, dynamic guidance with constant encouragement and motivation, which triggered us to great extent in completion. We are highly obliged and express our sense of gratitude to Mr. T. RAJESH M.E., Ms. M. VIDHYA M.Tech., for their valuable support and help. REFERENCES
[1] Chun-Sen Xu Xiang-Jian Chen Di Li Xiu-Hong Zhong Automatic Electric Meter Reading System Based on ZigBee, Wireless Communications, Networking and Mobile Computing, 2008. WiCOM '08. 4th International Conference on 12-14 Oct. 2008. Mora-Florez, J. Barrera-Nuez, V. Carrillo-Caicedo, Fault Location in Power Distribution Systems Using a Learning Algorithm for Multivariable Data Analysis, Power Delivery, IEEE Transactions on July 2007. Jayaweera, D., S. Galloway, G. Burt and J.R. McDonald, 2007. A Sampling Approach for Intentional Islanding of Distributed Generation. IEEE Trans. Power Syst., 22: 514-521. Bansal, R. C. Dr. (2005) "Optimization Methods for Electric Power Systems: An Overview," International Journal of Emerging Electric Power Systems: February 24, 2005 Agalgaonkar, A. P.; Kulkarni, S. V.; Khaparde, S. A.; and Soman, S. A. (2005) "Distributed Generation Opportunity under Availability Based Tariff and Reliability Considerations," International Journal of Emerging Electric Power Systems: Vol. 2 : Iss. 1, Article 1035. Yang Huping; Gu Yin; Zhang Yang; Bi Zhipeng; Reactive power optimization of power system based on interior point method and branch-bound method, Power Electronics and Intelligent Transportation System (PEITS), 2009 2nd International Conference on 19-20 Dec. 2009
Fig. 03 Normal condition
[2]
[3]
[4]
[5]
[6]
. Fig. 04 Power failure condition
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Autonomous Hybrid Renewable Energy System for Smart Grid Application

J.Vasanthakumar1,PG Scholar, Mrs.V.Sharmila Deve2, Assistant Professor Department of Electrical and Electronics Engineering Kumaraguru College of Technology, Coimbatore jvasanthirtt05@gmail.com.
Abstract:-In this paper, a hybrid generation system combining Photovoltaic (PV), Wind turbine (WT) and Battery is presented to supply stable power to residential power applications as standalone loads. The photovoltaic and wind systems are used as main energy sources while the Battery is used as storage device. Two individual DC/DC converters are used. Control with DC/DC converters is used for Maximum Power Point Tracker (MPPT) and hence maximum power extracting from the solar photovoltaic systems and wind turbine. The aim of this paper is to compensate power demand by renewable energy sources. If PV and WT generate power is lower than demand power, the Battery is controlled to discharge power to complete the difference of supply and demand power. If PV and WT generate power is higher than demand power, the Battery is controlled to charge power. The system was simulated by using MATLAB/Simulink. The simulation results show the proposed system can compensate power demand. Keywords: PV, Wind, Battery, Optimal dispatch controller, Matlab/Simulink
generator A statistic model of the wind speed [1] and a statistic model of the solar radiation are used as the inputs for the wind generator and the PV generator respectively. The single-phase grid inverter, boost converters on both generator sides are modeled by their local average behavior ignoring the switching transient. In the following sections, the different components of the system will be modeled, and the control strategies will be designed for the different parts of the system. Then simulation results using SIMULINK are presented for the whole system. II. PV Generator Model The PV generator is an array of PV modules connected in series and parallel. A simplified equivalent circuit of a solar cell consists of a diode and a current source which are connected in parallel. The photocurrent generated when the sunlight hits the solar cell can be represented with a current source and the P-N transition area of the solar cell can be represented with a diode. The shunt and series resistances represent the losses due to the body of the semiconductor and the contacts respectively. Such an equivalent circuit of the solar cell is shown in Fig. 2 [2-3]. The voltage and current relationship in the simplified solar cell model can be derived from Kirchhoff's current law. According to Kirchhoff's current law, all currents entering and leaving a node add up to zero. Then the output current can be calculated as in Eq. 2. In this equation, the last term can be neglected by assuming that the shunt resistance (Rsh) is very large. Eq. 2 is the solar cell model which can be used as one aggregated module model by considering the whole module working as a large area solar
I. Introduction Solar and wind energies, among other renewable energy sources, are the most available and distributed in all over the world. Applications with photovoltaic (PV) and wind have been increasing significantly due to the rapid growth of power electronic techniques. Generally, PV power and wind power are complementary since sunny days are usually calm and strong winds often occur on cloudy days or in nighttime. The hybrid PV-wind power system therefore has higher availability to deliver continuous power and results in a better utilization of power conversion and control equipment than either of the individual sources. A simulation and control study of a hybrid PV-wind generator system connected to the grid is proposed in this paper. Every major component of the system is modeled, and then the control strategies are applied to the system. Fig. 1 shows a simple diagram of the different components of the hybrid system connected to the grid. The PV generator is controlled by a DC/DC boost converter, where the duty ratio (Dpv) is used as the control means to track the maximum power (PMG) with a power electronic system that connects the wind turbine generator to the grid. The power electronic interface consists of; an uncontrolled rectifier, a boost DC/DC converter and the grid inverter that is shared with the PV generator. The Lead-Acid battery is also connected to dc bus. The power generated from the PV generator is supplied to the DC bus bar. The wind generator consists of a wind turbine directly driving a permanent magnet
Where, - Ipv: photovoltaic current -Io: Saturation current -Vs: Thermal voltage -Rs: Series Resistance -Rp: Parallel Resistance -a:Diode constant
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Fig.1. Block diagram of Hybrid Renewable Energy system time, the performance coefficient must be maximized. Therefore, it must be controlled. Its expression is,
=tip speed ratio of rotor blade tip speed to wind speed =the blade pitch angle Fig.2.Equivalent Circuit of Solar cell C1=0.51; C2=116;C3=0.4;C4=5;C5=21;C6=0.0068
III. Wind Generator Model: The wind generator subsystem consists of a wind turbine connected to a Permanent Magnet Synchronous Generator (PMSG) as shown in Fig. 1. We have considered that the blades are rigidly attached to the wind turbine; consequently the pitch angle of the blades is fixed, then the wind turbine mechanical torque produced by the wind energy, which drives the PMSG, can be modeled by Eq. 5 [4-5]. The expression of the output power is where, Pm=0.5AV3Cp (3) Fig.3.PV characteristics of solar cell
- Pm: Mechanical output power of the turbine (W), - Cp: Performance coefficient of the turbine, - : Air density (Kg/m3), - A: Turbine swept area (m2), - V: Wind speed (m/s). For a giving wind turbine, as the two parameters and A are constants, the value of the output power depends on the performance coefficient Cp and the wind speed. To maximize this output power, and as the wind speed is varying from time to Here,
-: Turbine angular velocity -R: Turbine radius
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against voltage (Pmpp-Vmmp) characteristics; the maximum power is obtained. A block diagram showing the maximum power point tracking control loop is shown in Fig. 5 [14][15].
By looking from the DC side of the rectifier, the PMSG can be modelled as a DC voltage source (Vw) and a series potential drop to represent the commutation overlap of the rectifier and the winding series resistance of the PMSG" as shown in Fig. 4. The series potential drop is the summation of the drop in the DC voltage due to the generator coil inductance and resistance Eq. 8, which can be modelled as an equivalent series resistance (Rw). From the equivalent circuit of the system shown in Fig. 2, the DC rectifier voltage can be calculated from Eq. 9.
Fig.5.MPPT control loop
V. Optimal Dispatch Controller:
The optimal dispatch controller, controls the flow of power to load. Input of controller is current of Solar, wind, load and battery State of charge(SOC). Solar and Wind current is greater than load current, the excess current stored in battery. Suppose battery SOC greater than 0.8 the battery should be disconnected. When Solar and Wind current less than load current, the remaining current from battery. If battery SOC is below 0.3, the battery should be disconnected. The controller
flow chart is shown in fig.6.
Fig.4. Circuit diagram for wind generator connected to DC bus IV. System Control Maximum power point tracking (MPPT) controllers are proposed to make the wind and the PV generators work in the maximum power mode that increases the energy captured from the wind speed and the solar radiation. IV.I. MPPT controller for PV generator The PV generator is a DC source, with its output characteristics depending on the solar radiation temperature and the load condition. To maximize the output power of the PV generator, a maximum power point tracking controller is implemented in the system. The controller proposed by measuring only the current in the output of the DC/DC converter. Due to the constant DC bus bar voltage in the output of the boost converter" the Power can be maximized by maximizing the boost Converter output current. This method is simple and suitable for this application [10]-[12]. IV.2.MPPT for wind generator The wind generator is an AC source of power, with its characteristics nonlinearly changing with wind speed and load condition. An MPPT controller is also implemented to maximize the output power of the wind generator. The DC/DC boost converter is used to maximize the power by measuring the DC output voltage of the rectifier (Vboosew) at the input of the boost converter and according to the curve fitting of the power.
Fig.6.Controller Algorithm Flow chart The controller is done by, write program on Embedded Matlab function.
Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore VI. Battery: For this simulation we are implementing the Lead-Acid battery. The battery have 200V and 2Ah rating. Initial battery charge 50%(SOC).
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Fig.7.Equivalent Circuit of battery where, -E : No load voltage (V) -E0 : Constant voltage (V) -K : Polarization voltage (V) -Q : Battery capacity (Ah) -A : Exponential voltage (V) -B : Exponential capacity (Ah)-1 VII. Simulation Circuit: The simulation circuit contains solar model, wind, battery and optimal dispatch controller. Solar, wind and battery are connected in parallel. A single phase bridge inverter connected to Dc bus. Five types of load connected to inverter side.
Fig.9. Load Profile IX. Simulation Results: IX.1. Load Current: The load current flows depend upon load profile as shown in Fig.10. At starting of simulation five different loads connected to system that is it takes 30A. After that 11A load is tripped and system has 19A current. during those loads solar, wind and battery are supplying the required current. Here the battery is discharged its power so load cannot take 19A current, due to that that particular load is tripped. Aftert hat required current is low, so solar and wind supplying those loads.
Fig.10. Load current IX.2. Comparison: The comparison of load current and load profile is shown in fig.11. Here the 19A load at duration of 80to 120 seconds, at 113 seconds, the particular load is tripped because generation is low and also battery reaches 30% of SOC.
Fig.8.Simulation circuit of Hybrid system VIII. Load Profile: The simulation is done by 200seconds.Initially full is connected, that is 30A load is connected for up to 80 seconds. After that 80 seconds to 120s (40 seconds), 19A load is connected.120 seconds to 160 seconds 4A load is connected. 160 seconds to 190 seconds 3A load is connected and finally 2A load is connected
Fig.11.Comparison of Load current with load profile
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[9] W.D. Kellog, M.H. Nehrir, G. Venkataramanan and V. Gerez, Generation unit sizing and cost analysis for standalone wind photovoltaic and hybrid wind/PV systems. IEEE Transactions on energy conversion. Vol. 13, N1, March 1998, pp. 70 -75. [10] Z. Salameh, F. Dagher and W. A. Lynch, Step-Down Maximum Power Point Tracker for Photovoltaic System, Solar Energy, Vol. 46, No. 1, pp. 278-282, 1991. [11] K. H. Hussein, I. Muta, T. Hoshino, and M. Osakada, Maximum Photovoltaic Power Tracking: An Algorithm for Rapidly Changing Atmospheric Conditions, IEEE proc. Gener. Transm. Distrib, Vol. 142, No. 1, pp. 59-64, Jan, 1995. [12] E. Koutroulis, K. Kalaitzakis, and N. C. Voulgaris, Development of a Microcontroller-Based Photovoltaic Maximum Power Point Tracking Control System, IEEE Trans. On Power Electronics, Vol. 16, No, 1, pp. 46-54, Jan, 2001. [13] K. Harada, G. Zhao, Controlled Power Interface between Solar Cells and AC Source, IEEE Trans. On Power Electronics, Vol. 8, No. 4, pp. 654-662, Oct, 1993. [14] S. Kim, and E. Kim, PSCAD/EMTDC Based modeling and analysis of a gearless variable speed wind turbine, IEEE Trans. On Energy Conversion, Vol. 22, no. 2, pp. 421-430, June 2007. [15] E. Koutroulis, and K. Kalaitzakis, Design of a maximum power tracking system for Wind-EnergyConversion applications, IEEE Trans. on Industrial Electronics, Vol. 53, no. 2, pp. 486-494, April 2006.
X. Battery SOC: Here battery discharging is shown in fig.the battery is tripped due its SOC reaches 30%.
Fig.12. Battery SOC curve XI. Conclusion: This paper presents a simulation and control for a autonomous hybrid PV-wind generator system connected to the DC bus. The dc voltage is inverted and used for load. The different components of the system were modeled and the control strategies for the different parts of the system were proposed. The simulation process illustrated the currents and voltages in the different components of the system with input conditions of solar radiation, wind speed and temperature. Reference:
[1] Stannard N, Bumby JR "Performance aspects of mains connected small-scale wind turbines "let Generation Transmission & Distribution 1 (2): 348356, MAR 2007 [2]Timothy U Townsend "A Simplified Method for Estimating the Long Term Performance of Direct Coupled Photovoltaic Systems" M.S. Thesis, Mechanical Engineering, U. of Wisconsin-Madison, 1989 [3] Martin A Green "Solar Cells: Operating Principles, Technology and System Applications" Prentice-Hall, Inc., Englewood Cliffs, N.J. 07632,1982 [4] Bumby JR, Martin R "Axial-flux permanent-magnet aircored generator for small-scale wind turbines",Proc. IEE - Electrical Power Applications" Vol. 152, No.5, September 2005, pp 1065-1075 [5] Bumby JR, Stannard N. and Martin R. 'A Permanent Magnet Generator for Small Scale Wind Turbines 'ICEM, 2006 [6] Ananed D K, Zmood R B "Introduction to Control Systems" British library cataloging in publication data, 1995, ISBN 07506-22989
[7] B.S. Borowy and Z.M. Salameh, Methodology for optimally sizing the combination of a battery bank and PV array in a wind/PV hybrid system. IEEE Transactions on energy conversion, Vol. 11, N2, June 1996, pp. 367- 375. [8] A.M. De Broe, S. Drouilhet and V. Gevorgian, A peak power tracker for small wind turbines in battery charging applications. IEEE Transactions on energy conversion, Vol. 14, N4, December 1999, pp. 1630-1635.
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Carrier Based Z-Source Inverter for Uninterruptible Power Supplies

K. CHITRA R. SENTHILKUMAR Department of Electrical and Electronics Engineering Bannari Amman Institute of Technology, Sathyamangalm. Chitra_pvs@rediffmail.com
Abstract - This paper proposes the performance
improvement of the Uninterruptible Power Supply (UPS) based on size reduction, efficiency improvement and power quality with the help of single phase Z-Source inverter where a symmetrical LC network is employed to couple the main power circuit of an inverter to a battery bank. The traditional inverters used for single phase UPS utilizes the step up transformer or dc-dc booster to increase the output voltage value. With the help of proposed Z-Source inverter any desired ac output voltage can be obtained by varying the boost factor. The boost factor is varied by varying the shoot through time period to boost the input voltage which is not allowed in traditional voltage source and current source inverter. To control the boost factor the carrier based control technique is proposed. The proposed UPS can maintain the desired ac output voltage at the significant voltage drop of the battery bank with high efficiency, low harmonics, fast response, single stage conversion, simpler and cheaper when compared with the traditional UPSs. The proposed UPS based on ZSI is modeled using MATLAB / SIMULINK with the carrier based control scheme and various factors such as output voltage, boost factor, THD are analyzed. Index Terms shoot-through, uninterruptible power supply (UPS), Z-source inverter, boost factor.
I. INTRODUCTION Uninterruptible Power Supplies (UPSs) provide clean and uninterrupted high quality power to critical loads such as communication systems, computers, life support systems in hospitals, data processing systems, industrial controls etc [1]. It provides emergency power under any normal or abnormal utility power conditions, including outages from a few milliseconds up to several hours duration. Mainly there are two types of traditional single phase UPS. The first type consists of ac/dc rectifier, battery, dc/ac inverter, step up transformer and filter. The second type of UPS consists of ac/dc rectifier, battery, dc-dc booster, dc/ac inverter and filter. The additionally used step up transformer and dc-dc booster in the conventional systems increases the weight, volume and cost of the system and also
decreases the efficiency. The voltage source inverter (VSI) and current source inverters (CSI) are the traditional inverters used to convert dc to ac in UPS. VSI and CSI can be used only for buck or boost the input voltage not for the buck-boost function. In the traditional inverters upper and lower switches of each phase leg cannot be triggered simultaneously, otherwise shoot-through will occur. So dead time in the pulse width modulation (PWM) signals has to be provided. Hence the output voltage waveform is distorted [4]. In this paper a new approach that is Z-source inverter is used for the single phase uninterruptible power supply (UPS). This ZSI overcomes the conceptual and theoretical limitations of VSI and CSI. This new topology offers the following advantages [4]: 1. The step up transformer is not needed to boost the voltage. 2. The ZSI provides a cheaper, simpler and single stage power conversion by combining dc-dc booster and dc/ac inverter. 3. The ac output voltage waveform distortion is reduced because the shoot through is allowed and the dead time in the PWM signals is absent in ZSI. 4. The Total Harmonic Distortion (THD) of the output voltage waveform is reduced under the pure resistive load and nonlinear load. 5. Fast transient response and good steady state performance can be achieved. The uninterruptible power supply (UPS) is classified into on line UPS, off line UPS, Line interactive UPS. In this paper on line UPS is used because the transfer time in the event of power failure is practically zero since the inverter is always ON. On line UPS provides the highest level of protection when compared with off line UPS. The Fig. 1 shows the block diagram of single phase UPS based on Z-source inverter. The main principle involved in this block diagram is by controlling the boost factor (shoot through time period) of Z-source inverter the output voltage of the UPS can be controlled.
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In this paper a new approach that is Z-souce inverter is used for the single phase uninterruptible power supply (UPS) which is shown in Fig. 4. This ZSI overcomes the limitations of traditional UPS. By increasing the shoot through time period in Z-source inverter the output voltage can be increased. Hence, this new topology does not require step up transformer or dc-dc booster to boost the voltage.
Fig. 1 Block diagram of single phase UPS based on ZSI
II. UNINTERRUPTIBLE POWER SUPPLY An uninterruptible power supply (UPS) is a device or system that maintains a continuous supply of electric power to certain essential equipment that must not be shut down unexpectedly [1]. The equipment is inserted between a primary power source, such as a commercial utility, and the primary power input of equipment to be protected, for the purpose of eliminating the effects of a temporary power outage and transient anomalies. The function of UPS is to provide clean, interrupt free supply of power to critical loads. This provides protection against power outages as well as suppressing incoming line transient and harmonic disturbances [1]-[3]. A. Traditional and Proposed UPS Mainly there are two types of traditional single phase UPS. 1. The first type consists of ac/dc rectifier, battery, dc/ac inverter, step up transformer and filter shown in Fig. 2. 2. The second type of UPS consists of ac/dc rectifier, battery, dc-dc booster, dc/ac inverter and filter shown in Fig. 3. In the first type of UPSs, the ac output voltage is higher than that of the battery bank; thus, a step-up transformer is required to boost the voltage. Due to the presence of the step up transformer, the inverter current is much higher than the load current, causing high current stress on the switches of the inverter. The transformer also increases the weight, volume, and cost of the system[3]. In the second type of UPSs, the additional booster is needed, leading to high cost and low efficiency. The controlling of the switches in the booster also complicates the system. Furthermore, the dead time in the pulse widthmodulation (PWM) signals to prevent the upper and lower switches at the same phase leg from shooting through has to be provided in the aforementioned two types of UPSs, and it distorts the voltage waveform of the ac output voltage[4].
Fig. 2. Traditional UPS with step up transformer.
Fig. 3. Traditional UPS with DC-DC Booster.
Fig. 4. Proposed UPS with Z-source inverter.
III. Z-SOURCE INVERTER The Z-source inverter employs a unique impedance network (LC network) to link the power source and inverter main circuit to provide both voltage buck and boost properties which cannot be obtained in traditional voltage source inverter (VSI) and current source inverter (CSI) where a capacitor and inductor are used respectively [4]. The Z-source inverter overcomes the conceptual and theoretical barriers and limitations of the traditional voltage source inverter (VSI) and current source inverter (CSI). As results, the new Z-Source inverter system provides ride-through capability under voltage sag, reduces line harmonics, and extends output voltage
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Z-source network makes the shoot-through zero state possible. This shoot-through zero state provides the unique buck-boost feature to the inverter. This shoot through zero state can be generated by three different ways: 1. shoot-through via first phase leg 2. shoot-through via second phase leg 3. combinations of two phase legs The ZSI has two operating modes: 1. Nonshoot-through mode 2. Shoot-through mode. Table 1 Switching states of Z-source inverter
Switching States Active state {1,0} Active state {0,1)} Null state {0,0} Null state {1,1} Shoot Through Zero state H1 Shoot Through Zero state H2 Shoot Through Zero state H3 S1 1 0 0 1 1 S1 1 S4 0 1 1 0 1 S1! 1 S3 0 1 0 1 S3 1 1 S2 1 0 1 0 S3! 1 1
range [5]. By controlling the shoot-through duty cycle and modulation index any desired output ac voltage can be obtained, thus there is no need for a dc-dc booster and step up transformer. The advantages of ZSource inverter are: 1. Buck-Boost operation at one stage 2. It minimizes the component counts 3. Increases the efficiency 4. Reduces the cost 5. Reduce inrush current and harmonics
Fig. 5. Z-Source Inverter (ZSI)
In Fig. 5, a two-port network that consists of a inductors (L1, L2) and capacitors (C1, C2) and connected in X shape is employed to provide an impedance source (Z-Source) coupling the inverter to the dc source. The dc source can be either a voltage or a current source. Therefore, the dc source can be a battery, diode rectifier, thyristor converter, fuel cell, an inductor, a capacitor, or a combination of those. Switches used in the inverter can be a combination of switching devices and diodes. A. Operating Principle & Equivalent Circuit of ZSI The unique feature of the Z-source inverter is that the output ac voltage can be any value between zero and infinity. That is, the Z-source inverter is a buckboost inverter that has a wide range of obtainable voltage. In Fig 5, the single-phase Z-source inverter bridge has seven permissible switching states (vectors) unlike the traditional single phase voltage source inverter that has four. The traditional single phase voltage source inverter has two active vectors when the dc voltage is impressed across the load and two zero vectors when the load terminals are shorted through either the lower or upper two devices, respectively. However, the single phase Z-source inverter bridge has three extra zero state (or vector) when the load terminals are shorted through both the upper and lower devices of any one phase leg (i.e., both devices are gated on) or any two phase legs. This shoot-through zero state (or vector) is forbidden in the traditional voltage source inverter, because it would cause a shoot-through. This zero state (vector) is called as the shoot-through zero state (or vector). The
Table 1 shows a total of seven switching states and their vector representations, where the switching function Sx (x =1, 2, 3, or 4) is defined as 1 when switch Sx turns on and as 0 when switch Sx turns off. Thus, the Z-source inverters have the following switching pattern [5]: 1. When two active vectors ({1 0}, {0 1}) are taken, the battery bank voltage is applied to the load through two inductances (L1 and L2) 2. When two null vectors ({0 0}, {1 1}) are taken, the load terminal is shorted by either the upper or lower two switches. 3. When the shoot-through zero vectors are taken, the load is shorted by the upper and lower switches at the same phase leg. B. Circuit Analysis and Output Voltage of ZSI Inductors L1 and L2 shown in Fig. 3.4 are assumed to have the same values and Z-source network is a symmetrical network[4]. L1 = L2 = L (1) VL1 = VL2 = VL (2) Capacitors C1 and C2 have the same values. C1 = C2 = C (3) VC1 = VC2 = VC (4) The shoot through state of the Z-source inverter is the operating state at which the switches in the same phase leg are turned ON. The H- bridge inverter is equivalent to a short circuit when the inverter is in the shoot-through zero state. During shoot through zero state the diode D is off. The Z-
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State
source inverter is working in shoot through states during time interval T0, during a switching period Ts. Shoot through time period (T0) is defined as the duration at which the switches in the same phase leg are turned on at the same time. Non shoot through time period (T1) is the duration at which the Z-source inverter is operating in any one of the two active states. TS = T1 + T0. (5) T0 = Ts - T1. (6) The equivalent circuit of the Z-source inverter in shoot through state is given in Fig. 6. From the equivalent circuit of Z-Source inverter during the shoot through state, the voltage equations are, V L = VC (7) (8) Vin = 0 Vd = 2VC (9)
The average voltage of inductor L1 (or L2) over one switching period in steady state operation is zero[4]. (VB - VC ) T1 + VC T0 = 0 (15)
VC= T1 VB T 1- T 0
(16)
Substituting (16) in (14)

V in = TS VB T 1- T 0
(17) (18)
V in = B V B
Where B is the boost factor.

B= TS T 1- T 0
1 1 - 2 T0 TS
(19) ; B1 (20)
B=
B=
1 1 - 2d
(21) (22)
d=
T0 TS
Fig. 6 Equivalent Circuit of ZSI in the shoot through State.
The non shoot through state of the Z-source is the one of the active switching states of the ZSI. When the Z-source inverter is working in non shoot through states during time interval T1, the diode D is on, and the H-bridge inverter can be considered as a current source Iin. The equivalent circuit of ZSI in the non shoot through state is shown in Fig. 7, and the voltage equations are VB = Vd (10) (11) VB = Vd = VC + VL V L = VB - V C (12) Vin = VC VL (13) Substituting the equation (12) in (13) Vin = 2VC VB (14)
Where, d is the shoot through duty ratio. If the voltage across the filter inductor is ignored, the output peak voltage of the inverter is given by, (23) V ac= M V in From the equation (18)
V ac = M BV B
(24) (25) (26)
BB = M B
V ac = M B V B = B B V B
Where, M is the modulation index. M 1. B is the boost factor B 1 BB is the Buck Boost factor. From the equation (26) the voltage gain of the ZSource inverter is given by,
V ac =M B=BB VB
(27)
Thus, any desired output voltage can be obtained by properly selecting the boost factor and the modulation index regardless of the battery bank voltage. 4. PWM CONTROL SCHEME OF ZSI The Z-source inverter has an additional zero state, called shoot through state. The methods used for
Fig. 7 Equivalent circuit of ZSI in the non shoot through
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Discrete, Ts = 5e-005 s. powergui DIODE RECTIFIER D
controlling the shoot through zero state are carrier based implementation, simple boost control method, maximum boost control and constant boost control. In this paper carrier based implementation control method is used to control the shoot through zero state. Fig. 8 shows the PWM switching sequence based on the triangular carrier method and the gate pulses for the switches S1, S2, S3 and S4 of the single phase ZSI. In every switching cycle, the two non shoot-through states are used along with two adjacent active states to synthesize the desired voltage. When the dc voltage is not high enough to generate the desired ac voltage, the additional shoot through states are used to boost the voltage. It should be noted that each phase leg still switches on and off once per switching cycle. Without change the total zero-state time interval, shoot-through zero states are evenly allocated into each phase. That is, the active states are unchanged. However, the equivalent dc-link voltage to the inverter is boosted because of the shoot-through states. The boost factor of the Z-Source inverter is given by,
B= 1 T -T 1 - 2 ( S 1) TS
1 1 - 2 (1-M )
Z-SOURCE INVERTER
Z-SOURCE L1
INVERTER
FILTER
g C
LOAD Io
C1
D1
D3
BATTERY C2
S1
S3 Lf
g C
+ i+v -
Vin Vo Io Scope
SINGLE PHASE AC SUPPLY D4 D2
Cf
RL
Vo
g C g C
S4
E
S2
E
L2
+v -
CARRIER BASED PULSE GENERATION
Fig. 9 Matlab/Simulink model of ZSI for UPS during normal power supply.
(28)
B=
(29) (30)
The simulated model of single phase Zsource inverter for single phase UPS during normal power supply is shown in Fig. 9. The input AC supply (230V peak - peak) is applied to the diode rectifier. The rectifier converts the AC into DC. This DC supply is given to the battery and the impedance source. The inverter gets the dc supply from the impedance source (Z-Source) which is used to boost the voltage. The AC output is taken from the inverter and given to the load through L-C filter.
Discrete, Ts= 5e-005 s. powergui DIODE RECTIFIER D
B=
1 2 M -1
Z-SOURCE INVERTER
Z-SOURCE L1
INVERTER
The voltage gain of the single phase ZSource inverter with simple boost algorithm is given by,
G= M 2 M -1
FILTER
g C
LOAD Io
C1
D1
D3
BATTERY C2
S1
S3 Lf
g C
+ i-
Vin
+ - v
SINGLE PHASE AC SUPPLY D4 D2
Vo Io Scope
Cf
RL
Vo
(31)
g C
S4
E
S2
E
For any desired voltage gain G, the maximum modulation index can be used is,
M= G 2 G -1
L2
+ - v
(32)
CARRIER BASED PULSE GENERATION
Fig. 10 Matlab/Simulink model of ZSI for UPS during power outage.
The simulated model of the single phase ZSource inverter for single phase UPS during power outage is shown in Fig. 10. During the power outage battery supplies the DC supply to the impedance source. In this paper the On-Line UPS is used since the inverter is always ON, the quality of load voltage is free from distortion. The firing pulses are generated using a carrier based control method. The triangular carrier
Fig. 8 Carrier based control scheme
g C
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wave is compared with dc voltages to produce the switching pulses for the switches S1, S2, S3 and S4. The Fig. 11 shows the switching pulses for the switches S1, S2, S3 and S4 in 1 second.
Fig. 13 Output voltage and current during power outage.
Fig. 11 Switching pulses for S1, S2, S3 and S4 in 1second
The Fig. 12 shows the output voltage and output current waveform for the single phase UPS based on single phase ZSI in 0.2 second during normal power supply Input Voltage (peak to peak) = 230V Output Voltage (peak to peak) = 300V Output Current (peak to peak) = 3A Boost Factor = 1.27 Shoot through time period = 2.15 ms The Fig. 13 shows the output voltage and output current waveform for the single phase UPS based on single phase ZSI in 0.2 seconds during power outage. During the power outage the battery supplies the power to the inverter. The uninterrupted power is supplied from the battery and there is no transfer time from normal mode to power outage mode.
The Fig. 14 shows the output voltage THD value for the ZSI. The THD value is high and the wave form is not pure sinusoidal before the filter. To obtain the pure sine wave L-C filter is used and the THD value is reduced. THD VALUE = 2.59%
Fig. 14 Output voltage THD 6. CONCLUSION In this paper the simulation of Z-Source inverter for a 2.5KW single phase UPS has been carried out. With the improved performance of ZSource inverter this UPS has the low total harmonic distortion and high efficiency. The Z-Source inverter overcomes the limitations of traditional inverters. By adjusting the shoot through state of the Z-Source inverter the boost factor can be varied. By increasing the boost factor the output voltage is increased, thus there is no need of step up transformer and dc-dc boost circuit. The boost factor is controlled by the carrier based control method. Simulation of single phase ZSI for UPS has been carried by using MATLAB / SIMULINK model and the results were obtained.
REFERENCES
Fig. 12 Output voltage and current waveform in 0.2 seconds
[1] M. S. Racine, J. D. Parham, and M. H. Rashid, An Overview of Uninterruptible Power Supplies, in Proceedings 37th Annual North American Power Symposium, Oct. 23 25, 2005, pp. 159164. [2] J. M. Guerrero, L. Garcia de Vicuna, and J. Uceda, Uninterruptible Power Supply Systems Provide Protection, IEEE Industrial Electrononics Magazine, vol. 1, no.1, spring 2007, pp. 2838.
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[3] C. G. C. Brancol, C. M. T. Cruz, R. P. Torrico-Bascope, F. L. M. Antunes, and L. H. S. C. Barreto, A transformerless single phase on-line UPS with 110V/220V input output voltage, in IEEE Power Electronics proceedings, Mar. 1923, 2006, pp. 348354. [4] F. Z. Peng, Z-source inverter, IEEE Transactions on Industrial Applications., vol. 39, no. 2, Mar./Apr. 2003, pp. 504510. [5] P. C. Loh, D. M. Vilathgamuwa, Y. S. Lai, G. T. Chua, and Y. W. Li,Pulse-Width Modulation of Z-source inverters, IEEE Transactions on Power Electronics, Vol. 20, No. 6, Nov 2005, pp.1346-1355. [6] S. Rajakaruna and Y. R. L. Jayawickrama, Designing Impedance Network of Z- Source Inverter, Power Engineering Conference, Vol.2, No.5, Mar/Apr 2005, pp.962-967. [7] J.M M. Shen, A. Joseph, J. Wang, F. Z. Peng, and D. J. Adams, Comparison of traditional inverters and Z-source inverter, in Proceedings of IEEE 36th Power Electronics, Sep. 1114, 2005, pp. 16921698. [8] Miaosen Shen and Fang Z. Peng, Operation modes and characteristics of the Z- Source Inverter with Small Inductance, IEEE Conference on Industrial Applications, IAS 2005, pp.1253-1260. [9] F. Z. Peng, M. Shen and Z. Qian, Maximum Boost Control of the Z-Source Inverter, IEEE Transactions on Power Electronics, Vol. 20, No. 4, July 2005, pp.833-838. [10]Quang-Vinh Tran, Tae-Won Chun, Algorithms for Controlling Both the DC Boost and AC Output Voltage of Z-Source Inverter, IEEE Transactions on Industrial Electronics, Vol. 54, No. 5, Oct 2007, pp.2745-2750. [11] F. Z. Peng, X. M. Yuan, X. P. Fang, and Z.M. Qian, Z-source inverter for adjustable speed drives, IEEE Transaction Power Electronics., vol. 1, no. 2, pp. 3335, Jun. 2003. [12] T. Meenakshi and K. Rajambal, Identification of an Effective Control Scheme for Z-source Inverter Asian Power Electronics Journal, Vol. 4, No.1, April 2010.
Chitra. K was born in Tamilnadu, India on May 2, 1981. She received the B.E degree in Electrical and Electronics Engineering from Bharathiyar University, in 1981. She is working as a lecturer in EEE department, Bannari Amman Institute of Technology. Currently she is doing part time M.E (PED) in Bannari Amman Institute of Technology, Sathyamangalam. Senthil Kumar.R was born in Tamilnadu, India, on November 2, 1966. He received the B.E degree in Electrical and Electronics Engineering from Madurai Kamaraj University, in 1989. He received his M.E (Power systems) from Annamalai University, in 1991. He has 15 yrs of teaching experience. Currently he is working as Associate Professor in EEE department, Bannari Amman Institute of Technology, Sathyamanglam. Currently he is doing research in the field of power converters for UPS Applications.
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Consideration and Implementation of Photovoltaic Power supply for Low power drives
Magal Chaithra and Megha Arora M.S.Ramaiah Institute of Technology Bangalore, Karnataka
Abstract: In this paper a model of boost converter and sinusoidal PWM single phase inverter which can be interfaced with solar arrays is proposed for low power AC drives. The model of boost converter proposed in this paper can be used to step up the voltage obtained from the solar array, this stepped up DC output is converted into AC using single phase PWM inverter for low power AC drives. This low power setup can be used in household applications, traction motors. The set up is controlled by digital technique and since this setup is compact and self sufficient can be used in drives required in railways. Both converter and inverter have individual control feedback which results in desired stepped up pure sinusoidal input for the AC drive.
Index Terms : PV Array, Boost Converter, PWM Single phase inverter, Gate drive circuits, Control feedback algorithm Introduction: Solar energy is best suited for most of the applications as it is environment friendly, cost effective. Solar cells convert sunlight directly into electricity using the photovoltaic (PV) effect. They are a promising technology for satisfying current and future energy demands in a sustainable and environmentally friendly way. However, the biggest hindrance in the commercial use of the SPV (solar Photovoltaic) is its high capital cost. But The initial estimates of the cost curves for Solar panels have proved to be overoptimistic [1].
Nevertheless the cost of the Solar arrays have come down a lot and as a result of this, the cost of the balance of system (BOS), i.e. components other than the SPV modules, have become comparable to the cost of the Modules. For small sized and low power systems the cost of the BOS may as 20% of the total cost of the system. Photovoltaic is made out of cells (Solar Cell), which are wired, together into a module. Many modules can be put together to make an array. We can generate useful amounts of electricity from a PV array. Each cell produces 0.5 volts when sunlight hits it. Lots of these cells can be put together to produce much higher voltages. The surface area of a cell and the intensity of the light hitting it determines the current. Cells can also be wired together to produce higher amounts of current. One square meter of PV at 10% would produce 100 Watts.. PV cells produce direct current (DC) power. The aim of this paper is to propose the system architecture for a photovoltaic power system for low power AC drives. Optimistically it can be suggested that the DC voltage of the Solar array can be stepped up using a DC step up converter and this DC power is inverted and utilized in low power drives. SYSTEM ARCHITECTURE: The setup consists of two sections. 1. Converter section:
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It consists of a boost converter, which gets 12v input from solar array. 12v input voltage is stepped up to 150v by giving a proper duty cycle while triggering IGBT. A control feedback algorithm is used for monitoring the output to maintain constant 150v output even if there is a drop in input from solar array. This is done by suitably varying the duty cycle after comparing the output with the desired value. The boost converter is a high efficiency step-up DC/DC switching converter. The converter uses a transistor switch, typically an IGBT, to pulse width modulate the voltage into an inductor. There are three main stages in this converter; Voltage boost stage, Feedback voltage control & Current monitoring. The heart of the design is the voltage boost stage. This stage consists of switch control, magnetic field storage element and power switcher. The feedback voltage control is to keep the output voltage constant at 24voltsnominal. Current monitoring is to prevent over load for output PV array and protect over current at the power switches. The DC/DC converters are widely used in regulated switch mode DC power supplies. The input of these converters is an unregulated DC voltage, which is obtained by PV array and therefore it will be fluctuated due to changes in radiation and temperature. In these converters the average DC output voltage must be controlled to be equated to the desired value although the input voltage is changing. From the energy point of view, output voltage regulation in the DC/DC converter is achieved by constantly adjusting the amount of energy absorbed from the source and that injected into the load, which is in turn controlled by
the relative durations of the absorption and injection intervals. These two basic processes of energy absorption and injection constitute a switching cycle. In other words, if the energy storage capacity of the converter is too smaller the switching period is relatively too long, then the converter would have transmitted all the stored energy to the load before the next cycle begins. This introduces an idling period immediately following the injection interval, during which the converter is not performing any specific task
Figure1: Block Converter
Diagram
of
Boost
The converter can therefore operate in two different modes depending upon its energy storage capacity and the relative length of the switching period.
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2. Single phase inverter:

The second most significant section of this power supply setup is Single phase inverter. This section gets supply of 150 DC volts from the Boost converter and converts it into 110 AC volts which can be used to drive single phase motor. The basic schematic diagram of photovoltaic inverter is as shown in the figure2. It consists of various blocks: single phase inverter, gate drive circuit and microcontroller. The power switches used for the inverter is considered as IGBT due to the benefits it provides as discussed in [5].The heart of the whole set up is microcontroller which provides the benefits of using digital methodology to generate the sinusoidal PWM signals to trigger the power switches i.e IGBTs used in photovoltaic inverter. Sinusoidal PWM is considered as control techniques as it assorts various benefits over other forms. The SPWM has advantages as high output quality, less Total harmonic distortion (THD). In case of SPWM techniques as the harmonics are pushed into a high frequency range decided by the switching frequency and also SPWM technique provides flexible control of output voltage and frequency with the line current being nearly sinusoidal in nature hence improving the overall power factor. The microcontroller consistently monitors the voltage levels at both input and output side to prevent the circuit from any sort of damage, depending on the voltage feedback control algorithm as discussed in latter in control approach section. Depending on the feedback it varies the duty cycle of the switches and hence the average value of the output voltage is maintained constant 110 AC volts. The microcontroller is also programmed to cut off the supply from load if it drops below the tolerance level ~ 2-5%. Apart from this a gate drive circuit is used which isolates the low power circuit from
the high control circuit to prevent it from damage.
Figure2: Block diagram of Inverter Section
Control Approach
A simple control technique is proposed in this paper. It uses voltagefeedback control technique where the output voltage of the boost converter is tracked continuously and compared with a reference voltage. The voltage difference is then used as a parameter for the microcontroller to produce a PWM signal with a set of duty cycle. PWM signal is used to control the switch SW in the boost converter. Figure3 shows the flow chart of the voltagefeedback control technique whereas Figure 9 shows the tracking process of the desired constant output voltage. With this control technique, any changes of the solar panel voltage will produce a constant output voltage at the end of the converter.
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From the proposed design, the boost converter is able to produce a constant output voltage of 150V from an inconstant solar panel voltage and inverter setup efficiently converts this boosted dc voltage to single phase AC output for low power AC drives. Microcontroller based control algorithms not only permits easy and efficient triggering of power switches in both converter and inverter but also efficiently monitors the output. The advantage of microcontroller is it easy to modify according to requirement as not in case of analog methodology. The total set up of the power system is simple, lightweight and small in size. For future works, It can also be used as power source for home appliances or standalone system.
Figure3 : Flow chart of the voltage-feedback control technique
References:
1. DESIGN AND SIMULATION OF DC/DC BOOST CONVERTER by B. M Hasaneen & Adel A. Elbaset Mohammed 2. Power electronics by Ned mohan, Udeland, Robbins 3. Development of High Efficiency Boost Converter for Photovoltaic Application IEEE journal 4. Development of a MicrocontrollerBased Boost Converter for Photovoltaic System, IEEE paper 5. Insulated gate bipolar transistor- IGBT
6. Technical paper By MITSUBISHI ELECTRIC B. Ismail, S. T. (November 28-29, 2006). Development of Single Phase SPWM Microcontroller-Based Inverter. First International Power and Energy Conference PEC (p. 437).Putrajaya, Malaysia: IEEE.
Conclusion
Figure4 : Block diagram of proposed system for photo voltaic low power system for drives
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Control of Power in a Transmission System Using D-FACTS Devices

Mereya Baby II M.E. Powersystems engineering Adhiyamaan College of Engineering, Hosur-Tamil Nadu 635 109 Email:mereyababy@gmail.com Phone No: 09495426829 R.Thilepa Assistant Professor Department of EEE Adhiyamaan College of Engineering, Hosur-Tamil Nadu 635 109
ABSTRACT
Flexible AC transmission systems (FACTS) devices can control power flow in the transmission system to improve asset utilization, relieve congestion, and limit loop flows.. D-FACT is a new concept for realizing the functionality of FACTS devices. In this technology total impedance or voltage required for the compensation has been distributed along the transmission line in series. It can be considered as a synchronous voltage source as it can inject an almost sinusoidal voltage of variable and controllable amplitude and phase angle, in series with a transmission line. Most of the injected voltage, which is in quadrature with the line current, provides the effect of inserting an inductive or capacitive reactance in series with the transmission line. This variable reactance influences the electric power flow in the transmission line. This paper illustrates the flexibility of control that is achievable with D-FACTS devices. D-FACTS converters are single-phase and floating with respect to the ground, there is no highvoltage isolation required between the phases. The impact of installing D-FACTS devices is examined by studying the sensitivities of power system quantities such as voltage magnitude, voltage angle, bus power injections, line power flows, and real power losses with respect to line impedance. Sensitivities enable us to quantify the amount of control D-FACTS devices offer to the system. Independently controllable lines are selected for power flow control and appropriate locations to install D-FACTS devices for line flow control are determined. Then, D-FACTS device settings are selected to achieve desired line flow objectives.
INTRODUCTION
A Flexible AC Transmission System incorporates power electronics and controllers to enhance controllability and increase transfer capability. This paper introduces the concept of a distributed static series compensator that uses multiple low-power single-phase inverters that attach to the transmission conductor and dynamically control the impedance of the transmission line, allowing control of active power flow on the line. The DSSC inverters are self-powered by induction from the line itself, float electrically on the transmission conductors, and are controlled using wireless or power line communication techniques. Implementation of system level control uses a large number of DSSC modules controlled as a group to realize active control of power flow. The DSSC can be used to either increase or decrease the effective line impedance, allowing current to be pushed away from or pulled into a transmission line. The DSSC concept overcomes some of the most serious limitations of FACTS devices, and points the way to a new approach for achieving power flow controlthe use of Distributed FACTS or D-FACTS devices.
POWER FLOW CONTROL

For controlling power flow on transmission lines, the series elements clearly have the highest potential and impact. The real and reactive power flow, P and Q , along a transmission line connecting two voltage buses is governed by the two voltage magnitudes V1 and V2 and the voltage phase angle difference,
( 1 2 )
as
163
P12
and
V1V2 sin XL
(1)
Q12
V12 V1V2 cos XL
(2) Fig1. Passive impedance injection as p.u. of XL (TCSC).
where is the impedance of the line, assumed to be purely inductive. A series compensator is typically used to increase or decrease the effective reactive impedance of the line, thus allowing control of real power flow between the two buses. The impedance change can be effected by series injection of a passive capacitive or inductive element in the line. Alternatively, a static inverter can be used to realize a controllable active loss-less element such as a negative or positive inductor or a synchronous fundamental voltage that is orthogonal to the line current [6], [7]. In the latter case, the power flow depends on the injected quadrature voltage Vq as
Fig 2. Quadrature voltage injection to achieve active impedance injection
P12
V1V2 sin V1Vq cos( / 2) XL XL

(3)
CONTROL POTENTIAL OF D-FACTS DEVICES.

For any power system, it is useful to be able to determine the control potential available from D-FACTS devices. Analysis of the control of power systems with FACTS devices [12], [13], [14] has been examined, but primarily with respect to transient stability, where FACTS devices can be used for control of certain modes of the system. In this work, we are interested in the ability of D-FACTS devices to provide control over line flows throughout the system. When effective line impedances change, power flows redistribute in the system. Our perspective is to show through steady-state analysis the ability of D-FACTS devices to control the way power flows distribute throughout the system. A. Identification of Independently Controllable Line Flows
sin( / 2) 2 v1 v 2 v 1 cos2 ( / 2) 2v v2 2
and the bracketed term is unity if V1=V2=V . Fig. 1 shows, for equal bus voltage magnitudes, the variation of power flow along a transmission line that can be achieved by injecting passive impedance or an active impedance [1].
In some scenarios, it may be clear which lines need to be targeted for control. The need to operate the system securely is costly but crucial.
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D-FACTS devices can be used to relieve a known overloaded element such as a line or transformer. The ability to relieve an overloaded element through the use of D-FACTS control is by itself a strong advantage. Since an overloaded line or transformer can prevent many power transfers from being able to take place, reducing the flow through the overloaded element by even a few percent improves the operation of the power grid. From a broader perspective, D-FACTS devices can be used throughout the system to provide the most comprehensive control. In order to provide the most complete and effective control for the entire system, it is necessary to identify how the control of line flows are related to each other. The coupling of the control of line flows is important to understand so that money and control effort are not wasted in attempts to independently control line flows which are highly coupled. The following matrices show trivial cases where controls of line flows are completely decoupled (a) and decoupled (b): x1 x 2 x3 x x 2 x3 a. b. 1
When the coupling index has an absolute value of 1, there is complete correlation, either positive or negative, between the ways the two line flows respond to D-FACTS control. When the coupling index is zero, the line flows have the ability to be controlled independently. B. Identification of Effective D FACTS Locations. D-FACTS devices are unique because they are well-suited to be placed at multiple locations in the system where their use could be the most beneficial. Comparatively, if only one FACTS device is used, all support goes to the same place. However, reactive power support is most effective locally. Sensitivities can be used to identify lines with a high impact for particular applications. Lines with higher sensitivities are able to provide more control, whereas lines with sensitivities of zero have no impact. The locations for D-FACTS devices are found by determining the lines with the highest sensitivities for the objective.
p fl ,1 1 0 0 p fl , 2 0 2 0 p fl ,3 0 0 1
p fl ,1 1 1 1 p fl , 2 2 2 2 p fl ,3 1 1 1
TRANSMISSION FLOW CONTROL
LINE
POWER
In the completely decoupled case, the vectors are orthogonal and the angle between them is exactly 90 degrees. In the completely coupled case, the row vectors are perfectly aligned and the angle between them is exactly zero degrees. When the row vectors are perfectly aligned but point in opposite directions, the angle between them is 180 degrees, but they are still completely coupled. Thus, coupling can be determined by comparing the cosine of angles of vectors [15]. The cosine of the angle between two row vectors v1 and v2
Once appropriate lines are targeted for control and effective locations for D-FACTS devices are selected, the problem of power flow control needs to be solved. The goal of the problem can be stated as a desire to attain specified line flows on any number of independently controllable lines through the control of line impedance settings of D-FACTS devices on a specified number of lines. It is not always possible to achieve a specified power flow on a line, so the line flow control equation, Pflow,calc(x) = Pflow,spec(x) (5) does not always have a solution. This is acceptable because line flow control is merely an additional benefit. The level of importance of a solution of the power balance equations is much higher than the line flow control equations. For any power system application, the power balance equations f (p,q) must always be satisfied, but if some control over the power
cos v1v 2
v1 .v2 v1 v2
(4)
of the total power flow to impedance sensitivity matrix + will be called the coupling index. The coupling index has values between -1 and 1.
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flow on a line can be achieved, that can be done as well. Optimization methods are useful for problems that do not have a solution [16]. The line flow control problem can be examined in an optimization framework which reflects the intuition behind what is being accomplished with D-FACTS devices. The objective is to choose D-FACTS line impedance settings to minimize the differences between the actual power flows and the desired power flows. The objective function is f0, where L is the number of line flows to be controlled:
Minimizing the objective function is equivalent to controlling real power line flows with DFACTS devices.
D-FACTS CONTROL FOR A GENERAL PROBLEM

The same control approach is extended to other power system problems as follows min 2(( ,) , ) (,) ( ( ,) ) = 0 (10) where f2 is the objective function for the problem of interest and D-FACTS devices are placed at locations in the system determined by the sensitivities of the objective function f2 to line impedance which are furthest from zero. The direction of steepest descent is given by f2, where f2 is the total derivative of the objective function with respect to x. Line impedance settings to minimize f2 are +1 = 2 (11) where is a positive, scalar step size. D-FACTS devices may then implement the final line impedance settings. This approach can be used to implement D-FACTS applications such as loss minimization and voltage control. A. Loss Minimization and Voltage Control. For loss minimization, if f2 is the losses, the total sensitivity to line impedances is given by f2 = . For voltage control including both raising and lowering system voltages, f2 is the sum of the differences of the bus voltages from specified values. The gradient f2, is given by f2, = 2 () V where V, the sensitivities of voltages with respect to line impedance, are the lower section of the state to impedance sensitivity matrix, = [, V] T. B. Comments on Other Solution Methods. The steepest descent optimization approach is a logical choice because it requires only knowledge of the sensitivities and the ability to solve the power flow, and it guarantees movement toward the optimum. The ability to guarantee descent is important since the goal is to determine the extent of D-FACTS abilities.
f o [ p flow ,calc ( x) p flow , spec ( x)] i2

i 1
(6)
The line flow control problem may be stated as follows: min 0 ( ,) ( (,) ) = 0 (7)
The first constraint of (4) represents the AC power balance equations. The next two constraints are constraints on how much DFACTS devices are able to change the line impedances. The gradient of f0 is given by the following, 0=2() (8) where the matrix is formed from elements of the power flow to impedance total sensitivity matrix, + . Thus, D-FACTS devices are able to control line flows on any lines with high enough sensitivities, not just their own line. Important connections exist between sensitivities and optimization theory [17], [18]. The sensitivities which determine independently controllable line flows and effective D-FACTS locations also exactly provide the gradient needed to solve (15) using steepest descent. Steepest descent steps are given by the following, where is a positive, scalar step size: +1 = 0 (9)
Knowledge of the total sensitivity of an equation to the control variables is enough to know how to minimize that function.
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One approach, often using Newtons method, treats the effective reactance of DFACTS devices as state variables and solves the modified power flow equations for the line impedances in addition to the other state variables. Problems include that Newtons method does not guarantee descent, may not converge, and may not exhibit expected behavior if started far from the solution. If second order sensitivities can be calculated or approximated, the class of Newton-like methods [18] may be worthwhile to investigate. Newtonlike methods also alleviate some of the problems with pure Newtons method.
SIMULATION
A controlled transmission system can be made up of a large number, of DSSC modules, each module containing a small rated single phase inverter, a communications link and a single turn transformer (STT) that is mechanically clamped on toand suspended fromthe transmission line conductor
closed relay contact (R1) that opens once control power is available. A current transformer is used to generate control power, allowing the DSSC module to operate as long as the line current is greater than a minimum level. The line appears to the inverter as an inductive current source. The single phase inverter uses four IGBT devices along with an output LC filter and a dc bus capacitance. The inverter output voltage is controlled using pulse width modulation techniques, and has two components. The first is in quadrature with the line current, and represents the desired impedance to be injected. The second is in phase with the line current, and allows compensation of power losses in the inverter, and regulation of the dc bus of the inverter. System commands for gradual changes are received from a central control center using a wireless or power line communication (PLC) technique.
Fig 3. Schematic power circuit. The STT uses the transmission conductor as a secondary winding, directly injecting the desired voltage into the cable itself. The inverter is self-powered by induction from the line, and can be controlled to inject a voltage that is orthogonal to the line current directly into the conductor. The module can either be suspended from the conductor or configured as a replacement for the conductor support clamp on an insulator. Further, since it does not require supporting phase-ground insulation, the module can easily be applied at any transmission voltage level. When the transmission line is not powered up, the STT is bypassed by a normally Fig 3. Simulation diagram
Fig4. Active power
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Existing Power Lines, IEEE Transactions on Power Delivery, Vol. 22. [5] H. Johal, D. Divan, Design Considerations for Series-Connected Distributed FACTS Converters, IEEE Transactions on Industry Applications, Vol. 43, No. 6. [6] D. G. Ramey, R. J. Nelson, J. Bian, T. A. Lemak, Use of FACTS Power Flow Controllers to Enhance Transmission Transfer Limits, Proceedings of the American Power Conference, [7] L. Gyugyi, C. D. Schauder, K. K. Sen, Static Synchronous Series Compensator: A Solid-State Approach to the Series Compensation of Transmission Lines, IEEE Transactions on Power Delivery, Vol. 12, No. 1. [8] L. Gyugyi, C. D. Schauder, S. L. Williams, T. R. Rietman, D. R. Torgerson, A. Edris, The Unified Power Flow Controller: A New Approach to Power Transmission Control, IEEE Transactions on Power Delivery, Vol. 10. [9] L. Gyugyi, Dynamic Compensation of AC Transmission Lines by Solid-State Synchronous Voltage Sources, IEEE Transactions on Power Delivery, Vol. 9, No. 2 [10] O. Alsac, J. Bright, M. Prais, B. Stott, Further Developments in LP-Based Optimal Power Flow, IEEE Transactions on Power Systems, Vol. 5, No. 3. [11] W. F. Tinney, V. Brandwajn, S.M. Chan, Sparse Vector Methods, IEEE Transactions on Power Apparatus and Systems, Vol. PAS-104, N [12] X. R. Chen, N. C. Pahalawaththa, U. D. Annakkage, C. S. Kumble, Controlled series compensation for improving the stability of multi-machine power systems, IEE Proceedings: Generation, Transmission and Distribution, v 142, [13] H. Okamoto, A. Kurita, Y. Sekine, A method for identification of effective locations of variable impedance apparatus on enhancement of steady-state stability in large scale power systems, IEEE Transactions on Power Systems, v 10, n 3. [14] X. R. Chen, N. C. Pahalawaththa, U. D. Annakkage, C. S. Kumble, Output feedback TCSC controllers to improve damping of meshed multi-machine power systems, IEE Proceedings: Generation, Transmission and Distribution, v 144, n 3.
Fig 5. Voltage and Current wave forms.
CONCLUSION
D-FACTS devices have the unique ability to be incrementally installed on multiple lines throughout a system to provide power flow control wherever needed. Effective D-FACTS device locations and independently controllable flows can be identified from sensitivities. After D-FACTS devices are installed in certain fixed locations, their control objective can easily be changed to target other lines flows. Thus, D-FACTS devices can provide widespread, versatile control for power systems. In this paper, the successful control of line flows with D-FACTS devices is presented for two test systems. A general approach for line flow control with D-FACTS devices is developed. The use of sensitivities in solving nonlinear problems can be extrapolated to any application of interest and to any system.
REFERENCES
[1] FACTS Working Group, Proposed Terms and Definitions for Flexible AC Transmission System (FACTS), IEEE Transactions on Power Delivery, Vol. 12, Issue 4, [2] P. Hassink, D. Matthews, R. O'Keefe, F. Howell, S. Arabi, C. Edwards, E. Camm, Dynamic Reactive Compensation System for Wind Generation Hub, IEEE PES Power Systems Conference and Exposition, [3] D. Divan, Improving Power Line Utilization and Performance With D-FACTS Devices, IEEE PES General Meeting, June 2005 [4] D. M. Divan, W. E. Brumsickle, R. S. Schneider, B. Kranz, R. W. Gascoigne, D. T. Bradshaw, M. R. Ingram, I. S. Grant, A Distributed Static Series Compensator System for Realizing Active Power Flow Control on
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Design and Application for PV Generation System Using a Soft-Switching Boost Converter with SARC
Balamurugan.T, S.Arunkumar MOUNTZION COLLEGE OF ENGG., & TECH,PUDUKKOTTAI balathamizhan.be@gmail.com
AbstractIn order to improve the efficiency of energy conversion for a photovoltaic (PV) system, a soft-switching boost converter using a simple auxiliary resonant circuit, which is composed of an auxiliary switch, a diode, a resonant inductor, and a resonant capacitor, is adopted in this paper. The conventional boost converter decreases the efficiency because of hard switching, which generates losses when the switches are turned on/off. During this interval, all switches in the adopted circuit perform zerocurrent switching by the resonant inductor at turn-on, and zero-voltage switching by the resonant capacitor at turn-off. This switching pattern can reduce the switching losses, voltage and current stress of the switching device. Moreover, it is very easy to control. In this paper, we have analyzed the operational principles of the adopted soft-switching boost converter, and it is designed for PV generation system. Simulation and experimental results are presented to confirm the theoretical analysis.
1. INTODUCTION
Before increased research about renewable energy, most of the energy used in industry depended on fossil fuel. But these days, because of fuel fossil exhaustion, which is due to limited reserves and environmental problems, the development and demand for renewable energy has increased. Fuel cells, water, wind, and photovoltaic (PV) energy are all renewable energy sources. Of these, PV energy is limitless and cleans. The solar cell has nonlinear V I and PV characteristics, which depend on the irradiance, the operating temperature and load condition of the cell. Therefore, the dcdc converter for a PV system has to control the variation of the maximum power point of the solar cell output. In other words, modulation of the duty ratio of the dcdc converter controls maximum power point tracking Recently, switch-mode power supplies has become smaller and lighter, because the
switching frequency has increased. However, as the switching frequency has increased, the periodic losses at turn-on/off have also increased. As a result, this loss brings increasing loss of whole system. Therefore, to reduce these switching losses, a soft-switching method is proposed, which involves an added auxiliary circuit, instead of a conventional hard-switching converter. However, the auxiliary circuit for resonance increases the complexity and cost. For some resonant converter with auxiliary switch, main switch achieves soft-switching but auxiliary switch performs hard switching. Thus, these converters cannot improve the whole system efficiency owing to switching loss of auxiliary switch. This paper proposes the soft-switching boost converter applied to an auxiliary resonant circuit for a PV generation system. It has better efficiency than a conventional boost converter. Moreover, this converter boosts the lower output voltage of the solar cell to the useful voltage for the load. The adopted converter has a simple auxiliary resonant circuit (SARC). Through this circuit, all of the switching devices perform softswitching under zero-voltage and zero-current conditions. Therefore, the periodic losses generated at turn-on and turn-off can be decreased. The adopted soft-switching boost converter is designed for a 700 W PV module. In this paper, the adopted soft switching boost converter is simulated by Power Sim (PSIM) software. Furthermore, its performance is confirmed by the PV Simulator and experimental setup.
Fig.1 Equivalent circuit of PV cell
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2. CHARACTERISTICS OF SOLAR CELL AND MODULE A solar cell is a kind of p-n junction semiconductor device. It converts light energy into electrical energy. Generally, as shown in Fig. 1, the equivalent circuit of the solar cell is composed of the internal serial resistance (Rs) and the shunt resistance (Rsh) of the diode. The output characteristics of the solar cell depend on the irradiance and the operating temperature of the cell. The solar cell output characteristics are expressed as [2], [13] Fig.3 Block diagram of the soft-switching boost converter. ----- (1) In (1), it is assumed that Rs equals zero and that Rsh equals infinity; thus, the equation can be simplified as If irradiance increases, the fluctuation of the open-circuit voltage is very little. However, the short circuit current has sharp fluctuations with respect to irradiance. However, for a rising operating temperature, the variation of the shortcircuit current is decreased, and the open-circuit voltage is decreased in a nonlinear fashion. As shown in Fig. 2, the output-voltage range of the PV module varies. Owing to this characteristic, the adopted converter must be designed for soft switching based on the outputvoltage range of the PV module.
------- (2) Irradiance and operating temperature are important factors influencing the solar cell characteristics. Fig. 2 shows the IV curves of the PV module.
3. BACKGROUND TO PV GCI TOPOLOGIES

An early type of GCI is the currentsource inverter (CSI) as shown in Figure 1a. In this GCI, a DC link inductor was utilized to act as a current source and a line frequency commutated inverter accommodated to produce a square-wave output current. Although, this concept is simple, it requires substantial filtering at the output stage to meet the grid harmonic standards.
Fig. 2. Simulated IV characteristic curves of Solarsim-10k. Figure 4: Existing converter topologies for PV systems a) CSI topology b) VSI topology c) Two-stage VSI with DC-DC boost converter.
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The most common GCI configuration uses a voltage source inverter (VSI), as shown in Figure 1b. Unlike the CSI topology, a large DC link capacitor is utilized to produce a constant input voltage. Then, a pulse-width modulated (PWM) inverter is used to generate a sinusoidal AC output current. The VSI topology tends to be slightly cheaper and more efficient than the CSI topology as the DC link capacitor has lower losses and may be lower cost than the DC link inductor [2]. It should be noted here that the power grid can also be treated as a voltage source. Figure 1c shows a two-stage converter topology which consists of a DC-DC boost converter and a VSI inverter. In this circuit, the boost converter performs maximum power point tracking (MPPT) for the PV panel, while delivering a constant DC input voltage to the VSI that is controlled to produce a sinusoidal output current. Although single-stage converters result in size and weight reductions compared with two-stage converters [2], they require more complex control algorithms to operate correctly, especially when employing MPPT [3]. On the contrary, two-stage converters often suffer in terms of efficiency and reliability due to the increased number of switching components.
The circuit uses a DC link inductor (L) in series with the PV panel to produce a constant-current source (Figure 2). A boost switch (will be named as a current wave shaper, WS in this paper) is used to produce a PWM output current that resembles a rectified sine wave that is in-phase with the grid. The thyristor based H-bridge inverter in the circuit unfolds the output of the current wave-shaper to produce a sinusoidal AC output current. An output LC filter (CF and LF) is used to remove the PWM switching components (Figure 2).
Figure 5 Proposed current source inverter topology the grid connected PV systems In the proposed circuit given above, when supplied from a DC current source, the boost switch produces an output current which is proportional to (1 d), where d is the PWM duty-cycle of the switch. Though the boost switch (WS) resembles a boost converter, under these Circumstances it operates as a current divider, or current wave shaper. An important feature of the circuit is that, due to the current control scheme implemented, the control algorithm does not require the use of an output current sensor. The H-bridge inverter (unfolding circuit) in the circuit is controlled by a microcontroller, which is also used to detect zero-crossings of the mains voltage and to control the duty-cycle of the WS switch. In addition, the microcontroller stores a look-up-table (LUT) that includes the reference current waveform. As can be seen in Figure 3, the thyristor switching is determined from the zero-crossing of the mains voltage (Vref), which ensures an output current that is synchronised with the grid voltage.
4. PROPOSED PV CONVERTER TOPOLOGY

A desirable primary feature of a GCI circuit is to feed a sinusoidal current into the grid, which is in phase with the grid voltage, hence a maximum power factor can be achieved and the power grid will not be polluted. In addition, it is also desirable that the GCI system should be efficient, low cost and high power density. The proposed two-stage PV GCI topology is based on a current-source inverter and illustrated in Figure 2. This circuit topology is an extension of a Switched-Mode rectifier (SMR) circuit that was originally proposed for automotive applications, where it acted as a DCDC converter. The SMR concept was investigated for use with a small-scale wind turbine in [6] as a current-source inverter. This paper examines the use of the SMR circuit topology with a PV cell, to operate as a gridconnected inverter.
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It should be emphasised here that although the thyristors in the H-bridge commutate at zero-currents, the on resistance of the WS switch creates a current divider with the load; thus the thyristors can only commutate properly if the on resistance of the switch is sufficiently low. This ensures that the load current is less than the latching current of the thyristor It should be reported here that due to the addition of an external inductor in the circuit proposed, the operation of the converter circuit is similar to the concept developed in , where the alternator itself had a large winding inductance. Furthermore, it can be noted that unlike the permanent magnet generator implemented in the PV cell application has a much greater constant current region (hence a wider power range), as seen in Figure 6. .
2) The parasitic components of all switching devices and elements are negligible. 3) The input voltage (Vs) is in the range of 150230 V. 4) This converter operates the continuous conduction mode at all intervals.
Fig. 7. Operational modes of the soft-switching boost converter for the PV generation system.
6. DESIGN PROCEDURE OF RESONANT INDUCTOR ANDCAPACITOR IN SARC

Fig.6 Current-Voltage Curves of a high inductance PM generator (left) and a PV cell (right). A. ZVS Condition of Switch To satisfy the zero-voltage switching (ZVS) condition, the resonant inductor current must exceed the main inductor current during the freewheeling interval of interval 4. During interval 4, the voltage of the resonant inductor and the current are expressed by (5) and (6), respectively. The ZVS condition of this converter is expressed by (7)
5. SOFT-SWITCHING BOOST CONVERTER FOR PV GENERATION SYSTEM

In Fig. 3, the adopted converter is controlled by ATmega128, which is an 8-bit microprocessor used to implement an MPPT [perturb and observe (P&O)]. Moreover, the PV simulator Solarsim-10K supplies the energy to this converter. The auxiliary circuit is composed of an auxiliary switch (S2), a resonant capacitor (Cr), a resonant inductor (Lr), and two diodes (D1 and D2). Shown in Fig. 4, the operational principle of this converter can be divided into six intervals. For a simple analysis of each interval of this converter, the following assumptions are made. 1) All switching devices and passive elements are ideal.
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B. Resonant Inductor In Fig. 6, the time of interval 2, which is the rising time of the resonant inductor current, is expressed by (10). For the maximum resonant current, the time of interval 3, which is the resonant time of the resonant inductor and capacitor, is defined as one-fourth of the resonant period. As a rule of thumb, the rising time of the resonant inductor current (intervals 23) can be set to 10% of the minimum on time. This is expressed as (12)
Fig. 8 shows the main inductor current and the pulse width modulation (PWM) gate signal of the main switch. When the main switch is turned on, the energy of inductor is accumulated. When it is turned off, this energy is transferred to the output. Fig. 9 shows the current and voltage waveforms of the switch. Via resonance of the resonant inductor and capacitor, ZVS and ZCS are achieved at turn-on and turn-off.
From (9) and (12), the resonant inductor is expressed as
C. Resonant Capacitor The resonant capacitor is connected to the switch in parallel. Thus, the waveforms of the resonant capacitor voltage and switch voltage are equivalent at turn-off. To satisfy the ZVS condition, the resonant capacitor can be selected to exceed ten times the output capacitance of the switch. However, the capacitor is charged by the main inductor current and the resonant inductor current at turn-off. Thus, it can be selected to exceed twenty times the output capacitance of the switch. Equation (12) is simplified to
Fig. 7 PSIM schematic of the converter topology.
The design of the resonant inductor and capacitor are based on (13) and (14).
Fig. 8. Simulated waveforms of the gate signal
This paper simulated the adopted softswitching boost converter and the PV module modeling of 700 W using the PSIM software.
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9. REFERENCES [1] Kjaer, S.B.; Pedersen, J.K.; Blaabjerg, F., "A review of single-phase grid-connected inverters for photovoltaic modules," IEEE Transactions on Industry Applications, vol. 41, no. 5, pp. 1292-1306, Sept.-Oct. 2005. [2] Calais, M.; Myrzik, J.; Spooner, T.; A gelidis, V.G., "Inverters for single-phase grid connected photovoltaic systems-an overview," IEEE Power Electronics Specialists Conference, vol. 4, pp. 1995-2000, 2002. Fig. 9. Simulated waveforms of the main switch voltage and the current. [3] Kuo, W.C.; Liang, T.J.; Chen, J.F., "Novel maximum power- point-tracking controller for photovoltaic energy conversion system," IEEE Transactions on Industrial Electronics, vol. 48, no. 3, pp.594-601, Jun 2001. [4] Soong W.L. and Ertugrul N., Inverterless High Power Interior Permanent Magnet Automotive Alternator, IEEE Transactions on Industry Applications, 2004, Vol. 40, no. 4, July/Aug, pp. 1083-1091. [5] J.-P. Lee, B.-D. Min, T.-J. Kim, D.-W. Yoo, and J.-Y. Yoo, Design and control of novel topology for photovoltaic dc/dc converter with high efficiency under wide load ranges, J. Power Electron., vol. 9, no. 2, pp. 300307, Mar. 2009.
[6] J.-J. Lee, J.-M. Kwon, E.-H. Kim, and B.-H. Kwon, Dual series resonant active clamp converter, IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 699 710, Feb. 2008.
8. CONCULSION
In this paper, we proposed a softswitching boost converter, which involved an added SARC in the conventional boost converter. This soft-switching boost converter is easy to control because the two switches are controlled by the same PWM signal. All of the switching devices in this converter achieved ZCS and ZVS by the resonant inductor and capacitor at turn/off. Therefore, the switching losses were reduced dramatically. The key results are : the DC link inductor must be sized carefully to minimize voltage and current ripples seen by the PV module, hence to maximize output power; the control of the current wave-shaper and the H bridge are simple, as the output current is linearly related to dutycycle; maximum power point tracking can be performed by monitoring the solar cell output power. This soft-switching boost converter can be applied to a stand-alone and a grid-connected system using a PV power conditioning system.
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Design and Implementation of Four Wire Inverter for UPS Applications

T. Alex Stanley Raja R. Senthil Kumar
Department of Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Anna University Tamil Nadu, India. E-mail: ramsenthil2@gmail.com
Department of Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Anna University, Tamil Nadu, India. E-mail: alexstanleyraja@gmail.com
Dr. Jovitha Jerome

Department of Control and Instrumentation Engineering, PSG College of Technology, Anna University, Tamil Nadu, India. E-mail: jjovitha@yahoo.com
ABSTRACT: - A method of harmonic elimination and output voltage control of a four leg inverter based three phase UPS is proposed. This paper presents the feedback loop control scheme for voltage source uninterruptible power supply (UPS) inverter with filter. The use of a four wire inverter increases the quality of the output whereas the implementation of soft switching technique increases the overall efficiency of the inverter by decreasing switching losses. Furthermore, in order to be able to respond load variations a feedback loop is constructed with a PI controller to realize closed loop control. The four leg inverters are used in many applications to handle the neutral current caused by the unbalanced and non-linear load. The main feature of a three phase inverter, with an additional neutral leg, is its ability to deal with load unbalance and maintain the desired sinusoidal output voltage waveform for all loading conditions and transients. The feasibility of the proposed modulation technique is verified by computer simulation and the experimental analysis of the four wire inverter is also discussed in this paper.
to control the neutral voltage and hence produces balanced voltages across each phase is Vdc.The two additional power switches in four wire doubles the number of inverter output states from 8(=23) to 16(=24).This improves the quality output waveform[9].UPS requires sinusoidal output with minimum total harmonic distortion[10]. It is achieved by using sinusoidal pulse width modulation (SPWM) technique. In this technique, the load voltage is compared with a reference voltage and the difference in amplitude is used to control the modulating signal in the control circuit of the power inverter. The three phase four wire inverter is suitable for high power UPS for its advantage of feeding unbalanced load and the higher dc voltage utilization [6]. The functional block diagram for four wire inverter is shown in Fig.1.The load neutral point voltage for the three phase four wire inverter is shown in Fig.2.
Index Terms - Four wire inverter, PLL, Soft Switching, THD, UPS. I. INTRODUCTION The four leg inverter is utilized in three phase four wire power converter and UPS applications due to its performance characteristics such as relatively low DC bus voltage and switching loss and capability to handle unbalanced load currents[1]. The fourth leg provides a path for the zero sequence currents for non-linear and unbalanced loads. Conventional three phase three wire inverters are suitable for supplying three phase balanced loads. For unbalanced three phase loads these four wire inverters able to provide a path for the neutral current. The two main ways for neutral wire connection are Inverter with split dc link capacitors Inverter with fourth (neutral) leg [2]. The first way is simplest one but it generates the zero sequence harmonics and a high voltage ripple over supply capacitor is produced by neutral currents when the load is unbalanced or non-linear. The second way requires additional power switches and quite complex control strategy. It offers different advantages, such as increased maximum output voltage value, a reduction of neutral currents and the possibility of neutral point voltage control[3],[4],[5]. In four leg inverters the load neutral wire is connected to the fourth leg as shown in Fig 2. This provides the flexibility
Fig.1.Functional Diagram for Four Wire Inverter
Fig.2.Three Phase Four Wire Inverter
The Fig.3 shows the block diagram for the four wire inverter for online UPS.
There are 14 non-zero voltage vectors and two zero vectors(1111),(0000).The three phase variables Kr, Ky and Kb can be transferred as orthogonal coordinates K ,K ,K using eq(1). Any three phase sinusoidal set of quantities can be transformed to an orthogonal reference. For given switching states of the inverter, the voltage vector components can be calculated as,
K K K
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Fig.3.Block Diagram of Four Wire Inverter for Online UPS
The main components of the UPS are rectifier, battery, four wire inverter, switches and load. When the main supply is present, the rectifier provides power to an inverter as well as battery ands it is charged. The inverter is on and feeds power to the load through UPS switch. The UPS switch is always ON and connects load to inverter output. The main switch is always off. But when the UPS fails, then load is connected directly to the mains through main switch. When the supply is not available, then battery bank supplies power to an inverter. Thus an inverter is always ON and it takes power from rectifier or battery. This paper is organized as follows: Section II provides the description of the four wire voltage source inverter. Selecting a feedback variable for the closed loop control circuit structure, controller for the proposed control strategy, operation and simulation and zero voltage switching are proposed in section III. Matlab implementation for the four wire inverter with system parameters are proposed in section IV. Section V provides the simulation results for four wire inverter with controller. The four inverter is experimentally verified in section VI. Finally conclusion is drawn in section VII. II. DESCRIPTION OF FOUR WIRE VOLTAGE SOURCE INVERTER The comparison of a three phase four wire voltage source inverter as shown in table I.
TABLE I COMPARISON OF 4-WIRE 3- PHASE INVERTER S.NO PARAMETER THREE PHASE THREE WIRE LOAD 1. 2. Number of required power switches Equivalent topology 3 independent single phase half bridge. 3 dependent single phase full bridge. 6 THREE PHASE FOUR WIRE LOAD 8
with respect to arbitratory reference. If axes are stationary and the -axis is aligned, then =0 at all times.
Where
cos cos( 2 / 3) cos( 4 / 3) =2/3 sin( 2 / 3) sin( 4 / 3) sin 1/ 2 1 / 2 1/ 2
K K K
r y b
(1)
is the angle of orthogonal set
Thus, we get
1 1 K 1 Kr =2/3 2 2 Ky K 0 3 3 K 2 2 K 1 1 1 b 2 2 2
(2)
The above matrix can be re-written as K =

K = K =
1 (2KR-KY-KB) 3 1 3
(KY-KB)
(3) (4) (5)
1 (KR+KY+KB) 3
TABLE II SWITCHING COMBINATION AND OUTPUT VOLTAGES FOR 4-WIRE 3 PHASE INVERTER SWITCHING STATES Vyn Vbn V V V Vrn 0000 0 0 0 0 0 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 Vdc Vdc Vdc Vdc - Vdc - Vdc - Vdc - Vdc 0 0 0 0 0 Vdc Vdc 0 0 Vdc Vdc - Vdc - Vdc 0 0 - Vdc - Vdc 0 0 Vdc 0 Vdc 0 Vdc 0 Vdc - Vdc 0 - Vdc 0 - Vdc 0 - Vdc 0 -1/3Vdc - 1/3Vdc - 2/3Vdc 2/3Vdc 1/3Vdc 1/3Vdc 0 0 -1/3Vdc - 1/3Vdc - 2/3Vdc 2/3Vdc 1/3Vdc 1/3Vdc 0 - 1/3Vdc 1/3Vdc 0 0 - 1/3Vdc 1/3Vdc 0 0 - 1/3Vdc 1/3Vdc 0 0 - 1/3Vdc 1/3Vdc 0 1/3Vdc 1/3Vdc 2/3Vdc 1/3Vdc 2/3Vdc 2/3Vdc Vdc -Vdc - 2/3Vdc - 2/3Vdc -1/3Vdc - 2/3Vdc -1/3Vdc -1/3Vdc 0
3.
Number of the output vectors
6(no zero vectors) 0.5Vd
16(14 active + 2 zero vectors) 0.577Vd
4.
Max achievable peak value of line to neutral voltage.
There are sixteen switch combinations possible in four leg inverters. The switching vectors are represented by states [Sn, Sr, Sy, Sb] of the inverter legs.
When the leg is denoted by 1 the upper switch is closed when the leg is 0 the lower switch of the leg is closed. The switch positions determine the phase to neutral voltages, which are transformed to coordinates using eq(2).Table II shows the phase to neutral voltages and
INFO Institute of Engineering, Coimbatore transformed voltages for each inverter switching state. The three phase four wire voltage source inverter, commonly used for three phase voltage generation as shown in Fig.4. It consists of eight switches Srp-Sxn and inductor LR-LX and capacitors CR-CB.The LC filter filters out the switching harmonics. The voltage source inverter able to generate balanced and high quality ac output voltage, shown in Fig.4. The three phase output voltage waveform shown in Fig.4. One line cycle is divided into six regions. In region 060, 120180and 240300, the voltage waveforms in Fig. 4 have similar pattern, i.e., one-phase voltage is always lower than the other two [7][11].
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6(a)
Fig.4. Three phase output voltages
6(b)
Fig.6. Equivalent circuit for four wire VSI for 60120
The main circuit diagram Fig.2 is equivalent to Fig.5 (a) in 060egion, which can be further organized into Fig.5 (b). The same equivalent circuit is also applicable to 120 180 and 240300 regions. The switching of inverter is shown in table III
For further analysis, following assumptions are made. 1) LR = LY = LB = LX = L. 2) CR = CY = CB = C. 3) Switching frequency is much higher than fundamental frequency
TABLE III SWITCHING LOGICS FOR PROPOSED CONTROLLER SWITCHES S1 S2 S3 S4 S5 S6 N1 0-60 60-120 120-180 180-240
ON ON OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF ON ON OFF ON OFF ON OFF
N2
OFF ON OFF ON OFF ON
5(a) 240-300 300-360
III.CONTROL CIRCUIT STRUCTURE a) Controller For Four Wire Inverter The block diagram for the proposed controller is shown in Fig.7.The component of proposed controller are phase lock loop, comparator, voltage controller, and gain control signal distributor. The input for the phase lock loop is the voltage feedback. The PLL responds to both the frequency and phase of the input signals automatically raising or lowering the frequency of a controlled oscillator until it is maintained to the reference in both frequency and phase. The comparator is used to compare the actual output voltage with the reference voltage and that output is fed into the voltage controller. The voltage controller is the PI controller. The PI controller is used to minimize the steady state error. The output of PI controller again compared with the reference voltage. The output of the voltage controller is
5(b) Fig.5. Equivalent circuit for four wire VSI for 060
In region 60120, 180240, and 300360, the voltage waveforms in Fig.5 have another pattern, i.e., one phase voltage is always higher than the other two[1]. With this Fig.2 is equivalent to Fig.6(a) in 60120 region, which can be further organized into Fig. 6(b).The same equivalent circuit is also applicable to 180240and 300360 regions. The switching of inverter is shown in table III.
given toInstitute of Engineering, Coimbatore INFO the control signal distributor which distributes the signal to the inverter.
Fig.7.proposed controller for four wire inverter
bandwidths simultaneously lowering dv/dt and EMI problems. The switching strategy for the inverter is shown in Fig.9. In this Fig.9 the control signals are compared with the carrier signal and produce the switching patterns for the inverter. The gating signals for each switches is shown Fig (b)-(g).It can be seen that all the switching patterns possess half-wave symmetry where the switches in the same arm do not conduct[8].
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The control block diagram for the inverter is shown in Fig.8. The control blocks are simulated through MATLAB/SIMULINK.
Fig.9.Generation of Pulses for Switches
Fig.8. Control block diagram for inverter
The implemented feedback loop makes use of Park transformation on the measured three-phase output voltages. This conversion is also referred to as abc-to-dqs transformation. The following equations are used for the said transformation:
2 Vd = * [Va * sin(t ) + Vb * sin(t 2 pi / 3) + Vc * sin(t + 2 pi / 3)] (6) 3 2 Vq = * [Va * cos(t ) + Vb * cos(t 2 pi / 3) + Vc * cos(t + 2 pi / 3)] (7) 3 1 (8) V = *[ V + V + V ]
o
Benefits of ZVS: Zero power Lossless switching transitions. Reduced EMI / RFI at transitions. High efficiency with high voltage inputs at any frequency. Can incorporate parasitic circuit and component L and C. The overall switching pattern for the inverter is simulated through simulink. The time variation of gate pulse, voltage and current of switches Srp and Srn are shown in Fig.10 and Fig.11 where ZVS operation can be clearly observed. When the switch is on i.e., the gate pulse is given to the switches the voltage across the switch and current is zero.
The instantaneous line to line voltage for three phase sinusoidal waveform is 4 Vs n (9) sin sin n t + V ab =
V bc
3 6 n 4Vs n sin sin n t = 3 2 n =1, 3 , 5 n 4Vs 7 n sin sin n t = 3 6 n =1, 3 , 5 n
n =1, 3 , 5
(10)
V ca
(11)
In the eq (9),(10),(11) triplen harmonics (n= 3, 6, 9, 12) would be zero in the line-line voltages.
b) Zero Voltage Switching Hard switching refers to stressful behavior of the power electronics device. During the turn on and turn off process, the power device has to withstand high voltage and high current simultaneously. This results in high switching losses and stress. a) Low switching frequency b) High switching loss c) High EMI d) Acoustic noise The drawbacks in hard switching can be overcome by using the method called soft switching. Soft switching converters constrain the switching of power devices to time intervals when the voltage across the device or the current through it is zero. It reduces the device switching losses and hence allows higher switching frequencies and wider control
Fig. 10.Gate signal, voltage and current of Srp
Fig.11.Gate signal, voltage and current of Srn
IV.MATLAB IMPLEMENTATION The proposed three phase four wire inverter is tested on online UPS system simulated on Matlab/simulink implementation. The Fig.12 shows the closed loop circuit in which control signals are given as input to the gate for the four wire inverter and the output of the inverter are the voltage taken after filter and before filter and line currents.
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V.SIMULATION RESULTS
Fig.14. Simulation result for output line voltage
The above waveform as shown in Fig.14 is the output line voltages. The output waveform is a sinusoidal and it is taken by using filter component and to reduce the harmonic in the output.
Fig. 12.Simulation circuit for three phase four wire inverter
From the above simulation analysis (i) The neutral leg provides a lower impedance loop for unbalanced current and triplen harmonics, so the imbalance of output is dramatically reduced. (ii) The neutral inductance LX can reduce the current that flows through the switching components of neutral leg.
Fig.15.Simulation result for output line voltage before filter
The above Fig.15 is the simulation result for output line voltage. The output is the stepped wave and it is taken without any filter components. The Fig.16 is the waveform for three phase four wire inverter output current which is taken between load and no load condition.
Fig.13. Simulation of gate pulse for four wire inverter
The Fig.13 is the simulation of gate pulse for four wire inverter in which the input of the gatting signals is taken from the control signal distributor. The simulation parameter is shown in table IV.
TABLE IV Parameter for Simulation Analysis Parameter Values DC bus Output voltage Output frequency Switching frequency Inductor resistance Filter inductance Filter capacitance Rated resistive load 400V 300V 50HZ 2000HZ 1 800e-5H 400F 100 Fig.17. THD for four wire inverter
Fig.16.Simulation result for output current
The THD analysis of four wire inverter is shown in Fig.17 and the THD level is 2.70%.The amount of harmonic is reduced in this inverter.
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VI.EXPERIMENTAL RESULTS
The hardware output for the four wire inverter is given in Fig.18.
Fig.22.Output line voltage waveform for phase Y
Fig.18.THD Analysis for the four wire inverter
The hardware output for the gate pulse of the inverter switches (srp-sbn) and neutral wire switch (sxp-sxn) as shown in Fig.18 and Fig.19 respectively.
Fig.23.Output line voltage waveform for phase B
The results are experimentally verified and the setup for four wire inverter is shown in Fig.23
Fig.19.Gate pulse for the four wire inverter switches
Fig.23.Experimental setup for four wire inverter
Fig.20.Gate pulse for the Neutral wire switches
The output line voltage result for the phase R, Y, B is shown in Fig.21, 22, 23 respectively. The three phase line output voltage waveforms are phase shifted by 120.
VII.CONCLUSION A feedback loop control strategy for four wire voltage source UPS system has been described in this paper. The basic features of feedback control systems, such as insensitivity to parameter variations and robustness, this scheme is capable of producing nearly perfect sinusoidal load voltage. The closed-loop controller produced output voltage waveforms that have lower harmonic content than the open loop controller. Moreover, the zero-voltage switching makes a great contribution to reducing dv/dt and di/dt of each switching device, thus resulting in reduced EM1 and switching losses. The fourth leg of the topology makes the inverter have the ability of handling unbalancing loads. The inductor in fourth leg reduces the current through the switching components. The experimental results for four wire inverter are analysed in this paper. REFERENCES [1] Eyyup Demirkutlu Sleyman etinkaya Ahmet M. HavaOutput Voltage Control of A Four-Leg Inverter Based Three-Phase UPS by Means of Stationary Frame Resonant Filter Banks pp.880-885,IEEE-IEMDC2007 [2] Dhaval C. Patel, Rajendra R. Sawant and Mukul C. Chandorkar Three-Dimensional Flux Vector Modulation of Four-Leg Sinewave Output Inverters
Fig.21.Output line voltage waveform for phase R
no. 4, pp. 1261 - 1269, April 2008 [3] Armando Bellini and Stefano Bifaretti Modulation Techniques for Three-Phase Four-Leg Inverters Proceedings of the 6th WSEAS International Conference on Power Systems, Lisbon, Portugal, September 22-24, pp.398-403,2006. [4] Bellini, and S. Bifaretti A Simple Control Technique for Three-Phase Four-Leg Inverters pp.s18-s23, SPEEDAM 2006. [5] Richard Zhang, V. Himamshu Prasad, Dushan Boroyevich and Fred C. LeeThree-Dimensional Space Vector Modulation for Four-Leg Voltage-Source Converters IEEE Transactions Power Electronics, vol. 17, no. 3, pp.314-326,May 2002. [6] Liu Zeng, Liu Jinjun and Li Jin Modeling, Analysis and Mitigation of Load Neutral Point Voltage for Threephase Four-leg Inverter pp.1581-1586, IPEMC 2009 [7] Lihua Li and Keyue Ma Smedley, A New Analog Controller for Three-Phase Four-Wire Voltage Generation Inverters IEEE Transactions. Power Electronics, vol. 24, no. 7, pp.1711-1721, July 2009. [8] Sabzali, and T. H. Abdelhamid A New Zero-Voltage Switching HF Link Single-Phase UPS System with Input PFCEPE 2005. [9] Salem M. Ali Marian and P. Kazmierkowski PWM Voltage and current control of Four-Leg VSIpp.196201,IEEE 1998. [10] Naser Abdel-Ftahim and John E. Quaicoe Analysis and Design of a Multiple Feedback Loop Control Strategy for Single-phase Voltage- Source UPS Inverters IEEE Transactions. on power Electronics, vol. 11, no. pp.532-541,4, July 1996. [11]Bor-Ren Lin and Wei-Chun Li Analysis of a Zero Voltage Switching Interleaved PWM Converter, International Review of Electrical Engineering (IREE), Vol. 5. n. 2, pp. 380-389, Apr 2010. [12]Ghazanfar Shahgholian, Jawad Faiz and Mohsen Arezoomand Dynamic Analysis and Control Design of a Single-Phase UPS Inverter with Novel Topology and Experimental Verification ,International Review of Electrical Engineering (IREE), Vol. 4. n. 4, pp. 513-523, Aug 2009. [13]Senthil Kumar, Jovitha Jerome and S. Nithya Bhama Analysis of three phase four wire Inverter for UPS fed unbalanced star connected load, International Journal of Computer and Network Society,(IJCNS),Vol.2,No.4,April 2010.
Proceedings of PEID-2011 IEEE Transactions. on Industrial Electronics, vol. 57, INFO Institute of Engineering, Coimbatore
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Alex Stanley Raja T. was born on October 5, 1986. He received his B.E Degree in Electrical and Electronics Engineering from Bannari Amman Institute of Technology, Sathyamangalam, Anna University. Currently he is pursuing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, affiliated to Anna University. His fields of interests include four wire inverter, multilevel inverter and power converters for UPS Applications.
SenthilKumar.R was born in Tamilnadu, India, on November 2, 1966. He received the B.E degree in Electrical and Electronics Engineering from Madurai Kamaraj University, in 1989. He received his M.E (Power systems) from Annamalai University, in 1991. He has 15 yrs of teaching experience. At present he is working as Associate Professor in EEE department, Bannari Amman Institute of Technology, Sathyamanglam. Currently he is doing research in the field of power converters for UPS Applications. Dr.Jovitha Jerome was born in Tamilnadu, India, on June 2, 1957. She received the B.E. degree in Electrical and Electronics Engineering and M.E. degree in Power Systems from College of Engineering, Guindy, Chennai. She did her DEng in Power Systems. Presently she is working as Professor and Head in Instrumentation and Control Engineering Department of PSG College of Technology, Coimbatore.
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Design and Implementation of FPGA Based Resonant Inverter For UPS Application
K.Seetharaman PG Scholar, R.Senthikumar Associative Professor ksramkannan@gmail.com
Abstract - A field programmable gate array based Controller is proposed for a dc link series resonant inverter. The Basic operation of the zero voltage switching inverter is briefly described. A strategy of decoupling the control of the dc link current from the load current is identified and referred as decoupled current control. The use of gate-controlled devices like metaloxide semiconductor field-effect transistor/insulated gate bipolar transistor/MOS-controlled thyristor permits a higher resonance frequency at the link of the inverter. The DCC strategy eliminates the conventional analogue controller. A digital sequence controller has been designed using the state machine technique for the reliable operation of the inverter. The digital design is implemented on a single chip FPGA. To verify the proposed control strategy and the FPGA controller, a prototype has been built and tested. The test results show that a sinusoidal inverter output voltage is maintained with total harmonic distortion less than 5% and a regulation of about 1% from no-load to full-load, including non-linear and transient loads. The performance of the inverter with the FPGA controller is promising and attractive for un interrupted power supply applications.
Design parameters have been taken from previous work and LC configuration is based on these parameters. Zero voltage switching (ZVS) at full load ensures very low losses in the bridge circuit while at reduced loads the mode of operation in the MOSFET switches in one arm of the bridge is zero current switching (ZCS). By adjusting the resonant frequency of the LCC tank we intend to maximize the range of ZVS and therefore increase the total efficiency of the bridge. Having decided on an LCC resonant inverter topology our primary efforts will be towards optimizing the LC parameters for the highest efficiency given varying loads.. The target application for LC resonant inverter topology detailed in this report is a high frequency distributed. This paper proposes a general implementation method of based-FPGA controller for a resonant inverter, such as LC series resonant inverter, LLC and LCC series-parallel resonant inverters, which use variable frequency variable duty cycle scheme such as VFAPWM control and variable frequency phase-shift control32. Then the small signal model of the close loop system for a resonant inverter is analyzed. Thus the compensator can be designed. Moreover, the implementations including variable frequency pulse width modulator, the PLL with the variable phase presetting
II.GENERAL CONTROL SCHEME AND CONTROLLER CONSTRUCTIONS
I.INTRODUCTION The increased use of distributed power systems (DPS) in recent years has driven the need for high efficiency power conversion techniques. Resonant inverters have come to be recognized as the next generation of power conversion circuits due to low component costs, small component sizes and high efficiency.. Designing an LC-type resonant inverter that can operate under resistive and reactive loads is still a challenging process. Efforts to improve the efficiency under varying loads have shown good promise. We intend to focus primarily on designing a LC topology to handle varied loads while maintaining constant output voltage with low total harmonic distortion. While LC topologies have been designed and tested for various applications, we intend to the FPGA phase shifter circuitry. A High-Frequency DC/AC Power Inverter is proposed which is capable of supplying power to an AC bus with varying loads.
Fig.1 shows a typical resonant inverter. Resonant tank could be LC series resonant components, LLC or LCC hybrid resonant components. If the switching frequency is above resonant frequency and duty cycle is 50%, the input impedance of resonant tank is inductive and output voltage leads the load current. With a suitable dead-time, zero voltage- switch (ZVS) could be obtained. With decrease of the duty cycle, the phase difference between the output voltage and load current reduces correspondingly. To keep ZVS, the switching frequency has to be increased. Hence, there are two control loops for this inverter and the other is duty cycle regulation loop used to regulate output
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For supplying uninterruptible power to the critical loads, UPS consist of the following main components as shown in Fig.2 1. Rectifier 2. Battery 3. Inverter 4. Static transfer switches Types of ups 1. 2. 3. Offline UPS Online UPS Line interactive UPS
power. Power control loop is the slow varying loop. To keep the switching frequency as narrower as possible, the phase presetting will be changed with the variation of output power.
IV. REVIEW FOR CLOSED LOOP SMALL SIGNAL MODEL OF A RESONANT INVERTER The model method for resonant inverter was presented. The key concept and resulting transfer functions are briefly reviewed a low pass filter (LPF) and an integral compensator have to be implemented for the power loop. Their parameters could be determined by analysis of the small signal circuits of resonant inverters. In the following,
Fig.1 (a) Resonant inverter, (b) resonant tank (c) and the waveforms of the inverter
III.UNINTERRUPTIBLE POWER SUPPLY A. INTRODUCTION In applications such as medical intensive care systems, chemical plant process control, safety monitors or major computer installation, where even a temporary loss of supply could have severe consequence, there is need to provide an uninterruptible power supply system which can maintain the supply under all conditions. Therefore, the function of UPS is to provide an interrupt free supply of power to the AC load, which cannot be directly fed from DC source and required DC to be converted into AC. This provides protection against power outages as well as suppressing incoming line transient and harmonic disturbances.
B. COMPONENTS OF UPS
Fig. 3 Small signal model of PLL
series resonant inverter with VFAPWM control will be used as a example to explain how to model a resonant inverter. Fig. 4 shows its small signal circuit model In addition, the phase difference between o v and L i should be higher than zero to keep ZVS. i.e., so v should lead L i . Thus the influence of the phase difference on the inverter has to be discussed. The phase difference can be solved as
Fig.2 Components of UPS
Fig. 4 Small signal circuit model of a half-bridge series resonant inverter with asymmetrical PWM control
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Series RLC circuit, and: It is sometimes more convenient to use the damping factor, which is dimensionless, instead of the attenuation factor, which has dimensions of radians per second, to analyze the properties of a resonant circuit. B.MINIMIZING THE ATTENUATION OSCILLATOR CIRCUITS: FOR
V .UNDAMPED RESONANCE FREQUENCY OF AN RLC CIRCUIT
0 =
1 LC
(1)
In the more familiar unit hertz (or cycles per second), the resonance frequency becomes
1 f0 = 0 = 2 2 LC
(2)
Resonance occurs when the complex impedance ZLC of the LC resonator becomes zero:
ZLC =ZL +ZC =0
(3)
For applications in oscillator circuits, it is generally desirable to make the attenuation (or equivalently, the damping factor) as small as possible. In practice, this objective requires making the circuit's resistance R as small as physically possible for a series circuit, or alternatively increasing R to as much as possible for a parallel circuit. In either case, the RLC circuit becomes a good approximation to an ideal LC circuit. However, for very low attenuation circuits (high Q-factor) circuits, issues such as dielectric losses of coils and capacitors can become important. For applications in band-pass filters, the value of the damping factor is chosen based on the desired bandwidth of the filter. For a wider bandwidth, a larger value of the damping factor is required (and vice versa). In practice, this requires adjusting the relative values of the resistor R and the inductor L in the circuit. VI. DERIVE PARAMETERS
The derived parameters include bandwidth, Q factor, and damped resonance frequency.
Both of these impedances are functions of angular frequency :
ZC =
1 jC
(4)
ZL =jL
(5)
Setting the magnitude of the impedance to be zero at = 0 and using j2 = 1:
ZLC |=L0 0 2 =
1 =0 0 C
(6)
A. BANDWIDTH The RLC circuit may be used as a band pass or band-stop filter by replacing R with a receiving device with the same input resistance. In the Series case the bandwidth (in radians per second) is
1 1 0 = LC LC
(7)
A. ATTENUATION
The attenuation is defined as
= 2 = 2
(8)
R L
(10)
R 2L
Alternatively, the bandwidth in hertz is
for the series RLC circuit, and
f=
(9)
0 R = = = 2 2L
(11)
1 2RC
The bandwidth is a measure of the width of the frequency response at the two half-power frequencies. As a result, this measure of bandwidth is sometimes called the full-width at half-power. Since electrical
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Variable frequency control (or phase control) is used for most induction cooking appliances based on half bridge series resonant inverters. but efficiency of the inverter decreases significantly with increase of switching frequency to lower the output power. Asymmetrical control strategy has applied successfully to half bridge converters. Efficiency is improved because of constant switching frequency and ZVS operation. But ZVS operating condition is lost under low load condition so as to result in high turn-on losses. Phase-shifted PWM with load-adaptive control method was used for full bridge inverter to adjust output power and reach ZVS operation over wide load range. But this control strategy cannot be used for bridge inverter. This paper proposes APWM with frequency tracking control strategy to regulate output power. ZVS operation can be kept over wider load range by the proposed method than constant frequency method; ad switching frequency can be changed over smaller range by it than variable frequency control method. This method is implemented in FPGA-based full digital controller.
power is proportional to the square of the circuit voltage (or current), the frequency response will drop to at the half-power frequencies.
B. Q FACTOR
The Q factor can be expressed in terms of the three devices in the circuit, from the basis of the definition:
Q= 0 =
(R ) L
1 LC
)=
1 R
L C
(12)
Damped resonance Main articles: Damping and Damping ratio The damped resonance frequency can be expressed in terms of the undamped resonance frequency and the damping factor. If the circuit is under damped, meaning
<0
or equivalently
(13)
<1
Then we can define the damped resonance as
(14)
d = 0 2 - 2 =0 1- 2
In an oscillator circuit
(15)
Fig5 FPGA-based full digital controller
A.SYSTEM CONFIGURATION FPGA-based full digital control system construction. The controller is implemented within FPGA (XILINX VIRTEXII 250), in which there is power loop. The digital implementation of maintains resonant operation over a wide range of frequency variation even if load or duty cycle is changed directly switching frequency value to VFPWM. The output voltage and current of inverter are measured, converted and provided into FPGA output voltage is multiplied directly by the current and the result of multiplier is fed into digital filter LPF. The output of the filter, which is equal with average output power, is used as input of integral controller. The output of pi controller provides duty cycle value for VFPWM.
=0
Or equivalently
(16)
=1
As a result
(17)
d 0
VII.SYSTEM CONFIGURATION AND OPERATION MODES
B.OPERATION MODE MODE1
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Under steady condition, the positive and negative load current wave form must be identical
R 2rL
ec=edc
e
1
R 2rL
(23)
VIII.IMPLEMENTATION OF THE CONTROL LOOP WITHIN A FPGA

fig 6 mode1
POWER
this mode1 operation can be describe by the following differential equation:
edc=
1 di idt + L dt + iR Edc c
(18)
the initial conditions at t=0 are (i) initial current i(0)=0 (ii) initial voltage on capacitor ec(t=0)=-ec
Closed loop design implies that as the load current changes the pulse width modulation used to control the bridge output voltage would be automatically adjusted. By varying the output of the bridge the power delivered to the load is varied. Thus maintaining the output power across the load terminals. By programming the gate pulse generation into a FPGA this closed loop design would be a simple addition to the inverter package. A reference voltage take from the output could be monitored and scaled to control the duty cycle of the control waveform thus varying the duty cycle of the bridge output voltage. A. LAW OF LOW PASS FILTER The obtained discrete-time control law of low pass filter is [1] Given by
i(t)= e-rt/2lsinrt Tm= tan-1(r2L/R)
(19) (20)
MODE 2
pn=k2pn1+k1(pn+pn1)
(24)
Where pnand p n1 are the new and one-cycle before values of average output power, respectively,. P n and 1 p n1 are the new and one-cycle before values of instant power obtained from multiplier output within FPGA, respectively. B.INTEGRAL COMPENSATOR The control law of integral compensator could expressed as
fig.7 mode2
this mode begin when mofet s2 is turned on and a reverse resonant current flow through the load.this mode of circuit operation can be described by
dn=dn-1+k3 (en-en-1) en=pref-pn
(25) (26)
vc=
1 di idt + L dt + iR c
(21)
Where en and en 1 are the new and one-cycle before values of the power error signal respectively, dn and dn1are the new and one-cycle before values of duty cycle, respectively. XI.SIMULATED CIRCUIT AND RESULTS
The initial condition i(t=0)=0
vc=edc+ec
(22)
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A. SIMULATION CIRCUIT
Fig10. Simulated Zero Voltage Switch wave form
Fig11. Simulated outputTHD Wave form (V=70.82, THD=2.68%)
Fig 8 Closed loop resonant inverter simulated circuit
B.SIMULATION RESULT
Fig12 Simulated controller
Result
for
Pi
Controller
in
FPGA
X.CONCLUSION
This paper proposes a general implementation method of based-FPGA controller for a resonant inverter, such as LC series resonant inverter, LLC and LCC seriesparallel resonant inverters, which use variable frequency variable duty cycle scheme such as VFAPWM control or variable frequency phase-shift control Due to regulation of both duty cycle and switching frequency and variation of the phase this control strategy can improve the performances of the resonant inverter.
Fig 9 .Resonant inverter simulated output current (I out) , output voltage(Vout) and power output (Pout)
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REFERENCES [1]J.Tian, G.Berger T.Reimann, M. Scherf, J.Petzoldt Design and Implementation of A FPGA-Based Controller for Resonant Inverters, 2007 Ieee. [2] A. Muthuramalingam, S. V. Vedula, And P. A. Janakiraman, , Ieee Performance Evaluation Of An FPGA Controlled Soft Switched Inverter , July 2006 [3] Rodolfo Pellizzoni, And Marco Caccamo, RealTime Management of Hardware and Software Tasks For FPGA-Based Embedded Systems, 2007. [4] Falk Karstens, And S. Trippel Programmable Trigger Logic Unit Based On FPGA Technology, Ieee 2005 [5]Yan Yin, And Regan Zane, Digital Phase Control For Resonant Inverters, Ieee 2004 [6] Luis A. Barragn, Denis Navarro, Jess Acero, And Jos M. Burdo FPGA Implementation Of A Switching Frequency Modulation Circuit For Emi Reduction In Resonant Inverters For Induction Heating Appliances Ieee 2008. [7] S Shih - Liang Jung Design and Implementation Of An FPGA-Based Control Ic For Ac-Voltage Regulation2005 Ieee [8] Zeliang Shu, Yuhua Guo, and Jisan Lian SteadyState And Dynamic Study Of Active Power Filter With Efficient FPGA-Based Control Algorithm, 2008 [9]Jos I. Artigas, Isidro Urriza, Luis Barragn, Denis Navarro, And Jos M. Burdo Power Measurement By Output-Current Integration In Series Resonant Inverters, 2009 [10]Hao L., A. P. Hu and G. A. Covic FPGA Controlled High Frequency Resonant Converter for Contactless Power Transfer
SenthilKumar.R was born in Tamilnadu, India, on November 2, 1966. He received the B.E degree in Electrical and Electronics Engineering from Madurai Kamaraj University, in 1989. He received his M.E (Power systems) from Annamalai University, in 1991. He has 15 yrs of teaching experience. At present he is working as Associate Professor in EEE department, Bannari Amman Institute of Technology, Sathyamanglam. Currently he is doing research in the field of power converters for UPS Applications.
K.Seetharaman. was born on January 30, 1988. He received his B.E Degree in Electrical and Electronics Engineering from Muthayammal Engineering College, Namakkal, and Anna University. Currently he is pursuing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, affiliated to Anna University of Technolgy.
188
DIGITAL SIMULATION OF MULTI-LEVEL INVERTER BASED DYNAMIC VOLTAGE RESTORER

N S Sakthivel Murugan
Kuppam Engineering College, Andhra Predesh

nssakthivel@yahoo.com
ABSTRACT This paper deals with simulation of multilevel inverter based DVR. The DVR circuit produces high quality voltage since it uses a nine level inverter. This DVR gives better solution to the voltage sag problem by injecting a voltage with reduced harmonics. DVR controls the voltage applied to the load by injecting voltage of proper amplitude and phase angle. Thus DVR is responsible for restoring quality of voltage derived to the end user. The consumer can be isolated from transients and disturbances caused by sags by using DVR. Multilevel inverter based DVR is simulated and the results are presented. Keywords: DVR, Multilevel inverter, MATLAB I. INTRODUCTION Power electronic devices contribute an important part of harmonics in all kind of applications, such as power rectifiers, thyristor converters, and Static VAr Compensators (SVC). The updated Pulse-Width Modulation (PWM) techniques used to control modern static converters such as machine derives, power factor compensators, or active power filters do not produce perfect waveforms, which strongly depend on the semiconductors switching frequency. Voltage or current converters as they generate discrete output waveforms, force the use of machines with special isolation, and in some applications large inductances connected in series with the respective load. In other words, neither the voltage nor the current waveforms are as expected. Also, it is well known that distorted voltages and current waveforms produce harmonic contamination, additional power losses, and high frequency noise that can affect not only the power load but also the associated controllers. All these unwanted operating characteristics associated with PWM converters can be overcome with multilevel converters, in addition to the fact that higher voltage levels can be achieved[1]-[5]. Multilevel inverters can operate not only with PWM techniques but also with Amplitude Modulation (AM), significantly improving the quality of the output voltage waveform. With the use of AM, low frequency voltage harmonics are perfectly eliminated, generating almost perfect sinusoidal waveforms with a Total Harmonic Distortion (THD) lower than 5%. Another important characteristic is that each converter operates at a low switching frequency, reducing the semiconductor stresses, and therefore reducing the switching losses [6], [7]. The principal objective of this paper is to determine the simplest converter topology in terms of the number of power semiconductors for a given number of levels. The
redundant levels are minimized, and the combination of bridges to maximize the number of levels [8], [9] and minimize power sources and semiconductors are analyzed.
Fig.1. Basic Multilevel inverters (a) two levels, (b) three levels and (c) m levels
II. MULTILEVEL CONVERTER CHARACTERISTICS
The principal function of the inverters is to generate an AC voltage from a DC source voltage. If the DC voltage sources connected in series, it becomes possible to generate an output voltage with several steps. Multilevel inverters include an arrangement of semiconductors and DC voltage sources required to generate a staircase output voltage waveform. Fig. 1 shows the schematic diagram of voltage source-inverters with a different number of levels. It is well known that a two level inverter, such as the one shown in Fig. 1(a), generates an output voltage with two different values (levels) Vc and zero, with respect to the negative terminal of the dc source (0), while a three-level module, Fig, 1(b) generates three different voltages at the output (2Vc, Vc and zero). The different positions of the ideal switches are implemented with a number of semiconductors that are in direct relation with the output voltage number of levels. Multilevel inverters are implemented with small DC sources to form a staircase AC waveform, which follows a given reference template. For example, having ten DC sources with magnitudes equal to 20 V each a composed 11level waveform can be obtained (five positive, five negatives and zero with respect to the middle point between the ten sources), generating a sinusoidal waveform with 100 V amplitude as shown in Fig. 2, and with very low THD.
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capacitors, which translates is that it requires a large number of capacitors, which translates to a bulky and expensive converter as compared with the diode-clamped inverter. Besides, the number of transistors used is the same with the diode-clamped inverter, and therefore, for a 51-level inverter, 100 power transistors are required. In order to overcome all these problems, a third topology, which will be called the transistor-clamped inverter will be presented and analyzed. C. Transistor-Clamped Inverter: The transistor-clamped inverter has the advantage of requiring the same number of power transistors as the levels generated, and therefore, the semiconductors are
Fig. 2 Voltage waveform from an 11-level inverter
It can be observed that the larger the number of the inverter DC supplies, the greater the number of steps that can be generated, obtaining smaller harmonic distortion. However the number of DC sources is directly related to the number of levels through the equation: n=m1 (1)
where n is the number of DC supplies connected in series and m is the number of the output voltage levels. In order to get a 51-level inverter output voltage, 50V supplies would be required, which is too much for a simple topology. Besides the problem of having to use too many power supplies to get a multilevel inverter, there is a second problem which is also important, the number of power semiconductors required to implement the commutator, as shown in Fig 1. Technical literature has proposed two converter topologies for the implementation of the power commutator, using force-commutated devices [transistors or Gate Turn-Offs (GTOs)]: a) the diode-clamped and b) the capacitor-clamped converter [2]. A. Diode-Clamped Inverter This inverter consists of a number of semiconductors connected in series, and another identical number of voltage sources, also connected in series. These two chains are connected with diodes at the upper and lower semiconductors as shown in Fig 3 (a). For an m-level converter, the required number of transistors T is given by T = 2 (m 1). (2)
(a)
Then, for example of a 51-level converter, 100 power transistors would be required (which is an enormous amount of switches to be controlled). One of the most utilized configurations with this topology is that of the three-level inverter, which is shown in Fig. 3 (b). The capacitors act like two DC sources connected in series. Thus, in the diagram, each capacitor accumulates VDC, giving voltages at the output of VDC, 0, or - VDC with respect to the middle point between the capacitors. B. Capacitor-Clamped Inverter: This inverter has a similar structure to that of the diode-clamped, however it can generate the voltage steps with capacitors connected as shown in Fig 4. The problem with this converter is that it requires a large number of
(b) Fig. 3. (a) The m-level and (b) three-level diode clamped inverter topology reduced by half with respect to the previous topologies. A 51-level converter requires 51 transistors (instead of 100 transistors). For an m-level transistor clamped inverter, which satisfies T = m. (3) In this topology, the control of the gates is very simple because only one power transistor is switched-on at a time. Then, there is a direct relation between the output voltage, Vout and the transistor that has to be turned-on. However,
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and despite the excellent characteristics of this topology, the number of transistors is still too large to allow the implementation of a practical converter with more than 50 levels. One solution for increasing the number of steps could be the use of H converters, like the one shown in Fig 6, which consists of connecting two of the previously discussed topologies in series (two legs). If transistorclamped inverters are used to build an H converter, the number of transistors required for an m-level inverter is m+1, which means only one more transistor than what is required for a simple leg configuration. However, the number of DC source is reduced to 50%, which is the most important advantage of H converters.
Output Voltage (V) 0 V1 V2 V3 V4 V3 V2 V1 -V1 -V2 -V3 -V4 -V3 -V2 -V1
S1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0
SWITCHING SEQUENCE S2 S3 S4 S5 S6 S7 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0
S8 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
Fig. 4. The m-level capacitor clamped inverter Another characteristic is that the H topology has many redundant combinations of switch positions to produce the same voltage levels. As an example, the level zero can be generated with switches in position S(1) and S(2), or S(3) and S(4), or S(5) and S(6), and so on. Another characteristic of H converters is that they only produce an odd number of levels, which ensures the existence of the 0-V level at the load. For example, a 51-level inverter using an H configuration with transistor-clamped topology requires 52 transistors, but only 25 power supplies instead of the 50 required when using a single leg. Therefore, the problem related to increasing the number of levels and reducing the size and complexity has been partially solved, since power supplies have been reduced to 50%.
Fig. 5(a) Simulation circuit of cascaded nine-level inverter III. SIMULATION OF CASCADED NINE-LEVEL INVERTER The cascaded nine-level inverter has been simulated using MATLAB software. The simulation circuit is illustrated in Fig. 5(a). The voltage of the cascaded nineTable 1. Switching sequence level inverter can be synthesized from the following switching combinations. The table 1 shows the switching sequence. The driving pulses for switches S1 & S2 are shown in following Fig. 5(b). The driving pulses for switches S5 & S6 are shown in following Fig. 5(c). The Fig. 5(d) shows the output voltage across inverter 1. The Fig. 5(e) shows the output voltage across inverter 2. Nine level inverter output is shown in Fig. 5(f). The frequency spectrum for the output inverter is shown in Fig. 5(g).
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Fig.5(b). Driving pulses for S1 & S2 Fig. 5(f). Output of nine-level inverter
Fig.5(c). Driving pulses for S5 & S6
Fig. 5(g). Frequency spectrum for output voltage
IV. CONCLUSION The dynamic voltage restorer is used to improve voltage sags caused by abrupt increase in loads. Multilevel inverters with large number of steps have been used in the DVR system. Multilevel inverter which requires minimum power supplies have been used in DVR system. The DVR can tackle the problem of harmonics caused by non linear loads in manufacturing industries. Other industries can also use DVR to compensate voltage sag. This paper shows simulation results of nine-level inverter based DVR. THD is found to be much less than that of single PWM inverter. The simulation results are similar to the analytical predictions REFERENCES 1] J.S. Lai and F.Z. Peng, Multilevel converters A new breed of power converters, in Proc. IEEE-IAS Annu Meeting, 1995, pp. 2348-2356. 2] J. Rodriguez, J.S. Lai and F.Z. Peng, Multilevel inverters A Survey of topologies, controls and applications, IEEE Trans Ind. Electron, vol. 49, no. 4, pp. 724-737, Aug 2002. 3] M. Manjrekar and G. Venkataramanan, Advanced topologies and modulation strategies for Multilevel inverters, in Proc. IEEE-PESC96 Conf. 1996, pp. 10131018.
Fig. 5(d). Output voltage across inverter-1
Fig. 5(e). Output voltage across inverter-2
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4] K. Corzine and Y. Familiant, A new cascade Multilevel H-bridge drive, IEEE-Trans Power Electron., vol 17, no. 1, pp. 125-131, Jan 2002. 5] J. Rodriguez, L. Moran, J. Pontt, P. Cornea and C. Silva, A high performance vector control of an 11-level inverter, IEEE-Trans Ind Electron, vol. 50, no. 1, pp. 8085, Feb 2003. 6] J. Dixon, L. Moran, A. Breton and R. Rfos, Multilevel inverter, based on multistage connecting of three-level converters, scaled in power of three, presented at IEEE Ind Electron., (IECON02) [CD-ROM]. 7] J. Dixon, M. Ortuzar and F. Rfos, Traction drive system for electric vehicles, using Multilevel converter, presented at 19th Electric vehicle symp. EVS 19 8] J. Dixon, A. Breton and F. Rfos, Multistage converters: A new technology for Traction derive systems. Presented at 20th Electric vehicle symp. EVS 20 9] J. Dixon, L. Moran, M. Ortuzar and R. Carmi, Voltage source active power filter, based on Multilevel converter and ultra capacitor DC-link, presented at IEEE Ind. Electron, (IECON04) 10] J. Dixon and L. Moran, A clean four-quadrant sinusoidal power rectifier, using multistage converters for subway applications, IEEE Trans Ind. Electron., vol. 52, no.3, pp. 653-661, Jun 2005.
Authors
N.S.Sakthivel Murugan has obtained his B.E. degree from Madras University and M.E. Degree from Annamalai University in the years 1998 and 2001 respectively. He has 10 years of teaching experience. He is presently a research scholar at Anna University. His research area is improvement of power quality using DVR.
Dr.Nirmalkumar has obtained his U.G. degree from Calicut University and P.G. Degree from Kerala University in the years 1972 and 1976 respectively. He has done his research from Bharathiyar University. He has 28 years of teaching experience. He is presently working as Prof. and Head of EEE department at BIT, Sathyamangalam. His research area is power quality issues in power systems.
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DYNAMIC STABILITY OF POWER SYSTEM USING ADVANCED INTELLIGENT CONTROLLER * D.Sabapathi Abstract In this paper, the power system with an excitation controller is represented as a class of large-scale, uncertain, interconnected nonlinear continuous-time system in strictfeedback form. Power system stabilizer (PSS) controller design is one of the methods of combining the PSS with the excitation controller (AVR) for the investigation of many different input signals. Subsequently, dynamic surface control (DSC)-based adaptive Neuro fuzzy controller is designed to overcome the repeated differentiation of the control input that is observed in the conventional backstepping approach. The NNs are utilized to approximate the unknown subsystem and the interconnection dynamics. By using novel online NN weight update laws with quadratic error terms, the closed-loop signals are shown to be locally asymptotically stable via Lyapunov stability analysis, even in the presence of Neuro fuzzy approximation errors in contrast with other Neuro fuzzy techniques where a bounded stability is normally assured. Simulation results on the IEEE 9-bus power system with generator excitation control are provided to show the effectiveness of the approach in damping oscillations that occur after disturbances are removed. By using a new variant of the projection scheme and dynamic surface control with NNs, the need for the repeated differentiation in the backstepping design procedure has overcome. The end result is a nonlinear decentralized adaptive state-feedback excitation ** S.Periyanayagi *** M. Valarmathi
controller for damping power systems oscillations in the presence of uncertain interconnection terms. Key Words: PSS, AVR, Fuzzy logic, stability, FLC. 1. INTRODUCTION Power system stability may be broadly defined as a power system that enables it to remain in a state of operating equilibrium under normal operating conditions and to regain an acceptable state of equilibrium after being subjected to a disturbance. Instability in a power system may be manifested in many different ways depending on the system configuration and operating mode. Traditionally, the stability problem has been one of the maintaining synchronous operations. Since power systems rely on synchronous machines for generation of electrical power, a necessary condition for satisfactory system operation is that all synchronous machines remain in synchronous or, colloquially, in step. This aspect of stability is influenced by the dynamics of generator rotor angle and power- angle relationships. 1.1 Literature review NNs based decentralized controller designs for the excitation and steam valve control is proposed and it also demonstrates the effectiveness of the controller designs (1). Eliminating the problem of explosion of complexity caused by the traditional backstepping approach is described (2). FACTS control design is complex due to the

Gpss(s)
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combination of differential and algebraic equations and it explains the Method to generate a nonlinear dynamic representation to enable more sophisticated control design (3). RVFL is an efficient universal approximator with the rate of approximation error convergence to order of zero which it enhances the accuracy of multivariate function approximations(4).Robust decentralized Power System Stabilizer (PSS) design approaches for power system matrix was represented and it addresses two approaches with their practical implications for large power systems(5).Controllers with arbitrarily small tracking error for uncertain, mismatched nonlinear systems was designed and it also represents the boundedness of tracking error semiglobally (6). 2. POWER SYSTEM STABILIZER 2.1 Introduction In power system network, when there is a mismatch between generation and the demand or the sudden change of load causes an oscillations in generator rotor. The basic function of a PSS is to add damping to the generator rotor oscillations by controlling its excitation using auxiliary stabilizing signals. To provide damping the stabilizer must produce a component of electrical torque in phase with the rotor speed deviations. The theoretical basis for a PSS may be illustrated with the aid of the block diagram shown in figure 1. Since the purpose of a PSS is to introduce a damping torque component, a logical signal to use for controlling generator excitations is the speed deviation r.
K4 v Ef + Vref +
d
Field circuit -
f
d
T K
+ + l 2Hs+
u
Gex (s)
k3 l+ST3
v1 K + k3 l+ST3 + K K
Figure 1 Block diagram representation with AVR and PSS.
If the exciters transfer function Gex(s) and the generator transfer function between Efd and Te were pure gains, a direct feed back of r would result in a damping torque component. However, in practice both the generator and the exciter (depending on its type) exhibit frequency dependent gain and phase characteristics. Therefore, the PSS transfer function, GPSS(s), should have appropriate phase compensation circuits to compensate for the phase lag between the exciter input and the electrical torque. In the ideal case, with the phase characteristics of GPSS(s) being an exact inverse of the exciter and generator phase characteristics to be compensated, the PSS would result in a pure damping torque at all oscillating frequencies. It should be recognized that the generator model assumed in the representation shown in figure 2 neglects amortisseurs to simplify the system model and allow its representation in the form of a block diagram. However amortisseurs could have a significant effect on the generator phase characteristics and should be considered in establishing the parameters of the PSS.
195 concept of partial truth- truth- values between completely true and completely false. Zadeh says that rather than regarding fuzzy theory as a single theory, we should regard the process of fuzzification as a methodology to generalize ANY specific theory from a crisp (discrete) to a fuzzy (continuous) from. Thus recently researchers have also introduced fuzzy calculus and fuzzy differential equations 3.2 Fuzzy Rule Base Fuzzy logic has been centered on the point that it makes use of linguistic variables as its rule base. Li-Xin Wang said that if a variable can take words in natural language as its values, it is called linguistic variable, where the words are characterized by fuzzy sets defined in the universe of discourse in which the variable is defined. Examples of these linguistic variables are slow, medium, high, young and thin. There could be a combinations of this variable too, i.e. slow-young horse, a thin young female. These characteristics are termed atomic terms while their combinations are called compounded terms. In real world, words are often used to describe characteristics rather than numerical values. For example, one would say the car was going at 100 miles per hour. Terms such as slightly, very, more or less, etc. are called linguistic hedges since they add extra description to the variables, i.e. very show, more or less red, slightly high, etc. At the heart of the fuzzy rule base are the IF-THEN rules. A fuzzy IF-THEN rule is expressed as, IF<fuzzy proposition>, THEN <fuzzy proposition.
Vt
Turbi
Vo
ne
G
Short circuit test
Exciter & AVR
Power System Stabilizers
ANFPSS
CPSS
OPEN
Figure 2 Block diagram overall power system network
3. FUZZY LOGIC 3.1 Introduction Fuzzy logic emerged into the mainstream of information technology in the late 1980s and early 1990s. Fuzzy logic is a derivative from classical Boolean logic and implements soft linguistic on a continuous range of truth values to be defined between conventional binary. It can often be considered a suspect of conventional set theory. Since fuzzy logic handles approximate information in a systematic way, it is ideal for controlling non-liner systems and fro modeling complex systems where an inexact model exists or systems where ambiguity or vagueness is common. A typical fuzzy system consists of a rule base, membership functions and an inference procedure [9]. Today, fuzzy logic is found in a variety of control applications including chemical process control, manufacturing and in such consumer products as washing machines, video cameras and automobile. Fuzzy logic is a suspect of conventional Boolean logic that has been extended to handle the
196 The structure of the Fuzzy Logic Controller (FLC) and its design consists of the following steps Identification of input and output variables. Construction of control rules. Establishing the approach for describing system state in terms of fuzzy sets, i.e., establishing fuzzification method and fuzzy membership functions. Selection of the compositional rule of the inference. Defuzzification method, i.e., transformation of the fuzzy control statement into specific control actions. Steps 1 and 2 are application specific and typically straightforward. There are several approaches to Steps 4 and 5 but most of the literature reports using minimum implication and center-ofgravity defuzzification. The design methodology in this tutorial centers on forming general rule membership functions and then determining parameters based on observed response to a disturbance. 3.4 Membership Function Each of the input and output fuzzy variables are assigned seven linguistic fuzzy subsets varying from negative big (NB) to positive big (PB). Each subset is associated with a triangular membership function to form a set of seven membership functions for each fuzzy variable. The membership function for each linguistic variable is as follows. From this rules the Fuzzy Associate Memory (FAM) table is developed as shown below. FAM TABLE Table No: 1 FAM Table
Propositions are linguistic variables or atomic terms as described previously. This type of rile-based system is different from the classical expert systems in that rules may not necessarily be derived from human expertise; they may also be derived from other sources. Three types of linguistic variable forms exist. 1. Assignment statements 2. Conditional statements 3. Unconditional statements 3.3 Fuzzy Logic Controller Design The traditional control design paradigm is to form a system model and develop control laws from analysis of this model. The controller may be modified based on results of testing and experience. Due to difficulties of analysis, many such controllers are liner. The fuzzy controller approach is to somewhat reversed. General control rules that are relevant to a particular system based on experience are introduced and analysis or modeling considerations come later. For example, consider the following general control law for a positioning system. This rule implements a control concept for anticipating the desired position and reducing the control level before the set point is reached in order to avoid overshoot. The quantities small and large are fuzzy quantities. A full control design requires developing a set of control rules based on available inputs and designing a method of combining all rule conclusions. The precise fuzzy membership functions depend on the valid range of inputs and the general response chrematistics of the system. Within power systems, fuzzy logic controllers have been proposed primarily MATLAB FIS Editor

ACCELEARATIONPOWER DEVIATION Speed Deviation BN MN LN Z LP MP BP
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BP BZ LP MP BP BP BP BP
MP LN BZ LP MP MP BP BP
LP MN LN BZ LP LP MP BP
Z MN MN LN LZ LP MP MP
LN BN MN LN LN BZ LP MP
MN BN BN MN MN LN BZ LP
BN BN BN BN BN MN LN BZ
Figure 3 System performances without PSS
4. SIMULATION STUDY To investigate the two-area fourmachine system performance the following disturbances were considered in the simulation studies 1. L-G fault at any one of the phase 2. Three phase to ground fault 4.1 Single Phase fault Figure 3 shows the system performance of with out PSS for single phase to ground fault occurs on the line 1 at 110 km. A single phase fault were applied at 1.10 sec and cleared at 1.2sec. Figure 4Shows the various system responses under delta omega () PSS. Figure 5, shows the various system responses of the fuzzy logic power system stabilizer. It should be noted that the oscillation under system with fuzzy logic PSS decays faster than under system with delta PSS and also fuzzy logic power system stabilizer achieves a significantly fast damping for power flow from bus 1 to bus 2. A three-phase fault of 0.2sec duration is simulated at line 1. Figure 7 shows the response of system under with out PSS. Figure 8 represents the result of the examined power system under delta- PSS. Figure 9 shows the response of system with fuzzy logic power system stabilizer.
Figure 4 System performances with

CPSS
Figure 5 System performances with FLPSS
Figure 6 System performances without PSS
Figure 7 System performances with CPSS
198 implement in the multi-machine systems and is shown to be quite effective in damping out both local and multimodal oscillations. 6. REFERENCES [1] W. Liu, S. Jagannathan, G. K. Venayagamoorthy, D. C.Wunsch, M. L.Crow, L. Liu, and D. A. Cartes, Neural network based decentralized controls of large scale power systems(2007). [2] S. Mehraeen, S. Jagannathan, and M. L. Crow, Novel dynamic representation and control of power systems with FACTS devices(2010). [3] S. Mehraeen, S. Jagannathan, and M. L. Crow, Novel dynamic representation and control of power systems with FACTS devices(2010). [4] B. Igelnik and Y. H. Pao, Stochastic choice of basis functions in adaptive function approximation and the functional-link net(1995) [5] G. K. Befekadu and I. Erlich, Robust decentralized controller design for power systems using inequalities approaches (2006). * D.Sabapathi (Corresponding Author) is currently doing his Ph.D Programme at Anna University of Technology, Coimbatore 641 047. Email: esec74@yahoo.co.in ** S.Periyanayagi is currently doing her Electrical & Electronics Engineering Student at M.P.Nachimuthu M.Jaganathan Engineering College, Chennimalai. Email: periyanayagi.chml @gmail.com *** M.Valarmathi, is currently doing her Electrical & Electronics Engineering Student at M.P.N.M.J.Engg. College, Chennimalai. Email: mathibeeee38@gmail.com
Figure 8 System performances with FLPSS
From the results, it should be noted that the oscillation under system with fuzzy logic PSS decays faster than under system with delta- PSS. The simulation results shows, the fuzzy logic controller applied to a power system stabilizer provided better dynamic response than the conventional power system stabilizer and the system with fuzzy logic power system stabilizer is the best one since it is effective for all test conditions. 5. CONCLUSION In this paper has been proposed a fuzzy logic power system stabilizer for stability enhancement of a two-area four-machine system. In order to accomplish the stability enhancement, speed deviation () and acceleration power deviation (P) of the rotor synchronous generator were taken as the inputs to the fuzzy logic controller. These variables take significant effects on damping the generator shaft mechanical oscillations. The performances of the system during single phase and three phase fault conditions are performed; the resultant characteristics of speed deviation, active power deviation, terminal voltage and active power transfer from bus1 to bus2 are observed. For the disturbance investigated, the FLPSS has increased damping of the system causing it to settle back to the steady state condition is much less time than the CPSS. The proposed stabilizer is easier to
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DESIGN AND SIMULATION OF UPQC TO IMPROVE POWER QUALITY AND TRANSFER WIND ENERGY TO GRID Mr. G.T.Ganesh kumar1, Mr. G. Srinivasan2, Mr.P.Moorthy3 Final year- ME Power Electronics & Drives, Madha Engineering College, Chennai-600 069 Senior Lecturer, Dept of EEE, Madha Engineering College, Chennai-600 069 3 Head of Department of EEE, Madha Engineering College, Chennai-600 069
2 1
Email-gt.gt.kumar@gmail.com Abstract- This study proposes a combined operation of the Unified Power Quality Conditioner (UPQC) with wind power generation system considering investment cost. The proposed system consists of a series inverter, a shunt inverter and an induction generator connected in the DC link through a converter. The proposed system can compensate voltage sag, voltage interruption, harmonics and reactive power. The speed of the induction generator is controlled according to the variation of the wind speed in order to produce the maximum output power. The investment cost of proposed system is compared with investment cost of separated use of UPQC and wind energy conversion system (WECS) and the economic saving due to use of proposed system is estimated. The validity of the proposed system is verified by the results of computer simulation.
Key words- Phase Locked Loop, Point of Common Coupling, Maximum Power Point Tracking, Pulse Width Modulation. INTRODUCTION One of the most interesting structures of energy conditioner is two back-to-back connected DC/AC fully controlled converters. In this case, depending on the control scheme, the converters may have different compensation functions. For example, they can function as active series and shunt filters to compensate simultaneously load current harmonics and supply voltage fluctuations. In this case, the equipment is called Unified Power Quality Conditioner (UPQC). An active shunt filter is a suitable device for current-based compensation. It can compensate current harmonics and reactive power. The active series filter is normally used for voltage harmonics and voltage sags compensation. The UPQC, which has two inverters that share one DC link capacitor, can compensate the voltage sag and swell, the harmonic current and voltage and control the power flow and voltage stability. Nevertheless, UPQC cannot compensate the voltage interruption due to lack of energy source in its DC link. Nowadays, generation of electricity from renewable sources has improved very much. Utilizing of wind energy as a renewable source to generate electricity has developed extremely rapidly and many commercial wind generating units are now available on the market. The cost of generating electricity from wind has fallen almost 90% since the 1980s. Wind is a variable and random source of energy. All types of machines, i.e., DC, synchronous, induction, depending on the size of the system have been used to convert this form of energy to electrical energy. Induction generators are more common and more economical by improvement of power electronics devices and drive methods. Various forms of systems can be used to have some level of control on the wind generation unit. In the variable speed constant frequency systems, power electronic devices are used to allow the rotor speed to be changed while the grid frequency is constant. In one scheme, as studied in this research, a Variable Speed Cage Machine (VSCM) system is used with a rectifier and an inverter connecting the cage induction generator stator to the grid. The advantage of the variable speed constant frequency system is that the rotor speed can be controlled. This makes it possible to capture maximum energy from the wind turbine. A method of tracking the peak power points for a VSCM system is suggested. PROPOSED SYSTEM In Fig1, there are six main parts in proposed system: wind turbine, induction generator, and maximum power point tracking which controls induction generator speed, PWM rectifier, shunt inverter and series inverter of UPQC. The modeling of each section is discussed separately and then the overall model is investigated.
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Figure 1 Proposed system Wind turbine: The output power from a wind turbine can be expressed in below: (1)
Fig. 2 Power coefficient factor versus tip-speed ratio for various pitch angles Therefore, the optimized rotational speed opt for maximum aerodynamic efficiency for a given wind velocity is given by: (5) Where, opt is the optimized tip-speed ratio which is zero and CP is maximum. Hence, to fully utilize the wind energy, should be maintained at opt, which is determined from the blade design. Then from Eq. 2: (6) Where, PM max is maximum mechanical output power of wind turbine at a given wind speed. Once the wind velocity VWIND is measured, the reference speed for extracting the maximum point is obtained from Eq. 5. Induction generator: In this study, a fifth order model for induction generator simulation is used. To overcome the complexity of the model, usually Parks transformation is used. The transformed induction machine equations are described below: (7)
(2)
(3) where, is tip-speed ratio, VWIND is the wind speed, R is blade radius, r is the rotor speed (rad sec-1), is the air density, CP is the power coefficient, PM is mechanical output power of wind turbine and TM is the output torque of wind turbine. The power coefficient CP depends on the pitch angle , the angle at which the rotor blades can rotate along its long axis and tip-speed ratio given by Eq. 4: (4) Where, is the blade pitch angle. For a fixed pitch type, the value of is set to a constant value MAXIMUM POWER POINT TRACKING: In this study, the pitch angle is kept at zero until the nominal power of the induction generator is reached. At high wind speeds, the pitch angle is increased to limit the input power (Fig. 2).
(8)
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The wind turbine converter is designed to control the rotational speed in order to produce the maximum output power, where the indirect vector control is used. The control part consists of a speed controller and the d-q current controllers. The d-axis current component is generally set to maintain the rated field flux in the whole range of speed, while the speed loop will generate the q-axis current component through a PI controller to control the generator torque and speed at different wind speed. The proportional and integral gains for speed controller used in simulation are KP = 12 and Ki = 25, respectively. VA RATING CALCULATION OF SHUNT AND SERIES INVERTER Volt Ampere (VA) rating of series and shunt inverters of UPQC determines the size of the UPQC. The power loss is also related to the VA loading of the UPQC. Here, the loading calculation of shunt and series inverters of UPQC with presence of DG at its DC link has been carried out on the basis of linear load for fundamental frequency. The load voltage is to be kept constant at Vo p.u. irrespective of the supply voltage variation: (25) (12) The load current is assumed to be constant at the rated value: (26) Assuming the UPQC to be lossless, the active power demand in the load remains constant and is drawn from the source: (27) In case of a sag when VS2<VS1, where x denotes the p.u. sag: (28) to maintain constant active power under the voltage sag condition as explained in (1): (29) therefore series inverter VA rating equals to: (30)
Where, is the number of poles in the induction generator. Equation 8 describes torque equation of an induction generator. Wind turbine converter: The mechanical output power of wind turbine and rotor speed for a given wind speed is determined by the intersection of wind turbine and the induction generator characteristic curves.Rotor flux reference frame is used for transformation of induction machine equations. Selecting the d-axis aligned with the rotor flux, the q-axis component of the flux will be zero. This makes the equations easier to handle. In this frame, the torque and flux Eq. 13 described in Eq. 8 can be rewritten as: (9)
(10)
(11)
where, Tr is time constant of rotor and equals
The Eq. 9-12, are the basis for field oriented control. This approach simplifies the induction machine control. The model is very similar to a separately excited DC machine where the flux depends on the field current and the torque is proportional to the flux and the armature current. The main problem associated with field oriented control is the requirement to estimate the flux axis angle. This is done either by measuring the flux at two different points (with 90 displacement), or estimating through rotor speed measurement. In this study, flux axis angle is calculated through rotor speed measurement. (13)
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main supply. Thus this converter act as a rectifier as well as inverter depends upon the requirements.
Injected current through shunt inverter is: (31 ) therefore shunt inverter VA rating equals to:
(32)
Figure 2.3 and 2.4 show VA loading of series and shunt inverters of UPQC for a wide range of power factor and supply voltage sag variations. The VA loading of inverters is calculated for occurrence of supply voltage sag from 10 to 50% and power factor variations from 0.6 lagging to unity power factor, with Zsh = 1 p.u in all cases. The range of supply voltage sag has been chosen such that most practical cases are observed to be in this range as available from power quality survey reports. BLOCK DIAGRAM
This study, a new configuration of UPQC is proposed that has a Wind Energy Generation System (WEGS) connected to the DC link through the rectifier as shown in Fig. 1. The significant advantage of this configuration in compare with separate operation of UPQC and wind energy generation system is reduction in using of one inverter and use of shunt inverter of UPQC as a WEGS`s inverter. The UPQC can compensate the voltage interruption in the source, while the WEGS supplies power to the source and load or the load only. There are two operation modes in the proposed system. The VA rating of series and shunt inverters of UPQC are estimated for proposed system. The investment cost of proposed system is compared with investment cost of separated use of UPQC and WECS using the VA rating calculations and the economic saving due to use of proposed system is estimated. SIMULATION Simulation has become a very powerful tool in industry application as well as in academics, nowadays. It is now essential for an electrical engineer to understand the concept of simulation and learn its use in various applications[8]. Simulation is one of the best ways to study the system or circuit behavior without damaging it. The tools for doing the simulation in various fields are available in the market for engineering professionals. Many industries are spending a considerable amount of time and money in doing simulation before manufacturing their product. In most of the research and development (R&D) work, the simulation plays very important role. Without simulation, it is quite impossible to proceed further. It should be noted that in power electronics, computer simulation and a proof of concept hardware prototype in the laboratory are complimentary to each other. However, computer simulation should not be looked upon as a substitute for a hardware prototype. In many cases, testing a real world system can be prohibitively expensive or out rightly impossible. Seeing how the generator of a power plant is going to be damaged in a real system is an example of an expensive exercise to conduct in reality. But by damaging the generator into a simulated fault condition, generator safety engineers can quickly evaluate potential designs and reduce the level of risk for it to sacrifice.
Fig. 3 Block diagram of UPQC SERIES INVERTER OF UPQC: The function of series inverter is to compensate the voltage disturbance in the source side, which is due to the fault in the distribution line. These converters operate as a controlled rectifier when supply is drawn from the main source. It also act as a inverter during supply inject from dc link to
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SIMULATION TOOLS Simulation of power electronic converters and can be done, either by (I) circuit oriented simulator (e.g. PSPICE, PSIM, TINA, electronics workbench, etc), or by (2) mathematical model based equation solvers using high level languages (e.g., C++, VISUALBASIC, etc.), or high level language based packages (MATLAB, MATHEMATICA, etc). In this we can use the circuit-oriented simulators (PSpice) also few software simulation tools are listed which are widely accepted by the engineering society, particularly by the electrical engineers. The simulation tools are in use in industries as well as academic institution. The program is not interactive, that is the circuit cannot be analyzed for various Component values without editing the program statements. PSPICE does not support an iterative method of solution. If the elements of a circuit are specified, pspice cannot be used to synthesize the circuit elements. The input impedance cannot be determined directly without running the graphic post-processor probe. The student version does not require a floating-point processor for running probe, but the professional version does not require such a co-processor. SIMULATION RESULTS Fig.6 Line compensation circuit with additional UPQC
Fig.7 Voltage across A and B at alpha=0 degree
Fig 4 Line model without compensation circuit
Fig.8 UPQC circuit model Fig 5 Voltage across A and B
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example, HVDC transmission systems require inverter at load center. Whenever multilevel inverters are used at the receiving end of power transmission, THD is reduced to a significant level compared to other Converters.
REFERENCES Fig.9 Voltage across A and B at alpha=36 degree 1. Basu, M., S.P. Das and G.K. Dubey, 2007. Comparative evaluation of two models of UPQC for suitable interface to enhance power quality. Elec. Power syst. Res., 77:821-830. Cavalcanti, M.C., G.M.S. Azevedo, B.A. Amaral and F.A.S. Neves, 2005. A Photovoltaic generation system with unified power quality conditioner function. 31st Annual conference of IEEE Industrial Electronics society, Nov. 6-10, IEEE, Brazil, pp:750-755. Datta, R. and V.T. Ranganathan, 2002. Variable-speed wind power generation using doubly fed wound rotor induction machine; A comparison with alternative schemes, IEEE Trans. Energy Convers, 17: 414-421. Han, B., B. Bae, H. Kim and S. Baek, 2006. Combined operation of unified power quality conditioner with distributed generation. IEEE Trans. Power Del., 21:330-338. Power Electronics, Muhammad H. Rashid. Power Electronics, B.C. Sen. www.ieee.org
CONCLUSION This study describes a combined operation of the unified power quality conditioner with wind power generation system considering investment cost. The proposed system can compensate voltage sag , voltage interruption, and control the harmonics and reactive power . The VA rating of series and shunt inverters of UPQC are estimated for proposed system. The investment cost of proposed system is compared with investment cost of separated use of UPQC and WECS using the VA rating calculations and the economic saving due to use of proposed system is estimated nearly 20%. The circuit with series converter and shunt inverter section is simulated. Series converter drawn the supply from main source so it act as a controlled rectifier. It is used to control the terminal voltage. Shunt inverter control the power flow .thus these two converter control the voltage sag and power flow control .Thus the performance of the system is improved using facts device . Multilevel inverter with 9-level steps has been done using PSpice simulink. The problem has been focussed in minimizing the number of power switches for a given number of levels. Different combinations and topologies were presented and mathematical relations for firing angles were developed. A multilevel inverter with individual dc sources has been proposed for use in large electric drives. Simulation and experimental results have shown that with a control strategy operates the switches at the fundamental frequency, these converters have low output voltage THD and high efficiency and power factor. In future scope, multilevel inverters are applied to power systems especially in long distance power transmission and bulk power transmission. For 2.
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5. 6. 7.
8. www.mathwork.com
Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore Energy Conservation
and Optimization in Process Industries
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(For Coimbatore Water Supply Scheme with Pillur reservoir as source) Ayyappan.S and Saravanan.T 1st year, M.E. Control Systems, PSG College of Technology, Coimbatore. E-mail: ayyappans2004@yahoo.co.in, t.saravanan@hotmail.com the fluid. The momentum produces an increase in pressure or flow at the pump outlet. The vast majority of pumps used today are of the centrifugal type. Our case study also discussed with only centrifugal pumps
Abstract:
The AC induction motor is the main stream for energy conversion in Industry sector. It has been estimated that about 70 % energy is consumed by industrial sector in India. From this, 70% energy is used for AC motors only. Much of the power that is consumed by AC motors goes into the operation of fans, blowers and pumps. It has been estimated that approximately 50% of the motors in use are for these types of loads. Basically, fans, blowers and pumps are designed to be capable of meeting the maximum demand of the system in which they are installed. However, quite often the actual demand could vary and be much less than the designed capacity. These conditions are accommodated by adding outlet dampers to fans & blowers or throttling valves to pumps. These are effective and simple controls, but severely affect the efficiency of the system. Variable speed control of the fan, blower or pump. This method produces a more efficient means of flow control than the existing methods. In addition, adjustable frequency drives offer a distinct advantage of energy saving with speed control of fans, blowers & pumps.
Where, N=Pump Speed Q=Flow P=Pressure W=Horse Power
Pumps:Characteristics and Operation

Pumps are generally grouped into two broad categories, positive displacement pumps and centrifugal pumps. Positive displacement pumps use mechanical means to vary the size (or move), the fluid chamber to cause the fluid to flow. Centrifugal pumps impart a momentum in the fluid by rotating impellers immersed in
Variable Speed Drive Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore Major methods of flow control by pumps, such as, by flow control valves and variable speed drives. By this method, the operating point for a given system load shifts along the system charteristics curve as the speed of the pump is varied and is represented in the below figure.
will be avoided.
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Month
Dam Level 1373'
Energy Consumption (as per EB bill) 659888 Units
Remarks
04/10
Before Installation of VFD After Installation of VFD
10/10
1373'
615632 Units
Savings
Rs.44,256.00 x Rs. 3.50/Unit =Rs. 1,54,896.00 Rs. 7,745.00
Electric Tax 5%
Conclusion:
Case Study:
Coimbatore water supply scheme with Pillur reservoir as source caters to the needs of a section of Coimbatore Corporation, 22 Town Panchayats and 523 rural habitations. The total quantity of Water supplied under this scheme is 125 MLD. Reason for Selecting Variable Frequency Drives (VFD) at this place Frequency persisting Variation problem is
The energy saving of the variable speed drive system is realized if the ratio of the maximum and minimum load is high and also if the system operates at less than the maximum load for a significant fraction of time. Thus Total=Rs.1,54,896.00+ Rs. 7,745=Rs. 1,62,641 in addition a demand of 100KVA is reduced, so that further saving of Rs.20,000.00. References: (1) Tamilnadu Water Supply Board (TWAD) Pillur Dam Site Visit. (2) IIT Kharagpur, Technical notes. (3) VariableFrequencyDrive Manufacture notes.(M/s.AMTECH Electronics, Gujarat) .
Pumping head reduced to 41m as against the designed head of 62m due to reduced depth of pump house and reduced intake tunnel entry As a result of reduced efficiency with regard to dropping performance curve. If Power failure occurs in (within a second) or short duration, the motor will not be stopped. The VFD will supply the stored DC supply to run the motor, thereby interruption during short term
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Interline Dynamic Voltage Restorer - An Economical Way to improve Power Quality

N. Naveen Kumar*, S. Kavitha **, *P.G Student, **Assistant Professor, EEE, Madha Engineering College, Chennai.-69 Email id: naveengce@gmail.com
ABSTRACT: To restore the load voltage, Dynamic Voltage Restorer (DVR), which is installed between the supply and a sensitive load, should inject voltage and active power from DVR to the distribution system during voltage sag. Due to the limit of energy storage capacity of DC link, it is necessary the minimize energy injection from DVR. In this paper the techniques of the supply voltage sag compensation in a distribution feeder are presented. In addition, a concept of inter-line dynamic voltage restorer (IDVR) that two DVRs in two different voltage distribution system are connected to a common DC link capacitor is proposed. One of these two DVR (low voltage) operates in voltage sag compensation mode and a novel control technique uses to inject minimum energy from DC link capacitor to low voltage distribution system. The other DVRs (medium voltage) control the voltage of DC link capacitor so that energy flows from medium voltage distribution system to the DC link capacitor. I. INTRODUCTION The most important power quality issues is voltage sags. The increasing usage of voltage sensitivity devices has made industrials processes more susceptible to supply voltage sags. Voltage sags may cause equipment tripping, shutdown for the domestic equipment, and miss-operation of drive systems. When a fault occurs in the system, the customer voltage drops below its nominal value on one or more phases. Voltage sags of down to 70% are much more common than complete outages. Dynamic voltage restorer (DVR) with energy storage can be used to correct the voltage sag at distribution system. A DVR is basically a controlled voltage source installed between the supply and a critical sensitive load. It injects a voltage on the system in order to compensate any disturbance affecting the load voltage. The compensation capacity of a particular DVR depends on the maximum voltage injection ability and the real power, which can be supplied by the DVR. When DVR restorers voltage disturbances, active power or energy should be injected from DVR to the distribution system. DVR could maintain load voltage unchanged during any kind of faults, if the capability of energy storage of DVR were infinite. Energy storage devices, such as batteries or super-conducting magnetic energy storage systems (SMES) are required to provide active power to the load when voltage sags occur. Because of the energy limitations of these devices, it is necessary to minimize energy injection from DVR. The inter line dynamic voltage restorer (IDVR) similar to the inter line power flow controller (IPFC) in transmission system uses from several DVRs protecting sensitive loads in different distribution systems to share a common DC link energy storage. In the simplest case, we consider two different voltage distribution system protected by two DVR. Low voltage DVR operates in voltage sag mitigation mode and uses a new minimal energy control method to inject active power from DC link capacitor for balanced and unbalanced voltage sags. In the same time medium voltage DVR keeps the voltage of DC link capacitor constant in order to control of active power flow from distribution system to DC link capacitor. II. DVR IN DISTRIBUTION SYSTEM Power circuit of a DVR in a distribution system is shown in Fig 2.1. The main function of a DVR is the protection of sensitive loads from voltage sags coming from network. Therefore, the DVR is located on approach of sensitive loads. If a fault occurs on other feeders, DVR inserts series voltage, Vdvr and compensates load voltage to pre fault Value. Distribution systems commonly use a deltastar or a star-star transformer. If delta-star transformer is used in distribution system, zerosequence voltages will not propagate through the transformer when earth faults occur on the higher voltage level. Therefore, restoration of positive sequence and compensation of negative sequence Voltage are necessary.
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current , load power angle and the phase angle of ith phase respectively. When a fault occurs in other lines , the left hand side voltage of DVR1, Vs1i drops and the DVR1 injects a series voltage, Vdvr1i through the injection transformer as Vdvr1i=VL1i-Vs1i , i=1,2,3
The main elements of the three-phase four- wire DVR are the energy storage system, the voltage source converter, the LC filter and the coupling transformers. The AC side of converter is connected to the line through a LC filter. Due to switching, the high order harmonics of converter must be removed by small high pass filters (represented by Ls Cs ). The sinusoidal pulse width modulation technique (SPWM) is commonly used to control forced-commutated converters. III. CONVENTIONAL CONTROL STRATEGY FOR DVR1 Several control techniques have been proposed for voltage sag compensation such as pre-sag method, in-phase method and minimal energy control. It must be said that the characteristics of the sensitive load determine the control method and the compensation strategy for the DVR. For example, the linear loads are not sensitive to phase angle jump and only magnitude of voltage is dominant. The control techniques should consider the limitations of the DVR such as the voltage injection capability (converter and transformer rating) and energy storage system limitation. The second limitation means that the minimization of exchanged active power from common DC link to the distribution system must be considered. A. Pre-Sag Compensation Strategy The most of nonlinear loads such as thyristorcontrolled loads, which use the supply voltage angle as a set point, are sensitive to phase jumps. To overcome this problem, this technique compensates the difference between the sagged and the pre-sag voltages by restoring the instantaneous voltages to the same phase and magnitude as the nominal pre-sag voltages. The disadvantage is the capacity limitation of energy storage device for the injection of active power. Fig 3.1 shows the phasor diagram of the pre-sag compensation strategy. In this diagram the subscript i is ith phase, Vs1i, VL1i , Vdvr1i , IL1i , represent the left hand side voltage of DVR1, the load voltage, the DVR1 injected voltage, the load
Fig 3.1 Phasor Diagram of Pre Sag Control
B. In-phase compensation In this strategy the restored voltage, Vdvr1i is inphase with the left hand side voltage of DVR1, Vs1i regardless of the load current and the pre fault voltage. The phasor diagram of this case is shown in Fig 3.2. The magnitude of Vdvr1i is so that the magnitude of VL1i is 1 pu and obtained as: Vdvr1=1-Vs1 The advantage of this method is that magnitude of injected voltage is minimum. Therefore, for a given load current and voltage sag the apparent power of DVR is minimized. The injected active power from energy storage to load for balanced sag is determined by the following equation,
Fig 3.2 Phasor Diagram of In Phase Control
C. Minimal Energy Technique For a given load and balanced sag if voltage phasor, Vdvr1 ,is perpendicular to the load current, IL1 , then the active power injection is not required to restore the voltage by the DVR1. Fig 3.3 shows the phasor diagram for the minimal energy control strategy. In this diagram, d , are
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assumed zero and the positive value of minimum injected active power is estimated as follows:
the angle of VL1 and Vdvr1, respectively. In this case, be obtained as,
Fig 3.4 Injected active power vs. injected voltage
Fig 3.3 Phasor Diagram of Minimal Energy control
If the supply voltage parameters satisfy the condition then
the value of d is feasible,

D. Suggested Control Strategy
As mentioned earlier, for shallow sag injected power, Pdvr is zero. However, for deep sag Pdvr1 is not zero. Considering the Fig, 3.4 for a given load current and Vs1 increase of results increase of Vdvr1 (i.e., both magnitude and phase angle). The relationship between the injected active power, Pdvr1, and the injected voltage Vdvr1 is illustrated in Fig 3.4. The parameter of this curve is a balanced three-phase voltage sag, for a given load (with Cos-1=0.8). It is obvious that for a 0.2 pu voltage sag the minimum value of Pdvr1 can be equal to zero. While, for the shallow sag (less than 0.2 pu) minimum value of Pdvr1 is negative and for deep sags (more than 0.2 pu) minimum value of Pdvr1 is positive. In the in-phase compensation strategy the apparent power of DVR is small and injected active power of DVR is considerable. But in the minimal energy technique injected active power is minimum and the apparent power of DVR is considerable. In this paper, the proposed strategy is the minimization of the injected active power for balanced and unbalanced sag. As an example, Fig.3.5 presents the relationship between the minimum injected active power, Pdvr and the balanced three-phase voltage sag for a DVR1 for a given load (with cos_1=0.8). It is obvious that the negative value of minimum injected active power is
Fig 3.5 Minimum injected active power vs. voltage sag
IV. INTER-LINE DYNAMIC VOLTAGE RESTORER (IDVR) Interline Dynamic Voltage Restorer (IDVR) is that two DVRs in two different voltage .Distribution System are connected to a common DC link capacitor is proposed. One of these two DVR operates in Voltage Sag compensation mode and a novel control techniques used to inject minimum energy from DC link capacitor to low voltage distribution system. The other DVRs controls the voltage of DC link capacitor so that energy flows from medium voltage distribution system to the DC link capacitor. The proposed system can compensate voltage sag, voltage interruption, harmonics and reactive power. AC source: It gives the AC supply to rectifier. The input side having one inductive filter. It is used to improve the input power factor.
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Converter-1: It is used to convert dc to ac voltage.the phase shift pulse method is used to control the inverter as a result to achieve the ZVS . Converter-2: It converts AC supply to DC supply. DC supply having some ripples. It is filtered with the help of capacitor filter. AC Load: Multi level inverter is generate ac output voltage. it is used to run single phase ac motor and any appliance required for ac voltage.
When a fault occurs in other lines, the left hand side voltage of DVR1, i.e., Vs1 drops and the DVR1 injects a series voltage, Vdvr1 through the injection transformer, Interline dynamic voltage restorer in the general form uses form several DVRs in different distribution feeder for compensate voltage sag that are connected to a common DC voltage link. Because of the feeders in IDVR system are obtaining from different grid sub stations and perhaps and different voltage levels, voltage sag appearing in one feeder may have lesser influence on the other feeder .
Micro controller: Micro controller is used to generate triggering pulse for MOSFET. It is used to control the outputs. Micro controller have more advantage compare then analog circuits and micro processor such as fast response, low cost, small size and etc. Driver 1 & 2: It is also called as power amplifier because it is used to amplify the pulse output from micro controller. It is also called as opto coupler IC. It provides isolation between microcontroller and power circuits. Regulated Power supply (RPS): RPS gives 5V supply for micro controller and 12V supply for driver. It is converted from AC supply. AC supply is step down using step down transformer.
When voltage sag occurs in feeder 1 may have less effect in feeder 2 and they can be supposed as two independent distribution feeder. In this case active power is drawn from common DC link instead of energy storage as shown in Fig.4.3 and DVR2 that is in normal condition injects active power to common DC link by controlling of DC link capacitor voltage. As mentioned earlier DVR2 injects active power Pdvr2 when a long duration voltage sag occurs in line 1 to compensate Pdvr1 and the converters power looses Ploss in Steady state as follows, Pdvr2 =Pdvr1+ Ploss The load 2 in feeder 2 is not sensitive to voltage phase angle. The control strategy for DVR2 is developed so that whenever active power injects to common DC link it maintains the magnitude of load voltage constant. Where Vs2, VL2 , Vdvr2 , IL2 , represent the left hand side voltage of DVR2, the load 2 voltage, the DVR2 injected voltage, the load 2 current , load 2 power angle and power injected phase angle respectively. By neglecting from harmonics in common DC link voltage all voltage and current in feeder 2 can be supposed harmonic free.
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injection power during shallow sag and minimizes injection power during deep sag and DVR2 injection active power is controlled by keeping constant common DC link voltage with good dynamic response and in the same time the inserted DVR1 voltage is equal or less than 0.6 pu
Figure 4.3 The simplest IDVR with two converter Figure 4.4 Equivalent circuit of power system Figure 4.5 Phasor diagram of DVR2
Fig 5.1 SAME LOAD AND DIFFERENT VOLTAGE CONDITION WITH COMPENSATION
Real power improvement: Real power is governed by the equation, P = Vs Vr Sin / X 1) Decrease the reactance of the line 2) Inject the voltage Among these, we follow the injecting voltage technique for real power improvement Reactive power improvement: Reactive power is governed by the equation, Q = | Vr| (| Vs| - |Vr|) X 1) Excitation control 2) Tap changing method 3) Idvr Out of the above specified methods our project employs, the technique of Idvr concept.
Fig 5.2 IDVR MODEL
BEFORE COMPENSATION Fig 5.3 OUTPUT VOLTAGE WITH VOLTAGE SAG FOR LINE 2
V. SIMULATION RESULTS The Interline Dynamic Voltage Restorer is simulated using the mat lab simulink and the results are presented here. The circuit model of the IDVR is shown in Fig.5.1. Scopes are connected to measure output voltage, driving pulses, output current Simulation results show that based on the suggested control strategy, DVR1 consumes zero
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VI. CONCLUSION In order to compensate voltage sag it is possible to use dynamic voltage restorer (DVR) in distribution system for a sensitive load. Due to the limit of energy storage capacity of DC link, it is necessary to minimize energy injection from DVR. In this paper the control strategies for the compensation of the supply voltage sag is presented. In addition, a new concept of restoration strategy based on dynamic voltage restorer is proposed to inject minimum energy from common DC-link in unbalance sags. Proposed control method makes zero injection power during shallow sag and controls DVR1 so that injection of power is minimized during deep sag. In the same time the other DVR injects energy to common DC-link by keeping voltage of common DC-link constant. Simulation results shows that the proposed method can minimize the injected active power of DVR from one feeder to other feeder. REFERENCES 1. S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, Design and Analysis of the Inverter-Side Filter Used the Dynamic Voltage Restorer, IEEE Transactions on Power Delivery, vol. 17, no. 3, July2002. 2. X. Lei, D. Retzmann and M. Weinhold, Improvement of Power Quality with Advanced Power Electronic Equipment, Electric Utility Deregulation and Restructuring and Power Technologies, 4 -7 April, IEEE 2000. 3. Il-Yop Chung, Dong-Jun Won, Sang-Young Park,Seung-Il Moon, Jong-Keun Park, The DC LinkEnergy Control Method in Dynamic Voltage Restorer System, Electrical Power and Energy Systems, vol. 25, 2003, 525-531. 4. Hongfa Ding, Shu Shuangyan, Duan Xianzhong, Gao Jun, A Novel Dynamic Voltage Restorer and its Unbalanced Control Strategy Based on Space Vector PWM, Electrical Power and Energy Systems, vol. 24, 2002, 693-699. 5. V. K. Ramachandaramurthy, C. Fitzer, A. Arulampalam, C. Zhan, M. Barnes and N. Jenkins, Control of a Battery Supported Dynamic Voltage Restorer, IEE Proc.-Gener. Transm. Distrib., vol. 149, no 5, September 2002. 6. Changjiang Zhan, Atputharajah Arulampalam, and Nicholas Jenkins, Four-Wire Dynamic Voltage Restorer Based on a Three-Dimensional Voltage Space Vector PWM Algorithm, IEEE Transactions on Power Electronics, vol. 18, no. 4, July 2003. 7. H. M. Wijekoon, D. M. Vilathgamuwa and S. S. Choi, Interline Dynamic Voltage Restorer: An Economical Way to Improve Interline Power Quality, IEE Proc.-Gener. Transm. Distrib., vol. 150, no. 5, September 2003.
Fig 5.4REAL POWER AND REACTIVE POWER FOR LINE2
AFTER COMPENSATION Fig 5.5 IDVR OUTPUT
Fig 5.6 VOLTAGE ACROSS LOAD 1 AND LOAD 2 (LINE 2)
Fig 5.7 REAL AND REACTIVE POWER FOR LINE 2
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An Adaptive Hysteresis Band Current Controller Based Active Power Filter For Harmonic Suppression And Reactive Power Compensation
T Rajesh1 V.M Ramakrishnan2
1.Assistant
R. Balahemalatha3
S.Nisha4
Professor. 2. Student 3. Student 4. Student
Info Institute of Engineering
Abstract-This paper presents a method for the harmonic and the reactive power compensation using a combined system of Static Var Compensator (SVC) and Active Power Filter (APF).The system has the function of power factor correction, voltage stability, and harmonic suppression. The small rating APF is used to filter harmonics generated by the nonlinear load and the TCR in the SVC and to suppress possible resonance between the grid and the passive power filter (PPFs). The configuration and principle of the combined system were discussed first, and then, the control method for the combined system was presented. An optimal nonlinear proportional integral control was proposed to improve the dynamic response and decrease the steady-state error of the SVC. Harmonic extraction with the synchronous reference frame (SRF) method and hysteresis current controller were proposed to improve the performance of APF. Simulation results show that the proposed combined configuration can effectively stabilize system voltage, correct power factor, and suppress harmonic currents. Simulation results carried out by MATLAB/SIMULINK 7.6.
I. INTRODUCTION
recent wide spread of power electronic equipment has caused an increase of the harmonic disturbances in the power Systems. The active power filter (APF) can solve the problems of harmonic and reactive power simultaneously. In SHAPF design and control, the instantaneous power theory may be complicated for the application of compensation current for the unbalanced and distorted mains voltage in most of time and most of industry power systems[1][2][3]. Thus, the Synchronous reference frame (SRF) based harmonic extraction is used here, since its proposal, has been applied in the control of threephase hybrid shunt active power filters. The proposed control algorithm gives an adequate compensating current reference even for non ideal
voltage system. Thus this paper presents the technique with the Synchronous reference frame (SRF theory) as a suitable method to the analysis of SHAPF control in the non-linear three-phase systems. The control of switching frequency is described with introducing an hysteresis band current control algorithm. Then, the simulation results are presented followed by the conclusion. To prevent the inflow of harmonic and reactive currents and to improve the operating ability of the transmission systems, a kind of Flexible AC Transmission System (FACTS) has been proposed. The Static VAR Compensator (SVC) is an important component of FACTS. It is usually installed in power transmission systems and serves in various ways to improve the system performance. By the rapid control of their reactive power output, the SVCs regulate system voltages, improve transient stability, correct power factor, reduce temporary over voltages and damp sub synchronous resonances. Usually, an SVC is composed of a Thyristor-Controlled Reactor (TCR) and Fixed Capacitors (FCs). However, a TCR will introduce harmonic currents. Another problem is the harmonic amplification. The TCR introduces harmonic currents, and the FC amplifies the harmonic currents generated by the TCR which could be mitigated by APFs.
The
II. COMBINED SYSTEM OF SVC AND APF

A. Static Var Compensator Here the SVC consists of a TCR connected in parallel with an FC in series with an inductor L (PPF),the conduction angle of the TCR depends on the firing angle . The relationship between and is = 2( ).
Fig 1 FC TCR Configuration
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on the technique used to compute the reference current, design of the inverter and the control method used to inject the desired compensation current into the line. C. The Combined System
The firing angle can be controlled to take any value between 90 and 180, corresponding to values of between 180 and 0.Harmonics generated by the TCR[1] can be as shown as (1) The relation between the fundamental component of the reactor current,[2] and the phase-shift angle is given by (2) The magnitudes of the harmonic currents[1] are (3) In order to eliminate low-frequency current harmonics (third, fifth, seventh), delta configurations (for zero sequence harmonics) and passive filters may be used, as shown in Fig. 2 B. Active Power Filter
Fig 3 Configuration of the combined system
Fig 2 Shunt active filter
One of the most popular active filters used for compensating reactive power and harmonics is the shunt active filter [3] shown in Fig. 2. The simple SAF arrangement with non-linear load is considered. The system comprises balanced threephase voltage sources (VR, VY, VB) feeding a three-phase diode bridge rectifier with resistive load. The SAF is connected to the three-phase line through the inductor L. The converter employed for the SAF is an IGBT based converter, it is a current controlled voltage source inverter which is connected in parallel with the load. This inverter injects an appropriate current into the system to compensate for the undesired components of load current that are responsible for low power factor. The performance of an active filter depends mainly
The combined system comprises a classical SVC and an active filter with a coupling circuit is shown in Fig 3. The SVC consists of TCR and fixed capacitor; TCR uses the delta connection, and FC uses star connection. Moreover, its capacitor is in series with inductor to form single tune PPF. The coupling circuit, which consists of L1, C1, and CF, is used for coupling the APF and the grid. L1 and C1 tune at fundamental frequency and then compose the coupling circuit with CF. The APF in parallel with the fundamental resonance circuit is directly connected in series with a matching transformer. The coupling capacitor CF sustains fundamental voltage of the grid, while APF only supports harmonic voltage, which greatly reduces the current requirements of APF and minimizes the voltage rating of semiconductor switching device. Because of these excellent characteristics, the combined system is effective to suppress harmonics generated by both TCRs and nonlinear loads, to compensate reactive power dynamically, and to improve voltage stability. III MODELLING AND DESIGN
A. Modelling of DSTATCOM
The modelling of DSTATCOM [6] is based on is base on the SRF method. Fig 4 shows the simplified single line diagram of DSTATCOM comprising of a DC link capacitor, IGBT based VSI, coupling filter and the PCC voltage. Here, Vsa, Vsb, Vsc: Voltage at PCC Vca, Vcb, Vcc: Inverter output Voltage Lf : Inductance of the Coupling filter Rf : Equivalent filter resistance C .DC link capacitor
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(8)
Fig 4. Simplified model of STATCOM
Neglecting the voltage harmonics produced by the direct and quadrature axis voltages, (9)
The per phase instantaneous PCC voltage is given as:
(4) where Vs is the RMS value of the PCC voltage, the relationship between the PCC voltage, inverter output voltage, and the current is given in (5)
As per the power balance theory, the instantaneous power at ac-dc terminals of the inverter is equal, giving the following power balance equation, (10) and the dc side circuit equation is given as
(5)
(11) Combining equation (7)-(11) the DSTATCOM model in state space can be written as: (12) where A is given as
The above equation can also be written as
(6)
Transforming equations (5) to synchronous reference frame using Parks transformation the equation becomes
(7)
Where the system frequency and m is is the modulation index of the converter, writing equations (7) in matrix form
Since d-q axes are not stationary, and they follow the trajectory of vector, within this synchronous rotating frame,Vs=Vsd and Vsq =0, the instantaneous active and reactive power as per the Instantaneous Reactive Power theory are described as:
(13) It can be concluded that the STATCOM performance can be controlled by controlling the active and reactive component of current id and iq
216 transients [7]. The principle conservation is applied as of energy
Therefore the choice of current regulation criteria is extremely important in the performace of STATCOM
B. Active Power Filtering Requirements An active power filter should at least be able to inject frequencies up to the 20th harmonic and ideally be able to compensate up to the 50th harmonic. This high frequency operation limits the size of the injection inductor. When the inductance is too large the maximum rate of change of current will be too low to track the steep current changes that occur with high frequencies and for small inductances, the rates of change of current will be high. Due to this, high switching frequency results and causes large losses in the semiconductor switches. This also leads to increased levels of electromagnetic interference and requires very high-speed comparisons of the actual current against the hysteresis limits. A three leg VSI is used as Active shunt compensator as shown in Fig. 3, and this topology has six IGBTs, three AC inductors, and one DC capacitor. The required compensation to be provided by DSTATCOM decides the rating of the VSC components. a) DC Capacitor Voltage The minimum dc-bus voltage of VSC of DSTATCOM should be greater than twice the peak of the phase voltage of the system [7]. The DC bus voltage is calculated as
(15) where Vdc is the reference DC voltage and Vdc1 is the minimum voltage level of DC bus , a is the overloading factor, V is the phase voltage, I is the phase current, and t is the time by which the DC bus voltage is to be recovered. Considering the minimum voltage level of the dc bus, Vdc1= V, Vdc= V, V= V, I= A, t= Cs, =, the calculated value of Cdc is F and is selected as F
c) AC Inductor
The selection of the AC inductance (Lf) of VSC depends on the current ripple icr(p-p), switching frequency fs, DC bus voltage (Vdc), and Lf is given as [7]
(16) where m is the modulation index and a is the overload factor. Considering icr(p-p)=5%, fs= kHz,m=1, Vdc=700 V, a= , the Lf value is calculated to be mH. A round-off value of Lf of mH is selected in this investigation.
d) Ripple Filter
(14) where m is the modulation index and is considered as 1 and VLL is the AC line output voltage of DSTATCOM. Thus Vdc is obtained as for VLL of 415 V and is selected as
b) DC Bus Capacitor
A low-pass first-order tuned at half the switching frequency is used to filter the high frequency noise from the voltage at the PCC. Considering a low impedance of for the harmonic voltage at a frequency of kHz, the ripple filter capacitor is designed as Cf= F. A series resistance (Rf) of is included in series with the capacitor (Cf). the impedance is found to be at fundamental frequency, which is large , and hence the ripple filter draws negligible fundamental current.
.
The value of dc capacitor (Cdc) of VSC OF DSTATCOM depends on the instantaneous energy available to the DSTATCOM during
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IV CONTROL METHOD COMBINED SYSTEM

A. Control Method of APF
OF
THE
Fig 6 Harmonic reference extraction
Fig 5 Principle of harmonic and reactive power detection
To effectively compensate the load harmonic currents, the active filter controller should be designed to meet the following three goals: Extract and inject load harmonic currents Maintain a constant DC capacitor voltage Avoid generating or absorbing reactive power with fundamental frequency components
1.
Harmonic Current Detection

For diode or thyristor rectifier loads, the most common harmonic currents are of the 5th, 7th, 11th, and 13th order. Although a high-pass filter can be used to extract these components directly from the line currents, it is not feasible to obtain high attenuation at the fundamental frequency due to the high current amplitude. The synchronous q-d reference frame controller developed for shunt active filter systems is used to generate the reference compensating current To get the reference harmonic current, first the load current is measured. The load current consists of fundamental component i1 and harmonic component ih . Using the band pass filter, with appropriate cut-off frequencies the fundamental current is extracted from the measured system load current. Using comparator, as shown in Fig. 6, the load current is compared to the fundamental component and the error is the reference harmonics signals.
instantaneous where, ih = (iha + ihb 2 + ihc 2 ) ,the magnitudes of the three phase harmonic currents. il = load current and i1 = fundamental component of the load current. Figure 5 presents the block diagram for the fundamental current extraction process with the synchronous reference frame method(SRF). The SRF method [4]-[5] is based on the determination of the instantaneous active and reactive currents (id and iq). The SRF method creates a reference frame of orthogonal axes that rotates at the supply frequency (d-q system), that is a synchronous reference. This synchronism with the supply can be achieved by a phase locked loop (PLL) connected to the supply voltages and currents. In this rotating reference, the fundamental current become a DC values in the id-iq currents that can be determined by some kind of low pass filer, like: butterworth or moving average.In order to calculate the id-iq currents, the invariant power Clarke transformation is applied to the stator currents, followed by the Park transformation, so that the three phase currents ia, ib and ic are transformed from three phase abc reference frame to two phase ds qs (--0)stationary reference frame currents ids and iqs (i,i,i0) using (4)
(17)
The currents ids and iqs (i, i, i0) are now transformed to synchronously rotating deqe reference frame currents id and iq by the unit vectors coos and sin as shown below (5);
(18)
where = t+ 0, 0 is the original phase angle of d-q reference frame; and the fundamental
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For the active filter to operate effectively it is important to maintain the dc capacitor voltage at a constant value. Since the active filter topology is essentially identical to that of an active rectifier, similar control strategies for the active rectifier are applicable. The dc capacitor voltage is directly affected by the real power transferred across the active filter. To keep the voltage constant, ideally no real power should be transferred. However, due to losses in switching devices and other components, a small amount of real power is needed. In the synchronous reference frame with the q-axis aligned with the voltage at the point of common coupling, the real power transferred can be expressed as
frequency unit vectors cos and sin are determined by PLL. The id and iq components can be both divided into alternating (AC) and constant parts (DC), as shown in equations (19)
= =
+ +
(19)
After the Park transformation the fundamental phase currents becomes the dc parts of the id and iq ( and ) and all the rest of the harmonics becomes the ac parts of them ( and )with the frequency offset equal to the supply frequency. Therefore , eliminating the ac parts of id and iq ,i.e., ( and ) by some kind of low
pass filter, fundamental currents at the d-q-0 system, i.e., ( and ), will last and so after
the transformation to the a-b-c system, they can be subtracted from the line phase currents. Once the currents were and determined, they must be transformed to the --0 i.e., (ipd and ipq) systems by the inverse Park transformation in equation (20)
which means that by adjusting the q-axis filter current the real power can be effectively controlled. The controller diagram is shown in Fig.7
(20)
And, so finally the components from the stationary reference frame ipd and ipq i.e., ( and )are transformed back to three phase reference frame;the a-b-c system by the inverse invariant power Clarke transformation in equation (21)
Fig. 7 . Active filter control algorithm
3. Reactive Power Control In most cases the active filter is rated based on the harmonic components. Although the active filter is capable of generating or absorbing reactive power, it is not intended to be used as a reactive power compensator. Therefore, a unity power factor for fundamental frequency components is required at the active filter terminals. Since the reactive power can be expressed as
(21)
Since the DC quantity in the deqe reference frame exactly corresponds to the harmonic frequency of interest, extraction of the DC quantity using the low pass filter ensures exact synthesis of the harmonic current in the abc reference frame. 2. DC Voltage Control Loop
this goal can be achieved by keeping the d-axis current at zero, as shown in Fig. 7. The combined control of dc capacitor voltage and reactive power uniquely determines the fundamental frequency component of the active filter output current. This current is then superimposed onto the commanded
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Within these limits even while the reference
harmonic currents, and the commanded filter currents iaf *, ibf *and icf * can be obtained. 4. Adaptive Hysteresis Band Current Controller Hysteresis current control is a method of controlling a voltage source inverter so that an output current is generated which follows a reference current waveform. This method controls the switches in an inverter asynchronously to ramp the current through an inductor up and down so that it tracks a reference current signal. This technique has proven to be most suitable for all the applications of current controlled voltage source inverters in active power filters. The hysteresis band current control is characterized by unconditioned stability, very fast response and good accuracy [8]. On the other hand, the basic hysteresis technique exhibits also several undesirable features, such as uneven switching frequency that causes acoustic noise and difficulty in the designing input filters [9]. A hysteresis current controller is implemented with a closed loop control system and is shown in diagrammatic form in Fig .7. An error signal, e(t), is used to control the switches in an inverter. This error is the difference between the desired current, i*ca , and the current being injected by the inverter, ica . When the error reaches an upper limit, the switches are switched to force the current down. When the error reaches a lower limit the current is forced to increase. The minimum and maximum values of the error signal are emin and emax respectively. The range of the error signal, emax emin, directly controls the amount of ripple in the output current from the inverter and this is called the Hysteresis Band. The hysteresis limits, emin and emax, relate directly to an offset from the reference signal and are referred to as the Lower Hysteresis Limit and the Upper Hysteresis Limit. The current is forced to stay.
current is changing. The ramping of the current between the two limits is illustrated in Fig.8. The switching frequency is altered by the width of the hysteresis band, the size of the inductor that the current flows through (L in Fig.7) and the DC voltage applied to the inductor by the inverter. A larger inductance will yield a smaller di/dt for a given voltage and so the slope of the saw tooth waveform in Fig .8 will be less.
Fig. 8 Operational waveform of hysteresis current controller
The hysteresis band current controller decides the switching pattern of active power filter. The switching logic is formulated as follows: If ica < (ica*- HB), for leg a (SA=1), the upper switch is OFF and the lower switch is ON. If ica > (ica*+ HB), for leg a (SA = 0), the upper switch is ON and the lower switch is OFF. The switching function SB and SC, which are for phases B and C respectively, are determined similarly, with the corresponding reference, the measured currents and the hysteresis bandwidth (HB). The switching frequency of the hysteresis band current control method described above depends on how fast the current changes from the upper limit of the hysteresis band to the lower limit of the hysteresis band, or vice versa. The rate of change of the actual active power filter line currents varies the switching frequency, therefore the switching frequency does not remain constant throughout the switching operation, but it varies along with the current waveform. Furthermore, the line inductance value of the active power filter and the dc link capacitor voltage are the main parameters determining the rate of change of active power filter line currents. The switching frequency of the active power filter system also depends on the capacitor voltage and the line inductances of the active power filter
Fig .7 Block diagram for hysteresis current controller
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(26) where t1 and t2 are the respective switching intervals and fc is the switching frequency. Adding equation (24) and equation (25) and substituting it to Equ. (26), it can be written as the follows:
configuration. The bandwidth of the hysteresis current controller determines the allowable current shaping error. By changing the bandwidth, the user can control the average switching frequency of the active power filter and evaluate the performance for different values of hysteresis bandwidth. In principle, increasing the inverter operating frequency can help to get a better compensation current waveform. However, there are many device limitations and the switching frequency increasing will cause switching losses increasing and EMI related problems. The range of switching frequencies is based on a compromise between these factors. Fig. 9 shows PWM current and voltage waves for phase a. The current a i tends to cross the lower hysteresis band at point 1, where the upper side IGBT of leg a is switched on. The linearly rising current (i+) then touches the upper band at point 2, where the lower side IGBT of leg a is switched on.
(27) Subtracting equation (25) from equation (24), we can get:
(28) Substituting equation (23) to equation (28) gives us the follows:
(29)
Substituting equation (24) to equation (28) and simplifying it gives us the follows:
(30)
Substituting equation (30) to equation (29), we can get:
Fig. 9 Current and Voltage Waves with Hysteresis Band Current Control
(31)
Where fc is modulation frequency, m=dica*/dt is the slope of command current wave. The hysteresis band can be modulated at different points of fundamental frequency cycle to control the switching pattern of inverter. For the symmetrical operation of all three phases, it is expected that the hysteresis bandwidth (HB) profiles HBa, HBb and HBc will be same, but have phase difference. The adaptive hysteresis band current controller changes the hysteresis bandwidth according to instantaneous compensation current variation (dic/dt) and Vdc voltage to minimize the influence of current distortion on modulated waveform.
The following equations can be written for the respective switching intervals t1 and t2 from Fig. 9. (22) (23) From the geometry of Fig. 9, it can be written as the follows: (24) (25)
221 SIMULATION RESULTS
Fig12 Three phase source voltage Fig.10. Adaptive Hysteresis Bandwidth Calculation Block Diagram
Equation (31) shows the hysteresis bandwidth (HB) is as a function of modulation frequency, supply voltage, dc capacitor voltage and slope of the ic * reference compensator current wave. The hysteresis band can be modulated as a function of Vdc and m, so that the modulation frequency fc remains nearly constant. This will improve the PWM performances and APF substantially. The adaptive hysteresis bandwidth calculation block diagram is shown in Fig. 10. The calculated hysteresis bandwidth (HB) is applied to the variable hysteresis band current controller shown in Fig. 11.
Fig 12 shows the three phase source voltage after implementing the static Var compensator and shunt active filter.
Fig 13 Three phase source current
Fig 13 shows the three phase source current after implementing the static var compensator and shunt active filter.
Fig.11.Variable Hysteresis Band Current Controller
Fig 14 Firing pulse for H-bridge inverter in shunt active filter
The produced pulses are sent to IGBT inverter. (V) SIMULATION RESULTS Numerical simulations have been conducted to validate the proposed topology.
Fig 14 shows the firing pulse for H-bridge inverter in shunt active filter .hysteresis current controller give pulse for inverter.
Fig 5.5 Harmonic Current Injected by Shunt Active Filter
Fig 5.5 shows the harmonic current injected by shunt active filter, the harmonic current having an opposite phase; it is connected parallel to load.
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implementation of shunt active filter is 29.62%. After implementing the shunt active filter in the circuit the THD level of current in the system is 1.56%. This shows that definitely there is some improvement harmonic suppression technique employed in the project. Compared to other control method, the control method proposed in this improves the performance of the combined system considerably.
Fig 16 Three phase load current Fig 5.6 shows the three phase load current. After implementing the shunt active filter the nonlinear load not collapse the supply voltage.
References
[1] An Luo, Zhikang Shuai, Wenji Zhu, and Z. John Shen,.: Combined System for Harmonic Suppression and Reactive Power Compensation, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 2, FEBRUARY 2009. pp. 418428 [2] JUAN DIXON, LUIS MORN, JOS RODRGUEZ and RICARDO DOMKE Reactive Power Compensation Technologies: State-of-the-Art Review PROCEEDINGS OF THE IEEE, VOL. 93, NO. 12, DECEMBER 2005. pp. 21442164 [3]Van der Broeck, Skudelny, H.C., and Stanke, G.V.: Analysis and realisation of a pulsewidth modulator based on voltage space vectors, IEEE Trans. Ind. Appl., 1988, 24, (1), pp. 142150. [4] Ruixiang Hao, Zhiguang Cheng, Xiaojie You, A Novel Harmonic Currents Detection Method Based on Rotating d-q Reference Frame for Active Power Filter351h Annul lEEE Power Elec~ronicSs pecialists Conference.,2004.PP .3034-3038
Fig 17 Current harmonic before implementing of shunt active filter
Fig 17 shows the current harmonic before implementing of shunt active filter. The THD value is 29.62%. The 5th, 7th, 11th, 13th order harmonics is present.
[5] Joy Mazumdar ,Ronald G Harley and Ganesh K. Venayagamoorthy, Synchronous Reference Frame Based Active
Filter Current Reference Generation Using Neural Networks IEEE Trans., 2006,PP.4404-4409 [6]D Masand,S Jain, G Agnihotri Distribution Static Compensator Performance under Linear and Nonlinear current Regulating methods J Electrical Systems 4-1 (2008) :91-105
BIOGRAPHY
Fig 5.8 Current harmonic after implementing of shunt active filter
Fig 18 shows the current harmonic after implementing of shunt active filter . The THD value is 1.56%.
CONCLUSION
A combined system consists of a classical SVC and APF for reactive power compensation and harmonics suppression is proposed. The topologies proposed in this thesis can suppression the THD. The current THD before the
Rajesh.T was born in Tamilnadu, India,on July, 1978. He received the B.E degree in Electrical and Electronics Engineering from Dr.Sivanthi Aditanar College of Engineering,Tiruchendur in the year 1999. He received his M.E Power Syatems Engineering from Thiagarajar College of Engineering, Madurai in the year 2001. He has 9 yrs of teaching experience. He worked as Asst. Professor in EEE department, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India for 8 years. Currently he isworking as a Assistant professor in the Department of Electrical and Electronics Engineering, INFO Institute of Engineering, Kovilpalayam, Coimbatore, TamilNadu, India. Currently he is doing research in the field of Reactive power compensation and Harmonic Mitigation.
223
HIGH-EFFICIENT MULTILEVEL HALF-BRIDGE CONVERTER

R.Anugraha*, Mrs. Vijayakumari.G**, *P.G Student, **Assistant Professor, EEE, Madha Engineering College, Chennai-69 Email id:anugrahareee@gmail.com
ABSTRACT A new high-efficient multilevel half-bridge converter is proposed. The proposed converter regulates the output voltage by adjusting applied voltage on the main transformer with an auxiliary circuit. Main switches are operated at both fixed duty ratio and switching frequency. ZVS operation is easily achieved and the transformer is effectively utilized with no dc offset of the magnetizing current. The ZVS operation of the auxiliary switches is easily realized by output inductor energy. The doubled switching frequency shown at the output filter reduces the output ripple current significantly. This paper presents theoretical analysis, simulation results & experimental results. Index TermsHalf-bridge converter, multilevel converter, zero voltage switching (ZVS). I. INTRODUCTION Recently, the efficiency problem in server power supplies has become an important issue because of its electricity consumption growth and cooling cost increase. Especially, the necessity of a highefficient server power system is emphasized in the medium power (600800 W) supplies since the server infrastructure has spread to small companies these days. For this purpose, several techniques have been proposed to reduce the switching losses and component stresses [1][9]. Among the proposed techniques, the conventional phase-shifted full-bridge (PSFB) converter [1][2], the active-clamp forward converter, and the asymmetric control halfbridge converter [9] are chosen as suitable topology for their zero voltage switching (ZVS) operation, resulting in lower current stress, and simple configuration. However, the usage of the PSFB converter is limited to medium power supplies since it adopts large number of main switches on the primary side. The PSFB converter increases the cost and decreases the power density of the converter. The active clamp forward converter has simple structure, but it is also suffered from high-voltage rating of the main switch. The voltage stress of the active clamp forward converter is the highest among three ZVS topologies, which increases the cost and degrades the performance of the converter. II. CONVENTIONAL ASYMMETRIC HALF-BRIDGE CONVERTER The asymmetric half-bridge converter shown in Fig.1 is the most attractive topology among three different techniques mentioned earlier. It has simple structure and wide ZVS range.
Fig. 1. Schematic diagram of the conventional asymmetric half-bridge converter Since, the voltage stress of the switches is clamped at its input voltage level. As a result, it has been chosen as the most suitable topology for the server system in middle power range. However, the asymmetric half-bridge converter also contains following drawbacks. The remained dc offset current at the magnetizing inductor decreases the transformer utilization, and the unbalanced voltage-/current stress degrades the performance of the rectifier stage. Furthermore, its nonlinear dc conversion characteristic requires higher duty variation for the same input variation compared to other linear converters. It makes the converter operated beyond the optimum operating point at highinput voltage specifications.
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III. PROPOSED TOPOLOGY A circuit diagram of the proposed dc/dc converter is shown in Fig. 2. Adopting an auxiliary switch ON the secondary side of the asymmetric half-bridge converter has been proposed as another solution. The auxiliary circuit is composed of an auxiliary transformer (T2) and two auxiliary switches (S1 and S2). The dc offset of magnetizing current problem could be solved effectively with this solution.
Mode 1 (t0t1): When commutation is completed at t0, mode 1 begins. In this mode, extra voltage is added to the nominal main transformer voltage for the regulation of the converter. Thus, the input capacitor voltage Vin/2 and reflected auxiliary transformer voltage, VS(2) are applied to the main transformer. The primary current increases linearly in this mode.
Fig. 2. Schematic diagram of the proposed converter The auxiliary circuit supplies additional voltage to the main transformer when input voltage decreases and regulates the output voltage. The magnetic size of the auxiliary transformer is much smaller than that of the main transformer, and the core loss in the auxiliary transformer is negligible at nominal operating condition. Thus, the main switches can be operated at 50% duty ratio and fixed switching frequency. Thus, their ZVS operation is easily achieved, and the transformer is effectively utilized with no dc offset of the magnetizing current. IV. DESCRIPTION - MODES OF OPERATION For the convenience of the mode analysis in steady state, assumptions are made as follows. 1) The switches M1, M2, S1 and S2 are ideal components except for their output capacitors and body diodes. 2) The capacitors C1 and C2 are large enough to be considered as constant voltage sources, (1/2)Vin 3) Turn ratio of the main transformer (T1) is n1 = NP 1 /NS 1 and n2 = NP 2 /NS 2 for the auxiliary transformer (T2). Each switching cycle can be divided into two half cycles t0t8 and t8t16.
Fig. 3. Mode 1 Mode 2 (t1t2): When S1 is turned off at t1, mode 2 begins. The output capacitors of the auxiliary switches CS 1 and CS 2 are charged and discharged, respectively, in a resonant manner. Since the large output inductor energy is participated in this resonance, the ZVS condition of S1 and S2 are easily realized.
Fig. 4. Mode 2
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Mode 3 (t2t3): After the auxiliary switch S2 is completely discharged, the current of the auxiliary circuit ipri(2) flows through the body diode of S2, as shown in Fig. 5. Thus, the voltage of S2 is sustained at 0 V, and the applied voltage to the main transformer remains at Vin /2.
from Vin at the same time by utilizing the large output inductance energy. This mode continues until the time when the primary voltage of the transformer reaches to 0 V.
Fig. 7. Mode 5 Mode 6 (t5t6): When the main transformer voltage Vpri(1) is decreased to 0 V, the voltage of main-switch M2 increases in manner of resonance between Llkg and CM1 + CM2. On the secondary side, both the rectifier diodes start to conduct and commutation of the two diodes D1 and D2 begin. This mode ends when voltage of the switch M1 discharges to 0 V.
Fig. 5. Mode 3 Mode 4 (t3t4): When the auxiliary switch S2 is turned on at time t3, mode 4 begins. Since the output capacitor of S2 is completely discharged in the previous mode, it is turned on under ZVS condition. The primary current decreases following the output inductor current in this mode.
Fig. 8. Mode 6 Fig. 6. Mode 4 Mode 5 (t4t5): The main switch M2 is turn off at the beginning of this mode. The voltage of the output capacitor CM2 is linearly charged from 0 V, and the voltage of CM1 is linearly discharged Mode 7 (t6t7): In mode 7, the primary current flows through the body diode of the main switch, M1. As the main transformer is regarded as short circuit, all voltages are applied to the leakage inductance and the primary current is sharply decreased.
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Fig. 9. Mode 7 Mode 8 (t7t8): When the main switch M1 is turned on at t7, this mode begins. The primary current, which was flowing though the body diode of M1 in the previous mode, changes the path to the channel of switch M1. Fig. 11. Simulation diagram proposed circuit
Fig. 12. Input voltage
Fig. 10. Mode 8 V. SIMULATION RESULTS The high-efficient multilevel half-bridge Fig. 13. Auxiliary Transformer Primary Side Voltage
converter is simulated using the mat lab simulink and the results are presented here. The circuit model of the half bridge converter is shown in Fig. 11. Scopes are connected to measure output current, voltage and speed of the motor.
Fig. 14. Main Transformer Primary Side Voltage
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REFERENCES [1] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, Design considerations for high-voltage high-power full-bridge zerovoltageswitched PWM converter, in Proc. Appl. Power Electron. Conf. Expo., 1990, pp. 275284. [2] X.Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian, Soft switched full bridge DC-DC converter with reduced circulating loss and filter requirement, IEEE Trans. Power Electron., vol. 22, no. 5, pp. 19491955, Sep. 2007. [3] J. Zhang, X. Xie, X.Wu, and Z. Qian, A novel zero-current-transition full bridge DC/DC converter, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 354360, Mar. 2006. [4] Y. Tao and S. J. Park, A novel ripplereduced DC-DC converter, J.Power Electron., vol. 9, no. 3, pp. 396402, Jan. 2009.[5] H. S. Choi, Design consideration of half-bridge LLC resonant converter, J. Power Electron., vol. 7, no. 1, pp. 1320, Jan. 2007. [6] N. Lakshminarasamma and V. Ramanarayanan, A family of auxiliary switch ZVS-PWM DC-DC converters with coupled inductor, IEEE Trans. Power Electron., vol. 22, no. 5, pp. 20082017, Sep. 2007. [7] X. Ruan, Z. Chen, and W. Chen, Zerovoltage-switching PWM hybrid full-bridge threelevel converter, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 395404, Mar. 2005. [8] R. L. Steigerwald, A comparison of halfbridge resonant converter topologies, IEEE Trans. Power Electron., vol. 3, no. 2, pp. 174 182, Apr. 1988. [9] J. C. P. Liu, N. K. Poon, B. M. H. Pong, and C. K. Tse, Low output ripple DC-DC converter based on an overlapping dual asymmetric halfbridge topology, IEEE Trans. Ind. Appl., vol. 22, no. 5, pp. 19561963, Sep. 2007. [10] R. Miftakhutdinov, A. Nemchinov, V. Meleshin, and S. Fraidlin, Modified asymmetrical ZVS half-bridge DC-DC converter, in Proc. Appl. Power Electro. Conf. Expo., 2005, pp. 567574. .
Fig. 15. Output Current
Fig. 16. Output Voltage
Fig. 17. Output Power VI CONCLUSION A new multilevel half-bridge converter was presented. By employing one small sub transformer and two small additional switches, the proposed converter shows better performance than the asymmetric half-bridge converter in entire load range. Also, it achieves good ZVS condition, and its symmetrical operation characteristic balances the voltage/current stresses on its components and eliminates the dc offset of magnetizing current, which degrade the utilization of the transformer. Therefore, the proposed converter can be used in middle power server system.
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Implementation of a High-Efficiency Full-Bridge Single-Stage Converter With Reduced Auxiliary Components

R. Sathiya priya*, S. Lakshmi**, *P.G Student, **Assistant Professor, EEE, Madha Engineering College, Chennai.-69 Email id: sathiyaramajayam@yahoo.co.in
ABSTRACT:
This project presents a single-stage circuit topology consisting of the association of a full-bridge isolated dcdc converter with two input inductors and two input diodes are connected to the mains network, in order to obtain an isolated ac/dc switch mode power supply, with sinusoidal input current. The proposed topology does not use an input bridge rectifier, common in similar applications. Boost rectification is used to obtain the PFC function and regulation of output voltage with galvanic isolation is a new technique that makes this topology unique, which also contributes to improve the converter efficiency. This project introduced, a full-bridge single-stage SMPS which reduces number of components with symmetrical current distribution through all the bridge transistors. These boost converters distribute the input power uniformly by the four-inverter transistors, thereby improving the efficiency and reducing current stress. Simulation results are obtained for 24w PMDC motor load. Recently, new PFC bridgeless promising solutions, mainly intent to replace the input rectifier and the boost converter, have emerged. These techniques were permitted to obtain good input current wave shaping with lower harmonic distortion and efficiency higher, >95%. However, to perform also high-frequency isolation and output dc voltage regulation, these topologies still need the presence of another converter (an isolated dcdc converter). Thus, the overall system will result in a high-cost two-stages converter, gaining only an increase in the efficiency, Consequently, these topologies are not suited for the application focused on this project, which is based in one-stage converter. Considering the constant interest of the industry in reducing the cost and the increase of efficiency of the SMPS, while maintaining the PFC function, several topologies of isolated ac/dc single-stage SMPS have been proposed, based on the forward and fly back dcdc converters for low-power applications. However, in the case of high-power applications, the voltage and current ratings of the power transistor and diodes increase considerably, thereby raising the cost of these solutions to values that can be even higher than those observed in the two-stage topologies. In view of the power limitation of these topologies, single-stage isolated full-bridge topologies with PFC function have been proposed recently. These topologies can perform input current wave shaping and output voltage control simultaneously, without using any additional transistors. However, these topologies are not optimized in terms of additional components and current distribution in the bridge transistors. Only two parallel input boost converters are provided using the low-side transistors, which leads to asymmetrical current distribution in the bridge transistors causing, a high current stress. An input bridge rectifier is also needed for these topologies. For the topologies, only one input inductor is used, but this inductor and the two lowside transistors have to support the maximum input current.
I. INTRODUCTION In modern switch mode power supplies (SMPSs) with galvanic isolation, the capacity to perform power factor correction (PFC) is a frequent characteristic, in compliance with the standard IEC-1000-3-2.This requirement is normally achieved with an additional input converter, typically a bridge rectifier, followed by a boost converter .For high power levels, the association of this input converter with the full-bridge isolated dcdc converter results in a two stages converter with the inherent characteristics: high cost and the necessity of having very high efficiency in each stage. It should be noted that, to obtain a global efficiency greater than 95% is necessary that each stage presents efficiency greater than 97.5%, which may be difficult and also expensive to obtain, when the second stage is a full-bridge converter.
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Block Diagram:
influence in the evolution of the input current in order to define simple design criteria namely, the maximum value of the output duty ratio DO max, Considering its impact on the input current distortion and the control angle that defines the beginning of the CCM operation in the input current. When the input mains voltage is low, the input boosts cannot generate sufficient current slope (diI /dt), even withDI =DI max, so that the input current does not follow the reference iR due to the input duty ratio limitation. III. MINIMUM INPUT POWER
Fig: 1 Block diagram
Proposed circuit diagram:
Fig: 2 High-efficiency full-bridge single-stage topology
II. ANALYSIS OF THE INPUT CURRENT EVOLUTION Analysis of input current takes into accounts not only low frequency associated to the input voltage, but it also has to consider the high switching frequency of the bridge transistors.
During the CCM operation of the output filter, the output duty ratio DO is constant, meaning that the input boosts have a minimum input duty ratio, i.e., DImin = DO /2. Considering the value of DImin and the value of the input inductances L, the converter imposes a minimum input power PI min. This minimum input power must be suppressed to avoid the increase of VCF voltage to uncontrollable values. This problem was solved by a halfcontrolled input rectifier, with a random control, which disconnects the converter from the mains if the capacitor voltage VCF stays out of control.With this circuit, it is possible to operate the output filter in CCM for very low loads and operate with no load. However, simpler and cheaper, a bridge diode can be used, if the output inductance LO is designed considering the correct boundary between the CCM and the discontinuous conduction mode (DCM), which guarantees the DO reduction with low loads.Note that the DO reduction implies the reduction of the minimum input power. This technique is also used in the proposed topology. This fact constrains the output inductance LO, which must guarantee the correct boundary between the CCM and the DCM to operate with low loads.
Fig: 4 Typical average evolution of the input current for Fig: 3 Input current distortion due to a high value of the input inductances minimum input power situation
Consequently, this section is dedicated to the explanation of the different low-frequency modes of operation of the input boost converters and their
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IV. MODES OF OPERATION OF THE PROPOSED CIRCUIT Modes of operation of proposed circuit performs rectification, boost conversion and inversion in a single stage using a full bridge inverter and two inductors. Rectification is done by two diodes instead of using a input bridge rectifier. Mode 1: Mode 1 is the power mode.During the positive half cycle, the input supply is boost rectified using diode DB1, capacitor CF, diode D3 and inductor L1. When MOSFET T3 and T2 are turned on,inveter operation begins. When these two MOSFETs are fired simultaneously, current flows through T3, transformer primary and T2.In the secondary side of the transformer, current flows through Do1, load Mode 3: Mode 3 is the power mode.During the negative half cycle, the input supply is boost rectified using diode DB2,inductor L1,diode D1 and capacitor CF..Mode 3 begins, When MOSFET T4 and T1 are turned on,inveter operation begins. When these two MOSFETs are fired simultaneously, current flows through T4, transformer primary and T1.In the secondary side of the transformer, current flows through Do2, load
Mode 2: Mode 2 is the recycling mode.During the positive half cycle, the input supply is boost rectified using diode DB1, capacitor CF, diode D3 and inductor L1..Mode 2 begins When MOSFET T3 and T2 are turned off,diodes D2 and D3 conducts ,energy is transferred back to source.In the secondary side of the transformer, current flows through Do1,load
Mode 4: Mode 4 is the power mode.During the negative half cycle, the input supply is boost rectified using diode DB2,inductor L1,diode D1 and capacitor CF...Mode 4 begins, When MOSFET T4 and T1 are turned off,diodes D1 and D4 conducts ,energy is transferred back to source.In the secondary side of the transformer, current flows through Do2,load
231
V. SIMULATION RESULTS
The full bridge single stage converter is simulated using the mat lab simulink and the results are presented here. The circuit model of the full bridge single stage converter is shown in Fig.5.1. Scopes are connected to measure output voltage, driving pulses, output current and speed of the motor.simulation results were carried out for 24W dc motor load.
Fig: 5.3 Inverter output Voltage
Fig: 5.4 Output Power
Fig: 5 Simulation diagram of proposed circuit
Fig: 5.5 Output Voltage
Fig: 5.6 Armature Current Fig: 5.1Input Voltage and Current VI. EXPERIMENTAL RESULTS The experimental results of the proposed topology and validate the design criteria presented in this project, a prototype has been developed with the following specifications: PO = 24W; VO = 12 V; TS = 10 s; DO <0.45 was obtained and DO = 0.4 was assumed. The input inductances L = L1 = L2 are designed, Lmax1=Lmax2 = 250 mH, LO =84H .For the capacitorCO, a 100-F/63V ultra low impedance (40 m at 100 kHz) electrolytic capacitor is used. For the power inverter, the following components are used: IN4007 for the auxiliary diodes, DB1 and DB2;IRF840(500-V,8A)Metal Oxide Semi Conductor Field Effect
Fig: 5.2 Triggering pulses
232
Transistors (MOSFETs)and IN4007 for the auxiliary diodes for the output rectifier diodes.
VII.COMPARISION TABLE: REFERENCES [1] B. Singh, B. N. Singh, A. Chandra, K. AlHaddad, A. Pandey, and D. P. Kothari, A review of single-phase improved power quality ACDC converters, IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962981, Oct. 2003. [2] E. H. Ismail, A. J. Sabzali, and M. A. Al-Saffar, Buck-boost-type unity power factor rectifier with extended voltage conversion ratio, IEEE Trans. Power Electron., vol. 55, no. 3, pp. 11231132, Mar. 2008. [3] M. M. Jovanovic and Y. Jang, State-of-theart, single-phase, active power-factor-correction techniques for high-power applicationsAn overview, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 701708, Jun. 2005. [4] L. Huber, Y. Jang, and M. M. Jovanovic, Performance evaluation of bridgeless PFC boost rectifiers, IEEE Trans. Power Electron., vol. 23, no. 3, pp. 13811390, May 2008. [5] Y. Jang and M. M. Jovanovic, A bridgeless PFC boost rectifier with optimized magnetic utilization, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 8593, Jan. 2009. [6] W. Wei, L. Hongpeng, J. Shigong, and X. Dianguo, A novel bridgeless buck-boost PFC converter, in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 13041308. [7] W.-Y. Choi, J.-M. Kwon, and B.-H. Kwon, Bridgeless dual-boost rectifier with reduced diode reverse-recovery problems for power-factor correction, IET Power Electron., vol. 1, no. 2, pp. 194202, Jun. 2008. [8] R.Redl, L. Balogh, andN.O. Sokal, A newfamily of single-stage isolated power-factor correctors with fast regulation of the output voltage, in Proc. IEEE Power Electron. Spec. Conf. (PESC), 1994, pp. 11371144.
COMPARISON
CONVENTIONAL CIRCUIT PROPOSEDCIRCUIT
EFFICIENCY
60%
90%
CONDUCTIONLOSS
4.05W
2.7W
NUMBER OFDIODES
NUMBEROFMOSFETS
VIII. CONCLUSION This project presents a detailed analysis and design of an optimized, single-stage, single-phase full bridge topology. Appropriate control allows for the operation of the isolated full-bridge converter in order to attain four parallel input boost converters to accomplish the PFC function. These boost converters distribute the input power uniformly by the four-inverter transistors, thereby improving the efficiency. Furthermore, the topology only uses two input rectifier diodes, which also reduce the converter cost and improves the efficiency, due to the reduced number of diodes in series for each boost state.
233
HIGH EFFICIENT SINGLE PHASE PFC CONVERTER

K.PREETHA, Lecturer Sriangalamman College of Engg Siruganur, Trichy. sivapreethu@gmail.com Mob: 9894840949 ABSTRACT: This paper 1. INTRODUCTION Conventional offline power converters with diode capacitor rectifiers have resulted in distorted input current waveforms with high harmonic contents. To solve these problems, several techniques have been proposed to shape the input current waveform of the power converter. A common approach to improve the power factor is a two stage power conversion approach. The two stage scheme results in high power factor and fast response output voltage by using two independent controllers and optimized power stages. The main drawbacks of the scheme are its relatively higher cost and larger size resulted from its complicated power stage topology and control circuits, particularly in low power applications. In order to reduce the cost, the single stage approach, which integrates the PFC stage with a dc/dc converter into one stage, is developed. These integrated Single stage PFC converters usually use a boost converter to achieve PFC in discontinuous current mode
proposes a novel single stage converter based on a quasi-active PFC scheme. In this circuit, the power factor is improved by using an auxiliary winding coupled to the transformer of a cascade dc/dc fly back converter. The auxiliary winding is placed between the input rectifier and the low frequency filter capacitor to serve as a magnetic switch to drive an input inductor. Since the dc/dc converter is operated at high switching frequency, the auxiliary windings produce a high frequency pulsating source such that the input current conduction angle is significantly lengthened and the input current harmonics is reduced. It eliminates the use of active switch and control circuit for PFC, which results in lower cost and higher frequency. In order to achieve low harmonic content, the input inductor is designed to operate in discontinuous current mode. Keywords: Fly back converter, PFC cell, PSIM software.
234 sensitive to the variation of components values. 2. BLOCK DIAGRAM DESCRIPTION 2.1.1 POWER SUPPLY: For this circuit, V in rms (100 240V) universal line voltage is given. 2.1.2 EMI FILTER: The EMI is transmitted in two forms: radiated and conducted. The switching converters supplied by the power lines generate conducted noise into the power lines that is usually several orders of magnitude higher than the radiated noise into free space. Metal cabinets used for housing power radiated 2.1.3 RECTIFIER: Here bridge rectifier is used for the conversion of AC to DC converters reduce of the the component
(DCM) operation. Usually the DCM operation gives a lower total harmonic distortion (THD) of the input current compared to the continuous current mode (CCM) operation. To overcome the disadvantages of the single-stage scheme, many converters with input current shaping have been presented, in which a high frequency ac voltage source (dither signal) is connected in series with the rectied input voltage in order to shape the input current. Another technique based on parallel connection of this dither signal, however, the harmonic content can meet the regulatory standard by a small margin. A new concept of quasi-active PFC is proposed to improve the efficiency of a single-stage converter by preventing the input current or voltage stress due the PFC cell from being added to the active switch. In this circuit, the dc/dc cell operates in DCM so that a series of discontinuous pulses is used to shape the input inductor current and the PFC is achieved. As the circuit uses resonance of circuit parameters to achieve PFC, the control of the power factor will be very
electromagnetic interference.
2.1.4 FLYBACK CONVERTER: Fly-back converter is the
most
commonly used SMPS circuit for low output power applications where the output voltage needs to be isolated from the input main supply. The output power of fly-back type
235 the leakage inductance of the winding. The flux associated with the primary winding leakage inductance will not link the secondary winding and hence the energy associated with the leakage flux needs to be dissipated in an external circuit (known as snubber). Unless this energy finds a path, there will be a large voltage spike across the windings which may destroy the circuit.
SMPS circuits may vary from few watts to less than 100 watts. The overall circuit topology circuits. The fly-back converter discussed in the above neglects some of the practical aspects of the circuit. The simplified basic idea and idealized the circuit converter. considered above essentially conveys the behind However a practical converter will have device voltage drops and losses, the transformer shown will also have some losses. The coupling between the of this converter is considerably simpler than other SMPS
Fig. 2.2 Practical fly back converter
primary and secondary windings will not be ideal. The loss part of the circuit is to be kept in mind while designing for rated power. The designed input power (Pin) should be equal to Po/, where Po is the required output power and is the efficiency of the circuit. A typical figure for may be taken close to 0.6 for first design iteration. Similarly one needs to counter the effects of the non- ideal coupling between the windings. Due to the non-ideal coupling between the primary and secondary windings when the primary side switch is turned-off some energy is trapped in
3. CIRCUIT DIAGRAM
Fig. 3.1 Circuit diagram of Reduction of Harmonics in

Single Phase Converter with PFC
3.1 CIRCUIT DESCRIPTION: The circuit comprised of a bridge rectifier, a boost inductor LB, a bulk capacitor Ca, in series with the auxiliary winding L3, an intermediate dc bus voltage capacitor CB, and
236 voltage, therefore, the inductor current iL Bis linearly increased from zero since it is assumed that the PFC cell operates in DCM. This current can be expressed as where, Vin= Vm | sin | -------(2)
a discontinuous input current power load, such as fly back converter. 3.2 PRINCIPLE OF OPERATION It is assumed that both the input inductor LB and the magnetizing inductance of the y back converter operate in DCM. Therefore, currents iL
B, im,
is
the
rectied input voltage, (to t1) = dTS is the ON-time of the switch (SW). Stage 2 (t1 t2): When the switch is turned OFF at t = t1, output diode Dobegins to be forward biased. Therefore, the energy stored in the transformer magnetizing inductor is delivered to the load through the secondary winding. Similarly, the diode D1is also forward biased and the voltage across LB now Vin VC B. Therefore, the current IL Bis linearly decreased to zero at t = t2(DCM operation), and the energy stored
and i2are zero at the beginning of
each switching period. It is also assumed that the average capacitor voltage VC ais greater than the average rectied input voltage |vin|. To ensure proper operation of the converter, the transformers turns ratio should be (N1/N3) 2 and the boost inductor LB< Lm. In steady-state operation, the topology can be divided into four operating stages. Stage 1 (to t1): When Do are voltage the switch
in LB is delivered to the dc bus capacitor CB. Therefore
(SW) is turned on at t = to, diodes D1and OFF, therefore, the dc-bus VC

B
is
applied
to
the
magnetizing inductor Lm, which causes the magnetizing current to linearly increases. This current can be expressed as
-------------------- (1)
The capacitor (Ca) is also discharging its energy to the dc bus capacitor CB and the
And since diode D1is OFF, the input inductor LBis charged by input
237 direction. Output voltage Output current
current given by
i3reverse
its
Therefore, the capacitor current is iD1 = iC B = iL B+ i3. At t = t3, the magnetizing inductor releases all its energy to the load and the currents im and assumed. i2 reach to zero level because a DCM operation is
Fig. 3.2(a) waveforms of the proposed PFC. (b) Equivalent circuit operation stages of the proposed PFC circuit during one switching period. COMPARISON BETWEEN THE CONVENTIONAL BOOST AND FLYBACK AND THIS PROPOSED CIRCUIT
Description Boost+ fly back (DCM+DCM) Semiconductors Passive components 3 diodes, 1 switch, 1 bridge rectifier 1 inductor, 2 2capacitors, winding transformers Switch current Efficiency ILB+ILM 70% Proposed converter (DCM+DCM) 2 diodes, 1 switch, 1 bridge rectifier 1 inductor, 3 3capacitors, winding transformers (N3/N1 ) ILB+ILM >90%
4. SIMULATION CIRCUIT 4.1. Simulation Circuit
4.2 Simulation waveforms Input current
238
Controlled by the ratio N3/N1 LM/LB and ratio winding
Capacitor voltage
Controlled by the ratio LM/LB
active input current shaper, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 132138, Feb. 2005..
THD
of
the
>20%
<10%
input current
2. S. Luo,W. Qiu,W.Wu, and I.

Batarseh, Flyboost power factor correction cell and a new family of single-stage AC/DC converters, IEEE Trans. Power Electron., vol. 20, no. 1, pp. 2433, Jan. 2005.
5. Conclusion The proposed method produces a current with low harmonic content to meet the standard specications as well as high efficiency. This circuit is based on adding an auxiliary winding to the transformer of a cascade dc/dc DCM y back converter. The input inductor can operates in DCM to achieve lower THD and high power factor. By properly designing the converter components, a tradeoff between efficiency and harmonic content can be established to obtain compliance with the regulation and efficiency as high as possible. REFERENCES
3. H. L. Do, Single-stage singleswitch power factor correction AC/DC converter, Inst. Electr. Eng. Proc. Electr. Power Appl., vol. 152, no. 6, pp. 15781584, Nov. 2005.
4. L. K. Chang and H. F. Liu, A

novel forward AC/DC converter with input current shaping and fast output voltage regulation via reset winding, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 125 131, Feb. 2005
5. K. Zhou, J. G. Zhang, S.
Yuvarajan, and D. F. Weng, Quasi active power factor correction circuit for switching power supply, IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1410 1414, May 2008.
1. N. Vazquez, J. Lopez, J.
Arau, C. Hernandez, and Elias Rodriguez, A different approach to implement an
239
Implementation of Matrix Converter for Controlling Input Voltage Variations

B Balabharathi B.E.,[M.E], PG Scolar, K.S.R.College of Engineering,Trichengode. email:balabhar@gmail.com
AbstractMatrix converter is a single-stage converter which directly connects a single phase voltage source to single phase load without dc-link components. Therefore, any harmonic distortion and imbalance in input voltage directly reflect to the output of the converter. Recently, many researchers have made an effort to cope with this problem. In this paper, under distorted input voltage conditions , behaviors of the MC controlled with Venturini method are analyzed and a PI controller based compensation method to prevent negative effects of input voltage is proposed. Since the proposed method is based on closed loop control of the output currents, it not only reduces the output harmonic contents but also ensures a stable control of the load currents. Some results are presented to prove the effectiveness of the proposed compensation technique. Index TermsMatrix converter, ac-ac converter, Venturini method, distorted input voltage, compensation.
S Chinnaiya M.E.,[Ph.D], Asst.Professor, K.S.R.College of Engineering,Trichengode.
II.SPMC
Fig.1.SPMC Circuit Configuration
I.INTRODUCTION Many theoretical studies have been investigated on Matrix Converter but have found very few practical applications in power electronics. One of the most interesting members of the power converter family is the matrix converter providing directly ac-ac power conversion. The matrix converter has received an increased amount of interest and has been studied intensely as an alternative to conventional indirect power converter systems in recent years, because it has outstanding advantages in following [2]-[3]. Sinusoidal input and output currents No bulky dc-link reactive elements Possible with unity displacement factor for any load Four-quadrant operation Simple and compact design Regeneration capability. These attractive properties have motivated researchers to study about the matrix converter [1]. In this work, the Xilinx Field Programmable Gate Array (FPGA) was used to produce the Sinusoidal Pulse Width Modulation (SPWM) switching algorithm with IGBTs as the SPMC power switching device. Prior to hardware imlementation, simulations were performed to predict the behaviour. A laboratory model test-rig of the SPMC was then constructed to perform investigations.
Fig.2.Bidirectional Switch Module. The SPMC requires 4 bi-directional switches as shown in Fig.1.each capable of conducting current in both directions, blocking forward and reverse voltages.The individual power switches using IGBTs are as in Fig. 2. The IGBT were used due to its popularity amongst researchers that could lead to high-power applications with reasonably fast switching frequency for fine control. The input and output voltage of the SPMC is given by (1) and (2) respectively with loads represented in (3). The input and output voltage of the SPMC is given by Vi (t) = 2 Vi sin it (1) (2) Vo (t) = 2 Vo sin ot Loads represents, (3) Vo (t) = Rio(t)+ L io(t)/dt Subscript i denote input, while o denotes output.
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III.SWITCHING STRATEGIES Driver circuits are designed to generate the SPWM patterns that are used to control the power switches, comprising IGBTs in the SPMC circuit. The switching angles, of the 4 bi-directional switches sij (i = 1,2,3,4 and j = a,b) where 'a' and 'b' are representing driver one and two respectively. The following rules are then applied * At any time 't', only two switches sij (i = 1, 4 and j = a) will be in 'ON' state and conduct the current flow during positive cycle of input source (state 1). * At any time 't' only two switches sij (i = 1, 4 and j = b) will be in 'ON' state and conduct the current flow during negative cycle of input source (state 2). * At any time 't' only two switches Su (i = 2, 3 and j = b) will be in 'ON' state and conduct the current flow during positive cycle of input source (state 3). * At any time 't' only two switches sij (i = 2, 3 andj = a) will be in 'ON' state and conduct the current flow during negative cycle of input source (state 4). Figs. 3 to 6 illustrates the application of those rules listed. Fig.5. State 3 (Positive Cycle)
Fig.6. State 4 (Negative Cycle) The output frequency is synthesized in multiples of input frequency of 50Hz (say 50Hz, 25Hz and 100Hz) and the operations are illustrated as in Fig.7. The sequences of switching are dependent on the time interval and state of the driver circuit, represented by table 1 (For the one cycle). Let's say the output frequency is 50 Hz. To Fig.3. State 1 (Positive Cycle) achieve this, when the supply voltage is positive the switch is in state 1 (Sla and S4a are turned ON). On the other hand switching state 2 are used during negative cycle to produce the next half cycle. For other output frequencies, the sequence of switching is similar to the 50 Hz output frequency as listed in table I1 with a total of four (4) different switching states, Fig.4. State 2 (Negative Cycle) capable of being used in various combinations to produce the desired effect.
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The working performance of the load has deteriorated, when it is exposed to the harmonic and non-sinusoidal currents. If unfavorable effects of the
TABLE 1: SEQUENCE OF SWITCHING CONTROL
I/P Freq
Output Freq 50 Hz
Time Interval 1 2 1 2 3 4 1 2 3 4
State 1 2 1 3 4 2 1 3 4 2
Switch ON S1a & S4a S1b & S4b S1a & S4a S2b & S3b S2a & S3a S1b & S4b S1a & S4a S3a & S2a S2b & S3b S4b & S1b
distorted input voltages are eliminated in the MC, the popularity of the MC will more increase. Some papers have been presented to reduce the influences of the distorted input voltages [2]-[6]. In this paper, a PI based compensation technique is proposed to get rid of the undesirable effects of the distorted input voltages for matrix converter controlled with Venturini modulation method. Since this technique improving the output performance of the MC performs closed loop control of the output current, single-phase output currents of the MC must be measured by using current sensors. The proposed method not only reduces the output harmonic contents but also ensures overcurrent protection and control for the load current. Some numerical and simulation results are presented to prove the effectiveness of the proposed compensation technique. VI.THE PROPOSED COMPENSATION SCHEME FOR DISTORTED INPUT VOLTAGE CONDITIONS In PI feedback compensation scheme, which is shown schematically in Fig. 3, the measured output currents are used to calculate the magnitude of the output current space vector (I ). If the input voltages of the MC are do sinusoidal and balanced, the output currents will be sinusoidal, too. Under this condition, I do is constant. However, if the input voltages of the MC are non-sinusoidal and unbalanced, I do will be not constant due to the output harmonic currents.
50 Hz
100 Hz
25 Hz
V. HARDWARE DESCRIPTION
Fig. 7. Block diagram of the SPMC test model. A test model of the SPMC consists of a phase detector circuit, control unit, driver circuit and a SPMC circuit is as shown in Fig. 7. The phase detector circuit is used to ensure that the output from control unit is synchronous with the frequency of the single phase input voltage. The driver circuit also act as an isolation device for the control unit to prevent voltage surges from damaging the control unit. However, the load side of the MC is directly affected by the distorted and/or unbalanced input voltages due to the lack of dc intermediate circuit in the MC. The distorted and/or non-sinusoidal input voltages may cause the undesirable harmonic currents. Fig. 8. PI feedback compensation scheme for matrix converter If Ido is kept constant, the output of the converter is not affected by disturbances in the input voltages. The proposed compensation technique is based on this principle and a PI controller is employed for this purpose.
242
the following parameters Input voltage Vi= 50V (rms) RLoad=50 IBGT type: BUP314D Sample Modulation index= 0.7 & 1.0
Accordingly, the PI controller system is fed by the instantaneous error of Ido (e(k)) in (4) and produces a variable voltage-gain (q) according to the disturbance of the input voltage. Duty cycles of the power switches are calculated, substituting the variable-voltage-gain-value produced by the PI controller.
e(k)=[
)-
(k)]
(4)
The output of the PI controller system is the voltagegain (q) and a saturation block has been added to the output of system, due to the magnitude of q can not exceed 0.866 and can not be negative.
Fig. 9 show the developed model for SPMC by using Matlab/Simulink at performs the operation of a direct AC-AC converter. Fig.10 shows the subsystem of SPMC Network.
VII. SIMULATION To show the validity of results, a simulation model was initially developed in MATLAB/Simulink to study circuit behaviour. This is then followed by an experimental test-rig constructed in the laboratory to verify that such converter is feasible and will subsequently be described. Simulations were done by means of the Power System Block (PSB) with in the MATLAB/SIMULINK (MLS) software package prior to implementation, while the laboratory model of the proposed SPMC was developed with
Fig.10. Subsystem of SPMC Network VIII. SEQUENCE OF SWITCHING CONTROL
In the case of 100 Hz (output frequency), for the

positive half cycles of the input the output is a both positive and negative cycle. The total time period of the output is 10 ms.The switches S1a and S4a are conducting in the positive half cycle of the input (0 to 0.005 sec) to get positive output and switches S2b and S3b are conducting in the same positive half cycle (0.005 to 0.01 sec) to get negative output. In the negative half cycle of the input, switches S3a and S2a Fig.9.Main model for SPMC Network are conducting (0.01 to 0.015 sec) to get positive output and switches S1b and S4b are conducting (0.015 to 0.02 sec) to get negative output. The operation is similar for 25 Hz of output frequency.
243
The waveforms of the output voltages for 25 and 50 Hz are shown in Fig. 13 and Fig. 14, respectively. In Fig 13(a) and 14(a), the output voltages of the uncompensated systems are given under the distorted input voltage conditions. As for the output voltages of the compensated systems are illustrated in Fig. 13(b) and 14(b). The black pulsing diagram is the output line voltage and the green line is average of the output line voltage in figures. As it is understood from the average value of the output line voltage, voltage. the proposed compensation technique has satisfactorily eliminated the harmonics of the output
IX. SIMULATION RESULTS The SPMC loaded by an R load and operated at fc=50 Hz, 100 Hz and 25 Hz was then simulated and verified experimentally. The following are samples of results.
Fig.11.Simulation result for 100 Hz output frequency (a) Output voltages without compensation .
(b) Output voltages with compensation Fig 13. Output line voltages for the MC the under distorted input voltage conditions (fo = 25 Hz)
Fig.12.Simulation result for 25 Hz output frequency In Matlab/Simulink we are using ideal switches only. Because of the usage of constant input we get the accurate output.But in practical applications, if the input voltages of the MC are distorted or unbalanced, the low order harmonics occur on the output current and voltage of the MC. But, under the same conditions, the proposed PI controller based compensation method has effectively decreased these harmonics.
(a) Output voltages without compensation
244
[4] R.Baharom, N. Hashim & M.K. Hamzah,
Implementation of Controlled Rectifier with Power Factor Correction using Single Phase Matrix Converter, IEEE PEDS 2009. [5] Zahirrudin Idris and Mustafar Kamal Hamzah , Implementation of a new Single-phase Cycloconverter based on Single-phase Matrix Converter Topology using Sinusoidal Pulse Width Modulation with Passive Load Conditions, IEEE Conference 2006. (b) Output voltages with compensation Fig 14. Output line voltages for the MC the under distorted input voltage conditions (fo = 50 Hz) [6] H.M.Hanafi, N.R. Hamzah, A.Saparon , and M.K.Hamzah, Senior Member, IEEE Improved
Switching Strategy of Single-Phase Matrix Converter as a Direct AC-AC Converter ,IEEE Conference ,2008. [7] Mohammad Shukri Hapeez, Ngah Ramzi Hamzah, and Mustafar Kamal Hamzah , Comparison of the Experimental Results of a Newly Developed Interfacing Method on a Single-Phase Matrix Converter Employing Safe Commutation Strategy , Proceedings of 2009 Student Conference on Research and Development (SCOReD 2009),16-18 Nov. 2009. [8] H. Mohd Hanafi, Z. Idris, M. K. Hamzah, Member, IEEE and Azilah Saparon , Modelling & Simulation of Single-phase Matrix Converter as a Frequency Changer with Sinusoidal Pulse Width Modulation Using MATLAB/Simulink , First International Power and Energy Conference PECon 2006 482 November 28-29, 2006.
X. CONCLUSIONS A PI controller based compensation technique is proposed to improve the output performance of the MC. The proposed method has satisfactorily reduced harmonics in the output currents and voltages under the distorted input voltage conditions. In addition to, this method allows the over-current protection and the control of the load current. Under undesirable effects of the input supply voltage, the proposed compensation technique is an effective method to reduce harmonics of the output current and voltage. Validity of this method is verified by the presented simulation results. REFERENCES [1] Zahirrudin Idris, Mustafar Kamal Hamzah and Ahmad Maliki Omar, Implementation of Single Phase Matrix Converter as a Direct AC-AC Converter Synthesized Using Sinusoidal Pulse Width Modulation with Passive Load Condition , IEEE Transactions on Power Electronics and Drives,2005. [2] Hulusi Karaca and Ramazan Akkaya,An Approach for Controlling of Matrix Converter in Input Voltage Variations, Engineering Letter.17:2,EL_17_2_11, Advance online publication:22 May 2009. [3] Zahirrudin Idris and Ngah Ramzi Hamzah, Modelling Single-phase to Single phase & Simulation of a new
cycloconverter based on Single-phase Matrix Converter Topology with Sinusoidal Pulse Width Modulation Using MATLAB/Simulink, IEEE PEDS 2005.
246
Implementation of Resonant Inverter with Inbuilt Boost Converter

M. Gayathri1,J.Baskaran2,P.Tamizharasi 3 1. PG Scholar, 2.Assistant Professor, 3. Professor Department of EEE Adhiparasakthi Engineering College,Melmaruvathur, Tamilnadu,India,
Abstract - This paper proposes a novel soft-switching Single phase acdcac converter to give high input power factor and low current distortion on the rectifier side and provide clean and stable ac voltage on the inverter side. Besides operating at constant frequency, all semiconductor devices operate at soft-switching without additional voltage stress. A significant reduction in the conduction losses is achieved, since the circulating current for the soft switching flows only through the auxiliary circuit and a minimum number of switching devices is involved in the circulating current path, and the rectifier in the Proposed converter uses a single converter instead of the conventional configuration composed of a four-diode front-end rectifier followed by a boost converter. An average-current-mode control is employed in the rectifier side of proposed converter to detect the transition time and synthesize a suitable low harmonics sinusoidal waveform for the input current. The sinusoidal pulse width modulation (SPWM) control strategy is employed in the inverter of proposed converter to achieve good dynamic regulation. Index Terms-Electronic correction(PFC) ballast,power factor
inverter, so that the two converters can be driven independently according to usual PWM techniques, providing excellent in fact, this system is the combination of the boost rectifier and the buck inverter. The boost rectifier performs the functions of power factor correction and boost acdc conversion. For minimization of size and weight of overall system, increasing switching frequency in them is required. However, increasing switching frequency will result in more switching losses. In order to overcome this problem, they must use individual soft-switching techniques. This solution will result in high complexity of overall circuit, high weight, high cost and low efficiency. In order to overcome previous problems, a number of zero voltage switching (ZVS) techniques which the auxiliary commutation cells are shared between the rectifier and inverter have been proposed.
II. ANALYSIS AND DESIGN OF THE PROJECT The conventional single phase ac-dc-ac converter with zero voltage switching by Chein-Ming-Wang is mostly used in high power applications. This constant frequency ac-dc-ac converter employs high frequency application but with low efficiency of about 80% and low reliability by the use of matrix converters. These have received considerable attention due to their potentiality to provide direct ac-ac conversion without energy storage. However they must use some four quadrant switches and use some snubber circuits to absorb over voltages coming from the inductive commutation. As a result circuit efficiency and reliability are affected. II. PROPOSED AC-DC-AC CONVERTER PWM rectifier-inverter systems with dc link using indirect ac-dc-ac conversion method. In this method a big tank capacitor in the dc link provides decoupling between the rectifier and the inverter, so that the two converters can be driven independently according to usual PWM techniques, providing excellent input and output
I. INTRODUCTION Matrix converters have received considerable attention due to their potentiality to provide direct acac Conversion without energy storage. However, they must use some fourquadrant switches, sense the switch voltage and current of there switches, and use some snubber circuits to absorb over voltages coming from the inductive commutation. As a result, circuit efficiency and reliability are affected. The conventional single-phase acdcac converter is shown in Fig. In this system, a big tank capacitor in the dc link provides decoupling between the rectifier and the
Corresponding Author: M.Gayathri is with Electrical and Electronics Department of Adhiparasakthi Engineering College, Melmaruvathur, email: sivaragupathi@yahoo.co.in.
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performances with high efficiency of about 90.5% and good reliability.
5) In the beginning of the switching, the resonant voltage is equal to and the resonant current is equal to zero Based on these assumptions, circuit operations in one switching cycle can be divided into twelve stages. The twelve dynamic equivalent circuits of the new softswitching single-phase acdcac converter are shown in below. IV. STAGES OF OPERATION OF THE SOFT SWITCHING SINGLE-PHASE ACDCAC CONVERTER
FIg .1. Proposed AC-DC-AC converter III. MODES OF OPERATION The circuit can be divided in three sections. The first section is the input rectifier which is operated at pulsewidth modulation continuous conduction mode and composed of Lin, S1, S2, D1, D2 and C1. This section performs the functions of power factor correction and boost acdc conversion at fixed frequency. It also provides the zero-voltage-switching on all semiconductors in the buck inverter. The second section is a ZVSPWM commutation cell to provide the soft-switching on the switches S1 and S2. It is composed of the auxiliary diodes Da1, Da2, the resonant inductor Lr, the resonant capacitor Cr, the transformer T, and auxiliary switch Sa . It is rated for a small power when compared to the output power. The third section is the output inverter with unipolar voltage switching. It is composed of the switches S3, S4, S5, S6 and output filter Lf, Cf. This section performs the function of conventional PWM buck dcac conversion with output voltage of variable amplitude and frequency. In the positive (negative) half-period of the desired output V0(t), the switch S4 (S3) always on, the switches S6 (S5)and S3 (S4) perform the inversion function at high frequency switching, while switch S1 or S2 perform the boost dcdc conversion function in PWM continuous conduction mode. For convenience in analysis, only the negative-half period of the desired output voltage is described. To simplify the analysis, it is assumed that the proposed single-phase ac dcac converter is operating in steady-state and the following assumptions are made during one switching cycle. 1) All components and devices are ideal. 2) During one switching cycle, the power factor preregulator Inductor Lin is large enough to assume that the input current iLin is constant and is much greater than resonant inductor. 3) During one switching cycle, the output filter inductor is large enough to assume that the output current is constant and is much greater than resonant inductor. 4) The capacitor is large enough to assume that the voltage is constant and ripple free.
A) STAGE 1 [t1 <t <t2]
Fig.2. Stage 1 [t1 <t <t2] Before t=t0, the switches S3, S4, S5 and S6 and maintain turn-on state, the switches S1 and S2 maintain turn-off state. The energy stored in inductor Lin is delivered to capacitor C1 while the output loop of the inverter is in a freewheeling state. This stage begins when Sa turns on with ZCS at t=t0. The resonant inductor Lr is charged linearly from voltage (1-1/n)Vc1, where n is turn ratio of the transformer. The resonant current increases linearly. The stage ends when the resonant current reaches and the body diodes of switches, and turn off with ZCS at t=t1. During this stage, the switches S4 and S5 are turned off at ZVS when the body diodes of switches S3, S4, S5, S6, are turnoff with ZCS at t=t1 . The resonance of Cr and Lr is started. The resonant voltage Vcr(t) is decreased and the resonant current iLr(t) is increased. The energy stored in capacitor C1 is gradually provided to the buck inverter. The stage ends when the resonant voltage VCr(t) becomes null. B) STAGE2 [t2<t<t3] In this stage, the diodes D1and D2 the body diodes of switches S1and S2 are turned on at ZVS when the resonant voltage Vcr(t) is equal to zero. Because the voltage across switches S1 and S2 is zero, this is the best time to turn on the switches S1 and S2 with ZVS. In this stage, the freewheeling loop is also formed by Da1, Lr, Sa, , the body diodes of S1, S2 and the diodes D1, D2.
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decreased. This stage is finished when the resonant voltage VCr(t) reaches Vc1 and the voltage Vpn(t) drops to zero.
Fig. 5. Stage 4[t4<t<t5] Fig.3. Stage 2 [t2<t<t3] Thus, the energy stored in resonant inductor Lr is delivered to the capacitor C1 via transformer T. The resonant current iLr(t) is decreased linearly. In this stage, the energy stored in capacitor C1 is continuously provided to the buck inverter and the input voltage Vin(t) charges the input inductor Lin. This stage ends when the resonant current iLr(t) drops to zero. C) STAGE 3[t3<t<t4] At t=t3, the resonant current iLr(t) is equal to zero. The body diodes of the switches S1, S2 and the diodes D1, Da1 are turned off at ZCS and this stage begins. In this stage, the input voltage Vin(t) charges continuously the input inductor Lin and the energy stored in capacitor C1 is continuously provided to the buck inverter. E) STAGE 5 [t5<t<t6] In this stage, because the voltage Vpn(t) drops to zero, the body diodes of the switches S3, S4, S5, S6 and the switch S4 can be turned on with ZVS. The switch S6 can be turn off with ZVS. The freewheeling loop is formed in buck inverter circuit.
Fig.6. Stage 5 [t5<t<t6] The energy stored in input inductor Lin is delivered to the capacitor C1. F) STAGE 6 [t6<t<t7] Although the assistance for soft commutation on the switches has been completed in stage 6, the switches S3, S4 must perform continuously the turn-on operation of the boost power factor pre-regulator. Therefore, the switch Sa is turned on with ZCS at t=t6 again for providing soft commutation on them and this stage begins. The resonant inductor Lr charges linearly from voltage (1-1/n) Vc1 again. Therefore, the switch Sa is turned on with ZCS at t=t6 again for providing soft commutation on them and this stage begins. The resonant inductor Lr charges linearly from voltage (1-1/n) Vc1 again.
Fig. 4. Stage 3 [t3<t<t4] The boost power factor pre-regulator has another feature, which provides the zero-voltage-switching on all semiconductors in the buck inverter. Although the duty interval DPFCTs is not complete, the switches must be turned off at t=t4 for providing soft commutation in buck inverter circuit. Therefore, this stage ends when the switches S1, S2 are turned off at t=t4 . D) STAGE 4[t4<t<t5] In this stage, the switches S1 ,S2 are turned off with ZVS. The energy stored in input inductor Lin charges the resonant capacitor Cr .Thus, the resonant voltage VCr(t) is linearly increased and the voltage Vpn(t) is linearly
Fig.7. Stage 6 [t6<t<t7]
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The resonant current iLr(t) increases linearly. The stage ends when the resonant current reaches ILink+ ILfk and the body diodes of switches and turn off with ZCS at t=t7. G) STAGE 7 [t7<t<t8]
I) STAGE 9 [t9<t<t10]
Fig.10.Stage 9 [t9<t<t10] At t=t9, the resonant current is equal to zero. The body diodes of the switches S1 and S2 the diodes D1, Da1 are turned off at ZVS and this stage begins. In this stage, the input voltage Vin(t) charges continuously the input inductor Lin . This stage ends when the duty interval DPFCTs is complete and the switches S1, S2 are turned off at t=t10. Fig.8. Stage 8 [t7<t<t8] J) STAGE 10 [t10<t<t11] During this stage, the body diodes of switches S5 and S6 are turned off with ZCS and the buck inverter circuit performs continuously the freewheeling state. The resonance of Cr and Lr is started again. The resonant voltage Vcr(t) is decreased. The resonant current iLr(t) is increased. The stage ends when the resonant voltage Vcr(t) becomes null. H) STAGE 8 [t8<t<t9] In this stage, the diodes and the body diodes D1, D2 of switches S1 and S2 are turned on at ZVS when the resonant voltage is equal to zero. In this stage, the switches S1, S2 are turned off. The energy stored in input inductor Lin charges the resonant capacitor Cr. Thus, the resonant voltage Vcr(t) is linearly increased and the voltage Vpn(t) is linearly decreased. This stage is finished when the resonant voltage Vcr(t) reaches Vc1 and the voltage drops Vpn(t) to zero.
Fig.11. Stage 10 [t10<t<t11]
Fig. Stage 8 [t8<t<t9] Because the voltage across switches S1 and S2 is zero, the switches S1 and S2 can be turned on with ZVS again. In this stage, the freewheeling loop is also formed by , the body diodes of S1 and S2 ,and the diodes D1 and D2 . Thus, the energy stored in resonant inductor Lr is delivered to the capacitor C1 via transformer T .The resonant current is decreased linearly. In this stage, the input voltage charges the input inductor again. Thus, this stage performs continuously the function of the boost power factor preregulator. This stage ends when the resonant current drops to zero.
K) STAGE 11 [t11<t<t12] In this stage, because the voltage Vpn(t) drops to zero, the body diodes of the switches S1, S2, S3, S4 and the switches S5 and S6 can be turned on with ZVS. The buck inverter circuit performs continuously the freewheeling state. The energy stored in input inductor Lin is delivered to the capacitor C1.
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Fig.12.Stage 11 [t11<t<t12] In this stage, because the voltage Vpn(t) drops to zero, the body diodes of the switches S1, S2, S3, S4 and the switches S5 and S6 can be turned on with ZVS. The buck inverter circuit performs continuously the freewheeling state. The energy stored in input inductor Lin is delivered to the capacitor C1.After stage 12, the circuit operation is returned to the first stage. V. SIMULATION RESULTS To verify the performance of the proposed control strategy, a MATLAB-SIMULINK prototype of the resonant inverter with inbuilt boost converter is developed. To illustrate the design feasibility of the proposed converter, a prototype with the following specifications is chosen: SIMULATION DESIGN VALUES: Vin(RMS input voltage) =220V Frequency =50HZ Input inductors =10mH Input capacitor =1000mF Output capacitor =1mF Load resistance =20Kohms Duty Cycle =50%. Transformer Ratio =1:1 SIMULATION CIRCUIT: RESONANT CIRCUIT OUTPUT WAVEFORM VI. CONCLUSION Pure ac output voltage is presented with simple and compact configuration. Thus, the proposed acdcac converter is applicable in UPS design. In the proposed circuit is operated at constant frequency, and all semiconductor devices is operated at soft-switching without additional voltage stress and current stress. A significant reduction in the conduction losses is achieved, since the circulating current for the soft switching flows only through the auxiliary circuit and a minimum number of switching devices are involved in the circulating current path. In addition, the rectifier in the A novel soft-switching single-phase acdcac converter with high input power factor and proposed converter uses a single converter instead of the conventional configuration composed of a four-diode front-end rectifier followed by a boost converter. An average-current-mode control is employed in the rectifier side of proposed converter to detect the transition time and synthesize a suitable low harmonics sinusoidal waveform for the input current. The sinusoidal pulse-width modulation (SPWM) control strategy is employed in the inverter of proposed converter to achieve good dynamic regulation. RESONANT CIRCUIT OUTPUT WAVEFORM
Continuous pow ergui

Scope L C1 Scope1 Pulse Generator1
+ v -
R Voltage Measurement
+ v -
Voltage Measurement1 Diode2

g
Diode1
1
g D
Mosfet
g m S D S
Series RLC Branch3 Series RLC Branch C Series RLC Branch2
Diode3
3
m S
6
m
AC Voltage Source
Scope2 R 1 2 7
+ v -
Voltage Measurement2
D D
T 4
8
g D S
Mosfet1
m S
5
m S m
Diode
Mosfet2
m S Tm
Pulse Generator
Pulse Generator2
M+ M
capacitor -start
Scope3
Single Phase Asynchronous Machine
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VIII ACKNOWLEGEMENT The work described in this paper was substantially supported by the management of Adhiparasakthi engineering college and faculty members of Electrical and Electronics Department. IX.REFERENCES [1] R. R.Verderber,O. C.Morse, and W. R. Alling, Harmonics from compact fluorescent lamps, IEEE Trans. Ind. Appl., vol. 29, no. 3, pp. 670674, May 1993. [2] M. K. Kazimierczuk and W.Szaraniec, Electronic ballast for fluorescent lamps, IEEE Trans. Power Electron., vol. 8, no. 4, pp. 386395, Oct. 1993. [3] M. C. Cosby, Jr. and R. M. Nelms, A resonant inverter for electronic ballast applications, IEEE Trans. Ind. Electron., vol. 41, no. 4, pp. 418 425, Aug. 1994. [4] A. J. Calleja, J. M. Alonso, E. Lopez, J. Ribas, J. A. Martinez, andM. Rico- Secades, Analysis and experimental results of a single-stage high-powerfactor electronic ballast based on flyback converter, IEEE Trans. Power Electron., vol. 14, no. 6, pp. 9981006, Nov. 1999. [5] J. M. Alonso, A. J. Calleja, J. Ribas, E. L. Corominas, and M. Rico- Secades, Analysis and design of a novel single-stage high-power-factor electronic ballast based on integrated buck half-bridge resonant inverter, IEEE Trans. Power Electron., vol. 19, no. 2, pp. 550559, Mar. 2004. [6] M. Ponce, A. J. Martinez, J. Correa, M. Cotorogea, and J. Arau, High-efficient integrated electronic ballast for compact fluorescent lamps, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 532542, Mar. 2006. [7 ] A. R. Seidel, F. E. Bisogno, and R. N. do Prado, A design methodology for a self-oscillating electronic ballast, IEEE Trans. Ind. Appl., vol. 43, no. 6, pp. 1524 1533, Nov./Dec. 2007. [8] J. C. W. Lam and P. K. Jain, A dimmable electronic ballast with unity power factor based on a single-stage current-fed resonant inverter, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 31033115, Nov.2008. [9] A. R. Seidel, F. E. Bisogno, T. B. Marchesan, and R.N. do Prado, Designing a self-oscillating electronic ballast with bipolar transistor, in Proc. 2002 Ind. Appl. Conf., pp. 10781083. [10] A. J. Calleja, J. M. Alonso, J. Ribas, E. Lopez, J. Cardesin, J. Garcia, and M. Rico-Secades, Electronic ballast based on single-stage high-powerfactor topologies: A comparative study, in Proc. IEEE 2002 28th Annu. Conf. Ind. Electron. Soc., pp. 11961201.
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Implementation of Space Vector Modulation for Voltage Source Inverter

First T.A Liphi, Student Member, IEEE, Second R. Senthil Kumar
side. The ac voltage may be variable or constant depending on the applications. In fact, the general name "converter given because the same circuit can operate as an inverter as well as a rectifier. A voltage source inverter should have a stiff voltage source at the input that is thevenin impedance should ideally be zero. A large capacitor can be connected at the input if the source is not stiff. The inverter output can be single phase or polyphase, and can have square wave, sine wave, PWM wave, stepped wave, or quasi-square wave output. The voltage-fed converters are used extensively and some of their applications can be ac motor drives, ac uninterruptible power supplies, Induction heating, ac power supply from battery, Photovoltaic array, or fuel cell, Static VAR generator or Compensator, active harmonic filter etc. [1], [2]. There are various techniques to vary the inverter gain. The most efficient methods for controlling the inverter gain (and the output voltage) are to incorporate pulse width modulation control within the inverter. The advantages of PWM methods are: 1) it is possible to substantially reduce or eliminate lower order harmonic frequencies. The higher order harmonics can be filtered by the load inductance itself 2) it is possible to control the output voltage without significantly adding to the total number of power circuit components of the inverter [3].
III.
Abstract---Among the various PWM techniques available for inverter switching, Space Vector Modulation has gained much importance. This paper introduces the concept of space vector modulation for voltage source inverters. The Space vector modulation scheme generates the inverter leg switching time from the sampled reference phase voltage amplitudes. It involves sector identification and lookup tables. The Space Vector Modulation for voltage source inverter is simulated using MATLAB/SIMULINK model and the results are analyzed for various switching frequencies. Index Terms---Inverter, Space Vector Modulation, THD.
I. INTRODUCTION The space vector modulation (SVM) method is an advanced, computation intensive PWM method and is possibly the best among all the PWM techniques. Because of its superior performance characteristics, it has been finding wide spread application in recent years. A power electronic inverter is essentially a device for creating a variable ac frequency output from a DC input [1]. The output frequency of an inverter is determined by the rate at which the semiconductor devices are switched on and off by the inverter control circuitry and consequently, an adjustable frequency ac output is readily provided. It is possible to control the output voltage as well as optimize the harmonics by performing multiple switching within the inverter with constant dc input voltage. The dc power input to the inverter may be battery, fuel cell, solar cell or other source. But in most industrial applications it is fed by a rectifier. A voltage fed inverter (VFD) or Voltage source inverter (VSI), is one in which has stiff dc voltage source at its input terminals. In many industrial applications, it is often required to control the output voltage of the inverter to cope up with the variations of the DC input voltage, for voltage regulation of the inverters and for the constant volt /frequency control requirements [2]. In spite of the complexity involved in the SVM (many output vectors) compared to carrier-based, it remains the preferred one due to the reduced power losses by minimizing the power electronic devices switching frequency. This paper presents the state-of-the-art of SVM technique and computer simulation works of SVM scheme in voltage source inverter. It also compares the results of the two level in terms of Total harmonic distortion (THD) and switching frequencies.
II.
SPACE VECTOR MODULATION
A different approach to PWM is based on the space vector representation of the voltages in the d-q plane. The technique of space vector modulation involves the concept of space vector [4]. In any three phase machine, the stator coils are distributed in space in a symmetrical manner i.e. each coil is placed at 120 degree with respect to each other. In this method the three phase quantities can be transformed to their equivalent 2-phase quantity either in synchronously rotating frame or stationary reference frames
Fig 1: Three Phase Quantities Transformed to Two Phase From this 2 Phase component the reference vector magnitude can be found and used for modulating the inverter output. Let the three phase sinusoidal voltage component be, Va=Vm sin wt, Vb=Vm sin (wt -120), Vc=Vm sin (wt +120). Equating the three phase machine quantities, we get
VOLTAGE SOURCE INVERTER
Voltage fed converters as the name indicates, receives dc voltage at one side and convert into ac voltage on the other
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(1) (2) (3) (4) The circuit of a three phase bridge inverter consists of three half-bridges, which are mutually phase shifted by 2/3 angle to generate a three phase voltage waves.
Va + Vb + Vc = 0 3 3 3 Vd =- ( Vb ) + ( Vc ) = Vm cos t 2 2 2 Vb Vc 3 = Vmsin t. Vq = Va 2 2 2 3 ( jwt ) Rotating vector, Vref = Vd = Vq = e 2
From equation (4) it can be seen that the space vector moves with a constant angular velocity and constant amplitude. In case of non sinusoidal quantities, the space vectors will not necessarily move with constant amplitude or constant angular velocity. The output of the inverters which are usually used in various applications are not perfectly sinusoidal .It contains appreciable amount of harmonics. So, the space vector of the stator voltages in these cases is of amplitude Vdc moving in steps and not with a constant angular velocity. In space vector modulation, a reference vector of the stator voltages is generated , which is made to move in the d-q plane in small steps so that it appears to move smoothly, as in the case with a sinusoidal supply. The space vector modulation is based on the space vector representation of voltages in d-q plane. After the transformation to the two phase quantities, the power as well as the impedance remains unchanged. In space vector modulation we try to generate a voltage reference vector at any point of time and the voltage reference vector Vref is sampled which is approximated by a time sequence of three well defined switching state vector nearest to the reference vector. This is done by sampling the switching state vectors in such a way that the total volt seconds generated by these vectors over an interval Ts equals the volt seconds generated by the reference vector Ts. The space vector modulation technique is a PWM technique that is relatively recent. It is amenable to digital implementation. This method has the advantage that it yields a higher value of fundamental voltage as compared to the other PWM techniques. As a result, it produces less harmonic distortion in the critical range where the ratio of switching frequency to fundamental frequency is low. It is possible to implement this technique in a simple manner and with a variety of switching devices. This method can also be used for high switching frequency. The space vector modulation technique differs from other SPWM technique in that there are not separate modulators used for each of the three phases. Instead, the complex reference voltage is processed as a whole. The space vector concept is used for deriving the switching instants for a two level PWM inverters. The PWM control is performed according to the space vector modulation technique. The controlling variables of a space vector modulator are the components of the stator voltage vector, referred to as the reference vector Vref in polar coordinates. The space vector modulation strategy approximates the reference vector during a sampling interval by a sequence of three nearest switching state vectors.
Fig 2: Simplified Two Level Inverter
Consider the simplified three phase inverter in the figure (2). At any time only one switch in each leg of the inverter is on. When the top of any leg of the inverter is turned on .The voltage at the midpoint of that leg with respect to the dc centre tap is Vdc/2.Let the former state be represented by +, the latter state by -.
Fig 3: Inverter Switching States
There are 8 possible states with the inverter. The line-line stator voltage will be: Vab=Vao-Vbo, Vbc=Vbo-Vco, Vca=VcoVao.The lines to neutral voltages are Van=1/3(Vab-Vca), Vbn=1/3(Vbc-Vab), Vcn=1/3 (Vca-Vbc). The phasors for each state of inverter also called the switching state vectors can be drawn as shown in fig (4). The vector of the inverter output voltage Vk can assume only seven different locations in the complex plane which are called the switching state vectors [5]. Vk=
( k. ) 2 { ( )Vdc .e 3 k=1,2, 3
{0
k=0
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During the sampling interval the desired reference vector is approximated in an average sense, and not the same as reference vector .So there is a voltage ripple. The ripple and there by the harmonic current can be reduced to some extent by switching as mentioned above. Also, by keeping the sampling frequency bery high compared to supply frequency, the ripple current can be reduced. The vector PWM gives a higher voltage output while still in modulation, by a factor of 2/3 or 15% more output without going to over modulation. The optimum PWM modulation is possible if only the three switching states adjacent to the reference vector are used and the cycle wherein the average voltage vector becomes equal to the reference vector consists of three successive switching states only. The redundancy of the zero switching states is used to minimize the number of commutations in switching sequences. SIMULINK IMPLEMENTATION
Fig 4: Space Vector Representation of Two Level Inverter
In the space vector modulation , the space phasor of the stator voltage is approximated by a reference phasor Vref which moves in the dq plane with smooth motion as in the case when a balanced three voltage is supplied to the stator.This is achived by sampling the switching state vector in such a way that the time average over a sampling interval Ts equals the time average of Vref over Ts.Considrer a 60 degree sector figure(5)described by a successive switching state vectors and two zero state vectors.
IV.
To implement the algorithm in Simulink, we shall assume that the three phase voltages are as given by equations 1 to 6.The switching time calculator provides the pulse duration for each switches of the inverter. The Simulation is performed for a DC source of value 300 V. At 0.667 MI the output line rms voltage is 200V.
Continuous powergui
Scope 5 f(u)
sector selection ts
Fig 5: Determination of Switching States
200
ta
Out1
vdc
Fcn
Saturation 2
tb
Subsystem1 f(u) Saturation 1
Vref .Ts = Vo.
To To + V7. + V1.T1 + V2.T2 2 2 Ts = To + T1 + T2
1/2 Gain 1 -KGain 2
-KGain 5
Math Function 2
NOT Logical Operator
The sampling time, Ts=1/fs, where fs=switching frequency. The switching state vector V1 is sampled for time T1, V2 for time T2 and V0 and V7 for time To/2 each such that (5) (6)
Fcn1
g C
Scope 1 Scope 2 atan 2 Trigonometric Function -KGain 6 angle to sector

In1Out1
g C
IGBT /Diode
IGBT /Diode2
IGBT /Diode1
g C
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Three -Phase Series RLC Load A B
-KGain 4
Out1
Scope 3
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Gain Three phase voltage 1 Math Function sqrt Scope
IGBT /Diode 3
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NOT Logical Operator 1
IGBT /Diode5
NOT Logical Operator 2
Math Function 1
-KGain 3
+v Voltage Measurement 4 Scope
Scope 6
From equations 5 and 6 T1 and T2 and To can be obtainrd.Considering the projection of V1, V2 and Vref on dq axis T1=Ts.m.sin (60-),T2=Ts.m.sin(), To=Ts(T1+T2) where m=Vref/Vdc, the modulation index and V1+V2+Vdc.The implementation of SVM involves generation of the gating pulses to each of the six devices of the inverter for the correct intervals so that the appropriate time intervals given by the three equations. Based on the sector in which the reference vector is present at any sampling interval, V1and V2 may be any of the six switching state vectors.V1 is active for time T1, V2 for T2 and V0 and V7 for To /2 each.
Fig 7: Simulink Implementation of SVM based Two Level Inverter
Fig 8: Sector Identification
Fig 6: Optimum Pulse Pattern of Space Vector PWM
Fig 9: Pulse Pattern for Two Level Voltage
g C
g C
g C
1/2
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shows that as the switching frequency and modulation index increase THD decreases. The proposed scheme has got the advantage of reduction in the device switching frequency for the same sampling rate which is essential when working with low frequency high power devices like GTOs. It is easy to implement using digital techniques. REFERENCES
Fig 10: Phase A Voltage at Switching Frequency 14,400 HZ, MI=0.85
Fig 11: Two Level Line to Line Voltage at Switching Frequency=14,400 HZ and MI=0.85
[1] Muhammad H Rashid, "Power Electronics, Circuits, Devices and Applications" [2] Bimal.K.Bose,"Modern Power Electronics and AC Drives [3] Zhenyu Yu, Arefeen Mohammed, Issa Panahi, A Review of Three PWM Techniques", American Control Conference Proceedings, June 1997 [4]Analysis and Realization of a Pulse width Modulator Based on Voltage Space VectorsHenz Willi Van Broeck, Hans-Christoph Skudelny, IEEE Transaction on Industrial Applications, January 1988, vol 24, no.1 [5]H Pinheiro,F Botteron,C Rech,L Shuch,R F Camarg,H A Grundling, J R Pinherio, Space Vector Modulation for Voltage Source Inverter: A unified Approach, IEEE Annual Conference , 2002,vol.1,pp 23-29 [6]Alexandru Savulescu, The Analysis and Simulation of the SVM Generator used for the Control of Electric Drives with Asynchronous Motors, 6 th International Conference on Electromechanical and Power Systems, October 2007
Fig 12: Total Harmonic Distortion of Two Level Line to Line Voltage at Switching Frequency=14,400HZ and MI=0.85
Table 1: Total Harmonic Distortion Values for Various Switching Frequencies and MI at Different Loading Conditions Switching frequency (hz) 200 2400 225 255 200 7200 225 255 200 14,400 225 255 0.667 0.75 0.85 0.667 0.75 0.85 0.667 0.75 0.85 65.34 63.08 62.51 60.77 59.54 58.70 58.44 57.69 56.87 Vlrms (v) MI THD
V. CONCLUSION The Space Vector Modulation scheme for voltage source inverter is tested using MATLAB/SIMULINK software. The performance of the two-level inverter was analysed.It
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Neuro-Fuzzy Controller for Non-Linear Buck and Quasi-Resonant Buck Converter

A.Rameshkumar1, Dr.S.Arumugam2
2
Research scholar, Government College of Technology, Coimbatore-13, India, arkr1966@yahoo.com. Chief Executive Officer, Nanda Engineering College, Pichandapalayam, Erode 638 052, arumugamdote@yahoo.co.in. weighted average of individual matrix in each switching interval [3] The two assumptions of this methodology impose severe limitation to its application range and hence an unified version namely Generalized State Space Averaging (GSSA) technique [4] is proposed in which time average of the individual switching internal matrix is used and it concentrates on low-frequency behaviour of the circuit giving thus a low order representation. Crucial to the performance of aforesaid converter is the choice of control methods and the objective is to select a methodology which is capable of improving its efficiency, reducing effect of disturbance due to line and the load variations, lessening electromagnetic interference and being less affected by variation in the components. An essential feature of the conventional methodology is that the control algorithm or strategy is analytically described by equations such as algebraic, difference, differential and so on; the synthesis of such algorithm requires a formalized analytical description of the system by a mathematical model [5]. However, a complex process like cement plant, nuclear reactor, etc., requires very complicated mathematical analysis and floating point algorithm which makes the implementation of mathematical model very tedious and time consuming. Hereto, if the required range of operation is high, a linear controller may exhibit degradation in the performance or even instability as non-linearities such as backlash, coulomb friction, etc., in the system cannot be properly compensated [5]. This reality, inevitably promotes the endeavour to control methods that incorporates non-linear dynamics into the design. Among the non-linear control methodologies available at present, a fuzzy interference or fuzzy-rule based system employs only IF-THEN rules to model the qualitative aspects of human knowledge and reasoning process without quantitative analysis. This fuzzy modeling or identification first explored systematically by T. Takagi and M.Sugeno has found numerous applications in both modeling and control [6] and were further extended by C.F.Juang and C.T.Lin to various areas of engineering such as control, communication and signal processing [7]. However, two basic aspects of this fuzzy modelling which needs better understanding are as follows: (i) No standard methods exist for transforming human knowledge or experience into the rule base and data base of a fuzzy inference system; and (ii) At present a need arises for effective method to tune the membership function
Abstract A Non-linear controller based on Neuro-fuzzy integrated adaptive system is implemented and its application to the regulation and dynamic control of output voltage of Buck and Zero Current Switching Quasi-Resonant Buck Converter is comparatively investigated. Neuro-fuzzy hybridization initially proposed by J.S.RogerJang results in an intelligent system which synergizes human-like reasoning method of fuzzy systems with the leaning and connectionist structure of neural networks in which the structure-learning algorithm is primarily used to find an appropriate fuzzy rule and the parameter-learning algorithm is then utilized to fine-tune the membership function and other parameters. The above topology is modeled using Simulink power system block of MATLAB software and operated at 200 kHz to evaluate its closed-loop performance with respect to line and load regulation. It is verified by simulation that the Neuro-Fuzzy integrated adaptive system modifies itself the characteristics of IF-THEN rules and structure of the system and thus achieves a good transient response characteristics under various conditions of operation. Key words: Generalised State Space Averaging (GSSA), QuasiResonant Buck Converter, Adaptive Network- Fuzzy Inference System (ANFIS), Line and Load Regulation.
I. INTRODUCTION Aerospace and industrial applications as of today demand stringently specified high power density converter and it is imperative to design such converter to operate at higher frequency to achieve high power density. Pulse Width Modulated (PWM) converter drew prime attention wherein the switch experiences hard switching at switching transitions if auxiliary circuit is not included and it leads to switching loss (Ps) as estimated from equation (1.0) (1.0) Where ton and toff are the ON-period and OFF-period of converter. With Zero Current Switching property, the switch in Quasi-Resonant converter works on the state of zero current during switching ON and OFF to offer advantages such as self commutation, low switching stress and loss, reduced electromagnetic interference and noise, and faster transient response to line and load variations [1]- [2]. In modeling and analysis of ac and dc behaviour of switched converter, a method namely State Space Averaging (SSA) is used because the different state matrix of each switching interval is replaced by an equivalent matrix which is the
Ps = 0.5 Vg Io (t on + t off ).fs
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Neuro-fuzzy controller in order to relatively compare the time-domain performance of Buck and Quasi-Resonant Buck Converter with respect to line and load regulation. III. SMALL SIGNAL MODEL OF POWER CONVERTER The Half-wave mode Zero Current Switching (ZCS) Quasi-Resonant Buck or step-down Converter in Fig. 1 uses a unidirectional switch [11] and is operated in discontinuous conduction mode. Its input-to-output voltage transfer function [12] is obtained by analyzing the circuit in its four modes of operation as shown in Fig. 2, 3, 4, and 5 and Table I using the aforesaid Generalized State Space Averaging (GSSA) technique and is depicted in equation (4.0).
in order to minimize the output error measure to a considerable extent [6]. Hence, a novel architecture called the Adaptive-NetworkBased Fuzzy Inference System or ANFIS is suggested to serve as a basis for constructing a set of fuzzy IF-THEN rules with appropriate membership functions to generate the stipulated input-output pairs. The Neuro-Fuzzy integrated system is thus a multi-layered connectionist network which brings not only the low-level learning and computational power of neural network into fuzzy system but also the high-level human-like thinking and reasoning of fuzzy system into the neural network [8]; it is henceforth used successfully in various applications by utilizing its network architecture and the associated learning algorithm. The objective of this manuscript is to implement a Neuro-Fuzzy controller to comparatively study the time-domain characteristics of Buck and QuasiResonant Buck Converter under five different conditions of operation Simulation results are hence depicted for the aforesaid operating conditions and the two vital time-domain specifications namely settling time and peak overshoot are hence used to measure the performance of the system [9].
Fig 1: ZCS QRC Buck Converter
II. GENERALIZED STATE-SPACE AVERAGING (GSSA)

METHODOLOGY The state equation of a periodically switched network with k different switched modes in each switching cycle is represented as (2.0) equation of (2.0) is defined on time interval The i between the limits (ti-1, ti) where
th
X (t)=Aix(t)+Bi(t) i = 1,2,...k
Fig 2: Inductor Charging Mode
ti-1=0+
j=1
i-1
j and ti=ti-1 +i
A. Theorem
For the network described by equation (2.0), if the switching frequency is much higher than the highest natural frequency of the state matrix Ai in each switching mode of operation and if the input control variable function Bi is bounded [10], then, equation (2.0) is characterized by the Generalized State-Space Averaging (GSSA) equation (3.0).
Fig 3: Resonant mode
x={ diAi}x+1/T
i=1
i=1 ti-1
Bi()d
ti
(3.0)
Fig 4: Capacitor discharging mode
where T is the switching period and is defined as T=
j=1
fs = 1/T is the switching frequency, fo = is the natural frequency of matrix Ai. , This methodology is used to obtain small-signal model of the Quasi-Resonant Buck Converter and its input-to-output voltage transfer function are utilized to implement a non-linear
Fig 5: Free wheeling mode
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controller on robotics application and Sugenos first car trained to turn and park by itself showed promising results; however, they are subjective and heuristic in nature and the choice of membership functions depends on trial and error methods. Hence, the learning ability of neural networks is integrated with fuzzy logic to afford a more promising method [13]. Neuro- fuzzy methodology in fuzzy modeling research field is divided into two major areas namely (i) the M.Mamdani model in which the linguistic fuzzy or non-crisp modeling is focused on interpretability and (ii) T.TakagiM.Sugeno model in which precise fuzzy modeling is focused on accuracy; the main advantage of second model is its ability to model a system accurately, either globally or locally [14]. The global learning ability motivates the practical applications of model in non-linear system estimation whereas the local learning ability provides a course of interpretability of the local models in the localized subspaces [15]-[17] Its design for the nonlinear power converter namely Quasi-Resonant Buck Converter desires a good knowledge of the structure of an Adaptive Network based Fuzzy Inference System or simply ANFIS [6] and it also saves the rule-matching time of the inference engine in the traditional fuzzy logic system [9]. An adaptive network, as its name applies, is thus a multilayer feed-forward network consisting of nodes and directional links wherein each node performs a particular function on incoming signals and a set of parameters pertaining to this node; the input and output nodes in this connectionist structure represent the input states and output control signals respectively and the nodes in hidden layers function as membership functions and rules. To reflect different adaptive capabilities, both circle and square nodes are used in this network in which a square or an adaptive node has parameters whereas a circle or fixed node has none. In order to achieve the desired input-output mapping, the aforesaid parameters are updated according to the given training data and a learning algorithm; the learning algorithm, in general, combines unsupervised learning and supervised gradient descent learning procedure to build the rule nodes and train the membership functions. Actually, there exist two learning paradigms for an adaptive network namely (i) online learning and (ii) off-line learning. With off-line learning or batch learning methodology, the update action is initiated only after the whole training data were presented whereas with on-line learning or pattern learning, the parameters are updated immediately after each inputoutput pair were presented. The various steps involved in design of a universal Sugenos integrated Neuro-fuzzy non-linear controller are mentioned hereunder A. Identification of input and output variables It is in this step, the design identifies the two key inputs [18] to the controller namely (i) error and (ii) change in voltage error the output of this Neuro-fuzzy controller is the
J M 1- i vo Hi = vg L J s 2 L o Co +s o -RCo i Hi R
Ji +1Hi
(4.0)
TABLE I DEFINITION OF THE STATE
No. 1 2 3 4
MODE Inductor charging Resonant Capacitor discharging Free wheeling
STATE OF THE SWITCH CLOSED CLOSED OPEN OPEN
STATE OF THE DIODE ON OFF OFF ON
where Vo = Output voltage, Vg = Input voltage, Lo = Filter inductor, Co = Filter (output) capacitor, R = Load resistor and
Vo Fs = Hi ( Vg,ILo ) Vg 2Fn ZniLo vg Ji ( vg,iLo ) = (1-cosi ) 2vg ZniLo ZniLo vg Hi ( vg,iLo ) = +i+ (1-cosi ) 2vg ZniLo M=
(5.0) (6.0) (7.0) (8.0)
Zn =
Lr Cr
Zi i=sin -1 - n Lo vg
(9.0)
IV. NEURO FUZZY CONTROLLER It is more appropriate to use a methodology from Artificial Intelligence to handle complexity of non-linearities in the system to achieve an intelligent control action. Intelligent control using Fuzzy logic is the ability of a controller to comprehend, reason and learn about a process and is used in a variety of applications ranging from the products used by consumer and process control in industries to medical instrumentation, information systems and decision analysis. It base its decision on inputs in the form of linguistic variables derived from the membership functions which are used to determine the fuzzy set to which a value belongs and degree of membership in that set. Scharfs self- organizing fuzzy
259
performance and is mentioned in Table II and the rule base in terms of surface view is depicted in Fig. 8.
incremental control action. B. Fuzzification The Universe of discourse of interval spanned by two input variables is partitioned into seven fuzzy subsets of Gaussian shaped membership functions assigning each subset a linguistic value; the various subsets are represented as NB (Negative Big), NM (Negative Medium), NS (Negative Small), ZE (Zero), PS (Positive Small), PM (Positive Medium), and PB (Positive Big) respectively. The two membership functions under consideration are requisite to have uniform shapes, parameters and functions meant for the sake of computational efficiency, efficient use of computer memory and consequently performance analysis. The main advantage to employ Gaussian function is that its continuity is usually required for most of conventional gradient-based, either first-or second-order optimization techniques [19]. The Gaussian membership functions for the two input variables are shown in Fig. 6 and 7.
Fig 8: Surface view of Rule-base TABLE II RULE-BASE FOR NEURO-FUZZY CONTROLLER
Fig 6: Membership Function For Error.
Fig 7: Membership Function For Change In Voltage Error.
C. Creation of rule-base The collection of rules is called a rule-base and the type of rule-base implemented here is usually of M.Sugenos first order. It expresses the input-output relationship in linguistic terms and is heuristic in nature. It is typically written in the form of IF-THEN structure and the two inputs are combined by AND operator. Fuzzy IF-THEN rules or the conditional statements are therefore employed to capture the imprecise modes of reasoning which play an essential role in the human ability to formulate decisions in an environment of uncertainty and imprecision [6]. 49 rules based on M.Sugenos architecture are formed based on the number of membership functions in order to play a key role in improvement of system
D. Defuzzification Conservation of fuzzy into crisp output is defined as Defuzzification. The output of each rule is a linear combination of two input variables plus a constant term and the final output is the weighted average of each rule output [6]. V. ADAPTIVE NETWORK BASED FUZZY INFERENCE SYSTEM (ANFIS) It is assumed that the fuzzy inference system under consideration has two inputs x and y and one output z. The topology used is a 2-input, type-3 structure of an Adaptive Network Based Fuzzy Inference System (ANFIS) with 49 IFTHEN rules wherein it has in total five layers and the arrow on the link indicates the normal signal flow direction when
260
VI. DESIGN DATA It is highly imperative to design a feedback system in such a mode that the output voltage of DC-DC Converter is accurately regulated at desired level in presence of fluctuations in input voltage and load [20]-[21]. Hence, in order to relatively compare the time-domain performance of the Neuro-fuzzy controller to the regulation of Output voltage of Buck and Quasi-Resonant Buck Converter, it is to be designed with the specifications given in Table III with the two main constraints [4] as mentioned hereunder. 1. The rating of the filter components must be much higher than the rating of the resonating components used in the switching converter. 2. The switching frequency must be higher than natural frequency of the low-pass filter at the output and hence state variables of filter state is regarded as constant in each cycle.
TABLE III: DESIGN PARAMETERS
this network is in use. The premise part of a rule delineates a fuzzy subspace while the consequent part specifics the output within this fuzzy subspace. A. Input Linguistic Layer Every node i in this layer perform with a node function
O1 = Ai ( x ) , i = 1.7. i
where x is the input to node i and Ai is the linguistic variable associate with this node function or in other words,
O1 is the membership function of Ai and it specifies the i

degree to which the given x satisfied the quantifier Ai.
Ai ( x ) is selected to be Gaussian-shaped with the range [-1,
1]. B. Conjunction Layer Every node in this layer multiples the incoming signals and send the product away. For instance,
i = Ai ( x ) . Bi ( y ) , i = 1.7.
Each node output represents the firing strength of the rule wherein i is the firing strength of a rule. C. Normalization Layer Every node in this layer calculates the ratio of the ith rules firing strength to the sum of all rules firing strength.
No.
1 2 3 4 5 6 7 8 9 10 11 12
Parameter
Input Voltage Output Voltage Resonant Inductor Resonant Capacitor Filter Inductor Filter Capacitor Load Resistance Switching Frequency Natural Frequency Resonant Frequency Load Current Output Power
Symbol
Vg Vo Lr Cr Lo Co R fs fo fr Io PO
Value
100 120 V 54 V 1.6 H 0.064 F 0.2 mH 20 F 10 100 200 kHz 2.5165 kHz 0.5 MHz 0.545.4 A 2.916 kW
i =
i , i = 1.7. i
The outputs obtained of this layer will be henceforth called as the normalized firing strength. D. Functional or Rule Layer Every node i in this layer perform a node function
Oi4 = i f i = i ( pi x+q i y+ri ) , i = 1.7.

where i is the output of layer 3 and ( pi, qi, ri ) is the parameter set. Parameters in this layer are referred to as consequent parameters. E. Summation Layer The single node in this layer is a circle node labeled which computes the overall output as the summation of all incoming signals.
O5 (Overall output) = i f i = i
i
iifi , i = 1.7. ii
VII. SIMULATION OF QUASI-RESONANT BUCK CONVERTER A Computer Simulation is an attempt to model a hypothetical situation on a computer and becomes a usual part of modeling many systems in engineering to gain insight into the operation of system. It shortens the process of overall design because it is easier to study the influence of a parameter on the behaviour of a system rather than accomplishing it in the laboratory on a breadboard [2]-[22]. The topology is therefore modeled by MATLAB software
The training is done assuming that no expert is available and the initial value for the parameters of membership functions is equally distributed along the Universe of discourse wherein the consequent parts of rule table is set to zero; the structure during training updates the membership functions and rule base parameters according to the nature of the gradient descent algorithm.
261
Converter gives better performance of Voltage regulation than that with the Buck Converter.
Ji/Hi Parameter = 0.0 Case 1: Minimum line and Maximum load condition
and is operated at higher switching frequency of 200 kHz in order to evaluate its closed-loop performance in respect of line and load regulation [23]. The transfer function of the Quasi-Resonant Buck converter is represented as
Ji M 1- vo Hi = Lo Ji Ji vg s 2 L o C o +s -RC o +1Hi Hi R
(4.0)
whereas the transfer function of Buck Converter depicted in Fig. 9 is represented in equation (10.0) as
Fig 9: Buck Converter
vo = vg
M Lo s 2 L oC o+ s +1 R
(10.0)
Fig 10: Output voltage of Case1 (Ji/Hi = 0.0) Case 2: Minimum line and light load condition
The Ji/Hi parameter in the input-to-output transfer function of converter is a function of input voltage (vg) and the current through resonant inductor (iL0). Ji/Hi is varied between -1.0 and 0.0 in steps of +0.2 for the half-wave mode wherein switch permits unidirectional flow of current [4]. Ji/Hi parameter = 0.0 depicts the result of digital simulation of Neuro-fuzzy control of Buck Converter and that of -0.2 to -1.0 depicts QuasiResonant Buck Converter. It is henceforth to compare the closed-loop performance of Neuro-fuzzy controller with Quasi-Resonant Buck Converter and that with the Buck or step-down Converter, five different operating points spanning the entire range of the converter are selected as mentioned hereunder [24]. Two categories of test namely line and load regulation are carried out to evaluate their performance at 200kHz and the two time-domain specifications such as peak overshoot [25] and settling time [26]-[27] are hence compared. Case 1: Minimum line voltage (Vg = 100V) and Maximum load (R = 10) condition Case 2: Minimum line voltage (Vg = 100V) and Light load (R = 100 ) condition Case 3: Mid range line voltage (Vg = 115V) and load (R = 40 ) condition Case 4: Maximum line voltage (Vg = 120V) and Maximum load (R = 10 ) condition Case 5: Maximum line voltage (Vg = 120V) and Light load (R = 100 ) condition. The results of Digital simulation for Ji/Hi parameter equal to 0.0 and -0.2 for various conditions of supply and Resistive load variations are shown in Fig.10 to Fig. 19 and Table IV. It is shown that Neuro-fuzzy control of Quasi-Resonant Buck
Fig 11: Output voltage of Case2 (Ji/Hi = 0.0) Case 3: Midrange line and load condition
Fig 12: Output voltage of Case3 (Ji/Hi = 0.0)

Case 4: Maximum line and Maximum load condition Case2: Minimum line and light load condition
262
Fig 13: Output Voltage of Case4 (Ji/Hi = 0.0) Case 5: Maximum Line and Light Load condition
Fig 16: Output voltage for Case2 (Ji/Hi = -0.2) Case3: Midrange line and load condition
Fig 14: Output voltage of Case5 (Ji/Hi = 0.0)
Fig 17: Output voltage for Case3 (Ji/Hi = -0.2)
Ji/Hi Parameter -0.2 Case1: Minimum line and Maximum load condition
Case4: Minimum line and Maximum load condition

Case5: Maximum line voltage and light load condition TABLE VI: SETTLING TIME OF THE CONVERTER
263
Settling time(ms) CASE Ji/Hi = -0.4 1 2

Fig 19: Output voltage for Case5 (Ji/Hi = -0.2) TABLE IV: TRANSIENT SPECIFICATIONS OF CONVERTER
Ji/Hi = -0.6 0.26247 2.9332 1.1644 0.2630 2.9355
Ji/Hi = -0.8 0.35840 3.4801 1.3974 0.34719 3.4804
Ji/Hi = -1.0 0.37383 3.9200 1.5671 0.43107 3.9203
0.19719 2.2326 0.91683 0.19726 2.2316
3 4 5
PEAK OVERSHOOT CASE BUCK (Ji/Hi= 0.0) 83.806 99.876 96.731 83.672 99.704 QR BUCK ( Ji/Hi =-0.2) 65.619 54.003 53.999 65.561 54.003
SETTLING TIME (ms) BUCK (Ji/Hi= 0.0) 1.3141 13.179 5.6861 1.3151 13.553 QR BUCK ( Ji/Hi =0.2) 0.5770 1.3106 0.47421 0.57749 1.3171
It is thus observed from Table V and VI that the dynamic performance of adaptive network based Fuzzy controller is superior and it is adaptive with the five different operating conditions as compared with the conventional PI controller. VIII. CONCLUSION Quasi-Resonant Buck Converter is a discrete, time variant system which experiences a high degree of non-linearity in its control characteristics; it in its open-loop mode or configuration is highly sensitive to variations in temperature or other factors such as changes in input or load and the output of such power converter cannot maintain constant voltage without a controller. Control strategies based on the linear systems theory cannot provide control algorithm to cope with the increasing complexity and therefore among the available non-linear control methodologies at present, the Neuro-fuzzy control scheme is proposed because it synergizes two techniques by combining the human-like reasoning methodology of fuzzy systems with the learning and connectionist structure of Neural networks and it covers a wider range of conditions of operation. The topology is modeled using MATLAB software to operate at a switching frequency of 200 kHz in order to evaluate its transient performance with respect to line and load variations. It is verified by Digital simulation that due to Quasi-Resonance there is a drastic change in the two time- domain specifications namely peak overshoot and settling time and the non-linear Neuro-fuzzy controller modifies itself the characteristics of rules and structure of the system and attains high reliability, improves the speed of response and hence in total, is effective control methodology for retaining the output voltage of Quasi-Resonant Buck Converter stable against supply and load disturbances.
1 2 3 4 5
The peak overshoot and settling time for Ji/Hi parameter varied from -1.0 to 0.0 in steps of +0.2 is depicted in Table V and VI.
TABLE V: PEAK OVERSHOOT OF THE CONVERTER
Maximum overshoot ( volts) CASE Ji/Hi = -0.4 56.799 54.002 54 56.773 54.002 Ji/Hi = -0.6 54.152 54.002 54.004 54.146 54.002 Ji/Hi = -0.8 54.017 54.001 54.003 53.998 54.001 Ji/Hi = -1.0 53.999 54.001 54.003 53.999 54.001
1 2 3 4 5
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[22] D.Maksimovic, A.M.Stankovic, V.J.Thottuvelil, G.C.Verghese, Modeling and Simulation of Power Electronic Converters, Proc. of the IEEE, Vol: 89, No.6, pp 898-912, June 2001. [23] P.T.Krein, Elements of Power Electronics, Oxford University Press, Oxford, pp 93-97, 2003. [24] K.Viswanathan, D.Srinivasan, R. Oruganti, A Universal Fuzzy controller for a Non-Linear Power electronic Converter, Proc. IEEE International Conference on Fuzzy Systems (IEEE02), Honolulu, HI, USA, pp 46-51, May 2002. [25] M.N.Bandyopadhay, Control Engineering: Theory and Practice, Prentice Hall of India, New Delhi, pp 88-92, 2003. [26] J.J.DAzzo and C.H.Houpis, Feedback Control System Analysis and Synthesis, Mc Graw Hill, Singapore, pp 80-84, 1984. [27] M.Gopal, Control Systems-Principles and Design,Tata Mc Graw Hill Publishing Company Ltd, New Delhi, pp 362-365, 1997.
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AUTHORS INFORMATION
A.Rameshkumar received his B.E Degree in Electrical and Electronics Engineering in April 1988 and M.E Degree in the field of Applied Electronics in November 1996 from Bharathiar University, Coimbatore. He is doing research on Non-linear control of Quasi Resonant Buck converter at Govt. College of Technology, Coimbatore affiliated to Anna University, Chennai. He is in teaching since the year 1988 and is presently the Professor and Head in the Department of Electrical Engineering at SSM College of Engineering, Komarapalayam:638 183. He is a member of IEEE since 2000. He is also a member in ISTE, IE (I) and a Fellow member in IETE. He has ten research publications in National and International conferences. His research interests are control and instrumentation systems and power electronics.
Dr.S.Arumugam, Ph.D obtained his B.E. Degree in Electrical and Electronics Engineering from the University of Madras in 1971, his MSc. (Engg.) Degree in Applied Electronics from University of Madras in 1973 and Ph.D. in Computer Science and Engineering from Anna University, Chennai in 1983. He has a distinguished career in teaching and research for more than 37 years. In the year 1974, he joined as Associate Lecturer in College of Engineering, Guindy, Chennai. He was elevated as Principal in 1998 and served at Government College of Engineering, Bargur and Government College of Technology, Coimbatore. In 2005, he assumed charge as Additional Director of Technical Education and Chairman, Board of Examinations, Chennai. He retired from service in 2007. Presently he is working as Chief Executive Officer (CEO) in Nandha Educational Institutions at Erode. He has successfully guided 12 research Scholars for their PhD and currently he is guiding 23 Research Scholars. He has published more than 100 Papers in National and International Conferences and Journals. He is a member in IEEE, ISTE; Fellow member in IE (I), IETE and senior member in CSI.
Study on Transient Stability of a Power System Using Series Compensator

Mayank Gupta and KK Mishra
KanpurInstituteofTechnology,Kanpur, kk kit@rediffmail.com
265
Abstract- The continuously growing demand for electric power has brought many private companies to contribute in power sector. Days are not far away when many private companies will generate and transmit power to various locations in India. Since the location of generating stations will be confined to area of raw material, the prime challenge for the company will be the stability of power system when power is transmitted over a long distance from generating station to the consumer end. With the advancement in power electronics, the application of series capacitor in EHV transmission line is an alternative for increasing electric power transfer capacity over long distance. In this paper, a generator connected to infinite bus bar has been considered and three phase short circuit fault created at the sending end. A flow chart developed based on modified Euler method to solve swing eqn. and programming carried out to solve the problem. The bank of capacitors is installed at the sending end. The capacitors are inserted and bypassed by GTO thyristor. The controlling of thyristor is based on different fault clearing time, compensation level and change in power P, angular speed and load angle . These cases have been studied and compared. Finally most suitable method has been suggested. Index Terms-Extra high voltage(EHV), gate turn off thyristor (GTO), gate controlled series capacitor (GCSC ), increment in power(P), increment in angular speed(), increment in load angle(), thyristor switched series capacitors (TSSC).
Series compensation is often the more economic alternative for sufficiently increasing long distance power transmission resulting in important technical advantages in power system behavior, increased steady state and transient stability limit, reduced voltage drops in receiving system during occurrence of severe contingencies, possibility of better load sharing between parallel transmission circuits and reduction in transmission losses. Series capacitor compensation is now more and more applied to long distance transmission systems. Series capacitor reduces the effective transmission line inductive reactance, therefore resulting in a large capacity for stable power transfer [1]-[3]. II. SERIES COMPENSATION In the recent years, a lot of development in the field of series compensator has been made. The power electronics involvement in the controlling of series compensator has also gone long way to solve stability problem. Series capacitor compensation is now more and more applied to long distance transmission system. The advantage of series compensator over shunt compensator also increased its importance as shunt compensation is ineffective in controlling the actual transmitted power which, at a defined transmission voltage, is ultimately determined by the series line impedance and the angle between the end voltage of line. The ac power transmission over long lines was primarily limited by the series reactive impedance of the line. Series capacitive compensation cancels a portion of the reactive line impedance and thereby increases the transmittable power. The variable series compensation is highly effective in both controlling power flow in the line and in improving stability. The basic idea behind series capacitive compensation is to decrease the overall effective series transmission impedance from the sending end to the receiving end, i.e. X in the P=(V2/X)sin , relationship characterizing the power transmission over a single line. A series capacitor compensated line, is assumed to be composed of two identical segments (Fig.1a). The corresponding voltage and current phasors are shown in Fig 1b. When the end voltages are same the magnitude of total voltage across the series line inductance, Vx=2 Vx/2 is increased by the magnitude of the opposite voltage, Vc, developed across the series capacitor; this results from an increase in the line current.
I. INTRODUCTION HE power that can be transmitted over a long distance transmission line, from the generation end to the load end is determined by the following stability condition. At the generation end the synchronous stability the so called first swing stability i.e. none of the connected generators should lose its synchronism as a result of disturbance on the connected transmission and at the load end voltage stability i.e. no voltage instability should occur which can lead to a voltage collapse at the load end. The fulfillment of these stability conditions often results in limitations of the transmitted power to a level much below the thermal capacity of such lines and perhaps even below the available generation capacity. The longer the distance, the wider is the gap between the limit set by the stability condition and the thermal capacity of the transmission line or the available generation capacity. Thus to effectively utilize the available transmission and generation capacity, some measures should be adopted to solve the stability problem.
The authors are with Kanpur Institute of Technology, Kanpur, affiliated to GBTU, Lucknow. Mayank Gupta is a final year B.Tech student and KK Mishra is an associate prof in Electrical & Electronics Engg deptt.. kk_kit@rediffmail.com, mayan.gupta36@gmail.com
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Fig 2a. The corresponding normalized terminal voltage Vr versus power P plots, with unity Pf load at 0, 50 and 75% series capacitive compensation are shown in Fig 2b.
Fig. 2 Effects of series compensation (a)a simple radial system (b) terminal voltage vs. P plot at varying compensation levels. Fig. 1 Series compensated system.(a) series capacitor compensated line (b)corresponding voltage and current phasors (c) P,Q vs. curve.
The effective transmission impedance Xeff with the series capacitive compensation is given by Xeff=X- Xc (1) Or, Xeff= (1-k) X (2) Where k is the degree of series compensation, i.e. k=Xc/X (3) 0 k< 1 The current in the compensated line, and the corresponding real power transmitted is given by: I= (2V/(1-k)X ) sin ( /2) (4) 2 P=Vm I=[V /(1-k)X] sin (5) The reactive power supplied by the series capacitor is given by: (6) Qc=I2Xc=[2V2/X] k/(1-k)2 ]*(1-cos ) The relationship between the real power p, series capacitor reactive power Qc, and angle is plotted at various values of the degree of series compensation k in Fig 1c. The transmittable power increases with the degree of series compensation k. The reactive power supplied by the series capacitor also increases sharply with k and varies with angle & in a similar manner as the line reactive power. The impedance of the series compensating capacitor cancels a portion of the actual line reactance and thereby the effective transmission impedance. In order to increase the current in the given series impedance of the actual physical, the voltage across this impedance must be increased. This is done by an appropriate series connected circuit element, such as a capacitor, the impedance of which produces a voltage opposite to the prevailing voltage across the series line reactance. Thus, an alternative compensating circuit element may be envisioned as an ac voltage source, which directly injects the desired compensating voltage in series with the line [2] Series capacitive compensation can also be used to reduce the series reactive impedance to minimize the receiving end voltage variation and the possibility of voltage collapse. A simple radial system with feeder line reactance X, series compensating reactance Xc, and load impedance Z is shown in
III. ANALYSIS AND RESULTS Transient stability program is a natural extension of load flow programme. In order to conduct transient stability studies of a large-scale power system network, we first of all conduct load flow studies of the power system in order to obtain system conditions prior to the disturbances. After conducting the load flow study the representation of the power must be modified to include remaining elements in addition to buses, transformers and transmission network. The remaining elements are rotating machines and loads. Hence the original bus impedance/admittance matrices must be modified to include at representations of rotating machines and static loads normally rotating machines are represented by their equivalent circuits and static loads by shunt impedance to ground. The operating characteristics of rotating machines such as synchronous or induction m/c are described by a set of algebraic and differential equations. The next step in transient stability studies is to create the disturbance and then solve asset of algebraic and differential equations of the power system to obtain system conditions during and immediately after disturbances. Transient stability analysis actually combines the solution of network (algebraic) equations with machine dynamics (differential) equations. The solution of swing equation is done by modified Eulers method. A flow chart based on modified Euler method developed and computer programming in c language written and implemented to solve the transient stability problem. The flow Chart is shown in Fig 3.
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Fig. 3 Flow chart developed for analysis
The variation in fault clearing time and its effect on the stability of system also solved. When the system became unstable due to increase in fault clearing time, the unstable system was brought into stable condition by insertion of capacitor in circuit with the transmission line. As we know, insertion of capacitor reduces the effective line reactance, the system became stable. The various levels of compensations applied in the system. In different cases, controlling of capacitor also implemented based on increment in , and P. The reduction in compensation level in a particular case was solved. This is the same case as TSSC, Where a bank of capacitor is removed in sequential manner, finally left with transmission line reactance only. In one of the cases, switching on and off of capacitor also implemented. This is same as the case of GCSC. In all the cases, unstable system was made stable [1]. A. Test Problem Based on flow chart given in Fig3, a computer programming developed to solve the stability problem. For this purpose a single generator connected to infinite bus is taken for the study. The fault is assumed to be near sending end and the installation of compensator is near the starting of transmission line. The fault is three phase short circuit (bolted fault). The test problem parameters are shown in table I
TABLE I TEST PROBLEM PARAMETERS Synchronous machine Infinite bus H=4.0 p.u, F=50.0 Hz, Xd=0.2p.u, P=1p.u, Q=0.75p.u, PL=0.0p.u, QL=0.0 p.u, Pm=1.0p.u E=1.0 p.u, =0.0, PL=0.0p.u, QL=0.0 p.u, Line reactance Xpq=0.08p.u
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B. Transient stability analysis and results The transient stability analysis done for the under mentioned cases:1) Case 1: Analysis with varying fault-clearing time, Tfc (uncompensated) i). Tfc = 0.2 sec The fault is cleared in 0.2 sec. The system is stable one. The increases as time increases, reaches up to max= 73.9337 degrees and then starts decreases. ii). Tfc =0.28 sec The fault clearing time is increased to 0.28 sec. The system is stable. The value of increases and reaches to a new max = 131.5976 degrees. Afterwards starts decreasing. iii). Tfc =0.29 sec. The fault clearing time is now increased to 0.29sec. The system is still under stable condition. But increases to max= 132.2666, still the afterwards starts decreasing. iv). Tfc =0.3 sec Now the fault clearing time is increased to 0.3 sec. The system becomes unstable. The value of keeps on increasing, it does not come down. This shows that 0.29 sec is the critical clearing time for the system. v). Comparison of results of different fault clearing timeThe combined curves are plotted for varying fault-clearing time. From the curves, it is clear that as we keep on increasing Tfc, the max increases until it reaches cc (critical clearing angle). After which the system becomes unstable. The cc is found to be 132.2666. The in case of Tfc =0.3 is always increasing. The of other Tfc are found to be stable. The graphs for other Tfc are appearing to be stable. The variation in at varying fault clearing time is shown in Fig 4.
In this case the capacitor is left permanently in the circuit on reclosing of the line. The value of Xc, capacitive reactance depends upon the degree of compensation. i). 25% compensation Analysis using different compensation level The capacitor is left permanently in the circuit on reclosing of line. The value of capacitive reactance is varied in different cases i.e. compensation level is varied. The ill effect of leaving capacitor permanently in the circuit is not discussed in the study. The impedance type series compensation is studied here. ii). 25% compensation The value of capacitive reactance (Xc) is taken as 0.02 i.e. K=0.25 where K is given by K=Xc/XL The effect of this compensation is that the system becomes stable. The max increases to a new higher value i.e. transient stability limit is increased. The value of max is found to be 157.8929.. iii). 50% compensation The value of capacitive reactance is taken as 0.04 i.e Xc=0.04, then k=50%. The max is less than the previous one, when the compensation level was lower. The max is found to be 149.5456. iv). 75% compensation As we keep on increasing the compensation level, the max decreases. The value of Xc = 0.06 is taken in this case. i.e. k=75%. The max is found to be 144.098. Which is less than the max when lower levels of compensations were applied. v). Variable compensation Starting from high level of compensation, bringing down to zero level of compensation:The same Tfc =0.3 sec is considered. The line is reclosed with series capacitor. Initially high level i.e. 75% compensation is applied from 0.3 to 0.4 sec, then 50% from 0.4 to 0.5 sec and 25% from 0.5 to 0.6 sec. Finally no compensation is applied afterwards. The total capacitor banks are bypassed. The transmission line is left with line reactance only. vi). Comparison between various levels of compensation The various cases in case2 have been compared and plotted in Fig5. It is evident from the curve that higher the value of compensation, lower is the max. The speed of the m/c is comparatively higher when higher level of compensation is applied. With 25% compensation the speed is around 290-330 rad/sec. The recommended level of compensation should be lower.
Fig. 4 Variation of with varying fault clearing time.
2) Case 2 : Analysis using series compensator The unstable system is made stable by using series compensator. The various compensation conditions are implemented viz.
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IV.
CONCLUSION
Fig. 5 Variation in with varying levels of compensation.
3) Case 3 Analysis based on controlling of series compensator In this case, the line is reclosed at 0.3 sec. Afterwards, the capacitors are inserted and bypassed depending upon the conditions mentioned below. The value of capacitive reactance is taken as 0.02 (i.e. 25% compensation) i). On basis In this case whenever 0, the capacitor is inserted. When <0, it is bypassed. It is seen from the Fig 6, the system is unstable. ii). On basis In this case whenever 0, the capacitor is inserted. When the <0, it is bypassed. iii). On P basis In this case whenever P0, the capacitor is inserted, whereas whenever P<0, it is bypassed. iv). Comparison of results of various controlling system The various curves have been plotted in Fig 6. From the fig 6, it is clear that the speed of the machine under controlling goes higher but comes down. The under keeps on increasing making the system unstable. The controlling under and P seems to better than . The best controlling is under basis. Here the max is comparatively less. The value of max under , P are 157.8929 and 164.8634 respectively.
In this chapter the system is subjected to various conditions. The effect of varying Tfc has been reflected. The critical fault clearing time is found to be 0.29 sec. The critical clearing angle is found to be 132.2666 degree. The CBs must be designed to operate well before 0.29 sec. The system becomes unstable on delaying Tfc. The system becomes unstable when Tfc increases to 0.3 sec. The use of series compensator brings down the system to stable condition even at Tfc =0.3 sec. With higher level of compensation the speed of the machine increases though the max comes down. The higher level of compensation has other adverse effect on the system like sub synchronous resonance. The ultimate purpose to control the first swing of the vs. time curve is even achieved with 25% compensation. Therefore lower level of compensation is always recommended. V. REFERENCES
[1]. Kamala Kant Mishra, Transient stability analysis of power system using series compensator, ME dissertation, Panjab University,2003 [2]. Narain G. Hingorani, Laszlo Gyugyi Understanding FACTS: Concepts and Technology of Flexible AC Transmission Systems, December 1999, Wiley-IEEE Press. [3]. Sen KK; Static Synchronous Series Compensator-theory, modeling and application, IEEE PWRD-13, No1, Jan 1998.
Fig. 6 Variation in with various controlling systems.
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Unity-Power-Factor Operation Based On Boost Active Clamp Topology

S.Bharath1, R.Vibin2
of 50 KHz. The power rating of each module is 500 W. The circuit configuration, operation, analysis, and design considerations of the proposed converter are presented. Finally simulation and experimental results obtained with the prototype are presented to demonstrate the performance and design considerations. Similar to a three-phase active rectifier, the output voltage has a dominant ripple of six times the line frequency. Thus, a smaller output filter capacitor is required. It also works under unbalanced input ac voltage maintaining almost unity power factor at the input. As a separate PFCPWM controller is provided for each module, the independent control is facilitated even under unbalanced input voltages. The PFC-PWM controllers are not very costly; therefore, increase in the cost is marginal. Reliability in term of availability of output power to some extent in case of failure of a module or single phasing is also achieved. The proposed converter KEY WORDS Active clamp, boost converter, three- maintains an input power-factor almost unity, regulated output voltage, and ZVS for all the switches even under variable load phase acdc converter, unity power factor. conditions. It has only two switches in each module, and has lesser components and lesser complexity compared. The I. INTRODUCTION proposed converter has applications such as drives, power Power electronic converters usages are increasing in the conditioning stages of UPSs, etc.. processing of electrical energy in industrial applications. Therefore, the converters with high power factor are II. DC-DC CONVERTER increasingly required in industries. In high-power range, mainly a three-phase system is employed. Most of the PE DC-DC converters are electronic devices used whenever we systems which get connected to ac utility mains use diode want to change DC electrical power efficiently from one rectifiers at the input. The nonlinear nature of diode rectifiers voltage level to another. They are needed because unlike AC, causes significant line current harmonic generation; thus, they DC cant simply be stepped up or down using a transformer. In degrade power quality, increase losses, failure of some crucial any ways, a DC-DC converter is the DC equivalent of a medic equipment, and so on. Therefore, stringent international transformer. harmonic standards are imposed, and hence power factor There are many different types of DC-DC converter, There are four main types of converter namely the buck, boost, and correction circuits are incorporated in PE systems. In this paper, a three-phase acdc converter with input buck-boost converters power factor almost unity and soft-switching topology in modular approach is presented. An identical single-phase boost Review of present power factor correction techniques type active clamped acdc converter is connected in each line of a three-phase AC source. Outputs of all the three converter Among three basic power converter topologies (boost, buck modules are connected in parallel to raise the power level. and buck-boost), the boost converter shown in Fig .1 is the one Each single-phase module is operated from 115-V, 50-Hz input most suitable for power factor correction applications. This is because the inductor is in series with the line input terminal to give regulated output of 500 V with a switching frequency through the diode rectifier, which gives lower line current 1 ripple and continuous input current can be obtained with an S.Bharath, PG Scholar, bharathbhadri@gmail.com 2 R.Vibin, PG Scholar, vibin.086@gmail.com average current mode control chip like UC3854. As a result, a small line input filter can be used. Furthermore, the power switch is in shunt with the main power flow so that the converter operates efficiently. However, the output voltage has to be higher than the line input 3 voltage for a boost converter. The buck converter is seldom used as a power factor correction ABSTRACT In this paper, a three-phase acdc converter using three singlephase pulse width modulated active clamped, zero-voltageswitched boost converter in modular approach is presented. The active clamp technique is used for zero-voltage switching of the main and auxiliary switches. The operating modes, analysis, and design considerations for the proposed converter are explained. To evaluate the performance of the proposed converter, finally simulation and experimental results for a 500-V, 1.5-kW prototype converter are presented. The proposed converter operates at almost unity power factor with reduced output filter size. The output voltage is regulated without affecting zero-voltage-switching, even under unbalanced three-phase input voltages.
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III. CIRCUIT DESCRIPTION application since the input current is discontinuous and it loses control when the line input voltage is lower than the output voltage. The buck-boost and flyback converters are able to Fig. 2 shows simplified block-diagram of a three-phase acdc control the average line input current.However, the power converter in a modular system. handling capability is smaller because of its higher voltage and current stresses. Therefore, the boost converter is currently the most popular PFC topology. To achieve unity power factor, the input power is the squared sine waveform while the output power is usually constant for most applications. Thus, the power is unbalanced between the input and the output over half the line cycle. This unbalanced power has to be stored in an energy storage element, like the bulk capacitor. For a boost converter, the output filter capacitor, which is the only bulk capacitor, can deal with this unbalanced power. Therefore, the output voltage has 2nd order line ripple, which is undesirable for many applications. Furthermore, the output voltage is higher than the input
Fig. 2:Three phase modular converter system Fig. 3 shows circuit diagram of the proposed single-phase module. The proposed converter consist of a small line filter
Fig 1:Power Factor correction Boost Converter
The output voltage is therefore higher than the input voltage, and it turns out that the voltage step-up ratio is equal to: Vout/Vin = 1/(1-D) where 1-D is actually the proportion of the switching cycle that Q1 is off, rather than on. So the step-up ratio is also equal to: Vout/Vin = T/Toff If we assume that the converter is 100% efficient the ratio of output current to input current is just the reciprocal of the voltage ratio: Iin/Iout = Vout/Vin So if we step up the voltage by a factor of 2, the input current will be twice the output current. Of course in a real converter with losses, it will be higher again.
Fig. 3: Single Phase Module of the Proposed Converter comprising of Lf and Cf and followed by single-phase line rectifier (D1 - D4) and a very small high-frequency bypass capacitor Cin . Unlike the conventional boost converter, in addition to the boost inductor Lb and the high-frequency (HF) rectifier output diode D; the resonant inductor Lr in series and resonant capacitor Cr in parallel are connected to the main switch Sm . The auxiliary switch Sa with series connected clamping capacitor Cc is connected between the drain of the Sm and the cathode of the D . The small capacitor Cn is used as a high-frequency bypass filter at the output of each module. Both the switches are driven in a complementary manner. The single output filter capacitor Co is used at the output of the proposed three-phase converter whose size get reduced drastically owing to the fact that, like the three-phase active rectifier, the dominant ripple frequency is six times the input source frequency. By sensing boost inductor current, output dc and input ac voltages, gating pulses are generated accordingly using PFCPWM IC (UC3854) and fed to Driver IC (UC3706). Drive IC
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body diode of the main switch starts conducting, and the output diode continues conduction. During this mode, the boost inductor current continues to decrease and the output diode current also starts decreasing. The negative resonant inductor current continues to decrease. This mode ends when it decreases to zero, and the body diode of the main switch ceases to conduct. To turn-on the main switch with ZVS, a gate pulse must be applied during this interval. Mode 2 : Fig. 4(b) shows the operating state of the circuit during this interval. At , the main switch turns on and starts carrying the positive resonant inductor current .Thus, ZVS of switch is achieved. The boost inductor current continues to decrease. This mode ends when output diode current becomes zero
provides complementary gate drive pulses with sufficient dead band. A PCB-mounted miniature current LEM is used for sensing the boost inductor current. When boost inductor current exceeds the set limit, drive pulses are disabled, hence the converter is protected. Proposed converter uses average current mode control. In average current mode control, boost inductor current is continuously monitored and controlled to follow the reference signal proportional to ac line voltage. Thus, input current is sinusoidal. To regulate output voltage, a multiplier circuit controls the amplitude of the sinusoidal current reference signal in accordance with the voltage error signal generated using the output voltage and rectified input ac voltage. When the load decreases, the output voltage increases. To maintain constant load voltage, the control circuit senses the load voltage and the pulse width is automatically reduced in the switching cycle and the output voltage is regulated and maintained almost constant. The control circuit varies the duty ratio in switching cycles over the input supply voltage cycle, as the instantaneous input supply voltage is varying over the cycle. IV. OPERATING PRINCIPLE
To simplify the analysis and operating modes of the circuit, the following assumptions are made. The semiconductor devices, inductors, and capacitors are ideal. The output filter capacitor Co is large enough to maintain constant output voltage Vo . The rectified output voltage Vin is constant over one switching cycle as switching frequency is very high compared to ac input frequency. The boost inductor Lb is much larger than Lr; and clamping capacitor Cc is much larger than capacitor Cr. The energy stored in Lr is larger than energy stored in Cr. Mode 3 :
Mode-2 Fig. 4(b)
The circuit behavior during one switching cycle can be During this mode, the main switch continues to conduct as explained in seven modes. shown in Fig. 4(c). A load is supplied by the output filter capacitor . Input power is stored in boost inductor and resonant Mode 1 : inductor . Therefore, the boost inductor current starts increasing. The resonant inductor current continues to increase. This mode ends when the main switch is turned off
Mode-1 Fig. 4(a) Fig. 4(a) shows the operating state of the circuit during this interval. The auxiliary switch is already in an off-state. The
Mode-3 Fig. 4(c)
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this interval, a gate pulse must be applied to auxiliary switch in order to achieve ZVS.
Mode 4 :
As shown in Fig. 4(d), the current, which was flowing through the main switch, is diverted to resonant capacitor . The voltage Mode 6 : As shown in Fig. 4(f), the auxiliary switch starts conducting. Thus, ZVS of switch is achieved. The boost inductor current continues to decrease. This mode ends when the auxiliary switch is turned off.
Mode-4 Fig. 4(d) across the main switch starts increasing from zero, and when it reaches , this mode ends. As soon as the main switch voltage reaches approximately equal to , the output diode starts conducting. The body diode of the auxiliary switch starts conducting only after the main switch voltage reaches . Since Mode 7 : the interval between the start of conduction of the diode and the start of conduction of the body diode of auxiliary switch is very small compared to switching cycle, this is not treated as a separate mode. Actually, current through continues until the body diode of the auxiliary switch starts conducting. Mode 5 : Fig. 4(e) shows the operating state of the circuit during this interval. The boost inductor current starts decreasing. The output diode continues conducting, and its current starts increasing. If clamping capacitor is large, then clamping capacitor voltage is almost constant, and inductor current decreases linearly, otherwise varies resonantly. This mode ends Mode-6 Fig. 4(f)
Mode-7 Fig. 4(g) Fig. 4(g) shows the operating state of the circuit during this interval. The boost inductor current continues to decrease. The voltage continues to decrease due to negative inductor current . When becomes zero, the body diode of the main switch starts conducting and this mode ends. The resonant inductor and the resonant capacitor form a resonance circuit. To achieve ZVS of the main switch , must reach zero at the end of this mode.
V.
SIMULATION
The digital computer simulation of the electrical circuit provides useful results that are used to predetermine the performance of the proposed electrical circuit. The proposed Mode-5 control method are simulated on a digital computer using Fig. 4(e) matlab7.0 Simulink Simpower system toolbox. The converter shown in Figs. 2 and 3 is simulated. The when the resonant inductor current becomes zero. Thus, the converter behavior is studied under unbalanced input voltages. body diode of the auxiliary switch ceases to conduct. During The components values are
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5.2 SIMULATION RESULT
INPUT VOLTAGE WAVEFORMS
and other specifications of the single-phase module of the proposed converter are as follows. Specifications: Input voltage: 115 V, 50 Hz. Output voltage: 500 V. Output power: 500 W. Total output power W. Switching frequency: 50 kHz. 5.1 SIMULATION CONVERTER DIAGRAM FOR PROPOSED
OUTPUT VOLTAGE WAVEFORM
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[9] J. A. Cobos, O. Garcia, J. Uceda, J. Sebastian, and E. Cruz, Comparison of high efficiency low output voltage forward High power quality three-phase acdc converters are being topologies, in Proc. IEEE PESC, 1994, pp. 887894. widely used in the industries. In this paper, a three-phase acdc converter using three single-phase modules adopting active [10] M. M. Jovanovic, A technique for reducing rectifier clamped boost topology has been presented. The operating reverse recovery related losses in high power boost converter, modes, analysis of the circuit, and design considerations are IEEE Trans. Power Electron., vol. 13, no. 5, pp. 932941, Sep. explained. The simulation and experimental results on 1998. laboratory prototype (500 V, 1.5 kW) are presented. The experimental results are in good agreement with simulation [11] R. Ayyanar, R. Giri, and N. Mohan, Active input voltage results. The proposed converter has smaller output filter and load current sharing in input-series and output parallel capacitor and lesser component count as compared to other connected modular dc-dc converter using dynamic inputtopologies. It operates at almost unity power factor, low THD, voltage reference scheme, IEEE Trans. Power Electron., vol. and high efficiency. In addition, it maintains unity power factor 19, no. 6, pp. 14621473, Nov. 2004. and regulated output voltage with ZVS over the wide range of [12] C. S. Moo, H. L. Cheng, and P. H. Lin, Parallel operation the load even-with unbalanced input voltages. of modular power factor correction circuits, IEEE Trans. Power Electron., vol. 17, no. 3, pp. 398404, May 2002. VI. CONCLUSION [13] M. L. Heldwein, A. Ferrari de Souza, and I. Barbi, A [1] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. simple control strategy applied to three-phase rectifier units for Pandey, and D. . Kothari, A review of three-phase improved telecommunication applications using single-phase rectifier power quality acdc converters, IEEE Trans. Ind. Electron., modules, in Proc. IEEE PESC 99, pp. 795800. vol. 51, no. 3, pp. 641660, Jun. 2004. [14] G. Spiazzi and F. C. Lee, Implementation of single-phase [2] B. M. Saied and H. I. Zynal, Minimizing current distortion boost power-factor correction circuits in three-phase of a threephase bridge rectifier based on line injection applications, IEEE Trans. Ind. Electron., vol. 44, no. 3, pp. echnique, IEEE Trans. Power Electron., vol. 21, no. 6, pp. 365371, Jun. 1997. 17541761, Nov. 2006. [15] M. A. Chaudhari and H. M. Suryawanshi, High power [3] M. R. Ramteke, H. M. Suryawanshi, and K. L. Thakre, factor operation of three-phase ac-to-dc resonant converter, Single-phase resonant converter in three-phase system in IEE Proc. Elect. Power Appl., vol. 153, pp. 873882, modular approach, EPE J., vol. 16, no. 4, pp. 513, Dec. Nov./Dec. 2006. 2006. [16] H. Bodur and A. F. Bakan, A new ZVT-PWM dc-dc [4] A. K. S. Bhat and R. L. Zheng, Analysis and design of a converter, IEEE Trans. Power Electron., vol. 17, no. 1, pp. three-phase LCC-type resonant converter, IEEE Trans. 4047, Jan. 2002. Aerospace Electron. Syst., vol. 34, no. 1, pp. 508518, Apr. 1998. [17] M. M. Jovanovic and Y. Jang, State-of-the-art, singlephase, active power-factor correction techniques for high[5] S. S. Tanavade, H. M. Suryawanshi, and K. L. Thakre, power applications-an overview, IEEE Trans. Ind. Electron., Novel single-phase ac-to-dc convertor using three-phase vol. 52, no. 3, pp. 701708, Jun. 2005. modified series-parallel resonant converter, IEE Proc. Elect. Power Appl., vol. 152, pp. 10271035, Jul. 2005. [6] R. L. Steigerwald, A comparison of half bridge resonant converter topologies, IEEE Trans. Power Electron., vol. 3, no. 2, pp. 174182, Apr. 1988. [7] T.-F. Wu and S.-A. Liang, A systematic approach to developing single-stage soft switching PWM converters, IEEE Trans. Power Electron., vol. 16, no. 5, pp. 581593, Sep.. 2001. [8] R. Watson, F. C. Lee, and G. C. Hua, Utilization of an active clamp circuit to achieve soft switching in flyback converters, IEEE Trans. Power Electron., vol. 11, no. 1, pp. 162169, Jan. 1996. REFERENCES
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ZVS BASED HIGH-EFFICIENT HALF-BRIDGE CONVERTER

1
S.SUBRAMANIAN
T.SUGANTHI 2.Ms. T.SUGANTHI, M.E., Asst.Prof./ EEE, Roever Engg. College, Perambalur.
1. S.SUBRAMANIAN II Yr ME., Roever Engg. College, Perambalur. Subramanian.kiruba@gmail.com Contact: 9789247215 ABSTRACT
A new ZVS Based High-Efficient HalfBridge Converter is proposed. The proposed converter regulates the output voltage by adjusting applied voltage to the main transformer with an auxiliary circuit while main switches are operated at both fixed duty ratio and switching frequency. Therefore, no magnetizing dc offset current exists on the main transformer and all switches can be operated with zero voltage switching condition. Furthermore, multilevel voltage shown at the output filter reduces the output inductance significantly. To verify these features of the proposed circuit, operational principle and experimental results will be presented with the prototype. The proposed converter has lower conduction loss and requires smaller filter inductance than the conventional asymmetric half-bridge converter. Half-bridge converter, no magnetizing dc offset current, zero voltage switching (ZVS).
Keywords:
of its electricity consumption growth and cooling cost increase. Especially, the necessity of a high-efficient server power system is emphasized in the medium power supplies. For this purpose, several techniques have been proposed to reduce the switching losses and component stresses. 1.1 EXISTING SYSTEM PROBLEMS Among the proposed techniques, the conventional phase-shifted full-bridge (PSFB) converter, the active-clamp forward converter, and the asymmetric control half-bridge converter are chosen as promising candidates for their zero voltage switching (ZVS) operation, relatively lower current stress and simple configuration. However, the usage of the PSFB converter is limited to medium power supplies since it adopts large number of main switches on the primary side. The PSFB converter increases the cost and decreases the power density of the converter. The active clamp forward converter has simple structure, but it is also suffered from high-voltage rating of the main switch. 1.2 PROPOSED SYSTEM In order to overcome all these drawbacks, a new high-efficient half-bridge converter is
1. INTRODUCTION The efficiency problem in server power supplies has become an important issue because
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proposed. The proposed converter employs an auxiliary circuit for the output regulation. The auxiliary circuit supplies additional voltage to the main transformer when input voltage decreases. Thus, the main switches can be operated at 50% duty ratio and fixed switching frequency. Since the main switches are always operated at 50% duty ratio, their ZVS operation is easily achieved, and the transformer is effectively utilized with no dc offset of the magnetizing current. Moreover, the ZVS operation of the auxiliary switch is easily realized by output inductor energy, and the doubled switching frequency shown at the output filter reduces the output ripple current significantly. 2.CIRCUIT DIAGRAM
composed of an auxiliary transformer (T2) and two auxiliary switches (S1 and S2). The main switches are always operated at 50% duty ratio, while the output voltage is regulated by controlling the phase differences. Deff between the main switches and auxiliary switches. When the input voltage decreases, Deff is extended and additional voltage is increased to compensate the decreased input voltage. As the auxiliary circuit is used only for the regulation, the magnetic size of the auxiliary transformer is much smaller than that of the main transformer, and the core loss in the auxiliary transformer is negligible at nominal operating condition. The current which flows into the auxiliary circuit is also low. The voltage applied to the Main Transformer is decreased in proportion with the turn ratio of the auxiliary transformer, thus the current rating of the auxiliary switches is much smaller than that of the main switches. In addition, the symmetric operation of the proposed converter makes the primary current be optimized on the conduction loss and increases the utilization of the transformers. 3. PRINCIPLE OF OPERATION For the convenience of the mode analysis in steady state, several assumptions are made as follows. The switches M1, M2, S1, and S2 are ideal components except for their output capacitors and body diodes. The capacitors C1 and C2 are large enough to be considered as constant voltage sources, (1/2)Vin Turn ratio of the main transformer (T1) is n1 = NP1/NS1and n2 = NP2 /NS2 for the auxiliary transformer (T2 ).
Cs C1 Llkg
S1 Dm1 Np2 Ip2
M1
Vdc
C2
Np1
Ns2
Cs
S2 Dm2
M2
D1
Lo Co
Vo
D2
Figure 2.1 Schematic Diagram of the Proposed Converter 2.1 CIRCUIT DIAGRAM DESCRIPTION Fig. 2.2 shows a circuit diagram of the proposed dc/dc converter. It is based on the conventional half-bridge converter, and the auxiliary circuit is employed on the primary side of the converter. The auxiliary circuit is
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The primary current is constant during the very short period;t1t2 , t2t3, and t4t5 . The output inductor Lo is operated in constant conduction mode. Each switching cycle can be divided into two half cycles t0t8 and t8t16. Because of symmetry, only the first-half cycle is explained and the operating waveforms for the proposed converter. 4. MODE OF OPERATION Mode 1 (t0t1): When commutation is completed at t0, mode 1begins. In this mode, extra voltage is added to the nominal main transformer voltage for the regulation of the converter. Vin and Thus, the input capacitor voltage 2 reflected auxiliary transformer voltage, VS(2) are applied to the main transformer. The primary current increases linearly in this mode with the slope of
Vin 2 + n Vs
1
Mode 4 (t3t4): When the auxiliary switch S2 is turned on at time t3, mode 4 begins. Since the output capacitor of S2 is completely discharged in the previous mode, it is turned ON under ZVS condition. The primary current decreases following the output inductor current in this mode. The primary current ipri is expressed as follows. ipri(1)(t)= 1
io (t) =
io ( t ) n1
-------(1)
(Vs(1) Vo) (t to) + ipri(1)(t 3) n1(Vs(1) )(Vo)

Lo
- - - - - - - - - - - - - - - - (2)
(2 )
Vo
Lo
Mode 2 (t1t2 ): When S1 is turned off at t1 , mode 2 begins. The output capacitors of the auxiliary switches CS1 and CS2 are charged and discharged, respectively, in a resonant manner. Since the large output inductor energy is participated in this resonance, the ZVS condition of S1 and S2 are easily realized. Mode 3 (t2t3 ): After the auxiliary switch S2 is completely discharged, the current of the auxiliary circuit ipri(2) flows through the body diode of S2. Thus, the voltage of S2 is sustained at 0 V, and the applied voltage to the main transformer remains at Vin
2
Mode 5 (t4t5 ): The main switch M2 is turn off at the beginning of this mode. The voltage of the output capacitor CM2 is linearly charged from 0V, and the voltage of CM1 is linearly discharged from Vin at the same time by utilizing the large output inductance energy. This mode continues until the time when the primary voltage of the transformer reaches to 0 V. Mode 6 (t5t6 ): When the main transformer voltage Vpri(1) is decreased to 0 V, the voltage of main-switch M2 increases in manner of resonance between Llkg and CM1 + CM2. The voltage of M2 and the primary current are expressed as follows Vcm 2 (t) =
i pri sin
(1 )
1 i pri n2
M
(1 )
(t 5)
L lkg 1 + C
M 2
M 2
L lkg 1 + C
M 2
t + VC
(t 5)
------
(3)
L lkg t CM 1 CM 2
ipri(1)(t) = ipri (1)( t 5) cos
---(4)
On the secondary side, both the rectifier diodes start to conduct and commutation of the two diodes D1 and D2 begin. This mode ends when voltage of the switch M1 discharges to 0 V.
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Mode 7 (t6t7): In mode 7, the primary current flows through the body diode of the main switch, M1. As the main transformer is regarded as short circuit, all voltages are applied to the leakage inductance and the primary current is sharply decreased. The primary current is expressed as ipri(1)(t ) 1 1 Vin + Vin 2 n2 (t t 6 ) + ipri (1)(t 6) - - - (5) = Llkg Mode 8 (t7t8): When the main switch M1 is turned on at t7,this mode begins. The primary current, that was flowing though the body diode of M1 in the previous mode changes the path to the channel of switch M1 . The primary current in this mode is expressed the same as that of the previous equation (4). This mode continues until following condition is satisfied: n1 ipri(1)(t) = iLo(t). - - -(6)
the proposed converter. Therefore, the transformer is fully utilized and it increases the power density of the system. However, the dc offset current in the magnetizing inductor is varied with the duty ratio in the asymmetric half-bridge converter. Thus, the utilization of the transformer is severely deteriorated in the asymmetric half-bridge converter. The dc offset current for the proposed converter and for the asymmetric half-bridge converter is expressed as follows: I0 I0 Deff ILm + = Deff ILm + n1 n1 ILm proposed = 0 ILm conventional = (1 2 D )
ns I0 np
6. ZVS Condition The ZVS conditions of the auxiliary switches in the proposed converter are well achieved because the output capacitors of the auxiliary switches are discharged by utilizing the large energy stored in the output inductance. For the main switches M1 and M2 , the auxiliary transformer helps increase its ZVS range. It is because the energy stored in the leakage inductance of the auxiliary transformer has also participated in the ZVS operation with the energy stored in the leakage inductance of the main transformer. Hence, the ZVS range can be extended with the leakage inductance of the auxiliary transformer. As the turn ratio of the auxiliary transformer increases, the required leakage inductance for ZVS operation is decreased. Therefore, the ZVS range in the proposed converter can be extended by increasing the turn ratio of the auxiliary transformer turn ratio. Also the auxiliary leakage inductance can be added in the proposed converter to achieve ZVS operation in
Figure 4.1 Operating waveforms of the proposed converter. 5. DC Offset Current in Magnetizing Inductor Since the switches of the proposed converter are controlled symmetrically, the dc offset of the magnetizing current can be easily eliminated in
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more extended load range. The condition to realize the ZVS operation in the proposed converter is presented in (7). 12(2COSS) _VS 0.5 VS /_1 +1n2__2 12Llkg i2pri(1) ------ (7) Where COSS is output capacitor of main switches. However, the ZVS condition of the asymmetric half-bridge converter is heavily depended on its dc offset of magnetizing current. Due to the offset current, the two switches in the same leg have different ZVS condition. The ZVS range of one switch is increased, but the range is decreased to the other switch in the same leg. Thus, to achieve safe ZVS condition in both switches, following condition (7a) must be satisfied. 12(2COSS)_12VS_2 12Llkg (ipri ILm)2 ---(7a)
Figure 7.1 Applied voltages on transformers
7. Design consideration There are two main factors that must be considered for the selection of turn ratio of the transformers in the proposed converter. These are the voltage regulation condition and the loss at the auxiliary circuit. In the proposed converter, the main transformer is always operated with its maximum duty ratio and output voltage is regulated by controlling the effective duty ratio of the auxiliary circuit. When the input voltage decreases, the auxiliary circuit supplies additional voltage to the main transformer for the compensation of the input voltage. Therefore, to satisfy the regulation condition, the voltage supplied by the auxiliary transformer must be able to increase as much as maximum input differences. This condition is expressed as follows: Dnom < Deff ,max < 0.5 (at, Vin,min) 0 < Deff ,min < Dnom (at, Vin,max) Figure 7.2 Range of the transformer turn ratio
Figure 7.3 Efficiency comparisons.
8.Simulation
The proposed converter is simulated by using the MATLAB software, simulted diagram and its gate pulse, output waveform are givenbelow.
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conduction loss and requires smaller filter inductance than the asymmetric half-bridge converter. Also, it achieves good ZVS condition, and its symmetrical operation characteristic balances the voltage/current stresses on its components and eliminates the dc offset of magnetizing current. Therefore, the proposed converter can be selected as a good candidate in middle power server system. Figure8.1 Simulation Diagram of the Proposed Converter REFERENCES
1) High-Efficient Multilevel Half-Bridge Converter In-Ho Cho, Student Member, IEEE, Kang-Hyun Yi, Member, IEEE, KyuMin Cho, Member, IEEE, and Gun-Woo Moon, Member, IEEE 2) C. Calwell, A. Mansoor, E. Consulting, and C. O. Durango, AC-DC server power supplies: Making the leap to higher efficiency, in Proc. Appl. Power Electron. Conf. Expo., 2005, pp. 155158. 3) J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, Design considerations for high-voltage high-power full-bridge zero-voltage switched PWM converter, in Proc. Appl. Power Electron. Conf. Expo.,1990, pp. 275284. 4) X.Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian, Soft switched full bridge DC-DC converter with reduced circulating loss and filter requirement,IEEE Trans. Power Electron., vol. 22, no. 5, pp. 19491955, Sep. 2007. 5) Y. Zhu and B. Lehman, Three-level switching cell for low voltage/highcurrent DC-DC converters, IEEE Trans. Power Electron., vol. 22, no. 5,pp. 19972007, Sep. 2007. 6) X. Ruan, Z. Chen, and W. Chen, Zerovoltage-switching PWM hybrid full-bridge three-level converter, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 395404, Mar. 2005. ------------------------------------
Figure8.2 Gate pulse wave of the switching device
Figure8.3 12Volt DC output wave 9.CONCLUSION A new ZVS based high-efficient half-bridge converter is presented and analyzed. By employing one small sub transformer and two small additional switches, the proposed converter shows better performance than the asymmetric half-bridge converter in entire load range. The proposed converter has lower
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Modeling and Simulation of 3 phase Induction Motor under dynamic load conditions
1
Snehaprabha T V 1 , Suresh Kumar P 2, Dr. Sanjay L1
Associate Professor, E&E Department, M.S.R.I.T, Bangalore 2 Former R&D Director, Hewlett-Packard, Bangalore order to understand and analyze vector control, the dynamic model of the induction motor is necessary. It is the objective of the article to derive and explain induction motor model in relatively simple terms by using the concept of space vectors and d-q variables. II. MOTOR PERFORMANCE AND EQUIVALENT CIRCUITS FOR MODELING Fig.1 shows the complete torque characteristics of an induction motor, which includes motoring, generating and braking. At standstill the slip(S) equals unity. At this point the torque produced is known as standstill (starting) torque -Tstart. To accelerate a load this standstill torque has to be greater than the load torque-TL
Abstract- Induction motors are becoming more and more of a favorite choice for applications in all segments of the industry due to its relatively lower cost, simplicity and rugged structure, thus making this as the general purpose machine for all types of drives. This has mandated a designer to understand its dynamic behavior before choosing for an application, as application oriented dynamic specification is quite difficult to get from a manufacturer. A dynamic simulation can more or less answer many of the design questions, and become quite handy to study the suitability of the machine for the targeted application from its fundamental specifications. Such an understanding is crucial for developing appropriate control techniques and for their implementations, including vector controlled drives of various kinds. Keeping this need in mind, dynamic simulation and analysis of 3 phase induction motor is presented in this paper. The two-axis model and the necessary equations are derived with respect to stationary reference frame. Steady state performance and responses to external input variations of the motor are analyzed using Simulink. A typical set of parameters is chosen using a lab test and the model is validated for some of the performance characteristics. This study focuses on the steady state operations and free acceleration under varying load conditions at rated stator voltages. This model can be easily extended for transient analysis also. Keywords- Induction Motor, Dynamic model, Simulink, Optimal Delay region, motoring performance
Fig.1 Induction Motor Torque- speed characteristic
I. INTRODUCTION AC motors are very economical, rugged and reliable due to the absence of commutators and brushes, but have inherently poor dynamic behavior. However, the dynamic behavior can be made to match that of an equivalent separately excited DC motor using Field Orientated or Vector Control [6,7,8,10 ]. This paper gives a preliminary study on dynamic model & its performance characteristics. Initially, the emphasis of this paper will be on the DQ model of the machine and its transformation equations. For developing the model stator reference frame is chosen. Flux linkage equations represented in state space can also be used for modeling. [1,2] The Steady-state model and equivalent circuit developed are useful for studying the performance of the machine in steady state. This implies that all electrical transients are neglected during load changes and stator frequency variations. The dynamic model considers the instantaneous effects of varying voltages/currents, stator frequency and torque disturbance. In
This study focuses on the motoring region. Specific points of interest on the motoring region are shown in Fig.2.
Fig.2 Motoring Torque characteristics of IM
The acceleration torque (Tacc) is defined as the entire range of the torque characteristic from start to no-load speed. The load torque should be maintained less than the induction motor
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developed torque during the entire acceleration phase. A standard motor must be able to deliver the rated torque in continuous operation without exceeding its temperature. According to standards the maximum torque must be >= 1.6 times rated torque. It must be possible to overload the motor for at least 15 seconds with this value at rated voltage and frequency. The operating point can rise above the rated value only for a short time to avoid overheating. Torque and speed of the motor are related by the equation (1) below, which is used for analyzing the performance under dynamic load conditions.
Fig.3 Equivalent circuit of IM
2 d Td = TL + J r (1) P dt
where Td is the motors developed torque. From the above Fig.2 , one can see that Tacc is contributed by the second term in the Eq(1) where P is the number of poles of the machine, and J is the moment of inertia & r motor speed in elec rad/sec . Since Torque is also calculated by dividing the Power by the instantaneous angular speed (Pm=Td.m) where
= r
III. DYNAMIC MODEL IM model is derived by using the concept of space vectors and 2 axis variables. Dynamic model can be obtained from different reference frame platform .Reference frames are very much like observer platforms.
m
Fig.4 Three phase to Two phase transformation
/(P/2), Td can also be expressed in terms of the stator
and rotor currents {Eq(9)} and that gives the means to simulate the dynamic behavior of the motor for varying torques. The key variables in the machine are the air gap power, mechanical and shaft output power, and electromagnetic torque. These are derived from the equivalent circuit of the induction motor. A simple per phase equivalent circuit model of induction motor is a very important tool for analysis and performance prediction at steady state condition. In the equivalent circuit shown in Fig.3, Rs (Rr) is the stator (rotor) resistance and M is the magnetizing inductance of the motor. Note that stator (rotor) inductance Ls (Lr) is defined by
The transformation equations from three-phase to the rectangular coordinates (Fig.4), for the current space phasor are:
id 1 = iq 0
1 2
3 2
1 2 23
ias i bs ics
(2)
The two-phase to three-phase transformation is achieved by:
Ls = Lls + M ; Lr = Llr + M
Where Lls(Lrs) is the stator (rotor) leakage inductance. Methods of determining circuit parameters from no-load test and locked rotor test are described in many literature & books.
ia (t ) =
2 3 d
i (t )
1 3 q 1 3 q
ib (t ) = 1 id (t ) + 3 ic (t ) = 1 id (t ) 3
i (t )
(3)
i (t )
Similarly, the equivalent transformation for voltages is given as,
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Va V b Vc
Vq cos 2 sin Vd = 3 0.5 V0
cos( 2 3) sin( 2 3)
0.5
cos( + 2 3) sin( + 2 3) 0.5
(4)
didr (Vds Rs ids ) / Ls + ( Rr idr + Lrr iqr ) / M + r iqs = dt M / Ls Lr / M diqr (Vqs Rs iqs ) / Ls + ( Rr iqr Lrr idr ) / M r ids = dt M / Ls Lr / M
The induction motor model in arbitrary reference frames is expressed as:
a Vqs R + L p Mp a Ls a M s s a a M Rs + Ls p Mp Vds a Ls = a Mp (a o ) M Rr + Lr p (a o ) Lr Vqr V a (a o ) M Mp (a o ) Lr Rr + Lr p dr a I qs a I ds a I qr I a dr
The developed torque (Td) can be expressed as
(5)
Td =
2 P M (iqs.idr iqr .ids ) 32
(9)
Where the superscript a refer to arbitrary frame. Stator reference frame model given below is a particular case of Eq(5).
The constant 2/3 arises due to the three phase power expressed in terms of a two phase quantity. The above equations describe the dynamic model of IM. IV. SIMULINK IMPLIMENTATION
s 0s Vqs Rs + Ls p s 0 Rs + Ls p Vds = 0 L p o M m 0 (a o ) M Mp
Mp 0 Rr + Lr p
o Lr
Mp o Lr Rr + Lr p 0
s I qs s I ds s I qr I s dr
(6)
where the superscript s refers to stationary frame. For convenience, the superscripts are omitted for further discussions. Expanding the matrix equation {Eq(6)}, we get four differential equations as shown in (7) below:
d iqs diqr
dt dt dids didr Vds = Rs ids + Ls +M dt dt diqr di Vqr = Rr iqr + Lr Lr r idr + M qs + Mr ids = 0 dt dt didr dids Vdr = Rr idr + Lr + Lr r iqr + M + Mr iqs = 0 dt dt
Vqs = Rs iqs + Ls
+M
The modules of induction motor are implemented in such a manner, that one can easily analyze the behavior of machine parameters. This would also make it useful for control and verification purposes in the future. The inputs of a squirrel cage induction machine are the three-phase voltages, their fundamental frequency, and the load torque. The outputs, on the other hand, are the three phase currents, the electrical torque, and the rotor speed. The d-q model requires that all the three-phase variables are transformed to two-phase stator ref frame rotating frame. The IM dynamic model implemented in this paper consists of 3 ph to 2 axis transformation module for V and I, a module to calculate electromagnetic torque Te and module to calculate rotor speed. Fig.5 shows the complete induction motor model using Simulink function blocks.
(7)
To solve these equations, they have to be rearranged as follows.

dids (Vds Rs ids ) / M + ( Rr idr + Mr iqs ) / Lr + r iqr = dt Ls / M M / Lr
diqs dt
(Vqs Rs iqs ) / M + ( Rr iqr Mr ids ) / Lr r idr Ls / M M / Lr
(8)
Fig.5 Simulink model of a powered Induction Motor
Practical realization of the Eq(8) & (9) in Simulink is shown in Fig.6.
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Fig.6 Implementation of the IM sub-block from Eq(8) Fig.7 Torque behavior when limiting torque is applied at start
While performing simulation one should note that, the sampling time should be selected not larger than one-tenth of the smallest time constant in the model. Do not select a smaller sampling time than required, either. A smaller sampling time does not necessarily increase accuracy , but the simulation time increases. V. SIMULATION RESULTS A 4 pole 3 HP squirrel cage induction motor with the following parameters is used for our simulation. Rs = 2.08 /ph ; Rr = 1.19 /ph Ls = Lr =0.28 /ph; M = 0.272 /ph J=0.25 Kgm2; B=0.1Nms One purpose of our simulation was to see how one can maximize the loading capacity of an existing motor by judiciously optimizing the time for applying the load. For this one needs to find out the limiting (maximum) load torque that can be applied at starting. This can be found by either by an iterative application of load manually, or by creating a looping construct at the TL input in Simulink. For this particular machine this torque happened to be 16.205Nm. It is found that the machine will not motor, if the applied load torque (TLA) at start is more than 16.205 Nm. Fig.7 shows the Torque behavior with time for this load, which is a straight line after transients indicating no acceleration.
However, if a small delay is introduced ( @500ms is a good choice) before applying this load , the machine could accelerate. To analyze the dependency of this delay on motor performance, variable delays are applied and a family of curves has been plotted as shown in Fig.8. TLA is chosen as 16.205 Nm.
Fig. 8. Behavior of developed torque for different time delays.
It is noticed from the characteristic that, when the torque is applied the acceleration trajectories of the machine follow with different slopes. This has significant implication on the dynamic responses & effectiveness of the motor. The impact of applying the load is more visible in the next graph (Fig.9) which illustrates the relationship of this delay to the motor current drawn from the mains. Any delay less than 1.5 seconds, the motor takes significantly larger time to develop the torque. Also the current drawn is 3-4 times the rated current as shown, which can potentially create overheating and damage.
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VI. CONCLUSIONS The paper illustrates a convenient and configurable model to study 3 phase induction motor for its performance characteristics using Simulink. The d-q axis model equations and stationary reference frame are used to demonstrate how the power of this software can be used to get the characteristic family of curves and thus quickly arrive at optimum load patterns, when a general purpose induction motor is investigated for its use for new applications. While the illustration is carried out for a varying torque scenario, one can easily appreciate the possibility of extending this for analyzing any other input to the machine by appropriately changing simple source designs. The concept of an optimal delay region(ODR) to apply load torque is introduced, which can improve the effectiveness and efficiency of the motor application. We hope students as well as designers would find the model and the process described here, very useful and convenient to understand the intricacies of this increasing popular general purpose drive. REFERENCES
1. Bimal K. Bose, Modern Power Electronics and AC Drives published by Prentice Hall 2. R. Krishnan, Electric Motor Drives-modeling, analysis and control, Pearson 3. P.C. Krause, Analysis of Electric Machinery, McGraw-Hill, New York, 1986 4. Dal Y. Ohm, Dynamic Model of Induction Motor for Vector Control, Article, Drivetech Inc., Blacksburg, Virginia. 5. Burak Ozpineci, Leon M. Tolbert, Simulink Implementation of Induction Machine Model A Modular Approach 6. T. Matsuo, V. Blasko, J. C. Moreira, and T. A. Lipo, "Field oriented control of induction machines employing rotor end ring current detection", IEEE Trans. Power Electron., vol. 9, no. 6, pp. 638 - 645, 1994. 7. C. M. Liaw, Y. S. Kung, and C. M. Wu, "Design and implementation of a high-performance field-oriented induction motor drive", IEEE Trans. Ind. Electron., vol. 38, no. 4, pp. 293 - 297, 1991. 8. Ba-Razzouk. A., Cheriti.A., Olivier.G, Sicard.P, Field-oriented control of induction motors using neural-network decouplers, IEEE Trans. Power Electron., vol. 12, no:4 pp. 752-763, 1997 9. G.R. Slemon, Electrical machines for variable frequency drives, Proceedings of the IEEE, vol. 82, pp.1123-1139, aug. 1994 10. Wade. S, Dunnigan. M.W, Williams. B.W, Modeling and simulation of induction machine vector control with rotor resistance identification , IEEE Trans. Power Electron.,vol. 12 no.3 pp.495-506, 1997
Fig.9 Behavior of Current peaks for different delays
Fig.10 shows another perspective in terms of the motors ability to pick up speed as a function of the delay. While it is true that provisioning the load changes the locus of the characteristics irrespective of the time of application, the impact on pick up is much higher if the delay is less than 1.5 seconds. Thus we get an important value of delay say dmin, below which the motor is inefficient as well as ineffective.
Fig.10 Influence of the delay on speed pick up
One can also see that the free acceleration phase is complete beyond 2 seconds. This is the time when application of the load will create a negative slope on the speed vs time graph. Applying load after this also ineffective, and less efficient for similar reasons. Let us call this delay as dmax . The region in time between dmin and dmax, form an interesting optimal delay region (ODR) for applying the load, that will help us make the motor carry much higher loads than its rated capacity. It can also be observed from the above figures that any viable load reaches its full torque capacity much faster than even lower loads, if applied in the ODR. This is a very useful piece of information for making an optimal choice of motor rating, especially for fluctuating loads that does not need very short response time. Thus ODR has a good potential as a design parameter for systems where there is flexibility in applying mechanical load , for instance, drives used in auto-transmission for electric vehicles.
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HYDROGEN CLEAN FUEL FOR PRODUCTION OF ENERGY FOR SUSTAINABLE DEVELOPMENT

K.VINOTH KUMAR1 KAVYA VENUGOPLAN2 NIMMY JOSEPH2 Lecturer/Research Scholar PG Students Department of EEE, School of Electrical Sciences, Karunya University, Coimbatore 641 114 Tamilnadu - INDIA Email: vinothkumar@karunya.edu, kvinoth_kumar84@yahoo.in
Abstract- A some of the renewable cleaner energies for sustainable development are solar, wind, hydropower, tidal and hydrogen energy. However, some of these sources have limitations in their applicability and wider choices. One of the cleanest energy source is the hydrogen fuel. Hydrogen fuel energy is abundant, since it is available in water, which covers 3/4 th of the earths surface. An attempt is made in this paper to describe the prospects of hydrogen energy, principle of production and utilization.
I.
INTRODUCTION
Energy consumption for various sectors such as domestic, industry and commercial are increasing day by day. The present per capita energy consumption in the developed countries is around 5.5.KWh/day wherein developing countries is around 1.2 KWh/day. By the middle of this century, the population in India will be around 1640 millions, and per capita energy consumption will be around 2.0 KWh/day. Most of the energy production (80%) today is from fossil fuels such as coal, lignite and petroleum. The fossil fuels as energy resources are highly associated with human health and environmental damage, global warming, ozone depletion, acid rains and eco system damages. Such consequences would eventually hamper sustainable growth of human societies. Renewable energies such as solar energy, wind energy, hydropower energy, tidal energy, thermal energy and hydrogen energy are the cleaner energies for sustainable development. However, some of these energy sources have limitations in their applicability and wider choices. Among the above energy sources, probably one of the cleanest energy source is the hydrogen fuel. Hydrogen fuel energy is quite abundant on the earth planet, since abundant hydrogen is available in water, which covers 3/4th of the earths surface. The present lecture is aimed to describe the prospects of hydrogen energy, its principle of production, utilization aspects and future exploitation in combination with other energy resources. 2.0 HYDROGEN GAS AS A FUEL Hydrogen is the simplest element known to man. Each atom of hydrogen has only one proton. It is also the most plentiful gas in the universe. Stars are made primarily of hydrogen.
The sun is basically a giant ball of hydrogen and helium gases. In the suns core, hydrogen atoms combine to form helium atoms. This process called fusion gives off radiant energy. This radiant energy (Fig.1) sustains life on earth. It gives us light and makes plants grow. It makes the wind blow and rain fall. It is stored as chemical energy in fossil fuels. Most of the energy we use today came from the suns radiant energy. Hydrogen gas is lighter than air and, as a result, it rises in the atmosphere. This is why hydrogen as a gas (H 2) is not found by itself on earth. It is found only in compound form with other elements. Hydrogen combined with oxygen, is water (H2O). Hydrogen combined with carbon, forms different compounds such as methane (CH4), coal, and petroleum. Hydrogen is also found in all growing things- biomass. It is also an abundant element in the earths crust.
Fig. 1 Radiant Energy
Hydrogen has the highest energy content of any common fuel by weight (about three times more than gasoline), but the lowest energy content by volume (about four times less than gasoline). It is the lightest element, and it is a gas at normal temperature and pressure. An energy carrier is a substance or system that moves energy in a usable form from one place to another. Electricity is the most well- known energy carrier. We use electricity to move the energy in coal, uranium, and other energy sources
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containing balanced charges of ions and electrons is called plasma. For plasma to exist, ionization is necessary. Plasma density refers to the electron density that is the number of free electrons per unit volume. The degree of ionization of plasma is the proportion of atoms, which have lost (or gained) electrons and is controlled by the temperature. Even a partially ionized gas in which as little as 1% of the particles are ionized, can have characteristic of a plasma. Plasma temperature is commonly measured in Kelvin or electron volts and is a measure of the thermal kinetic energy per particle. Plasma is sometimes referred to as being hot if it is nearly fully ionized or cold if only a small fraction of the gas molecules are ionized. 3.2 Water Plasma Steam power is a perfect plasma-generating medium: pollution free, and non-waste compound that has beneficial effects on the hygiene and sanitary conditions of work. Plasma in a water vapor can be made at different temperatures, depending upon the pressure of the water vapor. In water plasma, free electrons, water vapor and +ve ions like OH +, O+, and H+ are present. To ionize the water, the electrons should have energy of 12 volts. If it has to be achieved thermally, then the water has to be heated to a temperature of 12000 0K. The bulk of steam dissociates at a temperature of 4000K. Further increase in temperature provides for the hydrogen ionization with considerable amount of heat absorption. Thereafter, during the recombination in the anode area a large amount of power is released providing for the metal melting augmentation. The new technical devices for heat energy as well as energy containing gases (hydrogen and oxygen) from water will be the future industrial power installations. The use of water as a source of energy will solve many environmental problems in the planet. 3.3 Application Of Water Plasma Tool Water plasma device is a multi-functional, portable, and hand held device (Fig.2). It is a technological break through in the area of metal cutting (Fig. 3 & 4), welding (Fig.5), soldering, tempering, spraying, etc. as maximum efficiency is achieved when plasma technique is used.
from power plants to homes and businesses. We also use electricity to move the energy in flowing water from hydropower dams to consumers. It is much easier to use electricity than the energy sources themselves. Like electricity, hydrogen is an energy carrier and must be produced from another substance. Hydrogen is not widely used today but it has great potential as an energy carrier in the future. Hydrogen can be produced from a variety of resources (water, fossil fuels, biomass) and is a byproduct of other chemical processes. Unlike electricity, large quantities of hydrogen can be easily stored to be used in the future. Hydrogen can also be used in places where its hard to use electricity. Hydrogen can store the energy until its needed and can be moved to where its needed. 1.0 PRINCIPLE OF HYDROGEN PRODUCTION Since hydrogen doesnt exist on earth as a gas, we must separate it from other elements. We can separate hydrogen atoms from water, biomass, or natural gas molecules. The two most common methods for producing hydrogen are steam reforming and electrolysis (water splitting). Scientists have even discovered that some algae and bacteria give off hydrogen. Steam reforming is currently the least expensive method of producing hydrogen and accounts for about 95 percent of the hydrogen produced in the United States. It is used in industries to separate hydrogen atoms from carbon atoms in methane (CH4). Because methane is a fossil fuel, the process of steam of reforming results in greenhouse gas emissions that are linked with global warming. Electrolysis is a process that splits hydrogen from water. It results in no emissions but it is currently a very expensive process. New technologies are being developed all the time. Hydrogen can be produced at large central facilities or at small plants for local use. Every region of the country (and the world) has some resource that can be used to make hydrogen. Its flexibility is one of its main advantages. 3.0 UTILISATION OF HYDROGEN 3.1 What Is Plasma? Plasma may be defined as charged particles, which are close together so that, each particle influences many charged particles, rather than just interacting with the nearby particle. Plasma is typically an ionized gas and is considered to be distinct state of matter, because of its unique properties. It is a fourth state of matter. The term ionized refers to the presence of one or more free electrons, which are not bound to an atom or molecule. The free electronic charges make the plasma electrically conductive so that it responds strongly to electromagnetic fields. Plasma is formed by heating and ionizing a gas, stripping electrons away from atoms, thereby enabling the +ve and ve charges to move more freely. The ionized gas contains ions and electrons in about equal numbers so that the resultant space charge is very small. This region
Figure 2 Plasma Device
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Use of water plasma tool for welding in gas mode is similar to the regular gas welding process. The difference is that electric power and water are used instead of gas tanks to produce a high temperature jet flame. Filler rods and fluxes used for water plasma welding are the same as those for conventional gas welding. For carrying out welding in plasma arc mode, it is necessary to take into account, an increased level of heat flow, capable of heating the metal up to its whole depth. At high temperatures, within the plasma jet area, steam may also dissociate into hydrogen and hydroxyl. The latter does not dissolve in the metal, as it is a high resistant compound, thereby providing for improvement of the melted metal surface i.e., the metal surface is characterized by a metallic luster. 3.4 Construction Of Plasma Torch Figure 6 shows a plasma torch with the main parts indicated and which is in the form of a handgun. It is connected to the power supply unit via the power cable. The power supply unit is connected to the conventional electric system (220V, AC, 50Hz) a grounded power outlet.
Fig. 3 Metal cutting
Fig.4 Metal Cutting Fig. 6 Plasma Torch Cathode adjusting cap 15. Metal tank Sealing bush 16. Tank gasket Ring 17. Plastic body Filling plug 18. Connecting cable Adjusting cap limiting 19.MINUS power supply Device terminal Overheat sensor 20.PLUSpower supply Terminal Evaporator 21.Cathode module Spout 22. Torch activating knob Nozzle-Anode 23. Packing ring Cathode 24. Thermo contractible ring Torch body tightening nut
1. 2. 3. 5. 6. 8. 9. 10. 11. 13. 14.
Fig. 5 Metal Welding
Majority of the main parts of the plasma torch, are located inside the plastic body 17, which is two halves, fitted together. The metal tank, 15 is filled with liquid absorbing material, sliding cathode assembly 21 connected to the negative terminal of the power source through the contact plate
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Water may be used as a working fluid for cutting, and 40% water alcohol solution for welding, soldering and brazing. The device operates with a 220V socket connector and does not require a high voltage connection. The device can be carried to the worksite in a small bag with a total weight of only 6 Kg. 4. SOLAR PRODUCTION OF HYDROGEN: THE FUEL OF THE FUTURE Hydrogen is the cleanest fuel in the nature. Conventional cars can be run on hydrogen gas as a fuel in the same manner as they are running with natural gas. This fact has been amply demonstrated. Furthermore, neither carbon dioxide nor hydrocarbon pollution is produced during the burning of hydrogen. Indeed, the only by-product of H2 combustion is water vapor. However, some nitrous oxides will be produced, too, because the burning still uses air, which contains fourfifths nitrogen. The usage of hydrogen gas or fuel is restricted due to its non-availability on earth. Although, many bacteria in the soil produce hydrogen in fermentation reactions, other bacteria are quick to use the hydrogen because it is an excellent source of energy. Thus, abundant amount of elemental hydrogen is there, but it is all combined with oxygen in the form of water or other low-energy compounds. Although, we can extract hydrogen from water via electrolysis, the process uses energy. A money saving process of decomposition of water molecules into hydrogen and oxygen exists in nature. This process takes place during photosynthesis. Hydrogen atoms are separated from water molecules and are used as connecting links while forming organic molecules and oxygen is released into air. Is it possible to model an electrolytic process of water decomposition into hydrogen and oxygen, which takes place during photosynthesis? The photosynthesis has the ability to split water molecule into hydrogen and oxygen using light energy from solar system. However, scientists have not yet developed a means of mimicking the photosynthetic reaction on a scale sufficient to produce commercial amounts of hydrogen. The Boeing Corporation is working on a solar plant for the thermo-chemical decomposition of water. Given the efficiency of the order of 50% for this plant, the specific capital cost of the plant is estimated to $200-250/KWh. The hydrogen production cost is equivalent to gasoline cost of $1.65 to 2.35 per gallon. The hydrogen produced can be combined with metal hydrides, which can absorb the gas and release it when needed. With vehicles already being adopted to run on natural gas, hydrogen could slowly be phased in by mixing gradually increasing proportion of it with natural gas. Thus, there could be a smooth transition from the present fuel through natural gas to hydrogen. Major obstacle in the widespread use of hydrogen gas is lack of infrastructure to provide hydrogen fueling till the technology improves rapidly and is poised future commercial development
19, consists of cathode holder with replaceable cathode13, secured into its front part. Nozzle anode 11, connected to the metal tank 15 by means of spout 10, is powered by positive voltage from power supply (terminal 20). Nozzle anode 11 and cathode 13 form a discharge chamber, where the steam of the working fluid heats up to the plasma generation temperature due to the energy of electric arc. 3.5 Principle Of Operation Of Plasma Tool Figure 7 illustrates the principle of plasma tool operation. Brief pressing of the torch activating knob, activates the torch already filled with working fluid. When the knob is pressed, movable cathode module slides forward and touches the nozzle anode; thus completing the anode cathode short circuit. After releasing the knob the cathode module moves back by means of the return spring and an electric arc occurs between the cathode tip and nozzle anode. Thermal energy of the electric arc heats the water and it evaporates. The resulting pressure forces the steam to run to the opening of the nozzle anode. While passing through the electric arc area, the steam tears the arc from the internal surface of the nozzle, pulls it out and connects to the outer side of the outer edge of the nozzle anode. The steam surrounds the arc inside the fine bored nozzle opening and centers it; thus not allowing the arc to close onto the sidewalls of the opening.
Fig. 7 Principle of Plasma Tool Operation
While passing through the electric arc, part of the steam turns into the fourth state of matter plasma with the temperature up to 8000 0C, by means of which cutting, welding, soldering, and heat treatment of non-combustible materials is performed. Water plasma device is also highly efficient for pipeline, heating and central heating systems, power supply systems, assembly, plumbing, repairs of refrigerators, air conditioners and ventilation systems. The device is indispensable for operations performed in water Trenches, underground tunnel engineering operations, assembly of all kinds of underground utility systems, for the use on board of the ships and is also widely used in the nuclear industry.
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TABLE-1 TECHNICAL PARAMETERS Details Voltage For The Network Frequency Power Consumption Device Dimension Torch Weight Device Weight Temperature of the Flame Cutting Thickness range Cutting speed Width of cutting Working time of the Torch per fill 220V+ 10% 50-60 Hz Up to 2.5KW 11.5 X 17X 32.5 Cm 0.7 Kgs 5.5 Kgs 8,00000 C 0.5 to 10 mm Up to 8mm/sec 1.5 mm 20 30 Min Fig. 8 Liquid hydrogen fuel lifts the space shuttles Range
4.1 Hydrogen Using Vehicles About 7.8 million metric tonnes of hydrogen is produced in the United States today, enough to power 20 30 million cars or 5-8 million homes. Nearly all of this hydrogen is used by industry in refining, treating metals, and processing foods. Most of this hydrogen is produced in just three states: California, Louisiana, and Texas. The National Aeronautics and Space Administration (NASA) is the primary user of hydrogen as an energy fuel; it has used hydrogen for years in the space program. Liquid hydrogen fuel lifts the space shuttles (Fig. 8) into orbit. Hydrogen batteries called fuel cells power the shuttles electrical systems. The only by product is pure water which the crew uses as drinking water. Hydrogen fuel cells, Fig.9 (batteries) make electricity. They are very efficient, but expensive to build. Small fuel cells can power electric cars. Large fuel cells can provide electricity in out of the way places with no power lines.
Because of the high cost to build fuel cells, large hydrogen power plants wont be built for a while. However, fuel cells are being used in some places as a source of emergency power to hospitals and to wilderness locations, portable fuel cells are being sold to provide longer power for laptop computers, cell phones, and military applications. There are currently about 200 hydrogen-fueled vehicles in the United States mostly in California. Most of these vehicles are buses and automobiles powered by electric motors. They store hydrogen gas or liquid on board and convert the hydrogen into electricity for the motor using a fuel cell. Only a few of these vehicles burn the hydrogen directly (producing almost no pollution). Hydrogen vehicles are starting to move from the laboratory to the road. The U.S. postal service, a package delivery company, a few Florida park rangers, and a few private utility companies are also using hydrogen vehicles. It will probably be at least 10 years, through, before you can walk into your local car dealer and drive away in affordable hydrogen powered car.
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Fig. 9 Hydrogen fuel cells
Even then, you will need a place to refuel your hydrogen car. Currently, there are about 25 hydrogen-refueling stations nationwide. This is the so-called chicken and egg problem that hydrogen developers are working hard to solve. Namely: who will buy hydrogen cars if there are no refueling stations? And who will pay to build a refueling station if there are no cars and customers? One possible solution is to eliminate refueling stations entirely. Automobile manufacturers have already designed a refrigerator-sized hydrogen generator for your garage that works off electricity. Consumers would simply refill their cars with hydrogen each night while it is parked. 5. CONCLUSIONS Hydrogen is the cleanest fuel in nature and has wider applications. Use of Hydrogen due to its high flame velocity, can enhance the combustion rate of certain vegetable oils ethanol and other fuel oils, which have low flame velocity by mixing with them. Hydrogen as a fuel would yield zero emissions of green house and other environmental pollutants. Hydrogen gas can be conveniently utilized in dual fuel engines. By liquefying at high pressures, Hydrogen can be stored on an economic way. Hydrogen generation with solar power is strategic approach and would a futuristic technology. There is a need to economize the production of Hydrogen from water source; an active research in this field is to be augmented. REFERENCES [1]. Multiplaz-2500, Technology of future- www. Water plasma.com [2].www.guns.connect.fi/innoplaza/energy/story/Kanarev/ coldfusion/ - 194k [3]. www.youtube.com/watch?v=G9NvboKL43Q [4]. www.oceta.on.ca/profiles/sparktec/plasma_spark.html-12k
293
IMPLEMENTATION OF MULTILEVEL INVERTER TOPOLOGY FOR PV CELL APPLICATION

V.Srimaheswaran, J.Karpagam, R.Uthirasamy and A.Nirmal Kumar
Abstract The PV power generation have low efficiency due to the various constrains. This thesis gives a new proposed method to improve the performance of the PV system. The PV cell is connected to boost chopper and Multi-Level Inverter (MLI). In order to improve the efficiency and for making the power generator available to the grid MLI are employed. MLI have emerged as attractive high power medium voltage converter to the reduce harmonic component in the output current due to filter. In the proposed MLI there are 3-H bridge inverter to achive the 7-level output voltage. A SPWM technique is used to generate the PWM signal for inverter switches. Boost chopper is connected between the PV array & MLI. The purpose of boost chopper is to step-up the voltage and to produce continuous Current to MLI. Analog MPPT controller is employed for tracking the maximum power during varying temperature and irradiance. The PV models, boost chopper along with analog MPPT controller are simulated. Key words PV Array, Boost Chopper, MLI.
Multilevel inverter, which is the heart of a PV system, is used to convert dc power obtained from PV modules into ac power to be fed into the grid. Improving the output waveform of the inverter reduces its respective harmonic content and, hence, the size of the filter used and the level of electromagnetic interference (EMI) generated by switching operation of the inverter. In recent years, multilevel inverters have become more attractive for researchers and manufacturers due to their advantages over conventional three-level inverters. They offer improved output waveforms, smaller filter size, lower EMI and lower total harmonic distortion (THD) [4]. II. MODELING OF THE SOLAR CELL Thus the simplest equivalent circuit of a solar cell is a current in parallel with a diode. The output of the current source is directly proportional to the light falling on the cell. During darkness, the solar cell is not an active device; it works as a diode, i.e. a P-N junction. It produces neither a current nor a voltage. However, if it is connected to an external supply (large voltage) it generates a current Id, called diode current or dark current. The diode determines the V-I characteristics of the cell.
I.INTRODUCTION The demand for renewable energy has increased significantly over the years because of shortage of fossil fuels and greenhouse effect. Among various types of renewable energy sources, solar energy and wind energy have become very popular and demanding due to advancement in power electronics techniques. Photo-Voltaic (PV) sources are used today in many applications as they have the advantages of being maintenance and pollution free. Solar-electric-energy demand has grown consistently by 20%25% per annum over the past 20 years, which is mainly due to the decreasing costs and prices. This decline has been driven by the following factors: 1) an increasing efficiency of solar cells 2) manufacturing technology improvements and 3) economics of scale [1].
Fig. 1. Equivalent Circuit of a Solar Cell
V.srimaheswaran, PG scholar, EEE Department Bannari Amman Institute of technology Sathyamangalam., e-mail id: srimahes1985@gmail.com J.Karpagam, Assistant Professor, EEE Department Bannari Amman Institute of technology, Sathyamangalam. e-mail id: sujisumi@rediffmail.com R.Uthirasamy, Lecturer, EEE Department Bannari Amman Institute of technology, Sathyamangalam. e-mail id: rusamy83@yahoo.com
Fig. 1 shows the equivalent circuit of a solar cell, where, RS is the very small series resistance and Rsh is the quite large shunt resistance. Dj is the ideal P-N diode, Iph expresses as the photocurrent source generated proportionally by the surface temperature and insolation. V and I represent the output voltage and output current of the solar cell, respectively. According to the physical property of the P-N semiconductor, the I-V characteristics of PV module could be expressed.
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(1)
In addition, the modules reverse saturation current Isat. (2) The Iph is expressed in (3) represents the photocurrent proportionally produced to the level of cell surface temperature and radiation, where ISSO is the short-circuit current, Ki is the short-circuit current temperature coefficient, and Si is the solar radiation in W/m2 [2]. (3)
Fig. 3. PSIM model of PV subcircuit.
V-I CHARACTERISTICS Each solar cell has its own voltage-current (V-I) characteristic. Fig. 4 shows the V-I & P-V characteristic of a typical photovoltaic cell. The problem with extracting the most possible power from a solar panel is due to nonlinearity of the characteristic curve. The characteristic shows two curves, one shows the behavior of the current with respect to increasing voltage. The other curve is the power-voltage curve and is obtained by the equation (P=I*V).
PSIM-BASED PHOTOVOLTAIC MODULE MODELING In order to exhibit the influence of insolation and temperature, the tested scheme of SIMENS SP75 PV module developed from the PSIM software package is constructed as shown in Fig. 2 Equation (1) is reproduced as the PSIM module, while (3) represented the Iph.dll block in C-code for producing photocurrent Iph. The variable parameters, such as solar insolation and module surface temperature, are included in the external dynamic link library block (DLL), which allows users to write codes in C/C++ and link them with PSIM. In addition, the fault switch could switch the proposed PSIM module to engage in faulting simulation or normal operation.
Fig. 4. Solar Panel V-I Characteristic and Power Curve
Fig. 2. Scheme Diagram of PV Module using PSIM.
When the P-V curve of the module is observed, one can locate single maxima of power where the solar panel operates at its optimum. In other words, there is a peak power that corresponds to a particular voltage and current. Obtaining this peak power requires that the solar panel operate at or very near the point where the P-V curve is at the maximum [2]. III. DC-DC BOOST CONVERTER
Fig. 3 shows the inner sub circuit of the proposed PV module, the photovoltaic current is a function of itself, causing an algebraic loop problem. To solve this problem, the series resistance is always neglected in the conventional mathematical model to form a simple equation. Its results show that the proposed PSIM model can be significantly more accurate than the conventional model in simulating the PV module characteristics [3].
The boost converter will represent one of the most significant portions to the overall design of the Maximum Peak Power Tracker. Ideally, the maximum power will be taken from the solar panels. In order to do so, the panels must operate at their optimum power point. The output of the solar panel will be either shorted or open circuited through the opening or closing of a switch.
WAVEFORMS
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Fig. 8 shows the switch state, voltage and current waveforms. When the dc-dc converter operates in continuous conduction mode, the inductor current flows continuously when [iL(t) > 0].
Fig. 5. Step-Up (Boost) DC-DC converter
In the design, the switch will actually be a MOSFET, which will be controlled by our digital controller. For better understanding of the converter, we will model the overall design, with the MOSFET as a simple, ideal switch. The switch will open and close to control the voltage across the inductor, essentially operating the panels at their optimum power level. Fig. 5 shows the basic design of a step-up converter. As the name implies, the output voltage is always greater than the input voltage. The operation of the converter depends on the state of the switch. To better understand the operation of the converter, we will examine the operation of the circuit when the switch is opened or closed. Mode 1 When the switch is on as shown in Fig. 6 the diode becomes reversed biased and the output stage is isolated. At this point, the input is supplying energy to the inductor.
Fig. 8. Boost DC-DC Converter Switch State and Voltage and Current Waveforms
In steady state, the time integral of the inductor voltage over one time period must be zero. Thus Vd ton + (Vd Vo)toff = 0 (6)
Dividing both sides by the switching time, Ts, and rearranging terms, we obtain the equation that describes the relationship between the input and output voltages, switching time, and duty cycle [4].
(7) The equation [7] confirms that the output voltage is always higher than the input voltage. Assuming a lossless circuit, Pd = Po, also have (8) When the switch is off as shown in Fig. 7 the output stage receives energy from the inductor as well as from the input. In the steady-state analysis we present, the output filter capacitor is assumed to be very large to ensure a constant output voltage vo(t) = Vo
Fig. 6. Boost Converter Switch ON
Mode 2
IV. MULTILEVEL INVERTER A cascaded multilevel inverter consists of a series of Hbridge inverter units. The work of multilevel inverter is to synthesize a desired voltage from Several Separate DC Source. Fig. 9 shows the basic structure of a SDCS. Each SDCS is connected to an H-bridge inverter. The ac terminal voltages of different level inverters are connected in series. Unlike the diode-clamp or flying capacitor inverter, the cascaded inverter does not require any voltage clamping diodes or voltage balancing capacitors. The numbering order of the switches is S1, S2, S3, S4, S5, S6, S7, S8, S9, S10,
Fig. 7. Boost Converter Switch OFF
S11 and S12. Theof Engineering, Coimbatore as along as the INFO Institute numbering is immaterial switches are turned on and off in the right sequence to produce the desired output waveform.
4. 5. 6. 7.
For an output voltage level Vo = 0, all switches are turn off. For an output voltage level Vo = - Vdc /3, S3 and S4 are turned on. For an output voltage level Vo = - Vdc /2, S3 S4 & S7 S8 are turned on. For an output voltage level Vo = - Vdc , S3 S4, S7 S8 & S11 S12 are turned on.
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Table 1 shows switching table for a seven level inverter. The condition 1 indicates the switch is ON and 0 indicates means the switch is OFF. Thus, if one of the complementary switch pairs is turned on, the order of the same pair must be off. Four switches are always turned off at the same time. Fig. 10 shows the output waveform of 7 phase voltage of a seven level inverter [4].
Fig. 9. Cascaded Multilevel Inverter
Number of bridges to be used = (m-1)/2
(9)
The seven level inverter is considered to produce steeped output voltage. The DC rail 0 is the reference point of the output phase voltage. The steps to synthesize the seven-level voltages are as follows: Table: 1 Switching Table for Seven Level Inverter
Fig. 10. Output Voltage (phase) Waveform of 7-Level Inverter
V. SIMULATION MODEL
A. Simulation of PV Cell Output(Vo) Vo = Vdc Vo = Vdc/2 Vo = Vdc/3 Vo = 0 Vo = - Vdc/3 Vo = - Vdc/2 Vo = - Vdc S1 S2 1 1 1 0 0 0 0 S3 S4 0 0 0 0 1 1 1 S5 S6 1 1 0 0 0 0 0 S7 S8 0 0 0 0 0 1 1 S9 S10 1 0 0 0 0 0 0 S11 S12 0 0 0 0 0 0 1
1. 2. 3.
For an output voltage level Vo = Vdc, S1 S2, S5 S6 & S9 S10 are turned on. For an output voltage level Vo = Vdc /2, turn on S1 S2 & S5 S6 are turned on. For an output voltage level Vo = Vdc /3, S1 and S2 are turned on.
Fig. 11. Simulation Model of PV Cell
Input of the PV cell is temperature and solar insolations are given to the dynamic link library block. In this photovoltaic array model 4 series and 10 parallel are
connected as shown in Fig. 11. This PV system operates at a INFO Institute of Engineering, Coimbatore 25C & 1000W/m2. It generates a maximum power of 2787W at 70V as output voltage and 28.37A as output current. B. Simulation of PV Cell with Boost Chopper PV cell simulation model along with boost chopper is shown in Fig.12. Since the PV cell output is low voltage, the boost chopper is connected to boost up the voltage. The chopper gives the output of 100V for 70V input. The boost chopper output current and power delivered by boost chopper is 25A and 2787W respectively.
output power of 3KW at 214V, 11.7A is obtained. Total Harmonics Distortion for the output voltage is 1.4% and the current is 5.9%.
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Fig. 14. Simulation Model of PV Cell with Boost Chopper and 7- Level Multilevel Inverter with Filter
VI. SIMULATION RESULTS
Fig. 12. Simulation Model of PV Cell with Boost Chopper
C. Simulation of PV Cell with Boost Chopper & Multilevel Inverter without Filter
Fig. 15. Output Waveforms of PV Cell
Fig. 15 shows the output waveform of a PV cell. It shows the power, voltage and characteristic with respect to time for a PV system surface temperature of 25C and solar insolation of 1000W/m2, respectively. Form the results obtained it is found that the average value of power is 2787W, voltage is 70V and current is 28.37A.
Fig. 13. Simulation Model of PV Cell with Boost Chopper and 7- Level Multilevel Inverter without Filter
Output from boost chopper is given to the seven level multilevel inverter to get the AC output. This model is simulated without filter is given in Fig. 13. To get an approximate sinwave, multilevel inverter is used. It gives the output voltage as 300V with a seven stepped wave. D. Simulation of PV Cell with Boost Chopper & Multilevel Inverter with Filter Model of PV cell with boost chopper and multilevel inverter with filter is given in Fig. 14. Here LC filter is used to obtain the pure sinusoidal output waveform. A maximum
Fig. 16. Output Waveform of PV Cell with Boost Chopper
Fig. 16 shows the output waveform of PV cell with boost chopper. The given input to the chopper is 70V and boosted to an output voltage of 100V. The output of the boost chopper output is given to the multilevel inverter.

[1]
REFERENCES
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Jeyraj Selvaraj and Nasrudin Rahim A, Multilevel Inverter for GridConnected PV System Employing Digital PI Controller, IEEE Transactions on Power Electronics, Vol.56, No.1, pp 149-158, Jan 2009. Kuei-Hsiang Chao, Ching-Ju Li and Sheng-HanHo, Modeling and Fault Simulation of Photovoltaic Generation Systems Using Circuit Based Model, in proceedings on IEEE-ICSET Annual Meeting, Taichung, Taiwan, 2008, pp 290-294. SIEMENS Solar Module SP75 Specifications, Siemens Solar Industries,2002. M.H.Rashid, Power Electronics: Circuits, Devices, and Applications, 3rd ed. Englewood Cliffs, NJ: Prentice- Hall, 2004.
[2]
Fig. 17. Output Waveform of PV Cell with Boost Chopper and a 7-Level Multilevel Inverter without Filter
[3]
Fig. 17 shows the output waveform of PV cell with boost chopper and a 7-level multilevel inverter without filter. The boost chopper output is fed to the MLI. According to the output voltage is obtained for as a seven stepped switching sequence, with a value of 300V.
[4]
BIOGRAPHY
Srimaheswaran. V was born in Tamil Nadu, India.He received the B.E degree in Electrical and Electronics Engineering from Bannari Amman Institute of Technology, in 2009. Currently he is doing M.E Power Electronics and Drives in from Bannari Amman Institute of Technology, Sathyamangalam. His area of interest includes Power Electronics, VLSI and Digital Logic Circuits.
Fig. 18. Output Waveform of PV Cell with Boost Chopper and 7-Level Multilevel Inverter with Filter
Fig. 18 shows the output waveform of multilevel inverter for PV cell without MPPT controller. Here a LC filter is connected in the output side to get a pure sinusoidal waveform and to reduce harmonics. The waveform for RMS values of voltage 214V, current 11.7A, power 3KW, voltage THD 1.4%, current THD 5.9% for surface temperature of 25C & solar insolation 1000W/m2 are obtained. VII. CONCLUSION This thesis gives the clear idea about the cascaded multilevel inverter topology for PV cell. The voltage level of the PV panel is improved using boost chopper & multilevel inverter. The proposed multilevel inverter is to reduce both voltage & current THD of the inverter. The circuit topology, modulation law and operational principle of the proposed inverter were analyzed in detail. The performance of the PV system is increased with in solar insolation and surface temperature. MPPT controller not only tracks the maximum power point, but also reduces the volume and cost of MPPT circuit. In addition, the reaction time is better than circuits using other P&Q methods as well. Simulation results indicate that the THD of the seven-level inverter is much lesser than that of the conventional three-level inverter. The 3KW output power is obtained with above proposed topology.
J.Karpagam, She completed her Masters degree in the specialization of Power Electronics and Drives from Anna University Chennai, India. Presently she is working as Assistant Professor in the department of Electrical and Electronics Engineering at Bannari Amman Institute of Technology Tamilnadu, India and she is in this profession since 1999. Currently she is pursuing her Ph.D. in the area of multilevel converters applications to AC Drives under Anna University Coimbatore. Her area of interest includes Power Electronics, DSP applications to Power Electronics and Wind Power Generation, Solid State Drives, Power Converters, AC & DC drives. So far she has published around ten papers in national level and International conferences.
Uthirasamy.R was born in Tamilnadu, India, on April 06, 1983. He received the B.E degree in Electrical and Electronics Engineering from Sengunthar Engineering College, in 2005. He received his M.E Power Electronics and Drives from Government College of Engineering Salem in 2007. He has 3 year of teaching experience. Currently he is working as Lecturer in EEE department, Bannari Amman Institute of Technology, Sathyamanglam. Currently he is doing research in the field of power converter and UPS systems. Dr.A.Nirmal Kumar was born in the year 1951. He completed his PG and UG in Electrical Engineering from Kerala and Calicut University respectively. He completed PhD in Power Electronics in the year 1992 from P.S.G. College of Technology, Coimbatore under Bharathiar University. He was with N.S.S. College of Engineering for nearly 28 years in various posts before joining Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India in the year 2004. Presently he is working as Professor & head in the department of Electrical and Electronics Engineering at Info Institute of Engineering Tamilnadu, He is a recipient of Institution of Engineers Gold Medal in the year 1989. His current research areas include Power converters for Wind Energy Conversion System and Controller for Induction motor drives.
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Implementation of Simple MPPT Algorithm for PV Cell and SEPIC Converter

K.P.Santhi1, P.Sivaraman 2, Dr.A.Nirmal Kumar3
1 2
PG Scholar, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India.
Senior Lecturer, Department of EEE, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India.
3
HOD/EEE department Info Institute of Technology, Coimbatore {sivaramanpsr@gmail.com, sanjeevini08@yahoo.com}
Abstract - This paper proposes an implementation of Perturb and Observe (P&O) MPPT algorithm for PV cell application. SEPIC converter is used for the boost up of voltage from the Photovoltaic energy source. Because of the nonlinear behavior of the PV cell and to obtain the maximum utilization efficiency, a DC-DC power converter with MPPT controller is added for matching the load to the Photovoltaic Modules. The proposed Maximum Power Point Tracking controller tracks the maximum power point of PV module and adjusts the duty ratio of SEPIC converter based on its output to obtain the optimum matching of PV module with the load circuit. Among all other MPPT algorithms P&O algorithm has more advantages like higher efficiency, reliability, easy implementation and low cost. PV module and the MPPT algorithm are simulated in MATLAB/SIMULINK model. SEPIC converter is simulated in PSIM. Finally using simcoupler MATLAB /SIMULINK model of PV module and MPPT controller are coupled to the SEPIC converter Index Terms PV module, SEPIC converter, Maximum Power Point tracking, Perturb & Observe algorithm I.INTRODUCTION
are proposed and analysed in [7]. CUK and SEPIC converters are analysed in [1, 3] Power output of a solar PV module changes with changes in solar insolation level and with varying temperature. So a maximum power point tracker (MPPT) is needed to operate the PV array at its maximum power point. Different MPPT algorithms are discussed in [4]. The MPPT controller output is fed to the DC-DC converter to adjust the duty ratio of its switch. According to the duty ratio value the proposed converter can be operated in either step down or step up mode. The typical range of duty ratio value is zero to one. In this paper PV source fed DC motor is proposed with the SEPIC converter as interface circuit. Perturb and Observe (P&O) MPPT Algorithm is used to extract the maximum power point of PV module [4]. The overall block diagram is shown in fig1.
PV Module SEPIC Converter
Load
The photovoltaic energy system has becoming popular in the recent years, since it is one of the renewable energy technologies and it has the advantages of no environmental impacts , absence of fuel cost ,low maintenance, lack of noise ,elimination of wear through the absence of moving parts etc. Modeling and simulation of PV array based on circuit model and mathematical equations is proposed [5]. The mathematical model of the PV device may be useful in the study of the dynamic analysis of converters, MPP tracking (MPPT) algorithms, and mainly to simulate the PV system and its components using circuit simulators. Because of the nonlinear behavior of the photovoltaic (PV) cells, dc-dc power converters are added for matching the load to the photovoltaic modules. There are several topologies, including Buck, Boost, Buck-Boost, SEPIC, UK, Flyback, etc. Buck and Boost topologies allow decreasing and increasing of the output voltage respectively, while the other ones can do both functions. Buck, Boost, Buck Boost converters as interface circuits
MPPT Controller Fig1 Overall block diagram
II. MATHEMATICAL MODEL OF PV MODULE PV system directly converts sunlight into electricity. The basic device of a PV system is the PV cell. Cells may be grouped to form modules or arrays. More sophisticated applications require DC-DC converters to process the electricity from the PV device. These converters may be used to either increase or decrease the PV system voltage at the load. The proposed SEPIC converter is operated in boost mode. The practical equivalent circuit of a PV module is shown in fig.1 [2 & 8], while the typical output characteristics are shown in fig.2. The current source in the equivalent circuit represents the current generated by photons and its output
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maximum power point of the solar array is located at the knee of the curve. According to the maximum power transfer theory, the power delivered to the load is maximum when the source internal impedance matches the load impedance.
TABLE I
PV MODULE BPSX150S SPECIFICATIONS
is constant under constant temperature and constant incident radiation of light. The diode shunted with the current source determines the I-V characteristics of PV module. There is a series of resistance in a current path through the semiconductor material, the metal grid, contacts, and current collecting bus. These resistive losses
Fig2.Equivalent circuit of a PV module
are lumped together as a series resister (Rs). Its effect becomes very conspicuous in a PV module that consists of many series-connected cells, and the value of resistance is multiplied by the number of cells. The loss associated with a small leakage of current through a resistive path in parallel with the intrinsic device is represented by a parallel resister (Rp). Its effect is much less conspicuous in a PV module compared to the series resistance, and it will only become noticeable when a number of PV modules are connected in parallel for a larger system. The characteristic equation which represents the I-V characteristic of a practical photovoltaic module is given below [5]
Electrical Characteristics Maximum Power(Pmax) Voltage at Pmax(Vmp) Current at Pmax (Imp) Open-circuit voltage(Voc) Short-circuit current (Isc) Temperature coefficient of Isc Temperature coefficient of Voc
Value 150W 34.5V 4.35A 43.5V 4.75A 0.0650.015%/C -16020mV/C
Thus, the impedance seen from the converter side (which can be adjusted by controlling the duty cycle) needs to match the internal impedance of the solar array if the system is required to operate close to the MPP of the solar array.
V+IR s I=I PV -Io exp Vt n
V+IR s -- -1 Rp
(1)
G 00
Where I and V are the PV cell current and voltage respectively, IPV is the photovoltaic current, Io is the reverse saturation current of diode, Vt = NskT/q is the thermal voltage of the array with Ns cells connected in series, k is the Boltzmann constant (1.3806*10-23J/K), T is the temperature of the p-n junction ,q is the electron charge and n is the diode ideality constant. IPV and I0 are given as follows[5]
Fig3 .PV Module I-V and P-V characteristics
G IPV ={[1+a(T-Tref )] ISC } 1000

3 n qEg 1 1
III.MPPT CONTROL ALGORITHM
--------- (2)
T nk Tref - T I0 =Io(Tref ) -----------------(3) e Tref

Where a is temperature coefficient of Isc, G is the given irradiance in W/m2 and Eg is the band gap energy (1.16eV for Si).The single PV module specification is given in table I. Fig.3 illustrates the electrical characteristics of the solar array under a given insolation and temperature. The internal impedance of the solar array is low on the right side of the curve and high on the left side. The
Power output of a Solar PV module changes with changes in solar insolation level and with varying temperature. As seen in the PV (power vs. voltage) curve of the module there is a single maxima of power. That is there exists a peak power corresponding to a particular voltage and current. We know that the efficiency of the solar PV module is low about 13%. Since the module efficiency is low it is desirable to operate the module at the peak power point so that the maximum power can be delivered to the load under varying temperature and insolation conditions. Hence maximization of power improves the utilization of the solar PV module [2,3]. A maximum power point tracker (MPPT) is used for extracting the
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operating point exceeds the peak power and deviate to the right side of the P-V characteristic curve, the power at the next instant will decrease, thus, the direction of the perturbation reverses [10]. Fig5 shows the direction of power variation as a result of perturbation.
maximum power from the solar PV module and transferring that power to the load. A dc/dc converter (step up/step down) serves the purpose of transferring maximum power from the solar PV module to the load. A dc/dc converter acts as an interface between the load and the module as shown in fig4. By changing the duty cycle of the converter the load impedance as seen by the source is varied and matched at the point of the peak power with the source so as to transfer the maximum power. PV Module DC-DC Converter Load
MPPT Controller
Fig5. Perturb and Observe algorithm
Fig4 Block diagram of typical MPPT system
A .Methods Of Peak Power Tracking. The peak power is reached with the help of a dc/dc converter by adjusting its duty cycle such that the resistance corresponding to the peak power is obtained. Now question arises how to vary the duty cycle and in which direction so that peak power is reached. Manual tracking is not possible so automatic tracking is preferred to manual tracking. An automatic tracking can be performed by utilizing various algorithms [4, 10] B. Various types of MPPT algorithms: a. Perturb and observe b. Incremental Conductance c. Parasitic Capacitance d. Voltage Based Peak Power Tracking e. Current Based Peak Power Tracking The algorithm changes the duty cycle of the of the dc/dc converter to maximize the power output of the module and make it operate at the peak power point of the module. C Perturb and Observe Algorithm There are several MPP tracking methods in the literature [4]. Among them Perturb and Observe (P&O) algorithm is most widely used, especially for low-cost and easy implementations [6]. In P&O algorithm, a small perturbation is introduced in every iteration to alter the duty cycle in order to force the operating point to move near the MPP. This algorithm compares the power measured in the previous cycle with the power of the current cycle to determine the next perturbation direction If the power increases due to the perturbation then the perturbation will remain in the same direction. If the
When the steady-state is reached, the operating point oscillates around the peak power as the MPP will perturb continuously. In order to keep the power variation small, the perturbation size is kept very small yet this will cause the system to respond slowly during transients. The flow chart for P&O algorithm is illustrated in the Fig.6 .
Fig 6 The flowchart of P&O MPPT algorithm
Fig 7 SIMULINK Model of P&O Algorithm
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sides. These nonpulsating load and source currents are desirable to minimise the EMI and filtering requirements. The SEPIC (Single Ended Primary Inductor converter) topology with PV module and MPPT controller is shown in fig9.and it is proposed the converter is operated in CCM [2].The inductance and capacitance values are designed from [9].This converter has two inductors and two capacitors. The capacitor C1 provides the isolation between input and output. The SEPIC converter exchanges energy between the capacitors and inductors in order to convert the voltage from one level to another. The amount of energy exchanged is controlled by switch, which is typically a transistor such as a MOSFET. Analysing the ON and OFF states SEPIC converter switch the dynamic equations of the converter can be derived as the following [1]
MATLAB/SIMULINK model of P&O Algorithm is shown in fig7. The fig8 shows the pulses to drive the SEPIC converter switch which is the result of simulation model of MPPT algorithm.
Fig 8 Pulse production from the MPPT controller
IV.DESIGN OF SEPIC CONVERTER
dI L1 Vin Vc1 +Vc2 = + (S-1) ----------- (4) dt L1 L1 V dIL1 VC1 = S+ 0 (S-1) ------------------- (5) dt L2 L2
dVC1 I L1 I = (1-S)- L2 S --------------------- (6) dt C1 C1 dVC2 IL1 +IL2 I = (1-S)- 0 ---------------- (7) dt C2 C2
Since the PV generator exhibits a nonlinear V-I characteristic, its maximum-power point (MPP) varies with the solar insolation and temperature. At a particular solar insolation, there is a unique operating point of the PV generator at which the power output is maximum. Therefore, for maximum utilization efficiency, it is necessary to match the PV generator to the load such that the equilibrium operating point coincides with the MPP of the PV source. However, since the MPP varies with insolation and seasons, it is difficult to maintain maximum power operation at all solar insolations without changes in the system parameters. To overcome this problem, use of an intermediate DCDC converter is proposed [3, 7], which continuously adjusts the voltage and current and matches the PV source to the load [3]. The important requirement of any DCDC converter used in the MPPT scheme is that it should have a low input-current ripple. Buck converters and their derived topologies will give pulsating currents on the PV array side and thus require a larger value of input capacitance on the array side. On the other hand, boost converters and their derived topologies will present low ripple on the SCA side, but the load current exhibits more ripple and gives a voltage higher than the array voltage to the downstream loads. The requirement of load voltage, either low or higher than the array voltage, can be realised by means of buck boost converters. However, with this converter the array and load currents are pulsating in nature. Furthermore, the load voltage will be inverted with buckboost or CUK converters. Under these circumstances single-switch fourth order topologies, the SEPIC converter, provide the buck boost conversion function without polarity reversal, in addition to the low ripple current on the source and load
Fig 9 SEPIC converter topology with PV and MPPT
Where S is the status of the switch (1 for ON, 0 for OFF), L1 is the input inductance, L2 is the output inductance, C1 is the energy transfer capacitor, C2 is the output capacitor, Vin is the input voltage, Vo is the output voltage, VC1 is the voltage across capacitor C1, IL1 is the current though L1 and IL2 is the current through L2. Using the equation (6) and assuming that duty cycle D is an averaged S, it can be determined that for steady state the following equation is true:
I L1 D Iin = = I L2 1-D I0
------------------------ (8)
Assuming an ideal converter in which the input power is the same as the output power, then:
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Pin =P0
Vin Iin =V0 I0
-------------------------------- (9) ------------------------------- (10)
Combining equation (8) and (10), the relationship between input and output voltage is:
V0 D = Vin 1-D
-------------------------------- (11)
The converter design specifications are given in table II.

TABLE II
SEPIC CONVERTER DESIGN SPECIFICATIONS
Parameter Input Voltage Output Voltage Output Current Output Power Duty Ratio Switching frequency
Value 36V 220V 4.5A 1000W 0.8 25KHz
Fig11 Simulated Results for load voltage, current and power without MPPT controller
VI.SIMULATION RESULTS AND DISCUSSIONS
PV module and MPPT controller are simulated in MATLAB/SIMULINK.The simulation of SEPIC converter with RLE load is done in PSIM software. Using simcoupler SIMULINK model is coupled with PSIM model. The simulation model is shown in fig10. The simulated results are compared for the converter with and without MPPT controller of PV module. For the purpose of the simulation, constant irradiance and temperature is considered for the PV module.
Fig 12 SIMULINK simulation model for PV source and SEPIC converter with MPPT controller
Fig10 SIMULINK simulation model for PV source and SEPIC converter without MPPT controller
Fig11 shows the simulation simulated results of PV source and SEPIC converter without MPPT controller. The output voltage, current and power waveforms are shown in the result.
Fig13 Simulated Results for load voltage, current and power with MPPT controller
The simulation results are shown for a constant temperature of 303K and irradiance of 1000 W/m2. Fig 12
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[10] C.Liu, B.Wu and R.Cheung ,Advanced Algorithm for MPPT Control of Photovoltaic Systems in proceedings on Canadian Solar Buildings Conference, Aug-2004 IX BIOGRAPHIES Santhi.K.P received the B.E degree in Electrical and Electronics Engineering from Government College of Engg, Salem,Tamil Nadu, India in 2005. Currently she is doing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu. Her area of interest includes power converters, PV energy conversion and electric drives. P.Sivaraman.received the BE degree in electrical and electronic engineering from Bharathiar University, Coimbatore ,Tamilnadu, India, in 2002 and the M.Tech. degree from the School of Electrical and Electronic Engineering SASTRA,University, Thanjur ,Tamilnadu,India,in 2004. Now pursuing PhD in Anna University of Technology Coimbatore. From 2004 onwards he was working with the Bannari Amman Institute of Technology, sathyamangalam,Erode,Tamilnadu,India,where his current research interest include power converter for photovoltaic application and distributed power generation for rural area applications. Dr.A.Nirmalkumar completed his graduation and post graduation in Electrical engg from Calicut and Kerala Universit in 1972 &1976 respectively. Completed his Doctorate from Bharatiar University in 1992 area of specialization includes Power converter for renewable energy application and drives. He has more than 30 years of teaching experience. He is guiding at present 20 research scholars. He is the recipient of Institution of Engineers Gold Medal for the year 1989. He has many publications in national and international journals to his credit
and 13 shows the simulation model and results of same circuit with MPPT controller. Without MPPT controller the boosted value of output voltage is 193.1V, Current is3.89A and Power value is 754.8W.With MPPT controller the boosted Values are 221.4V, 4.49A and 1000W respectively. From the simulated results, when temperature of the solar radiation falling on the PV module increases, PV module voltage will get reduced and PV module current will get increased proportionately. When irradiance value increases, both PV module voltage and current get increased. With the implementation of MPPT controller the load voltage, current and power values are increased.
VII.CONCLUSION
This paper presented the implementation of Perturb and Observe MPPT algorithm for PV cell applications. SEPIC converter is analyzed as interface circuit between PV module and the load. The PV module was simulated based on the mathematical expression that governs the PV module behavior. The SEPIC converter was used to boost the PV module voltage. Perturb and Observe MPPT algorithm is used to track the MPP of PV module which can be implemented easily. The output voltage of the SEPIC converter and hence the voltage across the load is increased with this MPPT algorithm implementation.
VIII.REFERENCES
E. E. Jimenez-Toribio, A. A. Labour-Castro and F.M.RoDriguez, Sensorless Control of SEPIC and Cuk Converters for DC Motors using Solar Panels in proceeding on Electrical Machines and Drives conference, IEMDC-09, 2009, pp 1503-1510. [2] R. B. Darla, Development of Maximum Power Point Tracker for PV Panels Using SEPIC Converter in proceeding on Telecommunications Energy conference, INTELEC 2007, pp 650655. [3] M.Veerachary and K. S. Shinoy, V2- Based Power Tracking for Nonlinear PV Sources , IEE proceeding on Electrical Power Applications, Vol. 152, No. 5, pp 1263-1270, September 2005. [4] Trishan Easram, Patrick L. Chapman, Comparison of Photovoltaic Array Maximum Power Point Tracking Techniques, IEEE Transactions on Energy Conversion, Vol. 22, No. 2, pp 439-449, June 2007. [5] M. G. Villalva, J.R. Gazoli, E. R. Filho, Comprehensive Approach to Modeling and Simulation of PV Arrays, IEEE Transactions on Power Electronics, Vo. 24, No. 5, pp 1198-1208, May 2009. [6] M.S. Jamri and T.C.Wei, Modeling and Control of a Photovoltaic Energy System using the State Space Average Technique in proceeding on American Journal of Applied Science-7, 2010, pp 682-691. [7] J.G. Llorente,E.I.Oritz-Rivera, A.S. Llinas, Analysing the Optimal Matching of DC Motors to Photovoltaic Modules via DC-DC Converters in proceedings on Applied Power Electronics conference (APEC) ,pp-1062-1068 [8] H.L.Tsai, Ci-Siang Tu and Yi-Jie Su, Development of Generalised Photovoltaic Model using MATLAB/SIMULINK in proceedings on World Congress on Energy and Computer Science WCECS2008, USA ,October-2008. [9] Datasheet of Design a SEPIC converter by National Semiconductor, May2006. [1]
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Intercell Transformer Based Converter for Renewable Energy Application

R.Malathy 1, J.Baskaran 2,C.Sharmeela3 1. PG Scholar, 2. Professor, 3. Assistant Professor Dept of Chemical Engg, Anna University Department of Electrical and Electronics Engineering Adhiparashakthi Engineering College, Melmaruvathur.
AbstractThis paper mainly focuses on the development of a low-input voltage high power realization of a boost converter with the aim to demonstrate the feasibility and the interest of topologies using intercell transformer. The intercell converter have the common mode inductance that is in continuous conduction mode the leakage inductance is slightly above the minimum feasible leakage inductance. Considering the above mentioned character of the intercell transformer based converter it is well suitable for high power low-voltage renewable energy applications, the ICT based converter constitute a good candidate in that field. The effectiveness of the designed circuit is verified by experimentation.
These specifications lead the authors to design an original converter, the ICT-based multicell flyback. This topology recently described in [6], seems in adequation with such specifications, but its relatively complex operation requires developing a specific know-how; the authors have thus tried to push the design one step further to evaluate more precisely the potential of this topology. In the first section, the basic properties of ICT-based multicell flyback are recalled. Other points of interest such as the design of the ICTs and the number of cells are then discussed in a second section. Last, the different steps of the design and the experimental results are described.
Keywords Intercell transformer, coupled inductor, flyback converter. I .INTRODUCTION
Intercell
converters are now widely used, especially for low-voltage/high-current applications. Among which voltage regulator module (VRM) is probably the most prominent example. Other emerging applications fields of these topologies are provided by systems connected to low-voltage energy sources and storage elements as photovoltaic (PV) arrays, fuel cells, batteries, ultracapacitors [1][5], especially when these systems are onboard and weight and space savings are required. The aim of this paper is to present the design and implementation of a converter with a high power density; the main function is to feed a 12 kW/300 V load from the 15 Vdc of an embedded network with galvanic insulation. The specifications of this converter for the considered application are as follows. 1) Input voltage: 15 Vdc. 2) Output voltage 300 Vdc. 3) Output power: 12 kW. 4) Weight: to be minimized.
Fig.1. General topology of the ICT flyback converter. II. INTERCELL TRANSFORMER The ICT flyback converter has been detailed in [6]. Fig. 1 displays the topology of such an ICT flyback converter with k cells. It has been shown that ICTs can be implemented either as monolithic devices or as separate devices [7][9]. The leakage inductances shown in Fig. 1 (l12) are related to the coupling coefficient between homologous primary and secondary windings.
Corresponding author: R.Malathy is with EEE Department of Adhiparasakthi Engineering College, Melmaruvathur Email:maluravi02@gmail.com
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components of currents ik and iDk are in opposition like in a standard transformer. A 1-D model including eddy-current effects can thus be applied to calculate the copper losses in each of the two groups i1 , iD1 and i2 , iD2 . The losses in the two groups are identical. The common-mode components have the same amplitudes in all four windings but they have different signs. The 1-D approach still applies if an equivalent primary composed the two windings of phase 1 and an equivalent secondary composed the two windings of phase 2 are considered. The total joule losses are then the sum of the losses generated by the two components (differential mode and common mode), and are thus, easily calculated. A complete design method of the ICT has been presented in [10]. It involves deriving from the specifications (power, ambient temperature, frequency, current ripple, winding geometry, etc.), the core and copper losses, the heat exchange area, the operating temperature and, in the end, the number of turns and all the dimensions of the ICT. The main idea leading to coupled inductors comes from the following analysis. An inductor is designed to reduce the high frequency current ripple generated by switching in power converters.Hence, ltering is all the more efcient than inductor hasa high inductance value. A DC or AC low frequency current also ows through inductors. These components bring the converter power as for example the DC current component at the input or output of a DCDC converter or the fundamental component in a DCAC or ACDC power converter. Note that there is generally no functional need of inductors for these particular current components. Nevertheless, these low frequency current components greatly inuence the energy stored by the inductor(-Wem=1/2Li 2) as the low frequency current represents a large amount of the total current. However, the inductor sizing directly depends on the maximum amount of stored energy. Hence, low volume inductors can be addressed for high current level by reducing the inductance value. These two items lead to an opposite conclusion. The rst one involves using a high permeability material whereas the second involves a low permeability material that gives a smaller inductance providing a size reduction but also a worse ltering efciency. We can notice that a classical inductance is a technological trade-off between these two limits. Hence, the main idea is to design a magnetic device that offers two possible magnetic paths, one with a low permeability for the low-frequency DC or AC components and the other with a high permeability for the switching harmonics. This can be achieved by coupling or in other words, by merging together the cores of interleaved converter separate inductors. Fig. 1 shows a possible implementation for such device. In this example, the multiphase coupled inductor is built on a ladder core structure [10]. The low permeability path can be either the different air paths, either one extra gapped leg or a leg realized in a low permeability material. If
Fig.2. Current distributions in the windings of ICT The design of ICT is somewhat specific especially because of the shape and the distribution of the currents among the different windings, as explained in [10]. This is summarized in Fig. 2 related to transformer TR2 . Since planar transformers are to be used, the four windings should be stacked vertically with an interval of height ha separating the windings of one phase from the windings of the other phase. The interval allows choosing the coupling between phases and thus the ICT common-mode inductance (the storage inductance). For one phase, the ac ampere turns can be split in two components: the differential-mode and common-mode components. As can be seen from the waveforms in Fig. 2, the differentialmode
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balanced uxes are desired, a symmetrical structure must be implemented in order to provide balanced reluctance of all magnetic paths (Fig.3). Such a device can replace tinductors of an interleaved converter (Fig.4). III.COUPLED INDUCTOR Two inductors or coils that are linked by electromagnetic induction are said to be coupled inductors. When an alternating current flows through one coil, the coil sets up a magnetic field which is coupled to the second coil and induces a voltage in that coil.[4] The phenomenon of one inductor inducing a voltage in another inductor is known as mutual inductance. Coupled coils can be used as a basic model for transformers, an important part of power distribution systems and electronic circuits. Transformers are used for changing alternating voltages, currents, and impedances, and to isolate one part of a circuit from another. Three parameters are required to characterize a pair of coupled inductors: two self inductances, L1 and L2, and the mutual inductance, L12 = M. Circuits which contain coupled inductors are more complicated than other circuits because we can only express the voltage of the coils in terms of their currents. The following equations are valid for the circuit above with the dot locations and reference directions shown. Assuming further, that the magnetic fluxes are linear functions of the coil currents, we can express the magnetic linkages of the two coils as: 1(t)=L11i1(t)+L12i2(t) 2(t)=L21i1(t)+L22i2(t) are the mutual inductances of the inductors. Thus the two coils can be modeled by a pair of coupled linear electrical inductors. The above equation can be re-writen as in matrix form: =L According to Faraday's law, voltages across the inductors V1(t)=d1/dt+R1i1 V2(t)=d2/dt+R2i2 Hence, by differentiating the above equations =L +R Fig.4. Implementation of a balanced multiphase coupled inductor Fig.3.shows a possible implementation for such device. In this example, the multiphase coupled inductor is built on a ladder core structure .The low permeability path can be either the different air paths, either one extra gapped leg or a leg realized in a low permeability material. If balanced fluxes are desired,a symmetrical structure must be implemented in order to provide balanced reluctance of all magnetic paths. Fig.3.Implementation of a coplanar multiphase coupled inductor Where, R=
By energy considerations it is established that in general Where, L21 = L12 = M M 0 is the coupling factor. Hence, L is a symmetric matrix. Instead of the coupling factor M , mutual inductance is often expressed in terms of also the coefficient of coupling.
Is often used to express mutual inductance. Note, K1 For K=1, when the coupling is termed ideal.
that
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Fig.5. Intercell transformer fluxes Fig.4,and Fig.5, shows a DC components and harmonics at k x q x f, with an integer, lead to in-phase fluxes in all the vertical rods of the device and will add up in the common return branch (i.e. the high reluctance area) as depicted in the magnetic circuit model of the coplanar multiphase coupled inductor of Fig. 3These properties meet our requirement as we obtain a low inductance value for the dc component and a large inductance value for almost all alternating components except for harmonics at k x q x f,
Fig .7.Output waveform. The above waveform shows a low input DC voltage of 15v and the corresponding simulated DC output voltage of 300v.
IV.SIMULATION CIRCUIT OF INTERCELL TRANSFORMER BASED CONVERTER

K K1 Kbreak COUPLING = 0.99 K K2 Kbreak COUPLING = 0.99 K K3 Kbreak COUPLING = 0.99 K K4 Kbreak COUPLING = 0.99
1 1 2 L1 L9 1 2 L3 L11 2 2 1 2 1 1 L5 L13 L7 L15 2 1 2
V. CONCLUSION
M1 V1 = 0 V2 V2 = 5 IRF840 TD = 0 TR = 1ns TF = 1ns PW = 1u PER = 2u M2 V1 = 0 V3 V2 = 5 IRF840 TD = 1us TR = 1ns TF = 1ns PW = 1u PER = 2u M3 V4 V1 = 0 V2 = 5 IRF840 TD = 1us TR = 1ns TF = 1ns PW = 1u PER = 2u M4 V5 V1 = 0 V2 = 5 IRF840 TD = 0 TR = 1ns TF = 1ns PW = 1u PER = 2u
V1 15
A new ICT based dc/dc converter has been presented. The operation, analysis and design considerations were illustrated. Simulation results were shown to verify the operating principle. It is shown that this converter can boost up the voltage with low output inductance therefore the reverse recovery problem is reduced also switching losses. The circuit analysis is presented. The high switching frequency involved in this scheme results in less switching losses. VI. ACKNOWLEDGEMENT The work described in this paper is substantially supported by the management of Adhiparasakthi Engineering College and faculty members of Electrical and Electronics Engineering.
2 L2 L10
2 L12 L4
2 L6 L14
2 L8 L16
2
V-
R1 100k
C1 .99n D1 MUR150 D2 MUR150 D3 MUR150 D4 MUR150
V+
Fig.6 Simulation circuit of ICT based converter In the above boost converter circuit diagram the switch used for simulation is MOSFET,coupling co-efficient K is 0.99. And for this proposed simulation circuit, the DC input voltage is 15v.
VII. REFERENCES [1] F. Z. Peng, H. Li, G.-J. Su, and J. S. Lawler, A new ZVS bidirectional DCDC converter for fuel cell and battery application, IEEE Trans.Power Electron., vol. 19, no. 1, pp. 5465, Jan. 2004. [2] F. Blaabjerg, Z. Chen, and S. B. Kjaer, Power electronics as efficient interface in dispersed power generation systems, IEEE Trans. Power Electron., vol. 19, no. 5, pp. 11841194, Sep. 2004.
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[3] H.-J. Chiu and L.-W. Lin, A bidirectional DCDC converter for fuel cell electric vehicle driving system, IEEE Trans. Power Electron., vol. 21, no. 4, pp. 950958, Jul. 2006. [4] H. Xiao and S. Xie, A ZVS bidirectional DCDC converter with phaseshift plus PWM control scheme, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 813823, Mar. 2008. [5] R.-J. Wai, C.-Y. Lin, C.-Y. Lin, C.-Y. Lin, R.-Y. Duan, and Y.-R. Chang, High-efficiency power conversion system for kilowatt-level stand-alone generation unit with low input voltage, IEEE Trans. Ind. Electron., vol. 55, no. 10, pp. 37023714, Oct. 2008. [6] F. Forest, T. Meynard, E. Laboure, V. Costan, and J.-J. Huselstein, A multi-cell interleaved flyback using intercell transformers, IEEE Trans. Power Electron., vol. 22, no. 5, pp. 16621671, Sep. 2007. [7] P. J. Li, A. Stratakos, A. Schultz, and C. R. Sullivan, Using coupled inductors to enhance transient performance ofmulti-phase buck converters, in Proc. APEC2004, vol. 2, pp. 12891293. [8] P. Zumel, O. Garcia, J. A. Cobos, and J. Uceda, Tight magnetic coupling in multiphase interleaved converters based on simple transformers, in Proc. APEC2005, vol. 1, pp. 385391. [9] F. Forest, T. Meynard, E. Laboure, V. Costan, A. Cunière, and T. Martire, Optimization of the supply voltage system in interleaved converters using intercell transformers, IEEE Trans. Power Electron., vol. 22, no. 3, pp. 934942, May 2007. [10] F. Forest, E. Laboure, B. Gelis, V. Smet, T. Meynard, and J.-J. Huselstein, Design of intercell transformers for high power multicell interleaved flyback converter, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 580591, Mar. 2009.
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Mitigation of Back-Flashovers for 110-kV Lines at Multi-Circuit Overhead Line Towers A.Brighty Deborahl, M.Shanmugapriya, B.Subhanandhini,
M.Tech(PE&D), karunya university, brightydeborahl@gmail.com M.Tech(PE&D), karunya university, shanmupriya88@gmail.com M.Tech(PE&D), karunya university,
subhanandhini.be@gmail.com
Abstract--An increase of back-flashovers in a

110-kV system has been observed along an overhead line route that consists of multicircuit transmission towers of voltage levels 380-kV, 220-kV and 110-kV at the same tower. The height of multi-circuit towers varies in the range of 55 88 m. The 110-kV double circuit line is positioned at the lowest cross-arm of the tower as shown in Fig. 1 In the previous work back-flashover analysis was performed to identify which towers of the 5.2-km line route are rather prone to backflashovers of the 110-kV insulation As outcome of that work one insulator string of a duplex line insulator was replaced by a surge arrester at the selected towers of that route to reduce back-flashover rate of the 110-kV line. In the present paper a different mitigation method for back flashovers across 110-kV insulation strings is proposed. An additional ground wire is proposed to be installed along that 5.2-m line route in order to reduce the lightning overvoltages across the line insulators. Keywords: flashover, back-flashover, lightning stroke, lightning surge, transmission tower, EMTP. I. INTRODUCTION The tripping of a 110-kV double-circuit overhead line was increased in a certain region at thunderstorms, where relatively tall multicircuit transmission towers were installed. The multi-circuit transmission route consists of 380kV, 220-kV and 110-kV overhead lines at the same tower.Lightning strokes registered by lightning flash counters in this region showed a maximum stroke current of 90 kA. The high frequency measurement of the tower footing resistance with a 26-kHz measuring current has
revealed that the resistance value is relatively high at the three towers. A back-flashover analysis was performed which towers of that 5.2-km line route are rather prone to back-flashovers of the 110-kV insulation strings depending on different factors like tower footing resistance, tower surge impedance, tower height, etc [1], [2]. A measure to prevent back-flashovers is to replace oneinsulator string of a duplex line insulator by a surge arrester. It has been shown in a previous paper [1] line surge arresters can be successfully utilized to prevent backflashovers across 110-kV phase insulators at endangered towers. For lightning stroke 2009current amplitudes greater than 90 kA, flashover may occur at the adjacent towers due to discharge current of operated surge arresters, when the phase conductors at those towers are not equipped with surge arresters. Another method for the mitigation of backflashovers at the110-kV overhead lines on the same multi-circuit towers would be to install an additional ground wire as close as possible to the phase wires of the two 110-kV systems along that route with high risk of back-flashovers. By the additional ground wire near to the 110-kV phase wires the amplitude of lightning overvoltages appearing between the tower and phase wire can be reduced. A part of the lightning surge travelling along the tower enters into that additional ground wire and will be coupled through the capacitance between the ground wire and phase wires to the phase wires of the 110-kV system. Thus, the surge voltage difference appearing between the 110-kV phase wires and the tower will be reduced resulting in less back-flashover probability. The transients program EMTP-ATP [3] with the integrated simulation language MODELS is used to model the whole system to analyze lightning surge
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phenomenon on overhead lines as reported several times in publications [4], [5]. II. MODELING METHOD The modelling methods for the back-flashover analysis applied in this paper are based upon various publications in this field [3], [6] [9]. Since the modelling of the transmission system was described in detail in the previous papers [1], [2], here only a brief summary will be given.
A. Multi-Circuit Towers
The height of multi-circuit towers varies in the range of 55-88 m. The tower structure also varies from tower to tower along the 5.2-km route. The layout of a typical suspension tower is shown in Fig. 1. The distances are given in meters. The upper two cross-arms carry at left and right side a 220-Kv and 380-kV singlecircuit line, respectively. A 110-kV doublecircuit line is suspended from the lowest crossarms. Fig. 2 shows the location of the proposed additional ground wire at the tower. The tower is represented by loss-less Constant-Parameter Distributed Line (CPDL) model [3]. The propagation velocity of a traveling wave along a tower is taken to be equal to the light velocity [4], [10]. The surge impedance of the tower is calculated according to the formula given in [10] for the waisted tower shape [1], [12]:
R=
r1h2 + r2 h + r3 h1 where h = h1 + h2 h
R Z t waist = 60. ln cot{.5 tan 1 ( )} h R=
Fig. 1. Layout of a typical Fig. 2. The location of the additional ground wire at the tower multicircuit suspension tower For a tower of 76.5m height(1) deliver the following value Z t waist = 233.3 It is recommended in Japan [4] to consider frequencydependent effects for wave propagation along towers, when the tower footing impedance is represented by a linear resistance, which is the case in this study. The tower model consisting of CPDL model sections is added by RL parallel circuits at each section to represent traveling wave attenuation and distortion. The calculation of RL values is given in [1] based on [4]. The cross-arms are not represented in the tower model. B. Number of Towers Total 19 towers of a part of a line route shown in Fig. 4 are represented including all overhead lines. Direct lightning strokes to towers between tower #1 and #12 are analyzed. C. Transmission Lines All overhead lines at the same tower are represented by the CPDL model at f= 400 kHz. Ground wire is represented like a phase wire. Data of the conductors are: - 380 kV: 4 conductors/phase, ACSR 265/35 Al/St - 220 kV: 4 conductors/phase, ACSR 265/35 Al/St - 110 kV: 1 conductor/phase, ACSR 265/35 Al/St - ground wires: AY/AW 216/33 (aerial cable). (1)
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Fig. 3. Modelled part of the transmission line route with a junction at tower #1 (GW: ground wire, AGW: addional ground wire) In order to take into account the effect of the AC steadystate voltage of the lines on a lightning surge, the transmission lines are connected to AC voltage sources via multiphase matching impedance (surge impedance matrix).
D. Lightning Current and Impedance

The lightning stroke is modeled by a current source and a parallel resistance of 400 , which represents the lightningpath impedance [4]. Two different lightning current waveforms are used to represent a) first stroke and b) the subsequent strokes: a) CIGRE waveform of concave shape with front time, 3 s f T and time to half value, 77.5 s h T b) Linear ramp waveform with 1 s f T and 30.2 s h T Fig. 4 shows both current waveforms with a magnitude of 50 kA.
Fig. 4. CIGRE concave waveform and linear ramp function for lightning current representation, I = 50 kAIn this study three flashover models are applied for comparison purposes [1]: 1) Equal-area criterion by Kind [8], [10], [16]; 2) Leader development method by Pigini et al. [10],[15]. 3) Leader development method by Motoyama [6], [14]. 3 Wave deformation due to corona is not considered in the lightning surge simulations. The surge propagating on the ground wire can be normally deformed by corona. In this paper it is assumed that the lightning stroke terminates at the tower . The criterion by kind require two parameter U0 and f.it is tested simply by evaluating the following internal numerically.
[u (t ) u ] dtF
0
E. Flashover Models
Flashover models estimate the breakdown of the air between the arcing horns of the line insulators under nonstandard wave forms.
Where u(t) is the voltage waveform across the insulator When the time integral of the voltage difference (u U0) becomes greater than the value of F, then at t = tflo the flashover occurs. The unknown parameters U0 and F can be obtained from the 50 % sparkover volt-time characteristic of the insulator [1], [16]. The unknown parameters in (2) are determined according to [18]U 475.42 kV , F 0.304 Vs .
2) Leader development method by Pigini et al.

The flashover condition is estimated by the imposed voltage across the air gap. The leader onset condition is given as [13]
313
kV/m, 410 As/m, 2.5 m/(Vs) and 0.42 m/(Vs), respectively. The breakdown occurs when x LAVE attains D/2. If the applied voltage u(t) becomes less than E 0 .( D 2 x LAVE ) during the leaderdeveloping process, the leader is considered to stop its development. In this paper Motoyamas leader development method is presented as a nonlinear resistance using Thevenin-type user defined component in EMTP-ATP [3]. The interface of the leader model with the remaining circuit is shown in Fig. 5. Fig. 5.
0 ( ) p u t E D (3) where D is the gap length and 0 670 kV m p E . The equivalent leader-developing velocity vl (m/s) is computed according to following equation, which was evaluated by several measurements [15]:
where ll is the leader length in meter; u(t) is the voltage imposed to the air gap. The leader length is obtained by the integral of leader-developing velocity:
The breakdown occurs, when the leader length ll is equal to the gap length D.
3) Leader Motoyama
development
method
by
The flashover model by Motoyama [6], [14] is developed for short tail lightning impulse voltages based on experiments for 1m3m gap lengths. It is the only model, where the leader development can be modeled as a nonlinear resistance which interacts with the remaining circuit. The leader onset condition for positive polarity is used:
Interaction between the leader and electric circuit represented by Iterated-type component The voltage u(t) in (7) is equal to vth (Thevenin voltage seen from the leader). Since the leader current, iL is determined for a given u(t), the leader resistance, rL is calculated by the equation
where u(t) is the imposed voltage between archorns and D is the gap length in meter. Ts is the streamer developing time(=leader onset time). The leader developing process is defined by following equations:
The actual leader current, iL in Fig. 6 is calculated as follows:
where iL is the leader current; x LAVE is the average value of the leader-developing length; and Value is the leader developing velocity. The constants E0, K0, K1A, K1B are set to 750
To show how Motoyamas leader model performs, a lightning stroke to the tower #8 is simulated, where CIGRE wavefom with I = 75 kA is used. The lightning stroke causes a flashover across the 110-kV line insulator as shown in Fig. 7. The leader current starts to grow until breakdown, which is indicated by the vertical dashed line in Fig. 6.4
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Fig. 7. Comparison of the waveforms of a lightning surge across 110-kV line insulator with and without AGW A systematic analysis is performed as explained in [1] in order to determine back-flashover performance of the 110-kV system in the presence of the additional ground wire. Following two lightning current waveforms are injected to each tower in question. CIGRE waveform, I 20 90 kA; 3 s / 77.5 s Linear ramp function, I 20 90 kA; 1s / 30.2 s . The current amplitude has been increased in 5 kA steps from 20 kA up to 90 kA and backflashover across the 110- kV insulators has been examined simultaneously by the three flashover models. The simulation results are compared in figures 8 and 10 for the lightning current waveform CIGRE. In those diagrams the minimum lightning peak current is shown that causes a backflashover at the 110-kV insulator. The comparison is made between the cases with and without AGW for the three backflashover models by Kind, Pigini and Motoyama. In figures 11 to 13 the minimum lightning peak currents of linear ramp type (1/30.2 s) are compared between the cases with and without AGW for the three flashover models by Kind, Pigini and Motoyama. The results presented in the figures 8 to 13 show the amplitudes of the minimum lightning peak currents causing backflashover for the case with AGW are at least 10 kA higher than the case with only one ground wire. At the last two towers #11 and #12 there is no difference because the additional ground wire is considered to exist between towers #1 and #10.
Fig. 6. Flashover across the 110-kV line insulator at tower #8 for a lightning stroke with CIGRE waveform and I = 75 kA according to the leader development method by Motoyama 4) Representation of the Air Gap Breakdown The discharge in the air gap can be represented by a timedependent arc resistance, decreasing linearly from 10 to 1 in 0.1 s and to 0.1 in 1 s.
III. COMPARISON OF THE BACKFLASHOVER PERFORMANCE

The additional ground wire (AGW) as shown in Fig. 2 is considered to exist between towers #1 and #10. The influence of the AGW regarding the amplitude of the lightning surge voltage appearing across the 110-kV line insulators is for the inner (close to the AGW) phase wires higher than for the outer phase wires (far to the AGW). The effect of the additional ground wire on the lightning surge appearing across the 110kV insulator compared to the case without additional ground wire is illustrated in Fig. 7 for a lightning stroke to tower #3 with I = 60 kA and the waveform. Hereby the outermost phase wire is selected as worst case.
315
Fig. 11. Comparison of the minimum lightning peak currents of linear ramp type (1/30.2 s) causing back-flashover at the 110-kV insulators for the cases with and without AGW. Flashover model by Kind.
Fig. 8. Comparison of the minimum lightning peak currents of CIGRE waveform (3/77.5 s) causing back-flashover at the 110-kV insulators for the cases with and without AGW. Flashover model by Kind.
Fig. 9. Comparison of the minimum lightning peak currents of CIGRE waveform (3/77.5 s) causing back-flashover at the 110-kV insulators for the cases with and without AGW.
Fig. 12. Comparison of the minimum lightning peak currents of linear ramp type (1/30.2 s) causing back-flashover at the 110-kV insulators for the cases with and without AGW. Flashover.
Fig. 10. Comparison of the minimum lightning peak currents of CIGRE waveform (3/77.5 s) causing back-flashover at the 110-kV insulators for the cases with and without AGW. Flashover model by Motoyama.
Fig. 13. Comparison of the minimum lightning peak currents of linear ramp type (1/30.2 s) causing back-flashover at the 110-kV insulators for the cases with and without AGW. Flashover model by Motoyama. Taking the probability distribution relation for lightning crest current magnitudes according to IEEE [11]
into consideration, the reduction in the probability of lightning strokes causing back-
316
line, which is a part of a multi-circuit transmission route. Two different lightning stroke current waveforms have been applied. The backflashover performance is estimated by means of three different flashover models. The effectiveness of the additional ground wire as a mitigation method has been shown by comparison of the back-flashover performance with and without additional ground wire. The probability of the back-flashovers can be reduced significantly by this mitigation method. When the mitigation techniques 1) replacement of one insulator string by surge arresters and 2) additional ground wire, are compared with each other, following pros and cons can be stated as a summary for both techniques: At each tower 6 surge arresters are required for the double-circuit 110-kV overhead line. In order to prevent flashovers at the adjacent towers due to discharge current of operated surge arresters, surge arresters should be installed successively at each tower in the endangered area with high lightning activities. Consequently the resulting investment cost of this method is high. On the other hand, the probability of back-flashovers will be reduced substantially. The installation of an additional ground wire along the endangered overhead line route requires less investment, but the protection degree against back-flashovers is not so high compared to the solution with surge arresters, although the probability of flashovers can be reduced significantly by an additional ground wire as proposed inthis paper.6
flashover can be estimated. For example, or the mostly endangered tower #3 according to Fig. 8 (CIGRE waveform; flashover method Kind) the probability of back-flashovers is as follows: with only one GW: p(i45kA)27.5 % with additional GW: p(i60kA)15.2 % Table 1 compares mean back-flashover probabilities over 10 towers for the cases with one (1-GW) and two (2-GW) ground wires regarding flashover models and current waveforms.
For the lightning current waveform CIGRE approximately the probability of back-flashovers will be halved, if an additional ground wire can be installed. A reduction of backflashover probability of approximately 25 % is expected for the steep ramp current waveform
IV. CONCLUSION
A different method for the mitigation of backflashovers at the 110-kV overhead lines on the same multi-circuit towers has been presented in this paper compared to previous work [1], [2]. An additional ground wire as close as possible to the phase wires of the two 110-kV systems along the line route with high risk of backflashovers can reduce the amplitude of the lightning surge across the 110-kV line insulator. A systematic flashover analysis has been performed for a 110-kV double-circuit overhead
V. REFERENCES
317
[10] CIGRE WG 33-01: Guide to Procedures for Estimating the Lightning Performance of Transmission Lines, Technical Brochure, October 1991. [11] IEEE Working Group on Lightning Performance of Transmission Lines: A Simplified Method for Estimating Lightning Performance of Transmission Lines, IEEE Trans. on Power App. & Systems, Vol. PAS104, No. 4, pp. 919-927, April 1985. [12] Chisholm, W. A.; Chow, Y. L.; Srivastava, K. D.: Travel Time ofTransmission Towers, IEEE Trans. on Power App. and Systems, Vol. PAS-104, No. 10, S. 2922-2928, Oktober 1985. [13] IEEE Working Group on Estimating the Lightning Performance of Transmission Lines: IEEE Working Group Report Estimating Lightning Performance of Transmission Lines II Updates to Analytical Models, IEEE Trans. on Power Delivery, Vol. 8, No. 3, pp. 12541267, July 1993. [14] Motoyama, H.: Experimental study and analysis of breakdown characteristics of long air gaps with short tail lightning impulse, IEEE Trans. on Power Delivery, Vol. 11, No. 2, pp. 972-979, April 1996. [15] Pigini, A.; Rizzi, G.; Garbagnati, E.; Porrino, A.; Baldo, G.; Pesavento, G.: Performance of large air gaps under lightning overvoltages: Experimental study and analysis of accuracy of predetermination methods, IEEE Trans. on Power Delivery, Vol. 4, No. 2, pp. 1379- 1392, April 1989. [16] Fernandes, M.; Correia de Barros, M. T.; Ameida, M.E.: Statistical Study of the Lightning Overvoltages at a Gas Insulated Station Transformer, Proceedings IPST 1995 (International Conference on Power System Transients), Lisbon, 3-7 September 1995. [17] Koettniz, H.; Winkler, G.; Wenigk, K.-D.: Fundamentals of Electrical Operational Phenomena in Electrical Power Systems, (original title in German: Grundlagen elektrischer etriebsvorgnge in Elektroenergiesystemen), Deutscher Verlag fr Grundstoffindustrie, Leipzig, 1986.
[1] M. Kizilcay and C. Neumann, Backflashover Analysis for 110-kV Lines at Multi-Circuit Overhead Line Towers, Proc. International Conference on Power Systems Transients (IPST07), June 4-7, 2007, in Lyon, France. [2] M. Kizilcay and C. Neumann, Mitigation of common mode failures at multi circuit line configurations by application of line arresters against back-flashovers, presented at the CIGRE-Symposium on Transient Phenomena in Large Electric Power Systems, April 18-21, 2007, Zagreb, Croatia. [3] Canadian/American EMTP User Group: ATP Rule Book, distributed by the European EMTPATP Users Group Association, 2008. [4] Ametani, A.; Kawamura, T.: A Method of a Lightning Surge Analysis Recommended in Japan Using EMTP, IEEE Trans. on Power Delivery,Vol. 20, No. 2, pp. 867-875, April 2005. [5] Yamada, T.; Mochizuki, A.; Sawada, J.; Zaima, E.; Kawamura, T.;Ametani, A.; Ishii, M.; Kato, S.: Experimental Evaluation of a UHV Tower Model for Lightning Surge Analysis, IEEE Trans. on Power Delivery, Vol. 10, No. 1, pp. 393-402, Jan 1995. [6] H. Motoyama, K. Shinjo, Y. Matsumoto, N. Itamoto: Observation and analysis of multiphase back flashover on the Okushishiku test transmission line caused by Winter lightning, IEEE Trans. On Power Delivery, Vol. 13, No. 4, pp. 1391-1398, October 1998. [7] Dommel, H. W.: EMTP Theory Book, Bonneville Power Administration, conversion into electronic format by Can/Am EMTP User Group in 1995. [8] Schmitt, H.; Winter, W.: Simulation of Lightning Overvoltages in Electrical Power Systems, Proceedings IPST 2001 (International Conference on Power System Transients), Riode Janerio, June 24-28, 2001. [9] IEEE Fast Front Transients Task Force, Modeling and Analysis of System Transients Working Group: Modeling Guidelines for Fast Front Transients, IEEE Trans. on Power Delivery, Vol. 11, No. 1, pp. 493- 506, Jan. 1996.
319
Modeling and FEM Analysis of Surface Mounted Permanent Magnet Generator for Wind Energy Conversion System
R. Ashok Kumar1, R. Bharanikumar2 and A.Nirmalkumar ashok8308@gmail.com, bharani_rbk@rediff.com
3
Bannari Amman Institute of Technology, Sathyamangalam, India induction generators are used in wind power conversion systems: cage rotor, wound rotor with slip control and doubly fed induction rotors. The last one is the most utilized in wind speed generation because it provides a wide range of speed variation. However, the variable-speed directly-driven multi-pole Permanent Magnet Synchronous Generator (PMSG) wind architecture is chosen. The disadvantages of SCIG are the speed is not controllable and variable only over a very narrow range, in which only speeds higher than the synchronous speed are possible for generator operation. Because a higher slip means a higher dissipation of electrical energy in the rotor bars. A three-stage gearbox in the drive train is necessary for this wind turbine concept. Gearboxes represent a large mass in the nacelle, and also a large fraction of the investment costs. It is necessary to obtain the excitation current from the stator terminal of SCIG. This makes it impossible to support grid voltage control. In most cases, capacitors are connected in parallel to the generator to compensate for the reactive power consumption The other type of induction generator is woundrotor or doubly-fed type, termed as doubly-fed induction generator (DFIG). The expression doubly-fed applies generally to machines where electrical power can be fed or extracted from two accessible windings. Generally, the stator winding is connected to the grid and the rotor winding is connected to bidirectional power converter. Although, it has been extensively investigated for wind energy applications, but requires two excitation sources, one on stator and the other on rotor. DFIG requires sophisticated control but still inefficient due to additional losses III. DIRECT DRIVEN CONCEPT Compared to the geared drive concepts, directdrive concepts may be more attractive due to the advantages of simplified drive train and higher overall efficiency, reliability and availability by omitting the gearbox. Especially, most of larger machines are intended for offshore use where the trend has been toward very low maintenance designs. On the other hand, in various wind power generators, permanent magnet (PM) machines have
Abstract: This paper presents the electromagnetic design process and methodology, with an emphasis of finite element method and design procedure of a Permanent Magnet Generator (PMG) for Wind Energy Conversion Systems (WECS). FEM is used to study PMGs flux distribution and generated voltage for different rotor magnet topologies and shapes for various rotor speeds. By using the results and analysis we select the particular rotor configuration for direct driven applications. The results of PMG have been reported in this paper. Key words: Finite Element Method, Permanent Magnet Generator, direct driven wind turbines. I. INTRODUCTION Energy shortage and environment pollution are the important problems for the human lives and social development. Traditional mineral energy such as coal, oil and gas will be used out in a few years and will cause serious environmental problems. So the renewable energy, especially wind energy and solar energy have become more and more considerable all over the world. Consumption of energy based on fossil fuels is considered to be the major factor for global warming and environment degradation. The utilization of naturally occurring renewable energy sources as an alternative energy supply has been assuming more importance of less Power generation utilizing solar rays, geothermal energy, wind force and wave force has became a reality. Research on performance improvement of and cost reduction in such nonconventional energy conversion systems is being accorded the highest priority. Wind power generation has a strong connection to rotating machinery and hence its practical application is most promising. II. GENERATORS FOR WECS Both induction and synchronous generators can be used for wind turbine systems. Mainly, three types of
320
currents independent of stator parameters. As the rotor magnets and stator q and d axis are fixed in space that the winding inductances do not change in reference frames. Figure 1 & Figure 2 describes the dq model of PMG with rotor reference frame.
higher ratio of power to weight, reliability, and efficiency than electrically excited machines. In addition, the use of PM machines becomes attractive than before, because the performance of PM materials is improving and the cost of PM materials is decreasing in recent years. Therefore, these advantages and trends may make direct drive PM wind generator systems more attractive for wind turbine concepts, especially for offshore applications IV. MODELING OF DDPMG In wind power applications, multipole permanent magnet generators have become very attractive especially in small ratings. Developments in magnetic materials, on the other hand, enabled remanence levels up to 1.2T by using convenient NdFeB magnets resulting in competitive design of peripheral'' type generator structures. Such a design tends to replace the traditional ìnternal'' configurations involving ferrites. The magnet cost remains the most important concern in medium scale applications To predict steady state and transient behavior of the PMG a precise model of the machine is needed. The model should be used to find the dynamic response of the machine. The dynamic model considers the instantaneous effects of varying voltages, currents, stator frequency and torque disturbances. The dynamic model of the PMG is derived by using two phase machine in direct and quadrant axis. q-axis is 90 ahead of the d-axis with respect to the direction of rotation. This approach is desirable because of conceptual simplicity obtained with two sets of windings one on the stator and the other on the rotor. [8] The wind turbine drives a PMG whose terminal voltage equations can be described by the following set of matrix form
Fig.1. Direct axis model of PMG
Fig.2. Quadrature axis model of PMGs The expression for the electromagnetic torque in the rotor reference frame may be written as
3 P Te = ( Ld -Lq ) i q i d - mi q 2 2
(4)
[ Vabc ] =- [ R abc ][iabc ] + [ abc ]
(1)
The relationship between the rotor angular velocity of the generator r and the mechanical angular velocity of the rotor
The generator model is implemented entirely in dq-coordinates. That is to say, there are no AC-states in the model. The generator is modeled with dc voltages and currents in a rotor fixed rotating coordinate system with the d-axis being in the direction of the flux from the permanent magnets. The equations for the d- and q-axis voltages are as follows:
may be expressed as:
r =
P m 2
(5)
The rotational speed and torque may be related as:
Ti =J
d Vd =-R si d -Ld i d +r Lq i q dt d Vq =-R si q -Lq i q -r Ld i d +r m dt
m
(2) (3) following:
dm -Te dt
(6)
is inserted into equation (6) to get the
2 Ti =J r -Te P
(7)
The input torque corresponds to the torque (9) developed by the wind turbine. The output voltage from the PMG is sinusoidal so that,
Rotor reference frame is chosen because the position the rotor magnet determines the induced emfs and
321
the requirement. These are surface mounted permanent magnet synchronous machine, surface inset permanent magnet synchronous machine, Interior embedded permanent magnet synchronous machine, Interior embedded permanent magnet with circumferential orientation synchronous machine. It is designed, analyzed and visualized the different rotor topology models in Magnet software.
Va =Vs cos r
(8) (9) (10)
Vb =Vs cos r -1200

c s r
( ) V =V cos ( +120 )
0
Expressing the equation (8), (9) and (10)in a rotor reference frame may write: Vq =Vs (11)
Vd =0
(12)
Under the assumption of uniform air gap, the self inductance are independent of angular position, hence they are constant. For practical PMG, Ld = Lq = Ls . Under this assumption, substituting (11) and (12) into (2), (3) and (4) the voltage equation in q-axis and electromagnetic torque may be written:
Fig.3 Different type of configurations
( R s +Ls )2 +r 2 ( Ls )2 Vq =- i q +r m (13) R s +Ls 3 P Te = - mi q (14) 2 2

If
r 2 ( L s )2
is neglected then the equation (19) is linear. (15)
Then the equation may be rewritten as:
Vs =- ( R s +Ls ) i q +r m
V. GENERAL DESIGN PROCEDURE Determine application requirements. Rotor topologies. Select magnet grade. Select numbers of poles. Select number of stator slots and phase. Perform rough sizing estimate. Select air gap length and determine magnet loading 8. Lay out stator lamination dimensions 9. Solve for numbers of conductors and turns/coil 10. Calculate wire size, resistance and inductance/ phase. 11. Calculate performance. 12. Check temperature rise, current density, flux densities, demagnetization of magnet. 13. Modify design and reiterate until objective are met. 14. Mechanical design consideration. The next step of the design process involves the selection of the rotor configuration. Hence study is performed to determine which type of rotor configuration is best fit for 1. 2. 3. 4. 5. 6. 7.
Many factors will influence the accuracy of the design, which make the design complicated and time consuming, especially for new and special constructions. Some factors may be derived analytically with experience to modify the coefficients, while other factors cannot be derived theoretically. In those cases, numerical computation must be applied. In this paper, some critical coefficients like leakage coefficient and armature reaction coefficient, are and then numerically modified FEM by using Magnet software. For constant electric and magnetic loadings the increase in diameter (D) increases both current and flux. But the increase in Length (L) increases the flux alone. Hence the output power is proportional to D2L. It reflects the influence of size on the output power of the machine. The standard mathematical equations used in the design of PMGs are the wind speed, desired output voltage and power output. All designs were optimized to get high flux density in the air gap and obtained high efficiency. VI. PMGS CONFIGURATIONS Basically, Permanent Magnet synchronous generators can be divided into radial-flux and axial-flux machines, according to the flux direction in the air gap. The PMGs having various rotor topologies models form the comparison of different generator topologies for wind energy system and it is inferred that cost/torque of radial flux permanent magnet generator is superior to other generators. Radial flux generator uses less magnetic material over other permanent magnet generator. The cooling condition of the magnets is high in outer rotor radial flux machine. The rotational speed of a wind turbine varies between 30 and 1500 rpm, depending upon the size and speed of wind turbine and speed of the wind, but electricity has to be produced in the normal frequency range of 30 to 80 Hz. Because of the necessity to run the generator at unusually low rpm direct coupling results in a large
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diameter and more number of poles .The stator can be designed using the normal design procedure. VII. ANALYSIS OF PMG Due to the magnetic symmetry in the generator, only a fraction of the entire machine needs to be discredited in the finite element model, as shown in Figure 4
Fig. 6 Flux density showing colour code values
Fig. 4 Discretization of mesh model for PMG design.
With nonlinear BH curves of magnetic materials, excitation currents in stator and rotor windings, and boundary conditions provided, the magnetic potential distribution was solved by the FEM and is depicted in Figure 4. From the magnetic potential solutions at various field current excitations and stator-rotor positions for different geometrical combinations, other electrical and magnetic parameters can be derived. These derived parameters include flux density, flux, core losses, stored magnetic energy, force and torque, inductance and induced voltage etc.
These electrical and mechanical parameters and performance of the generators can be then evaluated and compared, based on which an appropriate generator design can be selected, fine-tuned and verified. Among the parameters of particular interests are the maximum flux density which affects core losses, and the flux linkage of the stator windings which determines the induced voltage of the generator.
FLUX LINKAGE vs ROTOR POSITION
0.08 0.06 0.04 0.02 0 -0.02 0 -0.04 -0.06 -0.08 20 40 60 80 100 120 140 160 180
FLUX LINKAGE
ROTOR POSITION (Degree)

R phase Y phase B phase
Fig. 7 Flux Linkage Waveform
Fig. 5 Surface mounted permanent magnet rotor flux distribution Fig. 5 shows the surface mounted rotor configuration of RFPMG. The surface mounted RFPMG with radial orientation has high power density intended generally for low speed applications. In this topology, the magnets are mounted on the surface of the outer periphery of rotor Fig. 8 Induced Phase Voltage
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BIOGRAPHIES
Ashok Kumar.R received his B.E Degree in Electrical and Electronics Engineering from Saranathan College of Engineering affiliated to Anna University, Chennai in the year 2009. Currently he is pursuing M.E in Power Electronics and Drives at Bannari Amman Institute of Technology, affiliated to Anna University of Technology, Coimbatore, TamilNadu, India. His field of interest is design of special electrical machines for wind energy conversion system.
VIII. CONCLUSION The PMGs is developed a combination of the theoretical method and the finite element method for the design of direct driven synchronous generators for variable speed wind turbines. The theoretical method has been used for the preliminary design and for the examination of a wide range of geometrical and electromagnetic variables. The finite element method has been used for fine-tuning and verifying the design. The performance characteristics have been evaluated using the finite element method.
REFERENCES
[1] Yaw-Ming Chen, Shu-Yuan Fan and Wei-Shin Lu, Performance Analysis of Linear Permanent-Magnet Motors With Finite-Element Analysis, IEEE Transactions on Magnetics, vol. 44, no. 3, pp. 377 385, Mar. 2008. [2] Seed Mohsen Hosseini, Mojtaba Agha-Mirsalim and Mehran Mirzaei, Design, Prototyping, and Analysis of a Low Cost AxialFlux Coreless Permanent-Magnet Generator, IEEE Transactions on Magnetics, vol. 44, no. 1, pp. 75 79, Jan. 2008. [3] Y. Cao, A novel synchronous permanent magnet planar motor and its model for control application, IEEE Transactions on Magnetics, vol. 41, no. 6, pp. 21562163, Jun. 2005. [4] Tan H. Pham, Mathematical Modeling of Bonded Isotropic Magnet Magnetization for the Finite Element Design Analysis of Brushless DC Motors, IEEE Transactions on Magnetics, vol. 40, no. 2 , pp. 790793, Mar. 2004. [5] Kid-Chan Kim, Ju Lee, The Dynamic Analysis of a SpokeType Permanent Magnet Generator With Large Overhang, IEEE Transactions on Magnetics, vol. 41, no. 10, pp. 38053807, Oct . 2005. [6] W. N. Fu, S. L.Ho, Zheng Zhang, Design of Position Detection Strategy of Sensor less Permanent Magnet Motors at Standstill Using Transient Finite-Element Analysis , IEEE Transactions on Magnetics, vol. 45, no. 10, pp. 46684671, Oct . 2009. [7] T.J.E.Miller, Brushless Permanent Magnet and Reluctance Motor Drives Clarendon Press Oxford, 1989. [8] Paul C. Krause, Oleg Wasynczuk and Scott D. Sudhoff, Analysis of electric machinery and drive systems Purdue University, 2004. [9] R.Krishnan, Electric Motor Drives Modeling, Analysis and Control Pearson Education, First Impression,2007. [10] Bimal K Bose, Modern Power Electronics and AC Drives, Pearson Education, Third impression, 2007. [11] A.K. SAWHNEY; A course in Electrical Machine Design, Dhanpat Rai & Co.,
Bharanikumar.R was born in Tamilnadu, India,on May 30, 1977. He received the B.E degree in Electrical and Electronics Engineering from Bharathiar University, in 1998. He received his M.E Power Electronics and Drives from College of Engineering Guindy Anna University in 2002. He has 9 yrs of teaching experience. Currently he is working as Asst. Professor in EEE department, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India Currently he is doing research in the field of power converter for special machines; vector controlled based synchronous machine drives, converters for wind energy conversion systems. Dr. ANirmal Kumar was born in the year 1951. He completed his PG and UG in Electrical Engineering from Kerala and Calicut University respectively. He completed PhD in Power Electronics in the year 1992 from P.S.G. College of Technology, Coimbatore under Bharathiar University. He was with N.S.S. College of Engineering for nearly 28 years in various posts before joining Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India in the year 2004. Presently he is working as Professor & head in the department of Electrical and Electronics Engineering at Info Institute of Engineering Tamilnadu, He is a recipient of Institution of Engineers Gold Medal in the year 1989. His current research areas include Power converters for Wind Energy Conversion System and Controller for Induction motor drives.
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MODIFIED 11 LEVEL CASCADED H-BRIDGE DC TO AC GRID TIED INVERTER INTERFACE WITH SOLAR PHOTO VOLTAIC CELL
Dr.S.Senthilkumar*1, M.Sathishkumar*2 *1 Assistant professor,*2 PG Student Govt College of Engineering, Salem, Anna University Coimbatore. Sengce2009@yahoo.com sadhishm@gmail.com
ABSTRACT - The proposed system presents a single phase 11-level (5 H-bridges) cascade multilevel DC-AC grid tied inverter. Each inverter bridge is connected to a 200W solar panel. Microcontroller Atmal 89c51 was used to control the circuit. A maximum output voltage method was implemented based on the inverter output power to assure optimal operation of the inverter when connected to the power grid as well as a Phase locked Loop for phase and frequency match. A novel FM scheme is account for voltage profile fluctuations among the panels during the day. Simulation and experimental results are shown for voltage and current during synchronization mode and power transferring mode to validate the methodology for grid connection of renewable resources. 1. INTRODUCTION Because energy resources and their utilization will be a prominent issue of this country, the problems of natural resource depletion ,environmental impacts ,and the rising demand for new energy resources have been discussed fervently in recent years .Several forms of renewable zero pollution energy resources including wind, solar, bio, geothermal and so forth ,have gained more prominence and are being researched by many scientists and engineers. Solar cell installations involve the use of multiple solar panels or modules, which can be connected in series or in parallel to provide the desired voltage level to the inverter. The cascaded H-bridge multilevel inverter topology requires a separate DC source for each H-bridge so that high power and or high voltage that can result from the combination of the multiple modules in a Multilevel inverter would favor this topology. To maximize the energy harvested from each string, a maximum power strategy is used. The task of finding the optimum operation point might increase the complexity and component count as the number of isolated DC sources increase. The approach chosen to deal with the number of input sources was to monitor AC output power parameters instead of DC input measurements. II. MULTILEVEL INVERTER AND PV INTERFACE An overview of the system is shown in Fig. 1. The core component of this inverter design is the four-switch combination shown in Fig. 1. By connecting the DC source to the AC output by different combinations of the four switches, Q11, Q12, Q13, and Q14, three different voltage output levels can be generated for each DC source, +Vdc, 0, and Vdc. A cascade inverter with N input sources will provide (2N+1) levels to synthesize the AC output waveform. The DC source in the inverter comes from the PV arrays, and the switching signals come from the multicarrier sinusoidal pulse width modulation (SPWM) controller. The 11-level inverter connects five H-bridges in series and is controlled by five sets of different SPWM signals to generate a near sinusoidal waveform. The connection to the grid is done through a
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Fig. 1 would send more power would
variable transformer to assure that at any time the number of H-Bridges used can be controlled, the grid voltage generated by the inverter is met and also to give more flexibility to the experiment since irradiance levels might not be enough. For that reason, an additional fixed 10mH inductance was added as the connection inductance for power transferring mode. The individual solar panel output power is proportional to solar irradiance variations that occur during the day. The MPPT algorithm will work sensing the output power so no feedback from the individual panels is provided to reduce the number of sensors. As can be seen in Fig. 1, the lower panels, in terms of control signals, will deliver more energy than the upper panels. In order to avoid uneven power to be drawn from the panels by the inverter, a different inverter control approach for the SPWM scheme is proposed here to be used with the solar panels that can account for the voltage profile variation of the panels that occurs during the day. The MPPT and grid synchronization algorithm are fed by output and voltage current signals to generate the gate driver signals as shown in Fig. 2. In Fig. 3 are shown the inverter and its cycle by cycle SPWM control methodology. The irradiance profile over a day changes a few orders of magnitude than a 60 Hz system. That means that a control change action over the modulation index can be taken over a few cycles of the 60 Hz control system. It is desired to get the same amount of power from each string, which cannot be achieved using a conventional SPWM approach. For example, the lower panels in
Fig 1. Multilevel inverter overview send more power than the upper panels as they are switching for a longer time. The sinusoidal nature of the current comes as another factor that makes the power drawn from different panels uneven. The multilevel cascade topology does not require any of the H-bridges to be switched in a determined sequence as would be the case for a diode clamped multilevel (DCM) converter. This gives freedom to switch the H-bridges in the circuit in any order, which can be used as strategy to equalize the power transferred from individual panels. The control strategy implemented shifts the carrier signal over N cycles in the case of a (2N+1) level inverter to make it possible to draw the same amount of power from each string. Shifting the carrier down for each cycle is the same as physically changing the position of the H-bridges shown in Fig 3(a) for an 11-level inverter. In that figure five cycles of the fundamental frequency are needed to have each panel switch position with the other four. The energy stored in the capacitor will come to help in this process in a cycle-by-cycle basis to avoid a considerable voltage drop due to its considerable large capacitance (1000uF).
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control the phase difference between inverter and grid by controlling .
Fig 2. Control block diagram III. SYNCHRONIZATION AND TRACKING CONTROL SYSTEM Fig III. The tracking method of the inverter. Synchronization between inverter and grid means that both will have the same phase angle, frequency and amplitude. This can be done noise proof with respect to the grid by sensing the grid voltage in a Phase Locked Loop (PLL). Typical PLL algorithms include inverse Park-based PLL, Hilbert transformerbased PLL, and transport delay-based PLL. The one to be included in this design is the transport delay-based PLL. Fig. 4(a) shows the block diagram of the PLL algorithm. Notice that the delayed angle can be directly controlled at the computer station during the experiment to provide the signal in quadrature with the grid, which is the input to the Park transform block. The PLL output is the actual angle position of the grid voltage. This signal is used to generate the sine wave that is used as the reference signal to the control system, which will generate the SPWM, signals to drive the switches. The time required for synchronization will be dependent on the PI block parameters. Fig. 4(b) shows the PLL synchronization Simulation. In that figure, the PLL starts its synchronization at 0.03 second, and it is in synchronization after about 0.13 second. Since the angle is now known, it is possible to SPECIFICATIONS Rated power Maximum power voltage Maximum power current Open circuit voltage Module efficiency 200W 56.2 3.56A 68.8V 16.1%
IV. SWITCHING PATTERN AND PHASE DELAY The switching pattern evaluation is an important step in the implementation of the proposed inverter configuration either through hardware or simulation. Here the switching frequency considered for calculation of the phase delay is the fundamental frequency namely 50Hz.The entire waveform is analysed in detail with the help of the modes of operation, the inverter output voltages. The inverter bridges are similar in operation, the only difference being the voltage level namely Vdc and Vdc/2. Considering the output voltage of an individual inverter as V, we can conclude that the switches s1, s4 accounts for the positive voltage and for the negative voltage the switches responsible being s2,s3. SWITCHES ON OUTPUT
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VOLTAGE 0 +V -V the load circuit in the circuit. The below shown the fig IV. Output voltage waveform.
0 1 2
0 4 2
Switching Strategies for Individual Bridge For an output voltage level V=0,turn ON the switches S1,S2,S5,S6. For an output voltage level V=vdc/2, turn ON the switches S1,S4,S7,S8. For an output voltage level V=vdc, turn ON the switches S3,S4,S5,S8. For an output voltage level V=3vdc/2,turn ON the switches S1,S4,S5,S8. The time delay is calculated as given, FOR 360 TIME DELAY WE NEED 0.02 sec FOR 15 TIME DELAY WE NEED .833 ms 1 MACHINE CYCLE = 1s HENCE .833 ms = 833 MACHINE CYCLES
Fig V. The main circuit of MATLAB simulation circuit of 11 level multilevel inverter with solar photovoltaic cell. Instead of sensing the individual panel voltages, the maximum power point tracking (MPPT) algorithm determines the optimal point of operation of the panel by calculating the output power and phase angle variation. It monitors output voltage and current parameters by making small changes on the phase angle and looking at the power variation, as in a hill climbing optimization method to track the maximum power point.
Fig IV. The pulse width waveform
V. THE OUTPUT VOLTAGE WAVEFORM The simulation circuits simulated by using the MATLAB/SIMLINK simulate the 11 level inverter circuit the simulation circuit the solar panel is replaced by an DC source connected to the circuit. The dc source is act as
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VI. CONCLUSION This proposed system presents eleven level cascaded H-bridge inverter which uses PLL and Maximum power with separate solar panels as DC sources to interact with the power grid. A frequency modulation technique was used to control the power and is very successful due to irradiance and use of capacitance for smooth operation.A driver circuit using IC2110 to generate signals to each bridges and proved to be successful. A maximum output power is obtained using this technique.
Fig VI. Output voltage of the multilevel inverter. FUTURE WORK The future system includes driver circuit using single IC to control the entire bridges used and the use of DSP processors to increase the switching frequency with reduced filter components. VII. REFERENCE [1] J. K. Steinke, Control strategy for a three phase AC traction drive with a 3-level GTO PWM inverter, in Conf. Rec. IEEE PESC, 1988, pp. 431438. [2] P. Hammond, A new approach to enhance power quality for medium voltage ac drives, IEEE Trans. Ind. Appl. , vol. 33, no. 1, pp. 202208, Jan./Feb. 1997. [3] W. A. Hill and C. D. Harbourt, Performance of medium voltage multilevel inverters, in Conf. Rec. IEEE IAS Annu. Meeting, Phoenix, AZ1999, pp. 11861192. [4] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, A new multilevel PWM method: A theoretical analysis, IEEE Trans. Power Electron. , vol. 7, no. 3, pp. 497505, Jul. 1992. [5] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, Multilevel PWM methods at low modulation indices, IEEE Trans. Power Electron, vol. 15, no. 4, pp. 719725, Jul. 2000. . Fig VIII. The current waveform of the 11 level multilevel inverter with solar Photovoltaic cell.
Fig IV. The output voltage waveform of the phase voltage
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[6] D. G. Holmes, The significance of zero space vector placement for carrier based PWM schemes, in Conf. Rec. IEEE IAS Annu. Meeting , 1995, pp. 24512458. [7] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E. Galvan, R. C.P. Guisado, Ma. A. M. Prats, J. I. Leon, N. Moreno-Alfonso, Power- Electronic Systems for the Grid Integration of Renewable Energy Sources: A Survey, IEEE Transactions on Industrial Electronics, vol. 53, no. 4, pp. 1002-1016, June 2006. [8] A. J. Morrison, Global Demand Projections for Renewable Energy Resources, IEEE Canada Electrical Power Conference, 25-26 Oct. 2007, pp 537-542. [9] J. Rodriguez, S. Bernet, Bin Wu, J. O. Pontt, S. Kouro, Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives, IEEE Transactions on Industrial Electronics, vol. 54, no. 6, pp. 2930-2945, Dec. 2007. [10] L. M. Tolbert, F. Z. Peng, Multilevel Converters as a Utility Interface for Renewable Energy Systems, IEEE Power Engineering Society Summer Meeting, Seattle, Washington, July 15-20, 2000, pp. 1271- 1274. [11] S. Khomfoi, L. M. Tolbert, Multilevel Power Converters, Power Electronics Handbook, 2nd Edition Elsevier, 2007, ISBN 978-0-12- 088479-7, Chapter 17, pp. 451-482. [12] S. Busquets-Monge, J. Rocabert, P. Rodriguez, S. Alepuz, J. Bordonau, Multilevel Diode-clamped Converter for Photovoltaic Generators with Independent Voltage Control of Each Solar Array, IEEE Transactions on Industrial Electronics, vol. 55, July 2008, pp. 2713-2723.
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Novel Single Phase Grid Connected Inverter for Photovoltaic Modules

Santhosh.C PG student Department of EEE Roever Engineering College Perambalur
mail2sanrathi@yahoo.co.in Akila.R
Lecturer ,Department of EEE
Roever Engineering College Perambalur
Abstract A novel single phase inverter for photovoltaic modules in which ripple current generation in dc link and boost inductor using the AC circuit of DC-DC converter is analyzed. A feed forward compensation method is used for reduction of ripples to reduce the ac ripple voltage in addition DC-AC inverter control system is used. To develop Control Scheme for Single Stage Inverter that maintains a constant output voltage and frequency supply for critical nonlinear loads irrespective of variations in the DC link voltage. The novel inverter operated in closed loop control provides constant output voltage and frequency supply. Switching Loss, Conduction Loss, Cost, and Electromagnetic Interference (EMI) are low. In order to achieve low frequency ac ripple is reduced by using closed loop feed forward compensation method. The proposed feed forward compensation method is verified by simulation results.
and MPPT control perturbation. Therefore MPPT efficiency is reduced by ripples and noise. The proposed current based maximum power point tracking technique (CMPPT) [1] uses a current reference . The advantage of CMPPT control has been verified. CMPPT can reduce ripple and achieve the MPP accurately. Therefore the system efficiency can be increased. However, the CMPPT also reflects a 2nd-order harmonic ripple to achieve the MPP, which is why ac ripple can be reduced by closed loop system is proposed in this paper.
o/p V/I Fig.1 Block diagram Modules for single phase inverter for PV
KeywordsCurrent based power point tracking, DC/DC converter, closed loop feed forward compensation, ripple reduction and DC/AC inverter I. INTRODUCTION Power electronics has been in the limelight in recent years in conjunction with the promotion of energy conservation. Power conditioners for generating solar power that output electric power dependent on irradiance and temperature, into alternating current electric power. Ordinary DC-AC inverter power supplies are controlled to output the amount of electric power required by the load, whereas PV power conditioners require controls to ensure efficient output of electric power supplied by PV modules. The energy-conversion efficiency of PV arrays is still low, and thus, the maximum power point tracking (MPPT) control technique is required to extract the maximum power from a PV array in order to achieve maximum operating efficiency. Most photovoltaic power conditioning systems (PV PCS) are adapted to voltage based maximum power point tracking (VMPPT) where the voltage reference is generated by dc/dc converter control .But VMPPT generates perturbation ripples in the maximum power point (MPP) because of the 2nd-order harmonic ripple reflection
Fig.2. Transformer less PV Single phase inverter Fig. 1 shows the block diagram of a single phase inverter for PV modules that contains a dc/dc boost converter and a dc/ac inverter. The output of the dc/dc converter voltage (the
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dc/dc boost converter regulated PV current Ipv, in order to perform a MPPT function. The dc/ac inverter is controlled to generate the grid current with a unity power factor.
input of dc/ac inverter in the dclink capacitor) is 60V and the output of the dc/ac inverter is 40V/60Hz of grid voltage. The dc/ac inverter converts dc-link voltage to ac voltage in order to transfer solar energy to grid voltage. With a linear load, the output current has the same frequency phase and sinusoidal waveform as the grid voltage. The inverter input voltage and current in the dc link are dc, but the current contains high frequency switching noises and a low frequency ripple component. Recently, Dr. Lai proposed an active control technique to reduce ac ripple for fuel cell applications [2], [3]. In this paper, a new control method for reducing the 120Hz ripple current, which is propagating into a dc/dc converter, is proposed for dc/dc converters. Ripple current perturbs the operating points of solar cells, it degrades the MPPT function of a PV single phase inverter and therefore, decreases the MPPT efficiency along with the entire Power Conditioning System operation efficiency [6], [7]. Therefore, the proposed control method can increase the operation efficiency. This paper details an analysis of the proposed method. Its feasibilities are verified by simulation.
Fig.5 .DC Link.
A. AC ripple generation in a DC-link Fig. 4 shows a single-phase full bridge dc/ac inverter, where the dc-link power from the capacitor Cd is used to generate the ac grid Vac. The grid voltage Vac and grid current Iac are defined as follows: Vac= Vmsint Iac = Im sin t where, = 2f; The input power Pdc and output ac power Pac of the dc/ac Inverter is calculated as: Pdc=VdcIdc (3) (4) Pac = VmIm sin t =VmIm (1-cos2t)/2
2
(1) (2)
Fig 3 solar cell circuit diagram
Since Pdc = Pac, the dclink current Idc is derived from (3) and (4).Therefore Idc consists of the dc component IDC and the ac component Idc(ac) like (5). Idc =VmIm(1-cos2 t)/2Vdc= IDC + Idc(ac) where, IDC =VmImcos2t /2VDC Idc(ac)= VmIm/2VDC. Thus, the dclink voltage ripple Vdc (ac) can be calculated by Fig.4 DC/AC inverter integrating the ac component Idc(ac) as (6) and indicating that Vdc(ac) contains a 120Hz component with the same phase as the (5)
II.PROPOSED CLOSED LOOP AC RIPPLE grid voltage Vac. REDUCTION METHOD. Vdc(ac) =1/C- Idc(ac) dt=VmImsin2t/(2. 2VdcC)
Fig. 2 shows a commonly used transformer-less type PV Single phase inverter for residential use. The PV Single phase inverter PCS is composed of a PV array, a dc/dc boost converter, a dc-link, a dc/ac inverter and an low pass filter. PV voltage Vpv has a wide voltage range, from 36V to 50 V, = Vm(ac) sin 2t (6) B. dc/dc converter control with a ripple free dclink PV voltage VPV is represented by the voltage gain of a boost converter as: VDC =VPV/(1- D) (7).
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(8) Fig 7. PWM Pulse generation waveform
VPV = (1- D) VDC = a
where a is the average value of the voltage across the switch S1 in the steady state and a is equal to VPV by ignoring the drop voltage in L1 in the steady state. Duty ratio D generation using the common triangular wave comparison method, where the peak value of the triangular wave is Vdc and a is the command voltage for the dc/dc converter. Vdc becomes VDC because of the ripple free dc-link condition. D =Va* / VDC: (9)
Therefore, Vpv and Va* can be calculated as (10) and (11) under the ripple free dc-link condition. VPV = a =(1-D) VDC = 1- (Va* / VDC) = VDC-Va (10)
Fig 8.Single phase inverter and filter output waveform IV .COMPARISON BETWEEN THE CONVENTIONAL EXISTING SYSTEM MPPT Harmonics reduction Control system Fig .6 Solar panel circuit diagram PWM Pulse Voltage based MPPT 41.8% Open loop system It can be generated by external circuit PROPOSED SYSTEM Current and voltage based MPPT >=50% Closed loop system
It can be generated depends on the output signal SINGLE PHASE INVERTER AND THIS PROPOSED
III. SIMULATION FOR SINGLE PHASE INVERTER

WITH AC RIPPLE REDUCTION
CIRCUIT
V. CONCLUSIONS A PV singlephase dc/ac inverters tends to draw an ac ripple current that perturbs the operating points of the solar cells continuously and it may reduce current based maximum power point tracking (CMPPT) efficiency. In this paper, the ripple current generation in the dc-link and boost inductor has been analyzed using an ac equivalent circuit of the dc/dc boost converter. A new feed-forward ripple current compensation method has been proposed to incorporate a current control loop into the dc/dc converter control for ripple reduction. The proposed method has been verified in simulation. It shows a 50 % reduction in peak-to peak ac ripple.
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Transactions On Industrial Electronics, Vol. 22, No. 6, pp. 1027-1036, Nov. 1986. S. M. Alghuwainem, Matching of a dc motor to a photovoltaic generator using a step-up converter with a current-locked loop, IEEE Transactions on Energy Conversion, Vol. 9, No 1, pp. 192198, Mar. 1994. M.A.S. Masoum, H. Dehbonei, E.F. Fuchs, Theoretical and experimental analyses of photovoltaic systems with voltage and current-based maximum power-point tracking, IEEE Transactions on Energy Conversion, Vol. 17, No. 4, pp. 514522, Dec. 2002. V.Blasko, V.Kaura, Operation of a phase locked loop system under distorted utility conditions, IEEE Transactions on Industrial Electronics, Vol. 33, No. 1, pp. 58-63 Advanced algorithm for MPPT control of photovoltaic systems C.Liu, B. Wu and R. Cheung Department of Electrical & Computer Engineering, Ryerson University, Toronto, Ontario,Canada M5B 2K3 Montreal, August 20-24, 2004
5.
REFERENCES:
1. H. Cha, S. Lee, Design and implementation of photovoltaic power conditioning system using a current based maximum power point tracking,in Proc. IEEE-IAS Annual Meeting, pp. 1-5, Oct. 2008. C Liu, J Lai, Low frequency current ripple reduction technique with active control in a fuel cell power system with inverter load, IEEE Transactions on Power Electronics, Vol. 22, No. 4, pp.1429-1436, Jul.2007. Enjeti, P.N., Shireen, W., New technique to reject dc-link voltage ripple for inverters operating on programmed PWM waveforms, IEEE Transactions on Power Electronics, Vol. 7, No. 1, pp.171-180, Jan. 1992. P. D. Ziogas et al., Rectifier-inverter frequency changer with suppressed dc-link components, IEEE 6.
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Optimized Power System Design with Help of Evolutionary Computing

P.Harikrishnan#1, N.S.Suresh *2
#
Department of electrical and electronics engineering, Anna University of technology, Coimbatore, India.
suresh173e@gmail.com
Abstract:- Power system stabilizers (PSSs) play an important role in suppressing low frequency oscillations. It is important to tune pss parameters, find optimal number of pss, and their locations while designing a power system. In multi-machine power systems, the objective of optimal PSS parameter tuning should not only be to damp electromechanical modes strongly related to the pertained generator, but also to take the damping status of other generators into account. An application of the intelligent search technique to find optimal parameters of power system stabilizer (PSS) considering fuzzy logic stabilizer helps attaining dynamic stability of power system. This paper presents an approach for the design of fuzzy logic power system stabilizers using genetic algorithms. In the proposed fuzzy expert system, speed deviation and its derivative have been selected as fuzzy inputs. In this approach the parameters of the fuzzy logic controllers have been tuned using genetic algorithm. Incorporation of GA in the design of fuzzy logic power system stabilizer will add an intelligent dimension to the stabilizer and significantly reduces computational time in the design process. It is shown in this paper that the system dynamic performance can be improved significantly by incorporating a genetic based searching mechanism. To demonstrate the robustness of the genetic based fuzzy logic power system stabilizer, simulation studies on multimachine system subjected to small perturbation and three phase fault have been carried out. Simulation results show the superiority and robustness of GA based power system stabilizer as compare to conventionally tuned controller to enhance system dynamic performance over a wide range of operating conditions. I INTRODUCTION The application of power system stabilizers for improving dynamic stability of power systems and damping out the low frequency oscillations due to disturbances has received much attention [1-3]. The
conventional PSS comprising a cascade connected lead-lag network with rotor speed deviation as input has made great contribution in enhancing system stability. Power system is a highly nonlinear system and it is difficult to obtain exact mathematical model of the system. In recent years, adaptive self tuning, variable structure, artificial neural network based PSS, fuzzy logic based PSS have been proposed to provide optimum damping to the system oscillations under wide variations in operating conditions and system parameters [6-8]. Recently, Fuzzy logic power system stabilizers (FLPSS) have been proposed to overcome this problem [9,10]. Fuzzy logic makes complex and non-linear problems much easier to solve by allowing a more natural representation of the situations being dealt with. Fuzzy Logic control appears to possess many advantages like lesser computational time and robustness. It has been shown that fuzzy logic is one of the best approaches for non-linear, time varying and illdefined systems. Fuzzy logic based power system stabilizer has been applied successfully for the enhancement of dynamic stability of power system [1112]. The application of fuzzy logic power system improves the damping of the system oscillations. However, optimum tuning of the parameters of FLPSS further required for better performance under wide variation of system operating conditions. Although, fuzzy logic controllers showed promising results, they are subjective and heuristic. There is no systematic design procedure for the tuning of the parameters of fuzzy logic power system stabilizer. The generation of membership functions and the selection of scaling factors have been done either, by trial-and-error, iteratively, or by human experts. Therefore, the design of fuzzy logic power system stabilizer (FLPSS) becomes a time consuming and laborious task. Genetic algorithms (GA) are search algorithms based on the mechanics of natural selection and survival-of-the-fittest. GAs is optimization procedures that were devised on population genetics. The recent approach is to integrate the use of GA and fuzzy logic systems in order to design power system stabilizer [13,14]. GA has been applied successfully to
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labels of the fuzzy sets defined for system input variables. (ii) Fuzzy Logic Reasoning Unit The observed values are used to identify the rule used to infer an appropriate fuzzy control action. The point-valued Max-Min fuzzy inference method is used in this study. (iii) Knowledge base The knowledge base consists of a database and a rule base. DATA BASE: The database provides the necessary definitions of the fuzzy parameters as fuzzy sets with membership functions defined on the universe of discourse for each variable. RULE BASE: The rule base consists of fuzzy control rules intended to achieve the control objectives. (iv) Defuzzification Unit Defuzzification is the process of mapping from a space of inferred fuzzy control actions to a space of non-fuzzy (crisp) control actions. A defuzzification strategy is aimed at producing a nonfuzzy control action that best represents the possible distribution of the inferred fuzzy control action. In this study, each of the input and output are Gaussian membership functions and number of membership functions is five. The universe of discourse chosen is + 1 to 1. The speed deviation and its derivative are chosen as inputs to the Flpss. The stabilizer is placed on the all four machines. B) Selection of Input signals of FLPSS: The first step in designing a fuzzy logic power system stabilizer (FLPSS) is to decide which state variables representing system dynamic performance must be taken as the input signal to FLPSS. However, selection of proper linguistic variables formulating the fuzzy control rules is very important factor in the performance of fuzzy controllers. For the present investigations generator speed deviation and acceleration are chosen as input signals to FLPSS. In practice, only shaft speed deviation is readily available. The acceleration signal can be derived from speed signals measured at two sampling instant by the following expression:
various power system problems [15]. The performance of FLPSS can be significantly enhanced by incorporating genetic based learning mechanism. The advantage of the GA technique is that it is independent of the complexity of the performance index [16]. This paper deals with the design method for the stability enhancement of a multi-machine power system using FLPSSs whose parameters are tuned using genetic algorithm. The proposed tuning scheme uses a GA based search that integrates a classical parameter optimization criterion based on Integral of Squared Time Squared Error (ISTSE). The main objectives of the research work presented in this paper are: 1. To present an algorithm for the design of fuzzy logic power system stabilizer using genetic algorithm for stability enhancement of multi-machine power system. 2. To study the dynamic performance of the system with the proposed GA based fuzzy logic power system stabilizer (GFLPSS) over a wide range of operating conditions. 3. To compare the performance of proposed GFLPSS with the conventional PSS (CPSS) and No PSS in the system. To demonstrate the capability of the enhanced system damping over a wide range of system loading conditions under small perturbation and three phase fault. II SYSTEM MODEL In this study a two area, 11-bus, 4-machine system is considered. Each synchronous machine is represented by non-linear sixth-order model as in the [3]. It is assumed that all the 4 generators are equipped with static excitation systems. All the four generators are provided with IEEE Type ST1A model of excitation system and turbine governors. The nominal system parameters and data are given in Appendix. The system used in the analysis is a two area system .The generators 1 and 2 are considered to form one area and generators 3 and 4 are considered to form second area. III DESIGN METHODOLOGY A) Structure of Fuzzy Logic Power System stabilizer (i) Fuzzification Unit Fuzzification is the process of mapping from observed inputs to fuzzy sets in the various input universe of discourse. The observed data is usually in crisp form, and fuzzification is required to map the observed range of crisp inputs to corresponding fuzzy values for the system input variables. The mapped data are further converted into suitable linguistic terms as
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rules and for every rule an output membership function is obtained. In this study, Mamdani Inference engine is used.
C) Membership Functions After choosing proper variables for input and output of fuzzy controllers, it is important to decide on the linguistic variables. The linguistic variables transform the numerical values of the input of the fuzzy controllers to fuzzy values. The number of these linguistic variables specifies the quality of control, which can be achieved using fuzzy controller. As the number of linguistic variables increases, the quality of control increases at the cost of increased computer memory and computational time. Therefore, a compromise between the quality of control and computational time is needed to choose the number of variables. For the power system under study, five linguistic variables for each of the input and output variables are used. All the investigations are carried out considering Gaussian membership functions. A Gaussian membership is defined as: E) Defuzzification To obtain a deterministic control action, a defuzzification strategy is required. Defuzzification is a mapping from a space of fuzzy control actions defined over an output universe of discourse into a space of non-fuzzy (crisp) control actions. There are different techniques for defuzzification of fuzzy quantities such as Maximum Method, Height Method, and Centroid Method. Here, COA Method has been used for defuzzification. F) Selection of fuzzy variables for optimization The input signals are normalized using normalization factors to obtain a wide range to cover the complete universe of discourse. Similarly, a denormalization factor is used to provide an adequate stabilizing signal. In the proposed design algorithm for FLPSS, the inner parameters of the fuzzy structure i.e., centers of membership functions and variance of the membership function are also optimized using genetic algorithm in addition to normalization and denormalization factors for input and output signals. IV OPTIMIZATION TECHNIQUE In this design, a genetic algorithm (GA) based search is used for the optimization of parameters of FLPSS. The GA based design integrates the parameter optimization criterion based on Integral of Squared Time Squared Error (ISTSE). An objective function that reflects small steady state error, small overshoots and oscillations has been selected for the optimization. The performance index J is defined as:
(2) where i = 1,2n and n is the number of membership function. In the present investigations, the optimum value of and c are determined using GA. The structure of all four FLPSS installed on each of the machine is same. D ) Rule Base The fuzzy rules play a major role in the design of FLPSS. The rules can be generated using knowledge and operating experience with the system or understanding of the system dynamics. The two inputs, speed deviation and acceleration, generate 25 rules for each of the machine. The rules are applied to generate FLPSS output. A positive control signal is for the deceleration control and a negative signal is for the acceleration control. The stabilizer output is determined by applying a particular rule expressed in the form of membership function. Different methods have been used for finding the output in which MinimumMaximum and Maximum Product Methods are generally used. For present study, Min- Max method is used. Finally, the output membership function of the rule has been calculated. This is carried out for all the
where (t) is speed deviation of the generator following 5% step increase in mechanical input torque i.e., Tm = 0.05 p.u. Fig. 2 shows the performance index J of the GA based ISTSE optimization method in different stages of the genetic search process. V DESIGN ALGORITHMS The sequential steps of the proposed design algorithm are presented by considering Gaussian
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membership functions for input and output variables. A universe of discourse, -1 to 1 is chosen and center of gravity (COG) defuzzification technique is used. The design algorithm consists of the following steps:
5.6 Mutation In natural evolution, mutation is a process where one allele of a gene is replaced by another to produce a new genetic structure. A mutation probability of 0.001 is considered. 5.7 Reinsertion
A) Population representation and Initialization Genetic algorithm operates on a number of potential solutions, called a population, consisting of some encoding of the parameters set simultaneously. The chromosomes are represented in single-level binary string. In this algorithm a set of 100 individuals is generated randomly. The sizes of the individuals are dynamically reduced to the 30 individuals in the later stage of generation. This increases the convergence rate. Also, the computational time reduces since, the probability of the occurrence of good individuals increases in the first generation. B) Objective function evaluation: The parameters of the FLPSS are tuned such that the system damping is enhanced. An ISTSE technique is used be minimize an objective function having the constraints on the parameter of the FLPSS. The objective function is defined as in equation (3). C) Fitness functions assignment VI PERFORMANCE ANALYSIS: The fitness function is used to transform the objective function value into a measure of relative fitness. The fitness function transforms the value ofobjective function to a non-negative. The mapping is required whenever the objective function is to be minimized as the lower objective function values corresponds to fitter individuals. In this study, fitness function transformation is linear. The transformation offsets the objective function, which is susceptible to rapid convergence. 5.4 Selection Selection is the process of determining the number of trials for a particular individual for reproduction and, thus, the number of offspring that an individual will produce. The roulette wheel selection method is used in this study. 5.5 Recombination This is a basic operator for producing new chromosomes in the genetic programming. Crossover, produces new individuals that have some parts of both parents genetic properties. The uniform single-point crossover is used in this study. The dynamic performance of four -machine system has been analyzed with the proposed GA based fuzzy logic power system stabilizer, conventional PSS (CPSS) and without PSS under various disturbances. The performance of the proposed GA based fuzzy logic power system stabilizer have been examined under small perturbation and three-phase fault at different system loading conditions. Power system toolbox (PST), MATLAB has been used for the analysis. In order to test the robustness of GA based fuzzy logic power system stabilizer to enhance system damping over a wide range of operating conditions, three loading conditions were considered: a light load, a nominal load, a heavy load. A) Small Perturbation A 5% step decrease in Vref1 i.e. Vref1 = 0.05 p.u. and 5% step increase in Vref3 = 0.05 p.u. have applied at different loading conditions. The dynamic responses of the GA based FLPSS (GFLPSS) are compared with the conventionally tuned CPSS and No PSS in the system. It is clear from the results that the damping to the system oscillations improves with the proposed GFLPSS as compare to CPSS and No After the operation of selection and recombination of individuals from the old population, the fitness of the individuals in the new population may be determined. The new individuals are inserted to maintain the size of the original population. 5.8 Termination of GA The GA is a stochastic search method; it is difficult to specify the convergence criteria. As the fitness of a population may remain static for a number of generations before a superior individual is found, the application of termination criteria becomes problematic. The termination of the GA has been done after prespecified number of generation is reached. The process iterates till the termination criteria has not met. Fig 1 shows the performance index J of the GA based ISTSE optimization method in different stages of the genetic search process.
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PSS. It is clear from the results that without any PSS in the system, the system oscillations are sustained, where as with GA based FLPSS oscillations are damped very quickly. The GFLPSS has a lower peak offshoot and smaller oscillations. It is clearly shown in Fig.3 & 4 that GFLPSS effectively and efficiently damp oscillations in the local as well as interarea mode. The dynamic responses for 34 , 13 considering small perturbation of Vref1 = -0.05 p.u. and Vref3 = 0.05 p.u. for nominal loading conditions are shown in Figs 2& 3 respectively. The dynamic responses for 12, 34, 13 considering small perturbation of Vref1 = -0.05 p.u. and Vref3 = 0.05 p.u. for heavy loading conditions and light loading conditions are shown in Figs 5, 6 respectively. The dynamic responses for 1, 2, 3 considering small perturbation of Vref1 = -0.05 p.u. and Vref3 = 0.05 p.u. for light loading conditions are shown in Fig 7 with genetic based fuzzy logic power system stabilizer (GFLPSS). The results shown in Figs clearly reveal that the GA based FLPSS settles oscillations in rotor speed deviations and overall better damped response as compare to CPSS. The GFLPSS work effectively in damping local as well as interarea modes of oscillations. B) Large Disturbance Test: To investigate the effectiveness of the GPSS under more severe conditions, A 3-cycle, three phase fault was applied at bus 7 at t = 0.5 sec for nominal, light and heavy system loading conditions. The fault is cleared by tripping the faulty line. It can be clearly seen from Figs.8-11 that the proposed stabilizer improve the settling time and peak offshoot following a threephase fault for different operating load. The stabilizer provide superior performance as compare to conventional power system stabilizer in terms of settling time. The system oscillations are increasing in magnitude without any PSS in the system. Simulation results reveal that the performance of the fuzzy logic power system stabilizers can be significantly improved by incorporating the genetic-based learning mechanism for tuning all parameters including FLPSS gains centers of membership functions and variance of Gaussian membership functions. The stabilizing signals under small perturbation for nominal loading condition with conventional PSS and GA based FLPSS are shown in fig. The results shown clearly indicate that proposed PSS provide effective stabilizing signal than CPSS under small disturbance.
fig 1. Variation of performance index J
fi g 2.Dynamic response for 1 , 2 , 3 and 4 considering Vref1 = -0.05 p.u. and Vref3 = 0.05 p.u. for light loading conditions with proposed PSS.
Fig 3.Dynamic response for 1 , 2 , 3 and 4 considering transitory 3-phase fault at light loading conditions with proposed pss.
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stabilizer, IEEE Transactions on Energy Conversion, 11(2), 1996,pp 97-103. [9]. Y. Y. Hsu and C. H. Cheng, Desi gn of fuzzy power system stabilizers for multimachine power systems, IEE Proceedings on Generation Transmission Distribution, Vol.137, Part-C, No.3, May 1990,pp. 233-238. [10]. T. Hiyama, Robustness of fuzzy logic power system stabilizer applied to multimachine power system, IEEE Transactions on Energy Conversion [11]. Hamid A. Toliyat, Javed Sadeh, Reza Ghazi, Design of Augmented Fuzzy Logic Power System Stabilizer, IEEE Transactions on Energy Conversion, Vol. 11., No.1, March 1996,pp.97-103. [12]. K.A. El- Metwally and O. P. Malik, Application of fuzzy logic stabilizers in a multimachine power system environment, IEE Proceedings on Generation Transmission Distribution,Vol.143, [13]. M. A. Abido and Y.L. AbdelMagid, Tuning of a fuzzy logic power system stabilizer using genetic algorithms, 4th IEEE International Conference on Evolutionary Computation ICEC 1997,pp.595-599 .
VII CONCLUSIONS This paper presents a method for the design of fuzzy logic power system stabilizers in a multimachine power system using genetic algorithm. A systematic approach for tuning the parameters of fuzzy logic power system stabilizer using ISTSE technique has been presented. The design algorithm for simultaneous tuning of fuzzy logic power system stabilizers has been tested for multi-machine model. The performance of the FLPSS can be significantly improved by incorporating the genetic-based learning mechanism for tuning of parameters of fuzzy logic power system stabilizer. Simulation results reveal that the dynamic performance of the system enhances with genetic based fuzzy logic power system stabilizer. Investigations reveal the performance of simultaneously tuned genetic algorithm based fuzzy power system stabilizers in a multi-machine system is quite robust under wide variations in loading conditions both for small and large disturbance for local as well as inter area mode. REFERENCES [1]. F.P. Demello and C. Concordia, Concept of synchronous machine stability as affected by excitation control, IEEE Transactions on Power Apparatus and System, Vol. 88, 1969, pp 316-329. E.V. Larsen and D.A. Swann, Applying Power System Stabilizers, Part IIII, IEEE Transactions, PAS Vol. 100, No 6, 1981, pp 3017-3046. P. Kundur, Power System Stability and Control, McGraw Hill Inc. 1993. Y.N. Yu, Electric Power System Dynamics, Academic Press, 1983. P. Kundur, M. Klein, G.J Rogers and M.S Zywno, Applications of Power System Stabilizers for Enhancement of overall system stability, IEEE Trans. PAS, Vol 4, No-2, May 1989, pp. 614-626. S Cheng, O.P Malik., G.S Hope., Design of self-tuning PID stabilizer for a multimachine power system, IEE Proceedings -Generation, Transmission and Distribution, Part C,1986;133(4),pp. 176-185. Y. Zhang, G.P. Chen, O.P. Malik and G.S. Hope, An artificial neural based adaptive power system stabilizer , IEEE Transactions on Energy Conversion, Vol.8,No.1, March 1993, pp.71-77. P Hoang, K Tomsovic, Design and analysis of an adaptive fuzzy power system
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Power Conversion Stage Reduction Using Z-Source Inverter with Different PWM Control Schemes for Wind Energy Conversion System
B.Indhumaty, R. Bharanikumar, A. Nirmal Kumar
Department of Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Anna University, Tamil Nadu, India . E-mail: indhumathyb@gmail.com
ABSTRACTWind energy has achieved a rapid development and made significant inroad into electrical power system among renewable energy sources. With increased use of wind energy conversion system, several technologies are developed for them. Permanent magnet generators utilized in these technologies have some advantages when compared to conventional generators such as no need of excitation, low volume and weight, high precision and deletion of gearbox. A variable speed wind energy conversion system with a permanent magnet generator and Z-source inverter is proposed in this paper. With the unique impedance network, the Z-source inverter advantageously exploits the shoot through state to boost the input dc voltage. In this paper, four PWM control methods such as sinusoidal PWM, simple boost control, carrier based PWM and third harmonic injection control are also employed to analyze the performance of Zsource inverter. The proposed wind energy conversion system is to be modeled using MATLAB / SIMULINK with the above said control schemes and the various factors such as dynamic response of ZSI, dc link voltage , boost factor, modulation index and THD are to be analyzed for various values of wind velocity. Index Termspermanent magnet generator (PMG), pulse width modulation (PWM), total harmonic distortion (THD), wind energy conversion system (WECS), Z-source inverter.
Fig. 1. Conventional WECS with PMG and three stage power conversion.
I. INTRODUCTION ITH the steady growth of electricity demand, the need for sustainable energy resources is also expected to increase considerably. Among various other energy sources, wind energy is more competitive due to its advantages such as clean, eco-friendly, cost effective and inexhaustible source of energy. The cost of wind power has continued to decline through the development of technology and increased production level [4]. The use of gearbox causes unpleasant noise and requires regular maintenance and also increases the loss of the wind turbine system [9]. Thus, the direct driven configuration is employed, where the generator is coupled to the rotor of a wind turbine directly and it operates in the low speed. Compared with the geared drive wind generator systems, the main advantages of direct drive wind generator systems are the elimination of mechanical reduction gear, reducing the size of the overall system, reduced installation and maintenance cost, low noise, quick response to the wind fluctuations and load variations.
The power converters coupled with the permanent magnet generator are mainly used to convert the output voltage and frequency from PMG to desired values for domestic and industrial loads [6]. Fig. 1 shows the conventional topology of WECS. This configuration is made up of diode rectifier, dc-dc boost chopper and three-phase inverter. The generated power of continuously varying is fed to the load through the power converter to provide constant voltage and frequency. Due to the fluctuating nature of wind velocity, the output and frequency varying continuously. The varying AC voltage is rectified into DC through a diode bridge rectifier and the dc voltage is then controlled to get the constant voltage by adjusting the duty cycle of a boost chopper. Then, the DC voltage inverted to get the desired AC voltage and frequency using a PWM inverter The traditional power converters are voltage source inverter and current source inverter. The voltage source inverter is fed from a dc voltage source with a relatively large capacitor connected in parallel and it is well known that maximum ac output voltage of VSI is less than the input dc source voltage. Thus, it is only a buck converter. Similarly, the current source inverter is fed from a dc current source with a relatively large inductor connected in series and its ac output voltage is greater than the input dc source that feeds the dc side inductor. Current source inverter is therefore a boost converter. Some of the limitations of traditional inverters are, Either a buck or boost converter. Distorted output waveforms. Un interchangeable main circuits Vulnerability to EMI noise.
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turning ON both the switches in the same inverter phase leg simultaneously. The distinct feature of Z-source inverter is its ability to produce ac output voltage of any value between zero and infinity, irrespective of the input dc voltage. . III.MATHEMATICAL EQUATIONS FOR PROPOSED PMG TOPOLOGY WITH WIND TURBINE AND ZSOURCE INVERTER A. Wind Turbine Model
Fig. 2. Proposed WECS with Z-source inverter.
To overcome these limitations ZSI was proposed for WECS [14]. It is single stage buck-boost converter. The ZSI consist of a unique impedance network, with which the buck-boost characteristic is obtained. Fig. 2 shows the proposed topology. In this topology, a new PMG based WECS with Z-source inverter is proposed, where the boost chopper is neglected. In this paper a detailed analysis on the different pulse width modulation schemes of ZSI is presented. By comparing the four control schemes based on boost factor, modulation index and THD, the best suited PWM scheme is to be identified for wind turbine driven permanent magnet generator fed ZSI. II. Description of Proposed WECS
Wind turbines can be classified into vertical axis type and horizontal axis type. Most modern wind turbines use a horizontal axis configuration due to the advantages of low cost, high efficiency and ease in design for high power ratings. The output power of the wind turbine is given as (1), [3] 1 P = R 2V 3 C p (1) 2 Where P is the mechanical output power of wind turbine (W), is the air density in ( K g / m 3 ), R is the radius of the turbine (m), V is the wind speed (m/s) and C p is the power coefficient of the turbine which in turn is a function of tip speed ratio and blade pitch angle (deg). Tip speed ratio is the ratio of blade tip speed to wind speed. C p is expressed as a function of the tip speed ratio given by (2),
Rt V
(2)
It is important to note that the aerodynamic efficiency is maximum at the optimum tip speed ratio. The torque value obtained by dividing the turbine power by turbine speed is given as (3), [2]
T t (V , t ) =
Fig. 3. Complete circuit of PMG with Z-source inverter and rectifier.
1 pR 3 C t ( )V 2
(3)
Where Ct () is the torque co-efficient of the turbine, given by (4),
The complete circuit of proposed WECS is illustrated in Fig.3. With the use of Z-source inverter, the inversion and also the boost function is accomplished in a single stage. Unlike the traditional inverters, Z-source inverter utilizes an impedance network that links the inverter main circuit with the dc source [14]. Fig. 3 shows the Z-Source inverter fed with a diode rectifier bridge. The output of the PMG is fed as input to the diode bridge rectifier through the rotor inductance and resistances. The diode bridge rectifier act as the DC source whose output is fed as input to Z-source inverter with input capacitor (Ca, Cb, Cc). During diode commutation and shoot through mode of the inverter, the line inductance may produce voltage surges which are suppressed with the help of the input capacitors. The impedance circuit of Z-source inverter is made up of two equal inductors (L1, L2) connected in series arms and two equal capacitors (C1, C2) connected in diagonal arms. The function of the rectifier which is coupled with PMG is to convert the variable ac voltage from the PMG into its equivalent dc voltage. This rectified dc output voltage is fed as input to the impedance network of Z-source inverter. Then the output of the impedance network is applied to the inverter main circuit which consists of six switches. The voltage boost capability of Z-source inverter is facilitated by
C t ( ) =
C p ( )
(4)
The power co-efficient Cp is given by (5),

116 Cp () = (0.4 * ) 50.5e 1
. 165 1
(5)
Where
1 =
1 1 0.035 3 ( + 0.089 ) +1
342 VL = VC , Vd = 2VC , Vi = 0
(15) Now consider that the inverter bridge is in one of the eight non-shoot through zero states for an interval of T1 , during switching cycle of T. From the equivalent circuit of Fig. 7, we have V L = V0 VC , Vd = V0 ,
B. Modeling of DDPMG
Vi = VC VL = 2VC V0
Fig. 8. Quadrature axis model of PMG
(16)
Where V0 is the dc source voltage and T = T0 + T1 . The average voltage of the inductors over one switching period (T) should be zero in steady state, from equations (15) and (16), thus, we have
A specific model of the machine is required to determine the steady state and transient behavior of the PMG. The equivalent circuit of q-axis model of PMG is shown in Fig. 8. The model of PMG can be obtained by means of two phase machines in direct and quadrature axes. The d-axis is a rotor magnetic axis and the axis that leads the d-axis by 90 is called q-axis. The equivalent circuit for a d-axis model of PMG with the rotor reference frame is shown in Fig. 9. [5]
Vc T1 = V0 T1 T0
T1 .V0 = VC T1 T0
(17)
Similarly, the average dc-link voltage across the inverter bridge can be found as follows:
Vi =
(18)
IV. PWM CONTROL SCHEMES FOR ZSI A. Sinusoidal PWM

Fig. 9. Direct axis model of PMG
The convention terminal voltage equation of the PMG driven by the wind turbine obtained from the above dq model may be expressed in the matrix form as, (7) [V abc ] = [R abc ][i abc ] + [ abc ] The complete model of the generator is derived in dqcoordinates. The voltage equations for d and q axes [7] are given by,
A new sinusoidal PWM technique as shown in Fig. 11 is employed as control scheme for ZSI. The reference sine wave is compared with the carrier to produce the required PWM pulses [2]. In this control scheme, for leg a of the inverter switch T1 is kept fully ON in the positive half cycle and the shoot through duty ratio is controlled by turning ON and OFF in negative half cycle. Similarly, the pulses for switches in the other two legs are also generated.
V d = R s i d Ld
V q = R s i q Lq
d i d + r Lq i q dt
(8) (9)
d iq r Ld id + r m dt
As the position of the magnets in the rotor determines, independently of stator voltages and currents, the instantaneous induced emfs and subsequently the stator currents and torque of the machine, the rotor reference frame is preferred. When rotor reference frames are considered, it means the equivalent q and d axis stator variables are transformed to the reference frames that are revolving at rotor speed. [1],[5]. C. Mathematical Analysis of Z-Source Inverter Assuming that the inductor L1 and L2 and capacitors C1 and C2 have the same inductance (L) and capacitance (C), respectively, the Z-source inverter becomes symmetrical. From the symmetry and equivalent circuits, we have [3][14] VC1 = VC 2 = VC , V L1 = VL 2 = VL (14) Given that the inverter bridge is in the shoot-through zero state for an interval of T0 , during a switching cycle T, and from the equivalent circuit of Fig. 6., we have
Fig. 11 Sinusoidal PWM control waveforms.
B. Simple Boost Control Scheme The simple boost control method [2] employs a straight line equal to or greater than the peak value of the three phase references to control the shoot through duty ratio as shown in Fig. 12. One straight line is equal to maximum of three phase reference and the other is equal to the minimum of three phase reference. When the carrier wave is greater than the upper line Vp or lower than the bottom line, Vn the circuit turns into shoot through state; otherwise it just operates as a conventional inverter. At modulation index M=1, the maximum shoot through duty ratio is zero, since it is limited by (1-M) [13].
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through state. Third harmonic injection can be used to extend the modulation index range. V. RESULTS AND DISCUSSION In this section , the proposed topology has been extensively simulated under system level simulation using MATLAB/SIMULINK. Different PWM control schemes are employed in Z-source inverter with different wind velocity and the comparison is done based on dynamic response of ZSI, THD, output voltage, boost factor and modulation index. The simulated results are compared with the hardware experimental setup.
Fig. 12 Simple boost control waveforms.
C. Carrier based PWM
A. Simple boost control scheme
Fig. 13 Carrier based PWM control.
All traditional PWM schemes can be used to control the ZSI. Fig.13 shows the traditional PWM switching sequence based on the triangular carrier method. When the dc voltage is not enough to directly generate the desired output voltage, the shoot through states are used to boost up the voltage. In every switching cycle, the shoot through state is added along with the non-shoot through state [2]. It should be noted that each phase leg switches ON and OFF once per switching cycle. The shoot through states is evenly allocated in each phase without the change in total zero state time intervals. Thus, the equivalent dc link voltage to inverter is boosted because of shoot through states. D. Third Harmonic Injection Control Method
Fig. 15. Dynamic performance of ZSI under simple boost control scheme at different wind velocity
Fig. 15. shows the dynamic performance of ZSI under simple boost control scheme at different wind velocity. The transition time period little bit higher than the THI control scheme. But the output voltage is almost constant for the constant wind velocity. The drop in voltage for change in wind velocity from 13m/s is 7m/s is 191V to 91.93V. Here, the drop in voltage is high when compared to carrier based PWM.
B. Carrier based PWM
Fig. 14 Sketch map of third harmonic injection control.
Fig.16. Dynamic performance of ZSI under carrier based PWM scheme at different wind velocity
The Fig.14 shows the sketch map of third harmonic injection control method. In this PWM method, a third harmonic component with 1/6 th of the fundamental component is injected into the three phase reference voltages [8] [10]. Va reaches its peak value at 3/2 M while Vb is at its minimum value -3/2 M at /3. Therefore, a unique feature can be obtained through two straight lines, Vp and Vn to control the shoot through time with 16% third harmonic injection. The maximum shoot through duty ratio can be calculated by (1-3/2 M). When the carrier is greater than Vp or smaller than Vn, the inverter works in shoot
Fig. 16 shows the variations in output voltage of ZSI with carrier based PWM scheme for changes in wind velocity. Here, the transition time taken by output voltage to settle under each change in wind velocity is more than that taken by THI control scheme. Since the wind velocity is fluctuating, the output voltage at a same wind velocity also seems to be varying under carrier based control scheme. When there is a change in wind velocity of 13 to 7m/s the output voltage varies from 198V to 88.38V. C. Sinusoidal PWM
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Fig.19 shows the voltage across Z-source network for a wind velocity of 14m/s. Fig.20 shows the variation of ZSI output voltage for different PWM schemes. The ZSI output voltages for zero boost factor are 70.71V for sinusoidal PWM, 53.74V for carrier based PWM and 84.85 V for both simple boost and third harmonic injection control methods. When compared to other control schemes in third harmonic injection control scheme the boost factor can be varied to a larger extend to get more output voltage. While increasing the boost factor the output voltage also increases. The maximum output voltage obtained from sinusoidal is 212.13V while that of third harmonic injection method is 244.85V.
Fig. 17. Dynamic performance of ZSI under sinusoidal PWM scheme at different wind velocity.
Fig. 17 shows the dynamic performance of ZSI under sinusoidal PWM scheme at different wind velocity. Here the output voltage is almost constant but there is a slighter transient at the starting period. Also the time taken to settle by the output voltage is high when compared to THI scheme. When there is a rise in wind velocity there is some transient voltage at the beginning then it goes to constant voltage. The drop in rms voltage from variations of wind velocity 13 to 7m/s is 141V which is very high compared to other techniques.
Fig. 28. ZSI output voltage of 198V when M=1 using THI control scheme.
D. Third harmonic injection PWM with filter

Fig. 18 shows the variation in output voltage of z-source inverter with THI control scheme due to variations in wind velocity .As the wind velocity increases, the output voltage also increases. For a wind velocity of 12m/s, the output voltage is about 183.84V, and if there is slow variation of wind velocity as 9m/s the output voltage is 134.35V. But if there is sudden change in wind velocity from 7 to 18 m/s, the voltage changes from 98.99V to 275.77V accordingly. In this scheme, the variations in output voltage with respect to wind velocity are almost narrow.
Fig. 29 THD spectra of ZSI output voltage THI control scheme when M=1.
Fig. 30 THD spectra of ZSI output voltage with THI control scheme.
Fig.18. Dynamic performance of ZSI under third harmonic injection scheme at different wind velocity
Fig. 28 shows the output voltage waveform of ZSI when third harmonic injection scheme is used with M=1. Fig. 29 and Fig. 30 shows the order of harmonics and the % of THD for third harmonic injection control when M=1 and for constant output voltage 220V VI. CONCLUSION This paper presents a detailed analysis of different pulse width modulation methods on Z-source inverter, showing how the various conventional PWM strategies can be modified to switch a voltage type Z-source inverter. With the proper addition of shoot through states, the Z-source inverter modulation methods can be used to produce the desired performance feature from conventional PWM strategies.
Fig. 19. DC link voltage across ZSI at wind velocity of 14m/s
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Bharanikumar.R was born in Tamilnadu, India, on May 30, 1977. He received the B.E degree in Electrical and Electronics Engineering from Bharathiar University, in 1998. He received his M.E Power Electronics and Drives from College of Engineering Guindy Anna University in 2002. He has 9 yrs of teaching experience. Currently he is working as Asst. Professor in EEE department, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India Currently he is doing research in the field of power converter for special machines; vector controlled based synchronous machine drives, converters for wind energy conversion systems.
VII. APPENDIX A. Specifications PMG: Rs=0.34 , Ls=0.65mH, m =1.2 T, No of poles=18 ZSI: 10A, 800V, L1 =L2 =L=160H C1 =C2 =C= 1000F REFERENCES
[1] [2] S. Rajakaruna, Y.R.L.Jayawickrama and N.N.Maw, Steady-state Analysis and Designing Impedance Network of Z-Source Inverters IEEE Trans. Ind. Elect. Vol.57, no.7, July 2010, pp. 2483-2491. Omar Ellabban, Joeri Van Mierlo and Philippe Lataire, Comparison between Different PWM Control Methods for Different Z-Source Inverter Topologies, European Conference on Power Electronics and Applications, September 2009, pp. 1-11. K.Srinivasan and Dr.S.S.Dash, Comparison of Traditional PWM Inverter and a Component Minimized Z-Source Inverter for Ac Drives, Journal of Electrical Engineering, Vol.9, 2009, pp. 13-12. U.Supatti and F.Z.Peng, Z-Source Inverter Based Wind Power Generation System, IEEE International Conference on Sustainable Energy Technologies, Nov. 2008, pp. 634-638. Bharanikumar.R, Senthil Kumar.R , Nirmal Kumar.A.N., Impedance Source Inverter for Wind Turbine Driven Permanent Magnet Generator, Power system Technology and IEEE Power India Conference,2008. POWERCON 2008. 12-15 Oct 2008. D.M.Vilathgamuwa, Wang Xiaoyu and C.J.Gajanayake, Z-Source Converter Based Grid-Interface for Variable-Speed Permanent Magnet Wind Turbine Generators, IEEE Power Electronics Specialists Conference, June 2008, pp. 4545-4550. Feng Wu, Xiao-Ping Zhang and Ping Ju, Modeling and Control of the Wind Turbine with the Direct Drive Permanent Magnet Generator Integrated to Power Grid, DRPT 2008, April 2008, pp. 57-60. Yu Tao, Hwa-Chun Lee, Ji-Seok Song, Doo-Young Song, Dong-Ok Kim, Sung-Jun Park and Chae-Joo Moon, Psim and Matlab Simulations Analysis on 3-Phase Z-Source Inverter, International Caribbean Conference on Devices, Circuits and Systems, April 2008, pp. 1-5. H.Polinder, F.F.A. Vander Pijl, G.J. DeVilder and P, Tavner, Comparison of direct-drive and geared generator concepts for wind turbines, IEEE Trans. Energy Conversion, Vol.21, September 2006, pp.725-733. Miaosen Shen , Jin Wang, Joseph A., F.Z. Peng , L.M.Tolbert and D.J.Adams, Constant Boost Control of the Z-Source Inverter to Minimize Current Ripple and Voltage Stress, IEEE Transactions on Industry Applications, Vol. 42, No.3, May-June 2006, pp. 770778 Monica Chinchilla, Santiago Arnaltes, Juan Carlos Burgos, Control of Permanent-Magnet Generators Applied to Variable-Speed WindEnergy Systems connected to the Grid, IEEE Transactions on Energy Conversion, Vol. 21, No 1, March 2006, pp.130-135. F.Z.Peng, A. Joseph, J. Wang and M. Shen, Z-Source Inverter For Motor Drives, IEEE Trans. Power Electronics, Vol. 20, No. 4, July 2005 , pp. 857863. F. Z. Peng, M. Shen and Z. Qian, Maximum Boost Control of the ZSource Inverter, IEEE Trans. Power Electronics, Vol. 20, No. 4, July 2005, pp. 833838. F. Z. Peng, Z-Source Inverter, IEEE Trans. Ind. Appl., Vol. 39, No. 2, March/April 2003, pp. 504510.
[3] [4] [5]
[6]
A.Nirmal Kumar was born in the year 1951. He completed his PG and UG in Electrical Engineering from Kerala and Calicut University respectively. He completed PhD in Power Electronics in the year 1992 from P.S.G. College of Technology, Coimbatore under Bharathiar University. He was with N.S.S. College of Engineering for nearly 28 years in various posts before joining Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India in the year 2004. He is a recipient of Institution of Engineers Gold Medal in the year 1989. His current research areas include Power converters for Wind Energy Conversion System and Controller for Induction motor drives.
[7]
[8]
[9]
[10]
[11]
[12] [13] [14]
BIOGRAPHIES
B.Indhumathy completed her B.E in Electronics and Communication Engineering from Anna University, Chennai in the year 2009. Currently she is pursuing her M.E Power Electronics and Drives at Bannari Amman Institute of Technology. Her area of interest includes Wind Energy Conversion System and power converters.
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POWER CONTROL USING UPFC SYSTEM

N.MURALIDHARAN, SUDHI.M.M
PERIYAR MANNAIMAI UNIVERSITY VALLAM- 613403, TAMIL NADU. EMAIL:sudhi.mms@gmail.com muralisat90@gmail.com
ABSTRACT
This paper provides a summary of FACTS Fundamentals and its system. The overall process for system studies and analysis associated with FACTS installation projects and the need for FACTS controller models is also discussed. Finally, an introduction to the basic circuits of several FACTS controllers is provided with a focus on their system performance characteristics. FACTS is applicable in parallel connection or in series or in a combination of both. The rating of shunt connected FACTS controllers is up to 800 Mvar, series FACTS devices are implemented on 550 and 735 kV level to increase the line transmission capacity up to several GW. The performance of two parallel FACTS devices the SSSC and STATCOM has been examined in terms of their ability to provide damping to a power system. Simulation results indicate that both the devices are capable of providing additional damping of oscillation.
of maintaining system's stability. Although many power systems were firstly devised several years ago, they are still continuously growing in complexity and extension. Many analysis and control tools share with electric power systems the same long history of research
I. INTRODUCTION
Electric power systems are among the most complex outcomes of engineering, being the result of the interconnection of a huge number of different devices. Safe and reliable operation of such systems is mainly the result of real-time action of several control devices, which ensures proper operation of the whole system both in steady-state and after an equilibrium condition is perturbed by sudden contingencies. Guaranteeing proper operation of electric power systems is therefore the problem
and practical application. Despite this long tradition, the continuous evolution in technologies has strongly affected power systems. In the past three decades, power system stabilizers (PSSs) have been extensively used to increase the system damping for low frequency oscillations. The power utilities worldwide are currently implementing PSSs as effective excitation controllers to enhance the system stability. However, there have been problems experienced with PSSs over the years of operation. Some of these were due to the limited capability of PSS, in damping only local and not inter area modes of oscillations. Flexible AC transmission systems (FACTS) have gained a great interest during the last few years, due to recent advances in power electronics. FACTS devices have been mainly used for solving various power system steady state control problems such as voltage regulation, power flow control, and transfer capability enhancement. As supplementary functions, damping the inter area modes and enhancing power system stability using FACTS controllers have been extensively studied and investigated. Generally, it is not cost-effective to install FACTS devices for the sole purpose of power system stability enhancement. In this work, the current status of power system stability enhancement using
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FACTS reviewed.
controllers was discussed and
II. TYPES OF FACTS 1. Static VAR Compensator (SVC) The static VAR compensator (SVC) is generally designed to operate in both inductive and capacitive continuous compensation (shown in fig.1). The TCR serves as the controller basis for the conventional SVC used for reactive power compensation for either voltage regulation or power factor correction. It is known that the SVCs with an auxiliary injection of a suitable signal can considerably improve the dynamic stability performance of a power system .In the literature, SVCs have been applied successfully to improve the transient stability of a synchronous machine . Then, the low frequency oscillation damping enhancement via SVC has been analyzed . It is shown that the SVC enhances the system damping of local as well as inter area oscillation modes. Self-tuning and model reference adaptive stabilizers for SVC control have been also proposed. The transient ability and steady state power handling capacity can be increased by using SVC at the intermediates buses of the long lines.SVC is the faster in response than synchronous condensers.
The thyristor-controlled series capacitor (TCSC) is also based on the TCR which was first developed for shunt connection (fig.2). When the TCR is used connected in series with the line, it has to be always connected in parallel with a capacitor because it is not possible to control the current if the equivalent of the transmission line and the sources is a current source.
Fig.2 Thyristor controlled series capacitor
Fig.1 Static Var Compensator (SVC) 2. Thyristor-controlled (TCSC): Series Capacitor
This circuit is similar to the conventional SVC, with the difference that the TCSC is connected in series with the line. In this compensator, the equivalent value of the series connected reactor can be continuously controlled by adjusting the firing-angle of the thyristors. As a consequence, this device presents a continuously controllable series capacitor. This device has been used for power flow control and power oscillation damping. 3. Static synchronous series compensator (SSSC) Series reactive power compensation is obtained by controlling the equivalent impedance of a transmission line, as to regulate the power flow through the line. The SSSC can be defined as a static synchronous generator shown in fig.3, which acts as a series compensator whose output voltage is fully controllable, independent of line current and kept in quadrature with it, with the aim of increasing or decreasing the voltage drop across the line, therefore controlling the
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power flow. Series connection of capacitors banks was the first method of series compensation. However, the impossibility to control in real time the level of compensation and the risk of initiating potentially dangerous resonances constitute serious drawbacks to this solution. A series voltage formed by the DC storage capacitor and the converter configuration will be introduced to the system in quadrature to the line current. Capacitive as well inductive compensation is possible. Such SSSC configurations are also used in the Unified Power Flow Controller (UPFC) as series part of the whole device .Two or more of the SSSC can be installed in a system in parallel lines or at major substations with several lines leaving to different areas. Such arrangement allows power flow control under severe system conditions.
voltage, differently from compensation achieved with fixed capacitor's banks or switched capacitor based compensator such as the Static VAR. Thus reactive power support can also be provided at low voltages, when it is most required. If DC voltage is supported by an external energy source or storage device, STATCOM can further enhance FACTS capabilities to improve power system.
STATCOM based on voltage sourced converter. (Fig.4) The control of reactive power in the STATCOM is done by controlling its terminal voltage. It is capable of supplying required reactive power even at small value of bus voltages where the reactive power supply capability gets limited to its susceptance limit. 5. Unified Power Flow Controller (UPFC): Unified power flow controller (UPFC) shown in fig.5, is one of the FACTS devices, which can control power system parameters such as terminal voltage, line impedance and phase angle. Therefore, it can be used not only for power flow control, but also for power system stabilizing control Unified power flow controller (UPFC) is a combination of static synchronous compensator (STATCOM) and a static synchronous series compensator (SSSC) which are coupled via a common dc link,
Fig.3 Static synchronous series compensator 4. Static Compensator (STATCOM): Several inverter controllers proposed for FACTS applications are able to control only the phase of output voltage and not its magnitude which is proportional to DC voltage. In these cases, output voltage regulation is achieved by angle control which determines active power exchange with the network to charge or dis Reactive power exchange achieved by the STATCOM shown in fig.4 is independent of network
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capacity of power plant #2 is exported to the 500-kV equivalent through three 400-MVA transformers connected between buses B4 and B5. Using the load flow option of the powergui block, the model has been initialized with plants #1 and #2 generating respectively 500 MW and 1000 MW and the UPFC out of service (Bypass breaker closed). The resulting power flow obtained at buses B1 to B5 is indicated by red numbers on the circuit diagram. Fig.5 UPFC to allow bi-directional flow of real power between the series output terminals of the SSSC and the shunt output terminals of the STATCOM and are controlled to provide concurrent real and reactive series line compensation without an external electricenergy source. The UPFC, by means of angularly unconstrained series voltage injection, is able to control, concurrently or selectively, the transmission line voltage, x and angle or alternatively, the real and reactive power flow in the line. The UPFC may also provide independently controllable shunt reactive compensation. III. APPLICATION OF UPFC CASE STUDY: A UPFC is used to control the power flow in a 500 kV /230 kV transmission systems. The system, connected in a loop configuration, consists essentially of five buses (B1 to B5) interconnected through transmission lines (L1, L2, L3) and two 500 kV/230 kV transformer banks Tr1 and Tr2. Two power plants located on the 230-kV system generate a total of 1500 MW which is transmitted to a 500-kV 15000-MVA equivalent and to a 200-MW load connected at bus B3. The plant models include a speed regulator, an excitation system as well as a power system stabilizer (PSS). In normal operation, most of the 1200-MW generation
Fig.6 shows the circuit diagram in which UPFC is used to control power flow The load flow shows that most of the power generated by plant #2 is transmitted through the 800-MVA transformer bank (899 MW out of 1000 MW), the rest (101 MW), circulating in the loop. Transformer Tr2 is therefore overloaded by 99 MVA. The demonstration illustrates how the UPFC can relieve this power congestion. The UPFC located at the right end of line L2 is used to control the active and reactive powers at the 500-kV bus B3, as well as the voltage at bus B_UPFC. It consists of a phasor model of two 100-MVA, IGBT-based, converters (one
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connected in shunt and one connected in series and both interconnected through a DC bus on Parameters of the UPFC power components are given in the dialog box. The series converter can inject a maximum of 10% of nominal line-toground voltage (28.87 kV) in series with line L2. The blue numbers on the diagram show the power flow with the UPFC in service and controlling the B3 active and reactive powers respectively at 687 MW and -27 Mvar.
the DC side and to the AC power system).
IV. SIMULATION RESULT:

The UPFC reference active and reactive powers are set in the magenta blocks labeled "Pref(pu)" and "Qref(pu)". Initially the Bypass breaker is closed and the resulting natural power flow at bus B3 is 587 MW and -27 Mvar. The Pref block is programmed with an initial active power of 5.87 pu corresponding to the natural flow. Then, at t=10s, Pref is increased by 1 pu (100 MW), from 5.87 pu to 6.87 pu, while Qref is kept constant at -0.27 pu.
At t=5 s, when the Bypass breaker is opened the natural power is diverted from the Bypass breaker to the UPFC series branch without noticeable transient. At t=10 s, the power increases at a rate of 1 pu/s. It takes one second for the power to increase to 687 MW. This 100 MW increase of active power at bus B3 is achieved by injecting a series voltage of 0.089 pu with an angle of 94 degrees. This results in an approximate 100 MW decrease in the active
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power flowing through Tr2 (from 899 MW to 796 MW), which now carries an acceptable load. V. CONCLUSION Thus the summary of the FACTS controllers is provided which helps in knowing the advantages of using it for the mitigation of power system losses. An illustration of using a FACTS device is given for the better understanding. In this study MATLAB environment is used to simulate the UPFC controller. It has been highlighted that FACTS devices can be augmented with supplementary controllers which can provide additional benefits such as increased damping of power system oscillations, steady state system performance, rapid control of reactive power flow, etc.
VI. REFERENCE
a. S.Tara Kalyani and G. Tulasiram Das,Control and performance of UPFC connected to transmission line, published at IEEE PES conference IPEC07, Singapore. b. Claudio Canizares, Edvina Uzunovic and John Reeve. Transient stability and power flow models of the unified power flow controller for various control strategies. Technical report # 2004-09. c. H. Fujita, Y. Watanabe and H. Akagi. 2006. Dynamic Control and Performance of a Unified Power Flow Controller for Stabilizing an AC Transmission System. d. J.Chen, T.T.Lie, Enhancement of Power system Damping Using VSC based Series Connected FACTS Controllers, IEEE Proceedings, Generation Transmission Distribution, Vol. 150. No. 3, May2003.
352
Power Quality Monitoring and Control

K.NATHIYA, P.DIVYAPRIYA VIVEKANANDA COLLEGE OF ENGINEERING FOR WOMEN
ABSTRACT: This paper proposes a remote oscillography system applied for power quality monitoring that allows users to capture waveforms from remote modules in real time, to analyze data, and to control a remote terminal using Ethernet networks. Two protocols are presented, i.e., one for monitoring and other for controlling. We also describe a low-cost remote module using an 8-bit microcontroller. I. INTRODUCTION The control of quality and reliability in power is currently a major concern. Noise-sensitive equipment and machines that need a steady stream of energy have become a standard. Because of that, concern about the quality of energy has increased, and customers are seeking the best option in the market of electrical energy. Customers also have their own problems. Todays industrial plants have a wide variety of noise-generating equipment that inject harmonics and pollutes electric lines. All these problems in an ac power supply that can disturb the proper operation of equipment are encompassed in the term power quality. To minimize problems related to power quality, action needs to be taken in case of disturbances. This creates a need for appropriate monitoring of electric lines at multiple locations simultaneously In the following sections, we will present the model of a system that is able to monitor and execute actions in electric lines with a different approach. The system allows not only realtime oscillography but also the control and monitoring of the power
quality parameter. By the use of realtime oscillography, it is possible to calculate and process all the power quality parameters of many remote modules in one single place and reduce the cost of these modules. This kind of strategy is possible by the use of highspeed networks like Ethernet.
Fig. 1. Monitoring system proposed. A central computer receives data from remote modules through the Ethernet network.
II. SYSTEM MODEL The system model is depicted in Fig. 1. A central computer controls and monitors all the activities in a remote station via an Ethernet interconnection. For remote oscillography purposes, each module continuously sends the waveform of one or more analog channels. This technique reduces the amount of computational processing needed by the remote module and, therefore, the final cost. An application running in the central computer processes the data, allowing the monitoring of quality parameters like voltage and current (RMS and Average), Frequency, apparent power, real power, reactive power, cosine theta, and fast Fourier transform (FFT). The system also allows a preprocessing of quality parameters in the remote station. This
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option decreases the network traffic but increases the computational processing needed by the remote station. The system also makes possible the exchange of information between the remote station and the central computer. This Features allow the read and write access of registers on remote stations for automation purposes. III. PROTOCOLS A. Standard Protocols The current protocols used in the industrial field, e.g., Realtime Transport Protocol (RTP), Simple Network Management Protocol (SNMP), and Modicon Bus (MODBUS) Transmission Control Protocol (TCP), do not enclose all the desired features to a proper operation of the proposed system.
RTISP CENTRAL RTMCP COMPUTER
response
Solicitation
REMOTE MODULE
Fig. 2. Proposed protocols. RTISP provides a constant stream of data, allowing oscillography, and RTMCP provides control.
The RTP protocol is used to transmit information in real time via the Internet. It is used in live audio and video transmission and allows real-time packet reception. It has the speed of User Datagram Protocol (UDP)/IP protocol stack and has its own mechanism of packet control. However, it does not have a suitable configuration mechanism of data to be transmitted in a packet (encoding, resolution, transmission rate, and number of channels), and the transmission is performed in only one direction. This protocol is not appropriate for oscillography because there is no suitable way to configure the sample rate, sample resolution, number of channels, and sample time stamps.
The SNMP protocol is used for computer network management. Many Uninterrupted Power Source (UPS) companies use it to manage its equipment. It is able to send alarm signals, does not need connection due to the use of UDP, and has a data structure called Management Information Base (MIB) that helps the configuration monitoring software. SNMP is, however, a complex protocol and does not allow the transmission of a large volume of data in real time. MODBUS is an oftenused protocol in industry automation. Its Internet version (MODBUS/TCP) is recent. This protocol is easy to implement, allows reading and writing of remote data, and is a well-known industrial standard. Its drawbacks are a Master/Slave topology, which limits the actions of peripherals, and the use of the TCP/IP protocol instead of UDP/IP, which decreases the speed performance. This protocol can be used to monitor and control power quality parameters, but it is not suitable for performing real-time oscillography. PROPOSED PROTOCOL: The protocols earlier listed have many important features for remote power quality monitoring. However, none encompasses all the features to perform real-time oscillography, power quality monitoring, and controlling. To fill this gap, we proposed a pair of protocols, i.e., the Real-Time Instrumentation Stream Protocol (RTISP) and the RealTime Monitoring and Controlling Protocol (RTMCP). The first protocol deals with oscillography data stream and alarm signals with real-time characteristics, and the second protocol is responsible for controlling the remote station and sending preprocessed power quality information (see Fig. 2).
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It is impossible to achieve truly real-time monitoring with computer networks due to the fact that networks introduce many delays during the information trip. In the case of using networks like the Internet, these delays can be completely unpredictable. This way, delays on the order of milliseconds can happen between an event and its reception. The real-time characteristics referred to in this paper are similar to those referred to by RTP. The RTMCP controls the remote module, regulates the data stream, and synchronizes the RTISP packets. It operates in RTISP packet structure. Interaction between the RTISP protocol and the TCP/IP suite protocol. Masterslave fashion, i.e., the central computer sends a request to a remote station and waits for its reply. Remote oscillography, as provided by RTISP, is a powerful tool for power quality analysis. It allows the observation of wave shapes of analog signals at remote sites. It is also possible to store this information for late analysis. No mechanism is provided for lost packet recovery in RTISP. A recovery feature would impact the system speed operation, and it is useless, considering the oscillography application. Fig. 3 depicts an RTISP packet. The RTISP header has 14 B and contains information like stream identification, packet index, time stamp of the first sample, and number of channels (analog or digital). This header then follows the information of each channel. Each channel has a 4-B header. For an analog Channel, the header identifies the channel number, the resolution of the sampled data, and the number of samples.UDP is a transport layer protocol. It provides a service with small transmission overhead and has port numbers that allow different applications
to concurrently send and receive data. The UDP datagram is encapsulated into the IP protocol. The IP protocol provides a virtual address, allowing data packets to be sent from one host to another. The IEEE 802.3 standard, also known as Ethernet, deals with the physical transmission of the data. It is possible to estimate the number of modules that can share the same Ethernet network using full-duplex mode by PackLGT =HeadRTISP +NCHANN (HeadCHANN+DataLGT) --- (1) DataLGT=SampleRATE sampleRES/PackRATE --- (2) Ethlen=InterGap+Ethpreamble+ Ethheader+ IPheader + UDPheader + RTISPlen + EthCRC. -- (3) PackLGT is the length of an RTISP packet in bytes. It should not exceed 1472 B. NCHANN is the number of channels sampled, HeadRTISP is equal to 14 B, and HeadCHANN is equal to 4 B. DataLGT is the length of the sample field of a channel in bytes, SampleRATE is the sample rate in samples per second, SampleRES is the resolution of a measurement sample in bytes per sample, which can be 8 and 16 bits, and PackRATE is the average packet rate in packets per second. The IEEE 802.3 frame length may be calculated by (3), where InterGap is the minimum idle period between frames. All other variables, except RTISPlen, are constants. Resuming, Ethlen = RTISPlen + 66 B. The number of remote modules in Table I considers a 10-Mb/s Ethernet network, SampleRATE = 8000 sample/s, and PackLGT 1472 B/packet. IV. RECEPTION APPLICATION
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A reception application was developed to process the data stream acquired and control remote modules. By the main window it is possible to visualize and manage the oscillography resources. By the submenu View, it is possible to open the Control panel, Measure, and FFT windows. The control panel window is responsible for starting a section with a remote module. This operation begins with the data stream used for oscillography. The measurement window deals
Fig. 3. Main window control panel.
with electrical parameters like RMS values, average values, frequency, apparent power, real power, and reactive power All these values are calculated by the reception application. The FFT window allows the spectrum analysis of a sampled channel. It is possible to adjust the number of points Sampled and freeze the window. The reception application displays each data stream as an oscilloscope connected to a measurement point. Up to six channels scan simultaneously be analyzed. This allows the analysis of the power quality in a three-phase line: three channels for voltage and three channels for current. The maximum
sample rate is 8000 samples/s, with a vertical resolution of 8 or 16 bits. This sample rate allows a spectral analysis of the first 66 harmonics. The vertical resolution impacts the network traffic generated by the RTISP. An 8-bit resolution, for example, reduces the traffic by half without a significant loss in the displayed waveform. This resolution is used by the majority of the digital oscilloscopes and is suitable for oscillography purposes. It is also possible to save data in standard files for late analysis and have more than one computer running the monitoring application. IMPLEMENTATION The reception application was written in C++, and it used the multithread concept. Three threads were used. The main thread deals with visual components like windows, button, menus, mouse, and keyboard. The other threads are infinite loops: One thread was responsible for receiving RTISP packets, and the other thread deals with the oscillography in the main window. Synchronization is necessary due to the data sharing between the threads. The receiving thread is responsible for receiving and ordering valid RTISP packets in a chained list The packets are ordered in a first-infirst-out (FIFO) fashion. As each RTISP packet has an index, it is possible to ordinate the chain list as FIFO and detects packet loss as well. This is necessary because it is impossible to guarantee the packet reception order in long networks. It did not use dynamic allocation for the RTISP packets to prevent memory fragmentations. The chain list can be accessed by other threads by means of a multiple exclusion semaphore. This prevents access during an actualization
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operation. The semaphore is only activated in reduced parts of the code because of the efficiency loss caused by an active semaphore. In the case of an active semaphore, a threat needs to wait until the semaphore is deactivated to continue its operation. The oscillography thread was introduced to improve the application response. Without it, two approaches could be considered. In the first one, the thread that controls the mouse, keyboard, and graphical objects would draw the graphic data. This would result in an unsatisfactory response in commands. In the second one, the drawing operation would be inserted in the thread responsible to receive RTISP packets. As the graphic operation is time consuming, some packets could be lost during the drawing. V.TESTS AND IMPLEMENTATION: ETHERNET NETWORK SUBMITTED TO RTISP PACKETS This test used three computers performing different operations connected by a 100-Mb/s network. One computer generates RTISP packets; the second computer receives the packets, and the third computer measures packet traffic by counting the number of UDP packets sent and lost. At a sending rate of 50 packets/s, no packet loss was detected for 1440-B-long packets. Without controlling the packet rate, a mean throughput of 6500 packets/s with packets of 1440-B size was achieved. At this condition, the transmission rate reaches 85 Mb/s, and the packet loss was lower than 0.17%
Fig.5. Remote module. (Upper board) Ethernet controller. (Lower board) Microprocessor and memory. (Left board) ADC.
LOW-COST REMOTE MODULE This hardware is able to operate as a remote module using a 10baseT Ethernet connection. All functions of the RTISP protocol and some functions of the RTMCP protocol were implemented. It also has the UDP, IP, Internet Control Message Protocol (ICMP), and Address Resolution Protocol (ARP) protocols. The following four devices are the main components: an 8051-compatible microcontroller running at 6 MHz, a 32kB static RAM, an Ethernet controller, and an 8-bit analog-to digital converter (ADC). The code was written in C. Only the ADC acquisition routine used an assembly language. This was made to guarantee a constant sample. The system achieves a sample rate of 2000 sample/s, allowing the spectral analysis of the first 16 harmonics. An increase in the processor speed to 18 MHz would allow the analysis of the first 50 harmonics. The main routine is an infinite loop that continuously checks if there are new data to be sent. If the data are ready, an RTISP packet is created, and the buffer used to store these data is considered empty. Meanwhile, another buffer is used to store the data acquired by the ADC. The number of input channels and the processor speed could easily be improved to achieve a six-channel, 8000-sample/s module without a significant cost increase. This is a good result for a power quality monitoring
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system in comparison with other proposed implementations that use PCs and VXI boards. These implementations do not perform remote real-time oscillography. In the measurement devices (or PCs) use the Internet to send power quality parameters to clients. In it used the VXI-11 standard to monitor and control remote instruments, including oscilloscopes. However, it does not allow reception of continuous data streams from remote acquisition modules. VI. FINAL COMMENTS: It is feasible to supervise the power quality using low-cost modules connected by Ethernet networks. Advanced features like real-time oscillography and FFT analysis are possible if all calculations are executed in the computer, which receives the data. The drawback of the proposed system is an increase in the network traffic. Considering this, we designed the RTISP protocol using the UDP protocol, which generates less traffic in comparison with the TCP protocol. Detection of power phase change is very important in quality measurement. In the proposed system, each packet has a time stamp that marks the first sample. This can be used to accurately determine the phase by means of time synchronization among the remote modules and the central computer. The use of GPS is an easy way to synchronize the module time, but it has cost implications. Network Time Protocol (NTP) is a protocol used to synchronize machines interconnected by Internet or Ethernet networks, but it cannot be used because the maximum precision reached has an error of 10 ms. A study proposing a precision synchronization mechanism to
improve the time synchronization precision over the Internet is presented in and This synchronization mechanism can achieve precision of microseconds over the Internet and is an option to substituting a GPS. To improve reliability and error recovery, it would be necessary to implement an acknowledge procedure because UDP has no package delivery guarantee. The necessity to resend data requires additional storage to keep the sampled values, resulting in a considerable increase in module cost. REFERENCES
[1] C. Sankaran, Power Quality. Boca Raton, FL: CRC, 2002, ch. 1. [2] 1998 Edition Information Technology Telecommunication and Information Exchange Between SystemsLocal and Metropolitan Area Specification, IEEE Std. 802.3, 2005. [3] H. Schulzrinne et al., RTP: A transport protocol for real-time applications. RFC 3550, Std. 64. [4] W. Stallings, SNMP, SNMPv2, SNMPv3, and RMON 1 and 2, 3rd ed. Reading, MA: Addison-Wesley, 1999. [5] Modicon, Inc., Modicon Modbus Protocol Reference Guide, 1996, West Boylston, MA: Ind. Autom. Syst. [6] J. Postel, User Datagram Protocol RFC 768, Aug. 1980. [Online]. Available: http://www.ietf.org/ [7] J. Postel, Transmission Control Protocol RFC 793, Sep. 1981, USC/ Information Sci. Inst. [Online]. Available: http://www.ietf.org/ [8] L. F. Auler and R. dAmore, Power quality monitoring and control using Ethernet networks, in Proc. Int. Conf. Harmonics Quality Power 10, Rio de Janeiro, Brazil, 2002, pp. 208213. [9] Tektronix Inc., Test, Measurement and Monitoring Product Catalog, 2003. [10] IEEE Standard Common Format for Transient Data Exchange (COMTRADE) for Power Systems, IEEE Std. C37.111-1999
358
REDUCTION OF HARMONICS IN INTEGRATED POWER FACTOR CORRECTION STAGE WITH HIGH EFFICIENCY DC-DC CONVERTER
V.karthika1, J.lakshmanaperumal2 1PG student, 2 professor, Department of Electrical Engineering, Government College of Engineering, Salem-11
ace_karthika@yahoo.co.in
ABSTRACT
Power factor correction allows power distribution to operate at its maximum efficiency. Active PFC uses a circuit to correct power factor of over 95%, reduce total harmonics. This paper presents harmonic reduction and improvement of power factor by single stage topologies with high frequency insulation. The input current harmonics is reduced by auxiliary windings which place between input rectifier and the low frequency filter capacitor and its eliminates the use of active switch and control circuit for PFC. In order to achieve low harmonic content, the input inductor is designed to operate in discontinuous current mode. Operating principle, analysis and experimental result of the proposed method are presented.
Fig1.circuit diagram of power factor correction
I.INTRODUCTION
The power factor of an AC electric power system is defined as the ratio of the real power flowing to the load to the apparent power in the circuit .In an electric power system, a load with a low power factor draws more current than a load with a high power factor for the same amount of useful power transfer.
approach to improving the power factor is a two stage power conversion approach but there is drawback like higher cost and larger size resulted from its complicated power stage topology and control circuits, particularly in low power application. In order to reduce the cost, the single stage approach, which integrates the PFC stage with a dc-dc converter in one stage, is developed. In this method a dither rectifier is used to reduce distortion and improve the power factor. The concept is illustrated in Fig.2. A non-linear Dead-zone element is supplied by a sinusoidal voltage whose amplitude is slightly higher than the dead-zone limitVB. Thus, the output signal is made up of narrow pulses having a high harmonic content (this situation is typical of the diode-capacitor rectifiers where the absorbed current takes the place of the output signal). Adding to the low-frequency input signal a high-frequency dither signal, with amplitude higher than VB, increases the conduction
Power supplies connected to ac mains introduce harmonic current in the utility because of this several problems such as voltage distortion, heating, noise and reduce the capability of the line to provide energy. To overcome this problem the PFC in power supplies is used. The input current waveform are shape by IEC 61000-3-2.A common
359
Intervals of the dead-zone element, thus reducing operated at high frequency, the auxiliary winding the low-frequency harmonic content is removed. produces a high frequency pulsating source
Such that the input current conduction angle is significantly lengthened and the input current harmonics is reduced. The input inductor LB operates in DCM such that a lower THD of the input current can be achieved. The structure, operation principles, and analysis of the proposed converter are presented in section II. Design example and the experimental results are presented in Section III.
Fig. 2. general block diagram of dither rectifier with PFC cell
Single-stage PFC converters meet the regulatory requirements regarding the input current harmonics, but they do not improve the power factor and reduce the THD as much as their conventional two-stage counterpart. The power factor could be as low as 0.8, however, they still meet the regulation. In addition, although the single-stage scheme is especially attractive in low cost and low power applications due to its simplified power stage and control circuit, major issues still exist, such slow efficiency and high as well as widerange intermediate dc bus voltage stress [5], [6]. To overcome the disadvantages of the single-stage scheme, many converters with input current shaping have been presented [3][12], in which a high frequency ac voltage source (dither signal) is connected in series with the rectified input voltage in order to shape the input current (see Fig. 2). Another technique based on parallel connection of this dither signal is presented in [13], however, the harmonic content can meet the regulatory standard by a small margin. In [14], a new concept of quasi-active PFC is proposed to improve the efficiency of a single-stage converter by preventing the input current or voltage stress due the PFC cell from being added to the active switch. In this circuit, the dc/dc cell operates in DCM so that a series of discontinuous pulses is used to shape the input inductor current and the PFC is achieved. As the circuit uses resonance of circuit parameters to achieve PFC, the control of the power factor will be very sensitive to the variation of components values New technique of quasi-active PFC is proposed As shown in Fig. 3 the PFC cell is formed by connecting the energy buffer (LB ) and an auxiliary winding (L3 ) coupled to the transformer of the dc/dc cell, between the input rectifier and the low-frequency filter capacitor used in conventional power converter. Since the dc/dc cell is
Fig.3. proposed quasi active PFC circuit diagram.
II.PROPOSED CIRCUIT FOR PFC

The proposed quasi-active PFC circuit is analyzed in this section. As shown in Fig. 2, the circuit comprised of a bridge rectifier, a boost inductor LB, a bulk capacitor Ca in series with the auxiliary windings L3, an intermediate dc-bus voltage capacitor CB, and a discontinuous input current power load, such as flyback converter. The flyback transformer (T) has three windingsN1, N2, and N3. The secondary winding N2 = 1is assumed. In the proposed PFC scheme, the dc/dc converter section offers a driving power with high-frequency pulsating source. The quasi active PFC cell can be considered one power stage but without an active switch. A. operating principles of the circuit Assume that both the input inductor LB and the magnetizing inductances of the flyback converter operate in DCM. Therefore, currents iLB, im, and i2 are zero at the beginning of each switching period. It is also assumed that the average capacitor voltage VCa greater than the average rectified input voltage |vin |. To ensure proper operation of the converter, the transformers turns ratio should be (N1/N3) 2 and the boost inductor LB < Lm. In steady-state operation, the topology can be divided into four operating stages.
360
The proposed circuit has less switch current stress, 1) MODE 1 (to t1 ): therefore, the conduction loss and switching losses are When the switch (SW) is turned on at t = to , diodes D1 and Do are OFF, therefore, the dc-bus voltage reduced, and the efficiency is improved correspondingly. This stage ends when the switch is turned off at VCB is applied to the magnetizing inductor Lm, which causes the magnetizing current to linearly increases. This t = t1. current can be expressed as im = VCB Lm(to t1 ). (1) And since diode D1 is OFF, the input inductor LB is charged by input voltage, therefore, the inductor current iLB is linearly increased from zero since it is assumed that the PFC cell operates in DCM. This current can be expressed as (2) Where, Vin = Vm| sin | is the rectified input voltage, (to t1) = dTS is the ON-time of the switch (SW), LB is the boost inductor and N1 , N3 are the primary and auxiliary turns ratio, respectively. At this stage, iLB = i3 and the capacitor Ca is in the charging mode. On the other hand, Do is reversed biased and there is no current flow through the secondary winding.Since the transformer is assumed ideal, based on Amperes law, it has N1 i1 + N2 i2 N3 iLB = 0 (3) 2) MODE 2(t1-t2): When the switch is turned OFF at t = t1 , output diode Do begins to be forward biased. Therefore, the energy stored in the transformer magnetizing inductor is delivered to the load through the secondary winding. Similarly, the diode D1 is also forward biased and the voltage across LB nowVin VCB. Therefore, the current ILB is linearly decreased to zero at t = t2 (DCM operation), and the energy stored in LB is delivered to the dc bus capacitor CB . Therefore
The capacitor (Ca ) is also discharging its energy to the dc bus capacitor CB and the current i3 reverse its direction. Therefore, the capacitor current is given by iD1 = iCB = iLB + i3 . (7)
Where i2 = 0 at this stage therefore, i1 = N3/N1iLB = N3/N1(i3) (3) Thus im = iCB i1 = iCB + N3/N1(i3) (4)
Fig. 5. mode 2
3) MODE 3 (t2-t3): At this stage, the input inductor current iLB reaches zero and the capacitor Ca continues to discharge its energy to the dc bus capacitor CB . Therefore, Fig. 4. mode 1 iD1 = iCB = i3 . Therefore, from (4) it can be seen that the magnetizing At t = t3 , the magnetizing inductor releases all its energy current im is supplied by the discharging current from to the load and the currents im and i2 reach to zero level the dc bus capacitor CB and the current i3 which is equal because a DCM operation is assumed. to input current iLB at this stage. The current through the main switch (SW) is given by iSW = im + iLB . (5)
361
In order to verify the proposed concept, a prototype of the converter shown in Fig. 2 was constructed and experimentally tested. To ensure proper operation of the converter, the dc bus voltage (VCB) must be higher than the input voltage, such that the diode D1 is OFF and the inductor LB stores energy when the switch (SW) is ON. Therefore, from (15) the inductor Lm must be higher than the input inductor LB. The DCM Fig.6. mode 3 flyback converter was designed and implemented for 50 V/80 W output, Vin,rms (100240 V) universal line 4) MODE 4(t3-t4): voltage, and overall efficiency of 86% is assumed. The switching frequency is selected to be 100 kHz and the This stage starts when the currents im and i2 reach to zero. DiodeD1 still forward biased, maximum duty cycle of is 0.45. The major components therefore, the capacitor Ca still releasing its energy to the of the circuit are follows: transformer turns ratio (N1 = dc bus capacitor CB.This stage ends when the capacitor 30,N2 = 10,N3 = 15) with core ETD34, Lm = 200 H, LB = 80 H, CB = 47 F, Ca = 22 F, Co = 470 F, the switch SW (SPW22N60), the bridge rectifier and diodes D1,Do using MUR1560.
Ca is
Fig. 7. mode 4
completely discharged and current i3 reaches zero. At t = t5 , the switch is turned on again to repeat the switching cycle.
Fig .9. measured input voltage and filtered input current at full load.
Fig. 5 shows the measured input voltage and filtered input current waveforms for a 100 Vac input voltage at full load. As it may be seen from Figs. 4 and 5, that selecting the turns ratio N3/N1 and the dc bus voltage VCB can be optimized in order to reduce the dead time and improve the quality of the input current
Fig.8.Key switching waveforms
III. EXPERIMENTAL VERIFICATION
Fig.10. Response between 50% and 100% of load
362
content of the input current compared to the Classes A and D regulation standards. Note that, in order to improve the visibility of the higher order harmonics, class A limits are scaled down by a factor of 5 (class limits/5). The measured THD = 7% and the power factor is 0.997. Obviously, the input current is much closer to the sinusoidal waveform and it meets the regulation standards. Fig. 7 shows the transient response of the converter for a step change of load between 50% and 100%. It may be seen that a fast dynamic response has been obtained. Fig. 8 shows the measured dc bus voltage VCB and efficiency of the converter for range of load and input voltage variation. It may be seen that the capacitor voltage can be maintained below 450 V by properly designing the turns ratio N3/N1 and the inductors ratio Lm/LB .Furthermore,the proposed converter can maintains 90% efficiency or above at high load.
Fig .11.Measured dc bus capacitor voltage and efficiency versus load power for a range of input voltage
IV. CONCLUSION
In this letter, a new ac/dc converter based on a quasi-active PFC scheme has been presented. The proposed method produces a current with low harmonic content to meet the standard specifications as well as high efficiency. This circuit is based on adding an auxiliary winding to the transformer of a cascade dc/dc DCM flyback converter. The input inductor can operates in DCM to achieve lower THD and high power factor. By properly designing the converter components, a tradeoff between efficiency and harmonic content can be established to obtain compliance with the regulation and efficiency as high as possible. Operating principles, analysis, and experimental results of the proposed method are presented. REFERENCES
1)Millman and hawkies c.c. integrated electronics mcgraw hill, 1972 2)Roy choudhury d, shail jain, linear integrated circuit, New Age International Publishers, New Delhi,2000 [1] O. Gracia, J. A. Cobos, R. Prieto, and J. Uceda, Single-phase powerfactor correction: A survey, IEEE Trans. Power Electron., vol. 18, no. 3,pp. 749755, May 2003. [2] R. Redle, L. Balogh, and N. O. Sokal, A new family of single-stageisolated power factor correctors with fast regulation of the output voltage, in Proc. IEEE PESC 1994 Conf., pp. 11371144. [3] C. Qian and K. Smedley, A topology survey of single-stage power factor with a boost type input-current-shaper, IEEE Trans. Power Electron.,vol. 16, no. 3, pp. 360368, May 2001. [4] T.-F. Wu, T.-H. Yu, and Y.-C. Liu, An alternative approach to synthesizing single-stage converters with power factor correction feature, IEEE Trans. Ind. Electron., vol. 46, no. 4, pp. 734748, Aug. 1999. [5] L. Huber, J. Zhang, M. Jovanovic, and F.C. Lee, Generalized topologiesof single-stage input-currentshaping circuits, IEEE Trans. PowerElectron., vol. 16, no. 4, pp. 508513, Jul. 2001. [6] H. Wei, I. Batarseh, G. Zhu, and K. Peter, A singleswitch AC-DC converter with power factor correction, IEEE Trans. Power Electron.,vol. 15, no. 3, pp. 421 430. [7] L. K. Chang and H. F. Liu, A novel forward AC/DC converter with input current shaping and fast output voltage regulation via reset winding, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 125131, Feb. 2005. [8] H. L. Do, Single-stage single-switch power factor correction AC/DC converter, Inst. Electr. Eng. Proc. Electr. Power Appl., vol. 152, no. 6, pp. 15781584, Nov. 2005. [9] J. Qian, Q. Zhao, and F. C. Lee, Single-stage singleswitch power factor correction ac/dc converters with dcbus voltage feedback for universal line applications, IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1079 1088, Nov. 1998. [10] S. Luo,W. Qiu,W.Wu, and I. Batarseh, Flyboost power factor correction cell and a new family of singlestage AC/DC converters, IEEE Trans. Power Electron., vol. 20, no. 1, pp. 2433, Jan. 2005. [11] M. M. Jovanovic, D. M. Tsang, and F. C. Lee, Reduction of voltage stress in integrated high-quality rectifiers-regulators by variable frequency control, in Proc. IEEE APEC 1994 Conf., pp. 569575. [12] J. Sebastian, A. Femandez, P. Villegas, M. Hemando, and J. Prieto, New topologies of active input current shapers to allow AC-to-DC converters with
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asymmetrically driven transformers to comply with the IEC-10003-2, IEEE Trans. Power Electron., vol. 17, no. 4, pp. 493501, Jul.2002. [13] N. Vazquez, J. Lopez, J. Arau, C. Hernandez, and Elias Rodriguez, A different approach to implement an active input current shaper, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 132138, Feb. 2005. [14] K. Zhou, J. G. Zhang, S. Yuvarajan, and D. F. Weng, Quasiactive power factor correction circuit for switching power supply, IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1410 1414, May 2008.
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Power Quality Enhancement In Distribution Systems Using USSC

T.Rajesh1 , T.Ramya2, G.Manochitra3
1.Assistant
Professor. 2. Student 3. Student
Info Institute of Engineering

Abstract-- This project deals with simulation of a unified series-shunt compensator (USSC) aimed at examining its capability in improving power quality in a distribution system. The power quality problems considered here are voltage sag, voltage swell and voltage unbalance. Similar to the UPFC in the transmission systems, the device USSC can be used in the distribution system. Unlike the UPFC where the inverters are connected in shunt -series fashion here the inverters are in series-shunt fashion. Simulations are carried out using the MATLAB software to validate the performance of the USSC model. Simulation results verify the capabilities of the USSC in performing voltage sag compensation, voltage unbalance mitigation and voltage swell compensation. Index TermsPower-quality mitigation, unified seriesshunt compensator, Distribution system
I.INTRODUCTION
N increasing demand for high quality,
reliable electrical Power and an increasing number of distorting loads have led an increased awareness of power quality both by customers and utilities. For power-quality improvement, the development of power electronic devices such as flexible ac transmission system (FACTS) and custom power devices have introduced an emerging branch of technology providing the power system with versatile new control capabilities. In general, FACTS devices are used in transmission control. Whereas custom power devices are used for distribution control. Since the introduction of FACTS and custom power concept, devices such as unified power-flow controller ,synchronous static compensator (STATCOM), dynamic voltage restorer (DVR), solid-state transfer switch, and solid-state fault current limiter are developed for improving power quality and reliability of a system. Advanced control and improved semiconductor switching of these devices have achieved a new era for power-quality mitigation. Investigations have been carried out to study the effectiveness of these devices in power-quality mitigation such as sag compensation, harmonics elimination, unbalance compensation, reactive power compensation, power-flow control, power factor
correction and flicker reduction. These devices have been developed for mitigating specific power-quality problems. For example, UPFC works well for powerflow control. DVR, which acts as series Compensator, is used for voltage sag compensation. STATCOM, which is a shunt compensator, is used for reactive power and voltage sag compensation. The STATCOM and DVR are only useful for compensating a particular type of power-quality problem and therefore, it is necessary to develop a new kind of unified series-shunt compensator (USSC) which can mitigate a wider range of power-quality problems. By using a unified approach of series-shunt compensators, it is possible to compensate for a variety of power-quality problems in a distribution system including sag compensation, flicker reduction, unbalance voltage mitigation, and powerflow control. However, not much work has been carried out in the development of a USSC. The objective of this paper is to explore the capabilities of a USSC in mitigating power-quality problems. The proposed model of the USSC considers the use of two 12-pulse inverters. The modeling and simulation of the USSC has been carried out using the well-known electromagnetic transient simulation program PSCAD/EMTDC. Analyzes have been made by comparing the performance of the USSC to that of the STATCOM and the DVR. II.POWER QUALITY ISSUES Widespread use of electronics in everything from home electronics to the control of massive and costly industrial processes has raised the awareness of power quality. Power quality or more specifically, a power quality disturbance is generally defined as any change in power (voltage, current, or frequency) that Interferes with the normal operation of electrical equipment. The study of power quality, and ways to control it, is a concern for electric utilities, large industrial companies, businesses, and even home users. The study has intensified as equipment has become increasingly sensitive to even minute changes in the power supply voltage, current, and frequency. The Institute of Electrical and Electronics Engineers (IEEE) has attempted to address this problem by developing a standard That includes definitions of power disturbances. The Standard (IEEE Standard 1159-1995, "IEEE Recommended Practice for Monitoring
Vdq VX
365
Electrical Power Quality") describes many power quality problems, the various power quality problems are 1. Transient 2. Interruptions 3. Sag / under voltage 4. Swell / Over voltage 5. Waveform distortion 6. Voltage fluctuations 7. Frequency variations The problems analyzed here which the USSC Can effectively mitigate are Voltage swell Voltage sag Voltage unbalance A. Voltage sag Sag is a reduction of AC voltage at a given frequency for the duration of 0.5 cycles to 1 minutes time. Sags are usually caused by system faults, and are also often the result of switching on loads with heavy startup currents. Undervoltages are the result of longterm problems that create sags. The term brownout has been commonly used to describe this problem, and has been superseded by the term undervoltage. B. Voltage swell A swell is the reverse form of sag, having an increase in AC voltage for duration of 0.5 cycles to 1 minutes time. For swells, high-impedance neutral connections, sudden (especially large) load reductions, and a single-phase fault on a three-phase system are common sources. overvoltages can be the result of long-term problems that create swells. An overvoltage can be thought of as an extended swell. C. Voltage unbalance A voltage imbalance is not a type of waveform distortion. Simply put, a voltage imbalance (as the name implies) is when supplied voltages are not equal. While these problems can be caused by external utility supply, the common source of voltage imbalances is internal, and caused by facility loads. More specifically, this is known to occur in three phase power distribution systems where one of the legs is supplying power to single phase equipment, while the system is also supplying power to three phase loads. D. USSC The USSC is a combination of series and shunt voltage Source inverters and its basic configuration are shown in Fig.1
Series Transformr XL Generator
Load
Shunt Transformer Inverter1 Inverter2
Fig.1 - Model of USSC
The basic components of the USSC are two voltage source inverters composed of forced commutated power Semiconductor switches, typically gate turn off (GTO) thyristor valves. One voltage source inverter is connected in series with the line through a set of series injection transformers, while the other is connected in shunt with the line through a set of shunt transformers. The dc terminals of the two inverters are connected together and their common dc voltage is supported by a capacitor bank. The USSC is almost similar to the UPFC, but the only difference is that the UPFC inverters are in shunt-series connection. And it is used in transmission systems whereas the USSC Inverters In series-shunt connection and it is used in distribution Systems. The principle operation of a USSC is described by first referring to the model shown in Fig.1. As mentioned earlier, the USSC consists of a shunt connected inverter and a series connected Inverter. The series connected inverter injects a voltage Vdq in series with the distribution line, which in turn changes The voltage VX across the distribution line reactance XL, changing the current and the power flow through the distribution line. The USSC behaves as an ideal ac-toac inverter, in which the Exchange of real power at the terminal of one inverter to the Terminal of the other inverter is through the common dc link Capacitor. It should be noted that the shunt inverter is controlled in such a way as to provide precisely the right amount of real Power at its dc terminal to meet the real power needs of the Series inverter and to regulate the dc voltage of the dc bus. Thus, Real power is absorbed from or delivered to the distribution line through the shunt connected inverter, which injects a current at the point of connection. Thus, USSC includes the functions of both series and shunt Connected inverters which generates or absorbs reactive power to regulate voltage magnitude and current flow at the AC terminal, respectively III.METHODOLOGY A. Voltage sag
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A voltage sag can be created with the circuit shown in Fig.2. The circuit comprises of generating source, step up and step down transformers, three loads with one loaded connected through a circuit breaker and a voltage measurement block. With the appropriate opening and closure of circuit breaker we can observe a voltage sag through the measurement block
Fig.4 - Circuit for simulating voltage unbalance
IV.RESULTS AND DISCUSSIONS A. Voltage sag

Fig.2 - Circuit for simulating voltage sag
B. Voltage swell A voltage swell can be created with the circuit shown in fig 3 all the components employed in this circuit is similar to that of the previous case i.e., voltage sag.
The output shown here in the Fig 5 is obtained from the voltage sag circuit shown in the Fig 2 without USSC .The circuit breaker will be in a closed state from 0.1s to 0.2s which leads to the addition of a 3-phase load in the circuit along with the other loads.
Fig.5 - Voltage sag with out USSC Fig.3 - Circuit for simulating voltage swell
The main and only difference here is the initial status of the circuit breaker is closed state. C. Voltage unbalance With the circuit shown in Fig.4 a voltage imbalance condition is simulated. With the single phase loads added to the two phases of the supply a voltage unbalance between the three phases observed.
Due to this additional load we can observe a dip in the voltage for the duration of 0.1s to 0 .2s as shown in the Fig 5.The transients shown in the output is due to the switching surges (due to the sudden opening of circuit breaker switch) at .1s. B. Voltage swell The output shown here in the Fig 6 is obtained from the voltage swell circuit shown in the Fig 3 without USSC .The circuit breaker will be in open state from 0.1s to 0.2s which leads to the rejection of a 3phase load in the circuit.
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Fig .6 Voltage swell with out USSC
Fig. 8 - Voltage sag mitigation
Due to this we can observe a swell in the voltage for the duration of 0.1s to 0.2s as shown in the Fig.6. The transients shown in the output is due to the switching surges (due to the sudden closure of circuit breaker switch) at 0 .2 s. C. Voltage unbalance The output shown in the Fig 7 is obtained from the circuit for voltage unbalance. Here in addition to the 3-phase load in the demand side, two single phase loads are added.
Fig.9 - Voltageswell mitigation
Fig.7 Voltage unbalance with out USSC
Fig.10 - Voltage unbalance mitigation
In the circuit shown in Fig 4 the two single phase loads are added in the phases A & C. The phase B is left free. Thus a voltage dip is observed without USSC in the two phases A & C irrespective of the phase B. V.IMPLEMENTATION OF USSC After implementing the USSC between the distribution source and the load side we can effectively mitigate the power quality problems. In the output wave form shown in Fig 8,9and 10 we can observe the reduction in the extent of voltage dip or swell in the output after implementing the USSC.
TABLE I With out USSC case

CASES Phase A (in volts) Phase B (in volts) Phase C (in volts)
Voltage sag Voltage swell Voltage unbalance
419.5
422
421
455
452
453
440
380
370
368
TABLE II With USSC case

CASES Voltage sag Voltage swell Voltage unbalance Phase A 435 Phase B 430 Phase C 432
443
439
440
440
415
428
CONCLUSION In this work , a unified approach to the mitigation of multiple power quality problems has been investigated by using USSC, which comes under custom power devices used to improve the power quality in the distribution systems. The USSC incorporating 12-pulse series and shunt connected inverters has been modeled in MATLAB/SIMULINK Software package. Simulations have been carried out to evaluate the performance of the USSC under various operating conditions and power-quality disturbances. The results obtained from the simulation shows the reduction in the extent of voltage sag, voltage swell, and voltage unbalance when compared to the circuit without USSC. REFERNCES [1] J. R. Enslin, Unified approach to power quality mitigation, in Proc.IEEE Int. Symp. Industrial Electronics (ISIE 98), vol. 1, 1998, pp. 820. [2] B. Singh, K. Al-Haddad, and A. Chandra, A review of active filters for power quality improvement, IEEE Trans. Ind. Electron., vol. 46, no. 5,pp. 960971, 1999. [3] M.-C. Wong, Y.-D. Han, and L.-B. Zhao, Study of distribution system unified conditioner (DS-UniCon), in Proc. 3rd Int. Power Electronics and Motion Control Conf. (PIEMC), vol. 3, 2000, pp. 13651370. [4] A. L. Olimpo and E. Acha, Modeling and analysis of custom power systems by PSCAD/EMTDC, IEEE Trans. Power Delivery, vol. 17, no.1, pp. 266272, Jan. 2002. [5] P. Pohjanheimo and E. Lakervi, Steady state modeling of custom power components in power distribution networks, in Proc. IEEE Power Engineering Society Winter Meeting, vol. 4, Jan. 2000, pp. 29492954. [6] N. G. Hingorani and L. Gyugyi, Understanding FACTS Concept and Technology of Flexible AC Transmission System. New York: IEEE Press, 2000.
[7] R. L. V. Arnez and L. C. Zanetta, Unified power flow controller (UPFC): its versatility in handling power flow and interaction with the network, in Proc. IEEE/PES Asia Pacific Transmission and Distribution Conf. and Exhib., vol. 2, Oct. 2002, pp. 13381343. [8] D. E. Soto-Sanchez and T. C. Green, Voltage balance and control in a multi-level unified power flow controller, IEEE Trans. Power Delivery, vol. 16, no. 4, pp. 732738, Oct. 2001. [9] C. Schauder, The unified power flow controller-a concept becomes reality, In IEE Colloq. Flexible AC Transmission SystemsThe FACTS,1998, pp. 7/17/6. [10] A. D. Le Roux and H. T. Mouton, A series-shunt compensator with combined UPS operation, in Proc. IEEE Int. Symp. Industrial Electronics, vol. 3, 2001, pp. 20382043. [11] C. Su and G. Joos, Series and shunt active power conditioners for compensating distribution system faults, in Canadian Conf. Electrical and Computer Engineering, vol. 2, Mar. 2000, pp. 11821186.
BIOGRAPHY
Rajesh.T was born in Tamilnadu, India,on July, 1978. He received the B.E degree in Electrical and Electronics Engineering from Dr.Sivanthi Aditanar College of Engineering,Tiruchendur in the year 1999. He received his M.E Power Syatems Engineering from Thiagarajar College of Engineering, Madurai in the year 2001. He has 9 yrs of teaching experience. He worked as Asst. Professor in EEE department, Bannari Amman Institute of Technology, Sathyamangalam, TamilNadu, India for 8 years. Currently he isworking as a Assistant professor in the Department of Electrical and Electronics Engineering, INFO Institute of Engineering, Kovilpalayam, Coimbatore, TamilNadu, India. Currently he is doing research in the field of Reactive power compensation and Harmonic Mitigation.
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A New Mechanism of Track Design for an all Terrain Mobile Robot and its Applications
R.ELAMURUGU ALIAS GOKUL#1 , M.Dhivya#2
#
Department of electrical and electronics engineering, Anna University of technology, Coimbatore, India.
1
rgokul88@yahoo.com
2
dhivya@gmail.com
Abstract Mobile robots are widely used in various in industrial applications. In rescue field the vehicles must often operate in an unstructured environment like under damaged building blocks during earthquake disaster. So those to detect the presence of live bodies in the unstructured rescue field environment and to avoid vibration; the arm is fixed in desired position between vehicle and ground surface. The main objective of this work is to design triangular shaped tracking wheel and concentrated on the arm position to avoid vibration. To design triangular shaped tracking wheel a new inventive concept of mechanism is presented in this paper. The mechanism is designed in a triangular shaped tracking wheel in which the inner construction can be manipulated depending on that particular terrain, thus this type of wheel is likely to move through all terrain.. Due to unstructured environment the vibration will be arises in the armed vehicle robot arm, so that it will be disturbed those vehicles to detect the presence of live bodies in rescue field. To avoid a vibration a Differential Evolution algorithm will be implemented in the armed vehicle system to maintain the constant position of the manipulator arm and for control the arm DC motor. KeywordsMobile Evolution Robot, Differential
Robot technology is an applied science that is referred to as a combination of machine tools and computer applications. It includes such diverse fields as machine design, control theory, microelectronics, computer programming, artificial intelligence, human factors, and production theory. Robot is the main component of a flexible production system (FPS). Other components of this system are machine tools, transport machines, control devices, and different auxiliary elements. A flexible production system is an automatically operating production system that can be easily reprogrammed and adapted to manufacture different products. Robot centered modules of FPS, called robot modules or robot systems are intended for specified technological operations like welding, surface coating, packaging, etc. The robot module includes one or more robots (with manipulators and control devices), pallets for details or products, auxiliary positioning, transport devices, etc. Therefore, robot control means control of a complete robot module and a certain part of the production process. A robot is a programmable, multifunctional manipulator designed to move material, parts or specialized devices through variable programmed motions for the performance of a variety of tasks. (RIA). Robots are physical agents that perform tasks by manipulating the physical world. They are equipped with sensors to perceive their environment and effectors to assert physical forces on it. A robot is the embodiment of manipulative, locomotive, perceptive, communicative and cognitive abilities in an artificial body, which may or may not have a human shape. It can advantageously be deployed as a tool, to perform different tasks in various environments.
I. INTRODUCTION The field of robotics has its origins in science fiction. The term robot was derived from English translation of a fantasy play written in Czechoslovakia around 1920. Todays, robots are highly automated mechanical manipulator controlled by computers. Robotics is the engineering science and technology of robots, and their design, manufacture, application, and structural disposition.
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II. PROPOSED ADAPTIVE GEOMETRY MOBILE ROBOT The main objectives of the proposed design are: To design a drive system that can adapt its own geometry in order to move through various environments such as rough platform, limited height passage or even climb up and down the stair. The maximum target velocity of robot is 5 m/s and the angular motion of each angle can vary from 95 to 150. To construct a basic platform that can be used to build a typical rescue mobile robot in future.
The serial communication RS-485 system is utilized to communicate between the computer and each microcontroller and the timing of serial communication for transferring data is 104s/byte.
In this paper we have proposed a triangular shaped caterpillar wheel as a triangular base of a robot. Each internal angles of the triangle wheel or adjusted by changing the rotation and linear displacement of the appropriate ball screws. This concept allows the robot to move along the level, rugged ground and climb up and down a stair as well. The communication software is developed for user to control robot in various situations.
Fig .2. Block diagram of Robot mechanism
An optical sensor is installed to prevent the damage and to limit movements of hardware for safety. In the implementation part, the angle of each link is adjusted between 95 and 150. The ball screws are used to regulate the linear displacement from 0 mm. to 100 mm to make the tracking wheel tight when the mobile robot moves through high tilt. The tracking wheel is able to move along the rugged terrain, climb up/down stair in which each step is 1525 cm. (height width) and its maximum slope is approximately 30.
For the control hardware a concept of distributed control has been utilized. 12 Atmel AT89C20510s are connected together to form a typical RS-485 serial network. this network is then connected to a RS-485<->RS232 converter to allow the above serial network to connect to a notebook which acts as console system for the triangular based robot. Fig.4 shows a typical control structure of the proposed robot.
Fig.3. Flowchart for move command
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III. ROBOT CONFIGURATION Industrial robots are available in a wide range of shapes, sizes, speeds, load capacities, and other capabilities. In this paper jointed arm robot is implemented to detect those live bodies under damaged building blocks in rescue field. JOINTED ARM CONFIGURATION: A robotic arm is a robot manipulator, usually programmable, with similar functions to a human arm. The links of such a manipulator are connected by joints allowing either rotational motion or translational (linear) displacement. The links of the manipulator can be considered to form a kinematic chain. The business end of the kinematic chain of the manipulator is called the end effector and it is analogous to the human hand. The end effector can be designed to perform any desired task such as welding, gripping, spinning etc., depending on the application. For example robot arms in automotive assembly lines perform a variety of tasks such as welding and parts rotation and placement during assembly.
It is natural to begin this discussion by considering the various possible types of motion in themselves, leaving out of account for a time the causes to which the initiation of motion may be described; Types of kinematics: i) Forward kinematics ii) Inverse kinematics DIRECT KINEMATICS: Forward or configuration kinematic equations for rigid robots. The forward kinematics problem is concerned with the relationship between the individual joints of the robot manipulator and the position and orientation of the tool or end-effector. Stated more formally, the forward kinematics problem is to determine the position and orientation of the end-effector, given the values for the joint variables of the robot. The joint variables are the angles between the links in the case of revolute or rotational joints, and the link extension in the case of prismatic or sliding joints. The forward kinematics problem is to be contrasted with the inverse kinematics problem, which will be studied in the next chapter, and which is concerned with determining values for the joint variables that achieve a desired position and orientation for the end-effector of the robot. INVERSE KINEMATICS: The inverse kinematic transformation converts end effectors position and orientation into joint angles and rates. The inverse dynamics transformation derives the joint torques corresponding to desired instantaneous joint positions, velocities and accelerations. Inverse kinematics is a mathematical method to find the degrees of freedom of a system subject to kinematic constraints. = f-1 (p)
Fig 4. Joint arm robot configuration
IV. ROBOT KINEMATICS: Kinematics is the branch of classical mechanics that describes the motion of objects without consideration of the causes leading to the motion or Kinematics is the study of the motion of rigid bodies without consideration of Newtonian laws. There are two distinct methods for solving the above equation. One to analytically solve the equation and the other is to solve it iteratively, which means that a simplified version of the equation are calculated and evaluated repeatedly over time. Analytical solutions are precise but the complexity of it arises when large chains of joints are tried to solve.
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Using the iteration method good approximations are computed with the use of the jacobian matrix. This paper is about inverse kinematics (IK). V. DIFFERENTIAL EVOLUTION: In simple terms, optimization is the attempt to maximize a systems desirable properties while simultaneously minimizing its undesirable characteristics. What these properties are and how effectively they can be improved depends on the problem at hand. Tuning a radio, for example, is an attempt to minimize the distortion in a radio stations signal. Mathematically, the property to be minimized, distortion, can be defined as a function of the tuning knob angle, F(x) = noise power/ single power Because their most extreme value represents the optimization goal, functions like are called objective functions. When its minimum is sought, the objective function is often referred to as a cost function. In the special case where the minimum being sought is zero, the objective function is sometimes known as an error function. By contrast, functions that describe properties to be maximized are commonly referred to as fitness functions. Since changing the sign of an objective function transforms its maxima into minima, there is no generality lost by restricting the following discussion to function minimization only. Tuning a radio involves a single variable, but properties of more complex Systems typically depend on more than one variable. In general, the objective function, f(x) = f(x0, x1, xD 1), has D parameters that influence the property being optimized. There is no unique way to classify objective functions, but some of the objective function attributes that affect an optimizers Performances are: Parameter quantization Are the objective functions variables continuous, discrete, or do they belong to a finite set additionally, are all variables of the same type Parameter dependence Can the objective functions parameters be optimized independently (separable function), or does the minimum of one or more parameters depend on the value of one or more other parameters (parameter dependent function) Dimensionality How many variables define the objective function
Modality. Does the objective function have just one local minimum (uni-modal) or more than one (multi-modal) Time dependency. Is the location of optimum stationary (e.g., static), or non-stationary (dynamic) Noise. Does evaluating the same vector give the same result every time (no noise), or does it fluctuate (noisy) Constraints. Is the function unconstrained, or is it subject to additional equality and/or inequality constraints Differentiability. Is the objective function differentiable at all points of Interest
DE or differential evolution belongs to the class of evolutionary algorithms that include evolution strategies (ES) and conventional genetic algorithms (GA). DE differs from the conventional genetic algorithms in its use of perturbing vectors, which are the difference between two randomly chosen vectors. DE is a scheme by which it generates the trial vectors from a set of initial populations. In each step, DE mutates vectors by adding weighted random vector differentials to them. If the fitness of the trial vector is better than that of the target vector, the trial vector replaces the target vector in the next generation. DE offers several strategies for optimization. They are classified according to the following notation such as DE/x/y/z, where x refers to the method used for generating parent vector that will form the base formulated vector, y indicates the number of difference vector used in mutation process and z is the crossover scheme used in the crossover operation to create the offspring population. The symbol x can be rand (randomly chosen vector) or best (the best vector found so far). The symbol y, i.e. the number of difference vector, is normally set to be 1 or 2. For crossover operation, a binomial (notation: bin) or exponential (notation: exp) operation is used. VI. LIVE BODY SENSOR: This paper also discloses a method for detecting presence of a live body. Initially the sensor transmits the infrared signal and receives back the same signals from the nearby live body of same wavelength, its converted into a required output. Hence it ensures the presence of live human body around its sensing range. Sensor has two sensing elements. The passive infrared radiation emitted from the live body will be received by the sensor elements. If there are varieties between the outputs of these elements due to
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the moment of the live body, output will be amplified by differential amplifier. The variable signal is further amplified by ac amplifier. This signal is set to a fixed level comparator and the output of the comparator is used to trigger a time delay module to obtain fastener output of the human body moment to drive a relay or switching input.
Fig 5.1 parameter 1 evaluation value
Table 1 Specifications of a live body sensor
VII. RESULTS AND ANALYSIS: In my project, a multipurpose manipulator control differential evolution algorithm is presented to solve the benchmark problems designed for the special session on real-parameter constrained optimization problems. The notion of the manipulator arm angle is employed to penalize the infeasible solutions. To the best of my knowledge, this is the first reported application of robotics is applied to the constrained optimization problems.
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Best parameter set returned by function differential evolution: parameter1: 0.8727 parameter2: 1.658 parameter3: 0.6109 Angle value: Delta 1: 50.0020 Delta 2: 95.0021 Delta 3: 35.0020
Mechatronics Monterey, California, USA, 24-28 July, 2005. [6] Thomas Wisspeintner, Abheek Bose, Paul G. Ploger. Robot Prototyping for Rough Terrain Applications and High Mobility with VolksBot RT. [7] Eric Colon, HichemSahli, YvanBaudoin. Distributed control of mobile robots with CORBA. [8] Yi Guo, Lynne E. Parker, David Jung and Zhaoyang Dong, Performance-Based Rough Terrain Navigation for Non holonomic Mobile Robots. [9] JorgConradt, Paulina Varshavskaya. Distributed Central Pattern Generator Control for a Serpentine Robot. [10] Bruch M.H., Laird R.T., Everett H.R., Challenges for deploying man-portable robots into hostile Environments.
VIII. CONCLUSION: The vibrations arises in the armed vehicle robot arm, due to unstructured disturbs the vehicle to detect those live bodies during earthquake disaster. To avoid the vibrations a Differential evolution algorithm technique is implemented in the armed vehicle system to maintain the constant position of the manipulator arm and for controlling the arm of the DC motor. The angle can be determined by using inverse kinematics technique. DE (Differential Evolution) is used to determine the angle the determined angle is fed to the DC motor. IX. REFERENCES: [1] WanayuthSanngeon, Nitin Afzulpurkar.(2009) Adaptive Geometry Track Design and Implementation for an all Terrain Mobile Robot [2] ChoomuangR. ,Afzulpurkar N.(2005) Hybrid Kalman Filter/FuzzyLogic based Position Control of Autonomous Mobile Robot. International Journal of advanced Robotic Systems, 2(3), pp 197-208. [3] Thomas Wisspeintner, Abheek Bose, Paul G. Ploger. Robot Prototyping for Rough terrain Applications and High Mobility with VolksBot RT [4] Ray Jarvis. An Articulated Six Wheel Drive Robot for Very Rough Terrain Navigation.Proc 2002 Australasian Conference on Robotics and Automation Auckland. [5] Alexander S. Boxerbaum , Philip Werk, Roger D. Quinn, Ravi Vaidyanathan. Design of an Autonomous Amphibious Robot for Surf Zone Operation: Part I Mechanical Design for Multi-Mode Mobility Proceedings of the 2005 IEEE/ASME International Conference on Advanced Intelligent
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Air Pollution Monitoring System Using Zigbee

D.Kalanithi
II M.E - Embedded System Technologies Anna University of Technology Coimbatore Coimbatore, Tamilnadu kalanithi4@gmail.com
Mr.K.N.Vijeyakumar M.E.,
Lecturer, Department of ECE Anna University of Technology Coimbatore Coimbatore, Tamilnadu
Abstract Environmental Air pollution monitoring
system (EAPMS) is used for monitoring the concentrations of major air pollutant gases. This system measures concentration of gases and temperature level using semiconductor sensors. The proposed system consists of a Mobile Data-Acquisition Unit (Mobile-DAQ) and a fixed Internet-Enabled Pollution Monitoring Server (Pollution-Server). The Mobile-DAQ unit integrates a single-chip microcontroller, air pollution sensors array, a Zigbee GPRS-Modem, and a Global Positioning System Module (GPS Module). The Pollution-Server is a highend personal computer application server with Internet connectivity. The Mobile-DAQ unit gathers air pollutants levels (CO, NO2, and SO2), and packs them in a frame with the GPS physical location, time, and date. The frame is subsequently uploaded to the Zigbee-Modem and transmitted to the PollutionServer via the public mobile network. A database server is attached to the Pollution Server for storing the pollutants level for further usage by various clients such as environment protection agencies, vehicles registration authorities, and tourist and insurance companies. The Pollution-Server is interfaced to Google Maps to display real-time pollutants levels and locations in large metropolitan areas. The system was successfully tested in the city of Sharjah, UAE. The system reports real-time pollutants level and their location on a 24-h/7-day basis.
Keywords-Air pollution, general positioning systems (GPSs), Microcontroller embedded systems, wireless mobile networks.
In addition to industries, automobiles, agricultural activities, and even ordinary homes contribute towards the environmental pollution. It is well known that some of these chemical pollutants have increased Environmental pollution has several aspects. The most serious aspect of environmental pollution is the air pollution, while two other aspects are water and soil pollution. Most of the above air pollution and quality monitoring systems are based on sensors that report the pollutants levels to a server via wired modem, router, or short-range wireless access points. In this paper, we propose a system that integrates a single-chip microcontroller and several air pollution sensors (CO, NO2, and SO2). The integrated unit is a sensor, Analog to digital converter and a Microcontroller. This unit can be placed on the top of any moving device such as a public transportation vehicle. While the vehicle is on the move, the microcontroller generates a frame consisting of the acquired air pollutant level from the sensors array and the physical location that is reported to the PC. A database server is attached to the PollutionServer for storing the pollutants level for further usage by interested clients such as environment production agencies and vehicles regeneration authorities. II RELATED WORK An Environmental Air Pollution Monitoring System (EAPMS) for monitoring the concentrations of major air pollutant gases complying with the IEEE 1451.2 standard. This system measures concentrations of gases such as CO, NO2, SO2, and O3 using semiconductor sensors. The smart transducer interface module (STIM) is implemented using the analog devices ADuC812 microconverter. Network Capable Application Processor (NCAP) was developed using a personal computer and connected to the STIM via the transducer independent interface. Three gas sensors were calibrated using the standard calibration methods [1]. Gas concentration levels and information regarding the STIM can be seen on the graphical user interface of the NCAP. Further, the EAPMS is capable of warning when the pollutant levels exceed predetermined maxima. An integrated volatile organic toxicants sensor with a Bluetooth device interface. The device is based on
I INTRODUCTION Over the past quarter century, there has been an exponential increase of industries, and these industries have caused complex and serious problems to the environment. The first and the foremost is the severe environmental pollution which has caused deterioration of atmosphere, climate change, stratospheric ozone depletion, loss of biodiversity, changes in hydrological systems and the supplies of fresh water, land degradation and stresses on systems of food producing, acid rain, and global warming.
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232 serial communicationports, 4 Control Area Networks ports, and SPI communicationports [9]. These resources are more than enough for theproposed application. B. Sensors Array The sensor array consists of three air pollutions sensors including Carbon Monoxide (CO), Nitrogen(N2), Dioxide (NO2), andSulfur Dioxide (SO2) [10].As Table I shows, the resolution of these sensors is sufficientfor pollution monitoring.
novel tuning fork sensor platform along with a wireless communication/ interface technology taken in an integrated system approach [2]. It features high sensitivity and selectivity. The sensitivity and selectivity are accomplished through the use of novel tuning fork sensor modified by design polymers and selective filtering. Experiments have shown that the device can detect toxic volatile organic compounds (VOCs) under high concentrations of common interferents from flavours and fragrances. Environment Observation and Forecasting System (EOFS) is an application for monitoring and providing a forecasting about environmental phenomena. We design an air pollution monitoring system which involves a context model and a flexible data acquisition policy. The context model is used for understanding the status of air pollution on the remote place [3]. It can provide an alarm and safety guideline depending on the condition of the context model. It also supports the flexible sampling interval change for effective the tradeoff between sampling rates and battery lifetimes. This interval is changed depending on the pollution conditions derived from the context model. It can save the limited batteries of geo-sensors. This paper proposes a remote monitoring system for the greenhouse environment. The system can be set in the monitoring spot. Real time data which gathered and simply disposed can be transmitted to the remote server by wireless module-GPRS &. CDMA IX. The dynamic WEB publishing can be 7 realized by the ASP.NET technique in the remote server. Embedded operation system-GC/OS-II has been ported in the system's microchip. GC/OS-II can manage collecting, displaying and saving data and so on. This method can significantly improve the system's Real-time, reliability and expansibility [5]. The remote monitoring system can realize the real time publishing and the historical data request. III. HARDWARE ARCHITECTURE To satisfy the systems functional and nonfunctional requirements,two major building blocks are needed, namely: a MobileData-Acquisition Unit (MobileDAQ) and a fixed Internet-EnabledPollution monitoring Server (Pollution-Server).The Mobile-DAQ unit is designed by integrating the followinghardware modules shown in Fig. 1. As the figureshows, the Mobile-DAQ consists of a 16-bit single-chip microcontrollerintegrated with a sensor array using analog ports.The Mobile-DAQ is also connected to a GPS module anda Zigbee-Modem using the RS-232 interface. Each of thesecomponents is described in the following. A. 16-Bit Single-Chip Microcontroller The microcontroller is a single-chip device that has richbuilt-in resources for digital input/output ports, 16 channels,8/10 bits analog-to-digital converter, 8 input/output interrupt-driven timers, 12 Kbytes of RAM, 4 Kbytes of EEPROM,256 Kbytes of FEEPROM, two RS-
Fig.1.System hardware basic building blocks.
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The system software architecture is divided into two layers structure: physical layer and application layer. A. Physical Layer This layer is responsible for acquiring the realtime data from the sensors-array and the physical location, time and date of the sampled pollutants from the GPS module. This information is then encapsulated into a data frame by the microcontroller. The microcontroller then sends each frame to the Zigbee-Modem through the RS232 interface. The Zigbee-Modem, in turn, sends each data frame to the Pollution-Server using the publicly available mobile network and the Internet.
Each of the above sensors has a linear current output in the range of 4 mA20 mA. The 4 mA output corresponds to zero-level gas and the 20 mA corresponds to the maximum gas level. compatible with the voltage range of the built-in analog-to-digitalconverter in the 16bit single chip microcontroller described earlier. C. GPS Module The GPS module provides the physical coordinate location of the mobile-DAQ, time and date in National Marine Electronics Association (NMEA) format [11]. NEMA format includes the complete position, velocity, and time computed by a GPS receiver where the position is given in latitude and longitude [12].The data packet from the GPS-Module includes an RMS Header followed by UTC time, data validity checksum, latitude, longitude,velocity , heading, date, magnetic variation and direction,mode , and checksum. The only information required for the proposed system is date, time, latitude and longitude. The GPS modem is interfaced with the microcontroller using the RS-232communication standard. D. Zigbee-Modem The proposed system uses a Zigbee-Modem as a communication device to transmit time, date, physical location and level of air pollutants. The modem used for the proposed system has an embedded communication protocol that supportsMachine-to-Machine (M2M) intelligent wireless Transmission Control Protocol (TCP/IP) features such as Simple Mail Transfer (SMTP) E-mail, File Transfer Protocol (FTP), and Simple Messaging Service (SMS) services Protocol. The modem supports an RS-232 interface that allows Serial TCP/IP socket tunneling. The modem also has rugged aluminum enclosure making it suitable for the proposed system [12]. E. Pollution-Server The Pollution-Server is an off-the-shelf standard personalcomputer with accessibility to the Internet. As Fig. 1 shows ,the Pollution-Server connects to the GPRSModem via TCP/IP through the Internet and the public mobile network. The server requires a private IP address for the Zigbee-Modem and communicates over a preconfigured port. The Pollution-Server connects to a database management system (MySQL) through a local area network (LAN). The Pollution-Server runs aWampServer [13] stack that provides the Apache Web Server in addition to the PHP Server-side scripting language. Clients such as the municipality, environmental protection agencies, travel agencies, insurance companies and tourist companies can connect to the Pollution-Server through the Internet and check the real-time air pollutants level using a normal browser on a standard PC or a mobile device. The Pollution- Server can be physically located at the Environmental Protection Agency (EPA) or similar government agencies. IV. SOFTWARE ARCHITECTURE
Fig. 2Data-frame payload.
Fig. 3.Mobile-DAQ software algorithm.
The physical layer is implemented using ANSI C language which is compiled to native microcontroller code. The software implementing the physical layer is composed of five functions, namely: ports-read() function, function, sensor-acquisition() function, GPS position() function, and data-frame() function. Are called from a main program that is stored on and executed by the Mobile-DAQ microcontroller. Ports-config() function: Developed to configure the digital inputs/outputs in addition to the resolution of the analog-to-digital converters that read the air pollutants level from sensor array outputs. Sensor-acquisition() function: Reads each pollutant level as a voltage from the signal conditioning circuit output via the built-in analog-to-digital converter module of the microcontroller.
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0.15, and 0.13 ppm, respectively. Following [14], the air quality is divided into four categories. An index value of 0100 corresponds to clean air, 101125 represent light pollution, 126150 signify significant pollution, and above 150 means heavy pollution. In summary, the AirPollution-Index function returns a pollution category from the raw pollutant data. Google-Mapper: PHP program running on the Apache web-server that reads the pollutant data from the mySQL database and plots it on a Google Map using the Google Maps API. In specific, an instance of a GMap object from is created using a JavaScript call.AGPolygon object based on latitude, longitude and the level of the pollutant is created for each region in the Map being shown. The color of the polygon follows the pollution category as calculated by the AirPollution-Index function. For example, for the UAE, a red color is used to denote Heavy Pollution indicating an AQI value of above 150, as shown in the Table II. This program allows a user to click on a particular polygon representing an area on the map. Upon clicking, the program shows an information window showing the pollution
GPS-read() function: Communicates with the GPS module through RS-232 and extracts latitude and longitude of the sampled air pollutant along with time and the date. Data-frame() function: Encapsulates the IP address of the Pollution Server, a port number, the three pollutants levels, latitude and longitude of the sampled location, and time and date of the when the samples were taken. The data frame is shown in Fig. 2. GPRS-transmit() function: Selectively sends the data frame to the GPRS-Modem using the RS-232 interface port. This frame is sent according to the algorithm shown in Fig. 3. As the figure shows, a data frame is only transmitted if the pollutants level has changed since the last reading.
TABLE II AIR QUALITY DESCRIPTION (MODIFIED FROM [14, TABLEIII])
Fig. 4 Example frame containing pollution and location data.
B. Application Layer The application layer consists of three primary modules: Socket-Server, Air-Pollution-Index, and GoogleMapper. Socket-Server collects and stores pollutant data from all the Mobile-DAQs. AirPollution-Index calculates pollution categories based on local pollution policies and regulations. Finally, Google-Mapper, makes this pollution information available over the Internet. Each module is described in the following. Socket-Server: Multithreaded Java program that uses Berkeley sockets to listen to a pre-configured port (e.g., ) for socket connections from the various remote MobileDAQs. Upon connecting with a Mobile-DAQ, the SocketServer spawns a software thread that parses the data frame containing pollutant data along with the sampling time and location, stores the data frame in a database using the mySQL database management system and closes the connection. Air-Pollution-Index: Function to convert the raw pollutant level received from each Mobile-DAQ to pollution standards called air quality index (AQI) using the formula [14]before the processor clock rises. The reason for this short forward shift of the integration interval is that most of the energy in synchronous circuits is consumed during signal transitions at the beginning of each clock cycle. AQI=(pollution level/pollution standard)*100 -- [1] The pollution standard is defined according the air quality standards of a particular region. For example, in the UAE,the pollutant standard for CO, NO2, and SO2 are 20,
Fig. 5 Public interface showing actual pollutant values.
V. IMPLEMENTATION AND TESTING The Environment Protection and Safety Section (EPSS) inDubai has monitored air quality since 1988 [14]. Their current system is based on six static monitoring stations located around the Dubai metropolitan area. These stations send air pollutant data to a central server using fixed line modem connections. The pollution data is also available to the public through their Web site. This system has worked well. However, the data collected is limited to the vicinity of the six monitoring stations. Consequently, a mobile system based on the hardware and softwarearchitecture described earlier was built and tested in the UAE. The designed sensor array consisting of CO, NO2, and SO2 was interfaced through a signal
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REFERENCES
[1] N. Kularatna and B. H. Sudantha, An environmental air pollution monitoring system based on the IEEE 1451 standard for low cost requirements, IEEE Sensors J., vol. 8, pp. 415422, Apr. 2008. [2] F. Tsow, E Forzani, A. Rai, R. Wang, R. Tsui, S. Mastroianni, C. Knobbe, A. J. Gandolfi, and N. J. Tao, A wearable and wireless sensor system for real-time monitoring of toxic environmental volatile organic compounds, IEEE Sensors J., vol. 9, pp. 17341740, Dec. 2009. [3] Y. J. Jung, Y. K. Lee, D. G. Lee, K. H. Ryu, and S. Nittel, Air pollution monitoring system based on geosensor network, in Proc. IEEE Int.Geoscience Remote Sensing Symp., 2008, vol. 3, pp. 1370 1373. [4] C. J. Wong, M. Z. MatJafri, K. Abdullah, H. S. Lim, and K. L. Low, Temporal air quality monitoring using surveillance camera, in Proc. IEEE Int. Geoscience and Remote Sensing Symp., 2007, pp. 28642868. [5] M. Gao, F. Zhang, and J. Tian, Environmental monitoring system with wireless mesh network based on embedded system, in Proc. 5th IEEEInt. Symp. Embedded Computing, 2008, pp. 174179. [6] W. Chung and C. H. Yang, Remote monitoring system with wireless sensors module for room environment, Sens. Actuators B, vol. 113, no. 1, pp. 3542, 2009. [7] J. W. Kwon, Y. M. Park, S. J. Koo, and H. Kim, Design of air pollution monitoring system using ZigBee networks for ubiquitous-city, inProc. Int. Conf. Convergence Information Technology, 2007, pp. 10241031. [8] M. AbuJayyab, S. Al Ahdab, M. Taji, Z. Al Hamdani, and F. Aloul, Pollumap: A pollution mapper for cities, in Proc. IEEE Innovations in Information Technology Conf., Dubai, UAE, Nov. 2006, pp. 15. [9] H. W. Huang, The HCS12/9S12: An Introduction to Hardware and Software Interfacing, 1st ed. Florence, KY: Thomson Delmar Learning, 2006. [10] Alpha Sense Gas Sensor Datasheets and Speculations. [Online]. Available: http://www.alphasense.com/alphasense_sensors/ sulfur_dioxide_sensors.html [11] National Marine Electronics Association Data. [Online]. Available: http://www.gpsinformation.org/dale/nmea.htm [12] GPRS-Modem Technology. [Online]. Available: http://www. comtechm2m.com/gprs-modem/gsm-gprs-modem.htm [13] WampServer. [Online]. Available: http://www.wampserver.com
conditioning circuit through analogue channels 5, 6, and 7 of the HCS12 microcontroller, as shown in Fig. 1. The sensor output voltages representing the level of gas for each pollutant (Vg ) were converted to a ppm value for each gas. The GPS module was connected to COM0 and the GPRS-Modem was connected to COM1 of the microcontroller. Fig. 4 shows a typical data frame being transmitted from GPRS-Modem to the Pollution-Server.
Fig. 6 Details of pollutant data shown in Fig. 5.
on top front of the bus to avoid contamination from the bus exhaust. The pollutant data was collected for 12 h. Fig. 6 shows how a user can use the Internet to access pollutant levels in a location covered by the bus. As the figure shows, Google Maps is used as the primary interface. Pollutant data is shown using different colored polygons that are superimposed on the map. Thecolor code used for these polygons was consistent with the AQI index of the Dubai Municipality. As the figure shows, different areas within the American University of Sharjah campus have different levels of pollutants. The yellow polygon shows light pollution while the green polygons show clean air according to the AQI index. As Fig. 6 shows, a user can click any of the polygons to retrieve details of the various pollutant levels. A user can further drill down by clicking to view the past data for any of the gases for this location. For example, Fig. 7 shows the history of CO pollutant for the last seven readings over an 8 h period for a given day.
VI CONCLUSION A wireless distributed mobile air pollution monitoring system was designed, implemented and tested using the GPRS public network. The system utilizes city buses to collect pollutant gases such as CO, NO2, and SO2. The pollution data from various mobile sensor arrays is transmitted to a central several that make this data available on the Internet through a Google Maps interface. The data shows the pollutant levels and their conformance to local air quality standards. It is worth mentioning that much more work is required to commercialize the system.
[14] Air Quality Index, UAE, Dubai Municipality. [Online]. Available: https://portal.dm.gov.ae/AirQuality/Airqualityindex.htm
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AN EFFICIENT THROUGHPUT ALGORITHM FOR MULTICHANNEL WIRELESS MESH NETWORKS

K.Mohanapriya1.V.G.Pratheep2 1.PG scholar in embedded system technologies 2. Assist. Professor in Electrical and Electronics Engineering
Velalar College of Engineering and Technology, Erode
ABSTRACT: Wireless mesh networks (WMNs) have emerged as a key technology for next-generation wireless networking. Furthermore, multicast communication is a key technology for wireless mesh networks. This paper proposes two algorithms: the Level Channel Assignment (LCA) algorithm and the Multichannel Multicast (MCM) to improve the throughput for multichannel and multi-interface mesh networks. The algorithms build efficient multicast trees by minimizing the number of relay nodes and total hop count distances of the trees. The algorithms use dedicated channel assignment strategies to reduce the interference to improve the network capacity. We also demonstrate that using partially overlapping channels can further diminish the interference. Furthermore, additional interfaces help to increase the bandwidth, and multiple gateways can further shorten the total hop count distance. We also observe that MCM achieves better throughput and shorter delay while LCA can be realized in distributed manner. IndextermsMesh,, Multicast, Channel assignment. 1. INDRODUCTION: Wireless Mesh Networks (WMN) has recently gained considerable popularity owing to their self-configuring, selfoptimizing and self-healing capabilities. These networks offer an attractive platform for a wide range of applications, such as public safety and emergency response communications, intelligent transportation systems, and community networks. A WMN consists of two types of wireless nodes: Mesh Routers and Mesh Clients. The Mesh Routers have improved computational, communication and power resources as compared to Mesh Clients. Mesh Routers are generally static and form the multi-hop backhaul network with optional access to other auxiliary networks. In addition, Mesh Routers are also typically equipped with multiple wireless network interfaces and are therefore able to establish high capacity connections. Mesh Clients are mobile devices, which take advantage of the existing communication infrastructure provided by the Mesh Routers. Multicast protocols in WMNs cannot be achieved by adopting or slightly modifying the multicast protocols for other
types of multihop wireless networks. Unlike mobile ad hoc networks or wireless sensor networks, route recovery or energy efficiency is not the major concern for mesh networks due to the limited mobility and the rechargeable characteristic of mesh nodes. Moreover, supporting potential major applications, such as Video On Demand, poses a significant challenge for the limited bandwidth of WMNs. Thus, it is necessary to design an effective algorithm for mesh networks [1]. Traditional multicast protocols for wireless networks assume that each node is equipped with one interface. A mesh network provides the nodes with multiple interfaces that can be used to improve the throughput substantially. However, channel assignment is subject to the number of available channels and interfaces, the network topology, the communication requests, and other factors. Interference cannot be completely eliminated due to the limited number of available channels. An inappropriate channel assignment strategy will result in throughput reduction due to the multichannel hidden terminal problem [2], disconnection of the topology [3], or unfair bandwidth allocation to various users [4]. In this paper, we aim to design a multicast protocol for mesh networks that has the following characteristics: 1) it improves the system throughput by allowing simultaneous close-by transmissions with multichannels and multi-interfaces, and 2) it assigns all the available channels to the interfaces instead of just the nonoverlapping channels. 2. LEVEL CHANNEL ASSIGNMENT ALGORITHM A common method for multicast is to build a multicast tree, where the source node is usually the gateway. In this paper, we first propose the LCA algorithm, which can be achieved by the following steps. First, the nodes obtain their level information. The BFS is used to traverse the whole network. All the nodes are partitioned into different levels according to the hop count distances between the source and the nodes.Second, we build a multicast tree based on the node level information. Initially, the source and all the receivers are included in the tree. Then, for each multireceiver v, if one of its parents is a tree node, then connect it with that parent, and stop. Next, the tree nodes decide their channel assignment with the level information.
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Thus, we get the channel assignment in Fig. 3. Where the number above the node represents the channel for receiving and the number below the node represents the channel for sending.
1. The source node (level 0 ) only uses one interface, which is assigned channel 0. This interface is responsible for sending packets to the tree nodes in level 1. 2. The internal tree node in level i ( i 1) uses two interfaces: one is assigned channel i -1 , which is used to receive packets from the upper level; the other is assigned channel i, which is used to forward packets to tree nodes at level i + 1. 3. The leaf in the level i ( i 1) uses two interfaces: one uses channel i-1to receive the packets from level i-1, the other uses channel i to forward the packets to the mesh clients within its communication range that desire to receive the packets. One example is shown in Fig. 1, where node s is the source and e, f, g are the multireceivers. Initially, {s, e, f, g} are included in the multicast tree.
Fig 3: Channel Assignment The LCA algorithm has two advantages: simple implementation and throughput improvement. It only needs one BFS of the network at the beginning, and it creates the multicast tree by connecting the multireceivers with the nearest tree nodes. The tree nodes then can decide the channels by themselves according to the level information, which can be realized distributed. At the same time, the use of multiple channels reduces the close-by interference and allows more simultaneous transmissions. 3. MULTICHANNEL MULTICST ALGORITHM To further improve the system throughput, we propose an MCM algorithm to minimize the number of the relay nodes and the hop count distances between the source and the destinations, and further reduce the interference by exploiting all the partially overlapping channels instead of just the orthogonal channels. 3.1 Multicast Structure Construction 3.1.1 Broadcast Structure When all the nodes are multireceivers, the multicast problem becomes the broadcast problem. We can say that broadcast is a special case of multicast. In order to focus on the basic idea of MCM, we first consider the situation that all the nodes are the multireceivers. . The broadcast structure in the mesh network is built by the following steps. The first step is realized by BFS, which is similar with the LCA algorithm. After the BFS traversal, all the nodes are divided into different levels. We then delete the edges between any two nodes of the same level, with which we get the elementary communication structuretree mesh.
Fig 1: Network Topology At first, since none of gs parents are tree nodes, randomly select one parent d as a tree node and connect g with d.We then choose ds parent b as a tree node and connect d with b. Since bs parent s is a tree node, we connect b with s and stop the process for including g in the multicast tree. Next, we start from the second multireceiver e. Connect e with its parent b and stop, since b is already a tree node. Similarly for the third multireceiver f, we connect f with c; c with a, and then a with s. Now the tree construction is complete since all the receivers are connected to the tree.
Fig 2: Multicast tree The constructed multicast tree is shown in Fig.2 We can see that in the tree, level 0 ={s}, level 1 = {a, b}, level 2 = {c, d, e} and level 3 = {f, g}.
In the second step, we identify the minimal number of relay nodes that form the broadcast tree. Using more relay nodes means more transmissions in the network. Because the number of available channels is limited by current technical conditions, more transmissions would result in more
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process is similar with the broadcast structure, except that we do not require that the relay nodes should cover those non receiver and non relay nodes of the lower level. We use a simple example to illustrate the process. There is a tree mesh in Fig. 5a, where nodes 6, 7, and 8 are multireceivers. First, we select node 4 at level 2 because it covers all the multireceivers at level 3.
interference and incur more bandwidth cost. Thus, minimizing the multicast tree size helps to improve the throughput.
(a)
(b)
Fig 5a: Network Topology
(c) Fig 4: Relay Node
(d)
For example Fig. 4a gives a i (i+1) subtree mesh, from which we can compute the number of parents of each node in level i + 1. The nodes 1, 5, and 7 have the minimal number of parents (one parent), and their parents are nodes a; c, and d. The numbers of children of nodes a; c, and d are three, two, and two, respectively. Since node a has the maximal number of children, a is chosen as a relay node. We then remove a and its child nodes 1, 2, and 3 from the subtree mesh. In the new subtree mesh, this is shown in Fig. 4b, the nodes 5and 7 have the minimal number of parents, and their parents are nodes c and d.We randomly choose c as one relay node since c and d both have two children. Afterward, we remove c and its children, and then get the subtree mesh shown in Fig. 4c. Similarly, with the process above, we select node d as a relay node. After removal of node d and its children, the level i 1 is empty, thus the algorithm stops. Finally, nodes a; c, and d are chosen as relay nodes at level i, which is shown in Fig. 4d. 3.1.2 MULTICAST STRUCTURE We propose to construct a slim structure by using the MCM Tree Construction algorithm. The goal of the algorithm is to discover the minimal number of relay nodes needed to construct a multicast tree. The search process starts from the bottom to the top. We use a boolean variable c[v] for any node v to represent that v is either a multireceiver or a relay node if c[v] is true. At each step, we intend to minimize the number of relay nodes at the upper level, which can cover all the multireceivers and relay nodes at the lower level. The
Fig 5b: Multicast Tree Next, we select node 2 at level 1, which covers all the multireceivers and the relay node at level 2. Finally, we get the multicast tree in Fig. 5b. 4. PERFORMANCE ANALYSIS 4.1 NETWORK SIZE We evaluate the throughput in different network sizes by assigning the number of nodes with 30 and assigning the number of the available channels with 12. We vary the number of multireceivers from 5 to 25 in a 30-node-sized network. We measure the throughput of the MCM algorithm, the LCA algorithm, and the single-channel algorithm in which only one single channel is used in the multicasting. The results are shown in Fig. 6. We can see that using multichannel and multiinterface significantly improves the throughput. The reason is that using different channels prevents the channel interference among close-by transmissions. Compared with LCA, MCM further improves throughput, although they both take advantage of multiple channels and multiple interfaces. This is because
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MCM builds a more efficient multicast tree and carefully assigns the channels on the tree; thus, it further reduces the interference.
REFRENCES [1].Guokai Zeng,Yong Ding, and Matt W. Mutka, Efficient Multicast Algorithms for Multichannel Wireless Mesh Networks IEEE Transactions On Parallel and Distributed Systems, vol. 21, no. 1,January 2010. [2] J. So and N. Vaidya, Multi-Channel Mac for Ad Hoc Networks: Handling Multi-Channel Hidden Terminals Using a Single Transceiver, Proc. ACM MobiHoc, 2004. [3] K. Ramachandran, E.M. Belding, K. Almeroth, and M. Buddhiko, Interference-Aware Channel Assignment in MultiRadio Wireless Mesh Networks, Proc. IEEE INFOCOM, 2006. [4] J. Tang, G. Xue, and W. Zhang, Maximum Throughput and Fair Bandwidth Allocation in Multi-Channel Wireless Mesh Networks, Proc. IEEE INFOCOM, 2006. [5]P. Li, N. Scalabrino, Y. Fang, E. Gregori, and I. Chlamtac, Channel Interference in IEEE 802.11b Systems, Proc. IEEE Global Telecomm. Conf. (GLOBECOM), 2007. [6] A. Mishra, V. Shrivastava, and S. Banerjee, Partially Overlapped Channels Not Considered Harmful, Proc. ACM SIGMETRICS/ Performance, 2006. [7] B. Raman, Channel Allocation in 802.11-Based Mesh Networks,Proc. IEEE INFOCOM, 2006. [8] S. Roy, D. Koutsonikolas, S. Das, and Y.C. Hu, High throughput Multicast Routing Metrics in Wireless Mesh Networks, Proc. 26th IEEE Intl Conf. Distributed Computing Systems (ICDCS), 2006. [9]A. Mishra, E. Rozner, S. Banerjee, and W. Arbaugh, Exploiting Partially Overlapping Channels in Wireless Networks: Turning a Peril into an Advantage, Proc. ACM/USENIX Internet Measurement Conf., 2005. [10] A. Raniwala and T. cker Chiueh, Architecture and Algorithms for an IEEE 802.11-Based Multi-Channel Wireless Mesh Network, Proc. IEEE INFOCOM, 2005. [11] M. Kodialam and T. Nandagopal, Characterizing the Capacity Region in Multi-Radio Multi-Channel Wireless Mesh Networks, Proc. ACM MobiCom, 2005. [12] M. Alicherry, R. Bhatia, and L. Li, Joint Channel Assignment and Routing for Throughput Optimization in Multiradio Wireless Mesh Networks, Proc. ACM MobiCom, 2005. [13] P.N. Klein, Multiple-Source Shortest Paths in Planar Graphs,Proc. 16th Ann. ACM-SIAM Symp. Discrete Algorithms, 2005. [14] P. Bahl, R. Chandra, J. Dunagan, SSCH: slotted seeded channel hopping for capacity improvement in IEEE 802.11 ad hoc wireless networks, in: ACM Annual International Conference on Mobile Computing and Networking, pp. 216 230,2003. [15] A. Acharya, A. Misra, S. Bansal, High-performance architectures for IP-based multihop 802.11 networks, IEEE Wireless Communications vol.10, no.5, pp. 22-28,2003.
Fig 6: Impact of Network Size 4.2 TRANSMISSION RATE We vary the transmission rate from 50 packet/s to 300 packet/s, and measure the throughput of MCM and LCA. Fig. 7 shows that MCM achieves much better throughput than LCA under different transmission rates. We also observe that the saturated transmission rates for MCM and LCA to achieve nearly the maximal throughput are 225 packet/s and 125 packet/s, respectively.
Fig 7: Impact of Transmission Rate 5. CONCLUSION An effective multicast structure is constructed to minimize the number of the relay nodes and the communication delay. The dedicated channel assignment helps to further reduce the interference as well. Compared with previous multicast approaches, our algorithms are based on the multichannel and focus on the throughput improvement. The performance evaluation shows that our algorithms outperform the single-channel multicast in terms of throughput and delay, and more efficient multicast structure and further improve throughput and reduce delay.
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ANALYSIS OF NON INVASIVE PULSE OXIMETRY WITH SINGLE LIGHT SOURCE USING FOURIER SERIES AND SOFT COMPUTING TECHNIQUES
R.MOULEESHUWARAPPRABU#1,P.HARI KRISHNAN#2 #1M.E.(C&I) Dept. of electrical and electronics engineering, Anna university of technology Coimbatore,Coimbatore. mouleeshuwarinstru@gmail.com #2 Lecturer, Dept. of electrical and electronics engineering,Anna university of technology Coimbatore,Coimbatore. hariora@yahoo.com
ABSTRACT
Pulse oximetry is a methodology by which the oxygen content in the blood could be measured. It is necessary to analyze the patients conditions in the intensive care unit especially during anaesthesia. The conventional pulse oximetry uses two light sources to determine the oxygen content. In the proposed method with the help of single light source the oxygen content is measured. To remove the artifacts appeared in the received signal various filters can be employed. Apart from that the Fourier series analysis could also be used to remove the artifacts. The type of hypoxia will be determined by means of the soft computing techniques. A comparative analysis between the Fourier series analysis and the various types of filters can be done. The best artifact removing technique will be determined. As a result, the accuracy can be improved. In addition to that the overall cost of the system can be reduced by using the single light source. To design a pulse oximetry system, this is used to determine the oxygen content in the blood through which the anaesthesia could be easily identified. By means of the value from this system we can treat the patients properly.
1 PULSE OXIMETRY USING TWO LIGHT SOURCES

1.1 System Explanation In order to build finger (or earlobe) probes which are small and unobtrusive, we need miniature light sources and detectors. Lightemitting diodes (LEDs) which work in the red and NearInfra Red (NIR) part of the spectrum are readily available. However, the average power which can be obtained from standard LEDs is limited and a very sensitive detector (such as a photomultiplier tube) would be required to detect the small amount of light transmitted through the finger. This problem can be overcome by using specialpurpose LEDs which have been developed, red LEDs are now being manufactured with internal lensing systems to give high intensity outputs. Similarly, high current NIR LEDs are designed to be pulsed so that the peak power available from them can be increased without increasing the average power. This makes it possible to detect the light transmitted through the finger with a simple, compact, solidstate photodetector such as a photodiode.
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Fig. 1.1 Block diagram of the pulse oximetry If we pulse both light sources, we can then micro seconds pulses to the red and NIR LED use a single photodetector in the finger probe, since drivers at a repetition rate of 1 kHz, as shown in silicon devices are responsive to light having Figure 2.5 (a frequency of 1 kHz is suitable visible and NIR wavelengths. We could, for because such a frequency is well above the example, use timing circuits to supply, say, 50 maximum frequency present3 in the arterial pulse)
Fig. 2.5 Timing signals for the LED drivers In this mode of operation, highintensity light outputs can be obtained with the NIR LED with currents of up to 1A over a low duty cycle. The transmitted light detected by the photodiode is amplified and converted to a voltage using an opamp configured as a currenttovoltage converter. At this point in the circuit the signal is fed to two identical sections, one for each of the transmitted wavelengths. Since the light is pulsed, we need to use a sampleandhold circuit to reconstitute the waveforms at each of the two wavelengths. The same timing circuits which were used to control the red and NIR LED drivers are also used to provide the control pulses for the corresponding sampleandhold circuits. The outputs from these circuits are then filtered with a bandpass filter (with 0.5 Hz and 5 Hz cutoff frequencies) in order to remove primarily the d.c. component but also high frequency noise. The resulting signals thus represent the cardiacsynchronous information in the waveforms and these are further amplified before they are converted to digital format for subsequent analysis by the microprocessor. It can be seen from the block diagram in Figure 2.4 that the output from each sampleand hold is also passed to a lowpass filter.
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8. Electrical interference and Motion artifacts. 9. Pressure on the Sensor and Hyperemia. 10. Failure to detect absence of circulation and hypoventilation. 1.3 Problem identification In order to have an accurate measurement, the proper artifact removal technique has to be used. Also for simplicity of operation, the synchronisation has to be eliminated. To achieve this number of sources has to be reduced to one. So, the new method will concentrate on single light source and proper artifact removing technique.
This is the first stage of an automatic gain control (AGC) circuit which adjusts the light intensity from the corresponding LED so that the d.c. level always remains at the same value (say 2V) whatever the thickness or skin Characteristics of the patients finger. There are two equally important reasons for deciding to use an AGC circuit, firstly, it means that the amplitude of the a.c. signal (which may vary between 0.1% and 2% of the total signal) is also within a predefined range and this makes the amplifier which follows the Bandpass filter easier to design. Secondly, the d.c. component of the transmitted red and NIR signals can be set at the same value (2 V) in each case. Hence it can be eliminated from the formula used by the microprocessor to calculate the oxygen saturation. A new index is defined as follows R=log10 (Iac) /log10(Iac) (2.7) In practice, it is not even necessary to convert the a.c. signal amplitudes at the two wavelengths to their logarithmic equivalents, instead a lookup table can be loaded into memory and this will contain the values of oxygen saturation corresponding to each value of the (Red pulse amplitude)/(NIR pulse amplitude) ratio. 1.2 Pitfalls and limitations Despite the reliance placed on the information received from this essential monitor, the underlying principles and limitations of pulse oximetry are poorly understood. 1. Dyshaemoglobinemias. 2. Poor function with poor perfusion. 3. Difficulty in detecting high oxygen partial pressures. 4. Delayed detection of hypoxic events. Delay in response is related to sensor location. 6. Erratic performance with irregular rhythms. 7. Nail polish - coverings and Loss of accuracy at low values. In order to eliminate the need for using two LEDs to get two different wavelengths of light. This would allow less calibration of the device. To do this we tried using a blue LED and a ruby. Passing the light through the ruby produces blue light and red light. The problem with using blue light is that it is absorbed at much higher rates in the body than infrared light. As mentioned in the first part of this report, the traditional pulse oximeter uses two Red and Infrared LEDs shining alternatively as its light source. It has to include some circuits to switching between these two LEDs and stabilize the ratio of Red to Infrared intensities so that the pulse 5.
2. PULSE OXIMETRY WITH SINGLE LIGHT SOURCE
Fig. 2.1 Block diagram
2.1
Selection
of
light
source
oximeter could make accurate and stable measurements. Our new idea is that, to simplify the circuitry for switching and calibration, replace the two LEDs by a Blue LED with a Ruby. Since the energetic photon from Blue LED can optically excite red emission from Cr:Sapphire (Ruby), the Red to Blue ratio is always fixed and theres no need for calibration. Besides, it is also possible to grow InGaN (Indium Gallium Nitride) Blue LED on the Ruby substrate and integrate them into one new device for pulse oximeter. The emission spectrum from a Ruby excited by a commercial Blue LED (1000 mcd intensity from DigiKey) is shown in Figure 3.1.
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necessary. Further, because the transmitted intensity of red and blue light was an order of magnitude different, a sensor with programmable sensitivity was also desired. TAOS has one such sensor, the TCS230 (I30). The TC230 provides a pulse train output with frequency being proportional to incident light intensity. The digital nature of this output further reduces the effects of 60Hz induced noise when sending the output over long leads from the probe to the main board. To switch between red and blue sensitivity, input S2 is tied high and S3 is switched with the However, a Fourier series is applicable only to periodic signals and, hence, cannot directly be applied to a PPG signal, which is quasi-periodic and no stationary. In the method being presented here, this problem is overcome by applying Fourier series on a cycle-by-cycle basis. First, a complete cycle of a PPG, as shown in Fig. 3.4(a), is identified and its time period, e.g., T1, is determined. Assuming that this first cycle endlessly repeats itself, Fourier coefficients, e.g., a0, ak and bk|k=1, 2, 3,..., , are computed, with T = T1 and stored. It should be noted here that these coefficients are strictly applicable only to the first cycle. Once the Fourier coefficients that are applicable for the first PPG cycle are computed and stored, the next cycle in the PPG signal (with period T2) is then identified and subjected to Fourier series expansion. This process is repeated for every cycle and in general, the mth cycle will be represented by its set of coefficients ma0, mak and mbk|k=1, 2, 3,..., . A reverse process is applied to reconstruct PPG signal fR(t) cycle by cycle from the stored set of coefficients.
The 694 nm red emission from Ruby has a very narrow bandwidth that could be a good optical source for spectroscopy. Figure 3.2 demonstrates the mechanism of Blue LED exciting Ruby. Blue photon excites the electrons in Chromium Ions of Ruby from ground state to 4F bands, then rapid non radiative decay happens and electrons transits back to a metastable doublet. 2.2 Selection of photodetector Because both red and blue light are transmitting through the patient simultaneously, a switchable sensor that selects sensitivity to the two colors was onboard pulse signal. This selects either a bank of 16 on chip sensors with red filters or blues filters. The time needed for the output to stabilize after a switch is only 1uS, which is negligible compared to the frequency of the signals being measured. Sensor sensitivity is also switched by tying input S0 to VDD and switching S1 with the pulse signal. This allows for a 100% output range when measuring blue light and a 20% output range when measuring red light (maximum output for red intensity is 1/5 that of blue). This provides a smaller disparity in red vs. blue output amplitude for the subsequent frequency to voltage converter stage and ultimately the final analog output.
3 ARTIFACTS TECHNIQUE
REMOVING
A novel method for removing motion artifacts from corrupted PPG signals by applying Fourier series analysis on a cycle-by-cycle basis has to be done. Aside from artifact reduction, the proposed method also provides data compression. Experimental results indicate that the proposed method is insensitive to heart rate variation, introduces negligible error in the processed PPG signals due to the additional processing, preserves all the morphological features of the PPG, provides 35 dB reduction in motion artifacts and achieves a data compression factor of 12. Commercial pulse oximeters utilize If a patient connected to a pulse oximeter moves, the contact between the sensor and the skin deteriorates and corrupts the PPG signals acquired during such movement periods with motion artifacts, resulting in erroneous and unreliable estimation of SpO2 during such periods. Hence, the reduction of motion artifacts in PPG signals is of particular concern within the context of pulse oximeters. The moving average (MA), adaptive and multirate filtering techniques proposed for the reduction of motion artifacts have limited application. . It is well known that any periodic signal can be decomposed into a set of sinusoids made of a fundamental frequency and its harmonics, as described by the Fourier series.
Fig. 3.1(a) Sample PPG. (b) PPG extracted from (a) with only the first seven Fourier coefficients. (c) PPG in (a) corrupted with motion artifacts. (d) PPG
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pulse oximeter. Use of the proposed method reduces the error in computation of SpO2.
extracted from (c) using the proposed CFSA method. CFSA is applied on the PPG of Fig. 3.4(a) and coefficients of up to k = 20 are computed. Then, each cycle of the PPG is reconstructed with a reduced set of coefficients, starting from kmax = 1 to 10. NRMSE in terms of decibels, as well as percentage, is calculated in each case and presented in Table3.1. From Table3.1, it is seen that it is more than sufficient to compute and store only the first seven significant Fourier coefficients of each cycle to retain all the morphological features of the given PPG signal with an accuracy of 0.5%. Fig. 3.4(b) shows the reconstructed PPG signal using only the first seven significant Fourier series coefficients.
REFERENCES
[1] M. R. Neuman and N.Wang, Motion artifact in pulse oximetry, in Proc. IEEE Conf. Med. Biol., 1990, vol. 12, pp. 20072008. [2] K. W. Chan and Y. T. Zhang, Adaptive reduction of motion artifact from photo plethysmographic recordings using a variable stepsize LMS filter, in Proc. IEEE Sensors, 2002, vol. 2, pp. 13431346. [3] J. Lee, W. Jung, I. Kang, Y. Kim and G. Lee, Design of filter to reject motion artifact of pulse oximetry, Comput. Stand. Interfaces, vol. 26, no. 3, pp. 241249, May 2004. [4] C. M. Lee and Y. T. Zhang, Reduction of motion artifacts from photoplethysmographic recordings is using a wavelet denoising approach, in Proc. IEEE EMBS Asian-Pacific Conf. Biomed. Eng., 2003, pp. 194195. [5] B. S. Kim and S.K.Yoo,Motion artifact reduction in photoplethysmography using independent component analysis, IEEE Trans. Biomed. Eng., vol. 53, no. 3, pp. 566568, Mar. 2006. [6] J. Yao and S. Warren, A short study to assess the potential of independent component analysis for motion artifact separation in wearable pulse oximeter signals, in Proc. 27th Annu. Conf. IEEE Eng. Med. Biol., 2005, pp. 35853588.
4 CONCLUSION
Thus by means of the single light source the oxygen level in the blood can be determined. Through the Fourier series analysis, the artifacts can be removed. Oxygen-saturation measurement with a pulse oximeter is plagued by artifacts whenever the patient connected to the oximeter moves. A new processing method employing Fourier series analysis has been used to reduce the effect of motion artifacts on pulse oximeter readings. Fourier series is applied on a cycle-bycycle basis to counter the quasi periodic and nonstationary nature of signals encountered in a
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Design Of ALUs Using Adaptive Clock Stretching

Miss.Bavithra.T 1, Mr.Sakthivel.P2
PG scholar in Embedded System Technologies, Department of Electrical and Electronics Engineering 2. Asst.Professor in Electrical & Electronic Engineering Velalar College of Engineering and Technology,Erode
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Abstract -- In this paper, we explore various arithmetic

units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder. This optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching.
Index Terms:
Adders, arithmetic logic unit, high-speed design, low power, multipliers, process variation tolerant design, supply voltage scaling.
1.INTRODUCTION
Across the rapid growth of the consumer electronics, the demand for Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including Computers, calculators, video cameras etc. In fact, there will be always need for high speed and low power digital products which makes digital design a future growing business. ALU (Arithmetic logic unit) is a critical component of a microprocessor and is the core component of central processing unit. Furthermore, it is the heart of the instruction execution portion of every computer. ALUs comprise the combinational logic that implements logic operations, such as AND and OR, and arithmetic operations, such as ADD and SUBTRACT. ARITHMETIC & LOGIC UNITS (ALU) are the core o f microprocessors where all computations are performed Demand for performance at low power consumption in todays general purpose processors has put severe limitations on ALU design. ALUs are also one of the most power hungry c o m ponents in the processor and are often the possible l o c a t i o n o f h o t - s p o t s . The presence of multiple ALUs in s u p e r s c a l e r pipelines further deteriorates the power and thermal issues [3]. Technology scaling has resulted in faster devices but at the same time the die-to-die delay
variations has also i n c r e s e d . Therefore, low-power ALU design while maintaining high yield under tighter delay constraint turns out to be a challenging problem. Supply voltage scaling is very effective in reducing the power dissipation due to quadratic dependency of switching power on supply voltage and exponential dependence of subthreshold leakage. Variable supply voltage and adaptive body biasing techniques have been proposed in [4] to jointly optimize the switching and leakage power of a multiply-accumulate unit. In [1], [2], the power consumption is reduced by observing the fact that the critical paths of arithmetic units are exercised rarely. Therefore, the supply voltage can be scaled down (while maintaining the clock frequency) to utilize the timing slack available between the critical paths and the longest off-critical paths. The off-critical paths (or short paths) are evaluated at rated frequency while the infrequent critical paths (or long paths) are evaluated in two-clock cycles. This allows aggressive scaling of supply voltage with minimal throughput degradation. In [1], the application of this methodology is shown for ripple carry adder. A new adder called Cascaded Carry Select Adder c sa is proposed in [2] which improve the existing Carry Select Adder (CSA) to make it amenable to supply voltage scaling and adaptive clock stretching operation. Various adder families [5][9] have been proposed in the past to tradeoff speed, power and area for possible use in ALUs. Of all the complex adder families, ripple carry adder (RCA) is the most area and energy efficient but with worst critical path delay. CSA is faster than RCA however, it has larger area due to logic duplication. KoggeStone (KS) [6] on the other hand, is among the fastest adders but consumes large area and power. Therefore, a family of sparse tree adders has been proposed to reduce area at the cost of slight increase in delay. Some examples of sparse tree adders are Brent-Kung, Han-Carlson, Sklansky, Quaternary tree adder etc. In Brent-Kung (BK) [7], the forward tree computes the longest carry fast and the intermediate carries are computed by a backward tree. Han-Carlson (HC) [8] computes the even carries first and generates the odd carries using a backward tree. The quaternary tree adder (QTA) [9] performs the computation with significantly less overhead than Han-Carlson adder. It combines the speed of the CLA with the lower complexity of the Carry-Select Adder (CSA). In [5], the various tree adders have been compared in the energy-delay space. However, adders (or hybrid-adders) have not been explored in terms of supply voltage scaling with adaptive clock stretching operation for low-power and high-yield ALUs.
This project is focused on the design of an efficient VLSI Architecture for high performance & low power ALUs using Adaptive Clock Stretching technique which is a feature of synthesizable cores, introduced by ARM Ltd. and adopted by TI in their OMAP platform, wherein the input test clock (TCK) is delayed (synchronized) before producing the resulting output clock (RTCK). During this synchronization period the target core samples Test Data In (TDI), Test Mode Select (TMS), and TCK with the core clock.
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D-trigger and is typically connected to the TCK_RET pin of the JTAG connector. In this paper, we explore various topologies of adders (e.g., RCA, C SA, BK, QTA) in terms of their amenability to above mentioned supply voltage scaling and adaptive clock stretching. We compare the power, area and speed of these adders at scaled supply and iso-yield conditions to determine the best candidate suitable for high speed and low power dissipation. We further propose careful optimization to design hybrid adders that would allow further scaling of supply voltage and tolerance to process variations with small area penalty. In hybrid adders we mix a small amount of a fast adder into a strategically selected portion of a slow adder in order to make the single-cycle short paths faster and creating room for further voltage scaling. We also extend this study to the design of lowpower multipliers. In summary, we make the following contributions in this paper. development and comparison of voltage scalable adder architectures with adaptive clock stretching for high-speed, low-power, and high-yield ALUs; proposal of hybrid adder design methodology that optimizes the short latency off-critical paths of the adders to allow further scaling of supply voltage with improved yield and tolerance to process variation; application and analysis of hybrid technique for the design of low-power, process-variation-tolerant multipliers at scaled supply.
Emulators can adapt to the RTCK output of these adaptive clocking cores using a simple scheme. This scheme requires the emulator to generate the next TCK edge only after receiving an acknowledge signal from the target, indicating that it has received and processed the previous edge. The target will acknowledge these TCK edges by repeating them (after some delay) on its RTCK output. This protocol creates a natural, target-controlled throttle for the TCK rate. A positive side-effect to this mechanism is that any delays introduced by the JTAG cable are automatically taken into consideration.
Fig. 1.1 Adaptive Clocking Mechanism Internally, the adaptive clocking mechanism is implemented as a multi-stage synchronizer consisting of several D-Triggers (Fig. 1.1) synchronizing the TCK to the core clock of the target (as well as transferring all other JTAG signals to the core clock domain).The number of synchronizers, Ns, is device-dependent, but has shown to be a value of 3 or 4 in OMAP cores at this time. RTCK is the output from the last
The rest of the paper is organized as follows. In Section II, we briefly discuss supply voltage scaling and adaptive clock stretching for low-power ALU design. We also explore different adder topologies for power, speed and yield. We propose hybrid adder design methodology in Section III. Low-power multiplier using adaptive clock stretching is presented in Section IV. In Section V, we use the hybrid adder design in the vector merging stage of carry-save multiplier (CSM) architecture. The practical challenges and tradeoffs are discussed in Section VI and finally, the conclusion is given in Section VII
Fig. 1. (a) Basic structure of variable latency adder. (b) Adaptive clock stretching operation in variable latency adder (Tc is the clock period).
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For other longer paths, the decoder output is automatically asserted and a clock stretching operation is performed to avoid timing failure. Note that in this example, any path longer than 17 full adder delay is considered critical, and evaluated in stretched clock to avoid delay failure. Since the probability of any path being longer than 17 full adder delay is very small, this technique results in very small throughput penalty. For the sake of convenience, we use the term short paths or short latency paths to refer to longest off-critical paths. The critical paths will be referred as long paths or long latency paths. The adaptive clock stretching operation in adders is further elucidated in Fig. 1(b) with the help of timing diagram for three pipelined instructions. Let us assume that out of these three instructions, the second instruction activates the long path. Therefore, adaptive clock stretching should be performed during the execution of second instruction for correct functionality of the pipeline. The regular clock and adaptive clock is shown in Fig. 1(b) for the sake of clarity. Note that, the second instruction is fired at cycle-2 but evaluated in cycle-4 using the adaptive clock. This is achieved by gating the clock edge in cycle-3 based on the output of critical path prediction logic. The gated clock in Fig. 1(b) suggests that we are essentially knocking-off clock pulses occasionally to avoid failures at rated clock frequency. Although better long latency path prediction can be made and performance penalty can be reduced by decoding more bits, the power/area overhead increases with decoder size (Section VI-B). Based on our simulations, 610 bit decoding is optimal; therefore in the rest of the paper, we have decoded 8 bits from the middle of the adder for analysis and simulation purposes. Fig. 2 shows the implementation details of the latency predictor block (LPB) that decodes the intermediate inputs to predict if the current computation requires clock stretching or not. The D flip-flop shown is necessary because LPB needs to remember the nature of input latency in the previous clock cycle in order to generate the correct value of enable in the current cycle.
II. LOW-POWER VOLTAGE SCALABLE ADDER ARCHITECTURES:

In this section, first we briefly discuss the concept of voltage scalable variable latency adders using adaptive clock stretching. Next, we develop different adder architectures based on RCA, C SA, BK and QTA that would enable supply voltage scaling and process variation tolerance, with minimal impact on speed, area and tolerance to process variation.
A. Variable Latency Adders Using Adaptive Clock Stretching

Variable latency adders are based on the fact that the critical paths are activated occasionally. Therefore, supply voltage can be lowered while maintaining the rated clock frequency. The off-critical paths are evaluated in 1-cycle (at rated frequency) while the clock period is stretched to 2-cycles when the critical paths are activated. This allows us to exploit the timing slack between long and short paths for supply voltage scaling. A pre-decoder is required to predict the activation of critical paths based on the input pattern. The concept of supply voltage scaling and adaptive clock stretching is illustrated by taking an example of a 32-bit ripple carry adder [Fig. 1(a)]. Since decoder consumes area, only few intermediate bits are decoded to predict critical path activation. In Fig. 1(a), bit-13 through bit-17 is decoded to predict whether the current input pattern can propagate the input carry (C12) through bit-17 or not. The decoding circuit is nothing but a set of XOR gates that determines whether is true or false (where ps are propagate signal [11]). For this choice of decoding, path through is the longest critical path whereas paths through and through are the longest off-critical paths (both as well as carry propagations are detected by this pre-decoding logic). The adder supply is scaled down while keeping the frequency same such that the longest off-critical paths can be computed without any delay failure.
Fig.2 Latency Predictor Block (LPB)
Fig.3. 32 bit cascaded carry select adder
One of the aspects of LPB that needs special mention is the

use of a negative D latch along with a positive edge triggered D flip-flop. The circuit (shown in Fig. 2) allows computation of the enable signal before the next set of inputs arrive (at the next rising edge of the clock), an aspect which is extremely critical for the success of our design methodology. The value of enable latched in the negative clock cycle is used to determine whether the output register will be written at the next rising edge of the clock or be delayed by one clock cycle to implement clock stretching. Disabling of the write operation to the input and output registers is achieved by clock gating as shown in Fig. 1(b). While considering the predictor block we make the important assumption that the latency detection circuitry is designed to be process tolerant by proper sizing of the transistors
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B. Voltage Scalable Variable Latency Adder Topologies:

Fig. 3 shows 32-bit C SA, BK and QTA adders with their long latency path and two short latency paths that determine supply voltage scaling. The long latency path is shown with bold line whereas the short latency paths are shown with dashed lines. In C SA [2], cascading is done by dividing the 32-bits into chunks of {2, 2, 3, 4, 5, 2, 2, 3, 4, 5}. The partial sum is computed in parallel for as well as using RCA. Next, the multiplexers select the appropriate sum based on the actual carry. Fig. 3(a) shows a 32-bit C SA. In the tree adders [Fig. 3(b) and (c)], black squares denote the computation of propagate and generate (p, g) whereas grey squares denote computation of generate (g) only. The buffers are denoted by empty triangles. In 32-bit BK adder [Fig. 3(b)], forms the long latency path. The pre-decoder determines whether the carry will propagate between bit-16 to bit-23. If the carry path is broken [as shown by dashed carry path in Fig. 3(b)] then will be computed at the same time as . Under this condition, will form the short latency path. In the QTA, the pre-decoder will predict the carry propagation between bit-16 to bit-23. In case the carry is not propagated, and will be computed independent of each other and will form the short latency paths. Intuitively, RCA is expected to allow better supply voltage scaling because of large timing slack present between long latency and short latency paths. However, the speed of the adder itself is slow. Tree adders, for example KS, are fast because they try to compute all paths in parallel. But in the process, it also reduces the timing slack between long and short latency paths. Further the dense routing wires increase area as well as delay. Sparse tree adders like BK and QTA, tradeoff the area with speed and also reduce the wiring overhead. The delay of critical path also determines the adders tolerance to process variation. Longer paths may experience less variations compared to shorter paths due to cancellation effect (i.e, the average current drawn by the logic gates in longer path remains same under intra-die process variation). Fig.5. EDE analysis of 64-b compound-domino and static adders in 130-nm technology. For analysis and comparison of adders, we experimented with 32-bit and 64-bit RCA, C SA, BK and QTA adders synthesized using Synopsis design compiler [12]. The simulation is done using Hspice with BPTM 70 nm [13] devices. The process variation is modeled as lumped variations due to interand intra-die process fluctuations. The (mean, sigma) of interdie and intra-die variation is taken to be (0, 40 mV) and (0, 20 mV), respectively.
Fig.4.Comparison of 32-b QT and KS adders. EDE versus simulation in 100-nm technology.
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Fig. 4 Power consumption under ISO Yield conditions for (a) ripple carry adder (RCA) , (b) cascaded carry select adder (CCSA)
Fig. 5. Hybrid adders. (a) RCA. (b) C SA. The long and short latency paths are shown by solid and dashed lines, respectively. The of the transistor is given by the summation of and change in due to inter- and intra-die nominal process variations. The operating frequency of the adders at nominal supply (1 V) is chosen such that the long paths meet 95% yield target. In order to determine the yield we run 5000 Monte Carlo simulation of the long latency critical paths. Supply voltage scaling is performed so that long paths meet 100% yield while the short paths latency meet 95% yield with respect to their delay targets. As discussed earlier, adaptive clock stretching is used with prediction logic to avoid delay failures at reduced supply voltage.
PDP whereas slower adders consume less power leading to small PDP. The plot suggests that BK can be the best choice for low power with variable latency operations. QTA is fast but consumes more power. The RCA is at one extreme with good robustness and reasonable PDP however, it is too slow to be practical for high-performance ALUs. C SA adder is the fastest among the adders considered here however; it is not practical for low-power ALU design because of large power dissipation (even at scaled supply and variable latency operation).
III. HYBRID ADDERS A.Basic Idea:

From Section II, it can be noted that the timing slack of short paths is exploited for scaling down the supply voltage and to maintain the required yield. Based on this observation, we propose hybrid adders that increase the timing slack of short paths by making them faster. Note that this is counter intuitive because conventionally, the critical paths are optimized to make them faster for better yield. However in this case, we optimize the off-critical (short latency) paths because the yield and power saving is determined by these paths at scaled supply voltage. Fig. 5(a) shows the basic strategy for hybrid adder design using RCA as an example where the middle portion of the adder is replaced with a fast adder topology (KoggeStone in this case). The main idea is to compute the intermediate carries faster using a faster adder topology and create room for further voltage scaling. The middle bits are chosen because these bits are common to both sets of short paths [i.e., carry generated from LSBs and ending in the middle and carry generated from the middle and ending at the MSBs as shown in Fig. 5(a)]
C. Comparison in Terms of Power Dissipation:

For power estimation, we applied a set of 1000 random test patterns to the adders to compute the average power using Nanosim [14]. Fig. 4(a) shows the power dissipation at nominal supply voltage as well as at reduced supply voltage. At reduced supply, we maintain 95% yield with respect to the short latency path delay and 100% yield with respect to the long latency path delay. The adder is operated with variable latency using adaptive clock stretching to avoid delay failures at reduced supply. For the sake of comparison, we also plot percentage saving in power for these adders [Fig. 4(b)]. The important points from this figure are (a) C SA adder consumes highest power due to large area and switching capacitance, RCA on the other hand consumes smallest power, (b) the % power saving also increases as we move towards the slower adders. Fig. 4(c) shows the power-delay product (PDP) of the adders. The faster adders consume large power resulting to increased
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Fig. 6. (a) Comparison of standard adder (at nominal voltage as well as at low voltage using adaptive clock stretching) and hybrid adders in terms of power and operating voltage. (b) Comparison of extra power savings with 32-bit and 64-bit hybrid adders. (c) Area overhead.
B.Design of Hybrid Adders

The following points should be noted for hybrid adder design: (a) the adder topology (for fast computation of intermediate carries) should be selected carefully because it increases the area overhead, (b) more timing slack can be obtained by making more number of intermediate carries faster, however it also increases the area overhead and; (c) the benefit of hybrid adder design diminishes if the original adder itself is very fast. Based on the aforementioned observations, we designed hybrid RCA and C SA. The hybrid designs for 32-bit adder width are shown in Fig. 5(a) and (b). In RCA, the middle 8-bits (i.e., bit-12 to bit-19) are implemented with fast adder to create more timing slack in short latency paths. An 8-bit KS adder is used for this purpose. In C SA, we implemented the 9 intermediate bits by KS adder (bit-11 to bit-19) as shown in Fig. 5(b). This is done owing to the irregular bit partitioning of C SA. It is worth mentioning that in the process of optimization, the hybrid adder becomes faster compared to conventional adder because the intermediate carries are also accelerated. For example, the RCA becomes faster because the middle 8-bits are accelerated. This is certainly an added advantage because for the iso-frequency scenario, this extra slack in overall adder delay can either be used to improve the yield or to scale down the supply voltage further for power savings. In hybrid adders, the supply voltage can be reduced further while maintaining similar/better yield. The operating voltages of the standard and hybrid adders are also shown in Fig. 6(a).The extra power saving of 32-bit and 64-bit hybrid adders at reduced supply (compared with standard variable latency adder at low voltage) is presented in Fig. 6(b). Simulation shows that for 32-bit adders, 30%50% extra power saving can be obtained using hybrid design. For 64-bit adders the power saving varies between 18% 20%. This is due to the fact that only 8 intermediate bits have been optimized for speed. More power saving can be obtained by optimizing 16 intermediate bits (at the cost of more area overhead). The power saving in the hybrid adders come at the price of area overhead. Fig. 6(c) shows the area overhead for 32-bit and 64-bit adders. For the adder examples illustrated in this paper, the overhead is within 10%. Note that, the area overhead presented here does not account for the decoder overhead (for prediction of long latency path activation) since it is common for both conventional and hybrid adders. Furthermore, the area overhead/power saving in hybrid adders can vary depending on the implementation choice of intermediate 8-bits. For example, KS implementation can be more area intensive but may provide large slack whereas BK/HC can be balanced in area but provide less timing slack. At scaled supply, the throughput penalty of both the standard adders and the hybrid adders is same. This is because the signal probabilities of primary inputs are the same and the same number of bits is decoded for adaptive clock stretching. In order to determine the throughput penalty due to adaptive clock stretching, we employed the adders in the execution stage of five stage pipelined processor. Simulation with the SPEC2000 benchmark programs show a throughput loss of3% (this is discussed in Section VI). An important point to note is that, while designing the decoding circuitry for fast adders, we make sure that the delay of decoding is less than the short latency path delay by proper sizing of the decode logic. This ensures that the decision to stretch the clock period is taken beforehand.
C.Simulation Results:
For simulation, we follow similar setup as explained in Section II-B. The experiments have been done on both 32-bit as well as 64-bit RCA and C SA. Note that, for 64-bit hybrid RCA we implemented the middle 8-bits to speed-up the short latency paths. However, for 64-bit C SA, we replaced the middle 10-bits with KS adder (to maintain the uniform structure of the adder). The supply voltage reduction of hybrid adders is performed in a conservative manner to ensure that 95% yield is maintained at scaled supply (at rated frequency and adaptive clock stretching). For the sake of comparison, in Fig. 6(a) we plot the power savings in both the standard adder (at nominal supply as well as scaled supply with adaptive clock stretching) and hybrid adder (at scaled supply with adaptive clock stretching).
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IV. LOW POWER MULTIPLIERS AT SCALED SUPPLY

We have also applied adaptive clock stretching technique to two classes of multipliers namely the carry-save (CSM) and the Wallace tree multipliers (WTM) [11]. In Fig. 7, we show an CSM and its critical paths. The methodology involved in splitting of the critical path in case of the multipliers is slightly different than that of adders. For the adders considered in Section II, the few middle order primary input bits were the inputs to the LPB. However, finding a low-complexity decoder, which can predict in advance the long or short latency operation of the multiplier, is extremely difficult due to the large overhead associated with hardware implementation of decoder. Hence, we relax the constraint that inputs to LPB should be chosen from the primary inputs. Instead, we allow LPB inputs to be the intermediate stage outputs of the multiplier. In the two types of multipliers that we considered, CSM and WTM, the final stage of multiplication consists of a vector merging adder (VMA). In both the multiplier architectures, we consider that the VMA is implemented as a C SA. We split the critical path in the multiplier using the internal bits, which are inputs to the VMA. The resulting short latency paths (SLP1, SLP2) are shown in Fig. 7. Multipliers have many paths of similar delays and under variations any one of these paths may become critical. Hence, we make an assumption that all potential critical paths in presence of variability have common carry propagation path of the VMA. The critical path delay (or the long latency path) is equal to the sum of path delays through the non-VMA part of the circuit and the delay through the VMA. Hence, by breaking the critical path in the adder stage, we take care of paths that have probability of becoming critical under variations. Since we use VMA inputs as our inputs to the LPB, there is a probability that sufficient time may not be available for the enable to be computed by the time the falling edge of the clock arrives. We circumvent this problem by using a negative D latch along with the positive edge triggered D flip-flop (instead of a negative D flip-flop) in the LPB as shown in Fig. 2. Our technique is also applied to WTM, shown in Fig. 7(b). WTM consists of a tree part and a VMA part. The tree part consists of stages, each of which contributes an adder delay to the critical path. The critical path delay is the sum of the number of stages in the tree and the delay through the VMA
For instance, in a 16x16 WTM (using 3:2 compressors), there are 6 stages in the tree part and a 27 bit VMA. Hence, the critical path delay is the sum of 6 adder delay and the worst case carry propagation delay of VMA. We note that there is a great potential to be exploited in case of WTM because of the relatively large size of the VMA. This gives us greater scope for Vdd scaling, resulting in power savings. In Fig. 7(b), a 6 x 6 WTM, showing the tree part and the VMA part is illustrated. In a manner similar to the splitting of critical paths in CSM, the critical path in WTM is cut into SLP1 and SLP2 as shown in Fig. 7(b). The slack between long latency path (LLP) and the maximum of SLP1 and SLP2 can be used for supply voltage scaling as explained in Section II-A.
A. Simulation Results
In this section we compare multipliers (12, 16 bit CSM and 8, 12, 16 bit WTM) implemented in the conventional and our proposed design. All the arithmetic units mentioned above were implemented in 70 nm BPTM technology [13]. The metrics used for comparison were parametric yield improvement, power dissipation, Energy-Per-Computation (EPC), area overhead and throughput penalty. We used VHDL to design the multipliers. The VHDL code was synthesized using Synopsis Design Compiler [12]. In order to obtain the parametric yield in presence of process variations, we ran Monte Carlo simulations in Hspice, assuming a Gaussian Vth variation distribution of zero mean and standard deviation of 40 mV. The power dissipation results were obtained by simulating 1000 random input vectors in NanoSim. In all the arithmetic units considered, the yield of our proposed design was found to be 100% under a nominal supply voltage of 1 V. This can be attributed to the fact that the short latency paths under variations do not exceed the one clock cycle bound and the long latency path, if activated, is evaluated by adaptive clocking scheme. In our simulations we consider two iso-yield conditions: 1) when the proposed design is operated at 1 V and 2) when conventional design is operated at 1 V. In order to have an iso-yield of approximately 100%, when the proposed design is operating at 1 V, the conventional design had to be operated at 1.1 V which gives 24% and 29% power savings for CSM and WTM, respectively, as shown in Fig. 8(a) and (b). However, for the conventional design operating at 1 V, if a certain yield target is desired (CSM Yield 93%, WTM Yield 96%), then the proposed design can operate at a lower
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supply. Table I shows the percentage EPC savings. Fig. 8(c) and (d) show the power dissipation under iso-yield conditions for the conventional design operating at 1 V and the proposed architecture at a scaled down supply (to meet the same yield target). An interesting observation is that the percentage power savings increases with an increase in the number of bits in the multipliers. This is due to the fact that, with an increase in the length of the critical path, more timing slack can be exploited, in terms of supply scaling, after splitting the critical path.
The complication with CSM is that there are many critical paths of similar length. One of the possible critical paths is illustrated in Fig. 9(a) by bold line. The vector merging RCA is replaced with the hybrid-RCA discussed in previous section to speed up the off-critical paths [shown by dashed line in Fig. 9(a)]. Note that, if vector merge stage is implemented by any other adder topology (e.g., C SA), then a corresponding hybrid adder design can be used to optimize the short latency paths. stages are computed fast whereas the vector-merge stage is implemented by ripple carry adder (RCA) to simplify the design.
V. HYBRID MULTIPLIERS
In previous section, we presented the multiplier designs for low power, process tolerance and adaptive clock stretching operations. In this section, we discuss the hybrid multiplier design for low power and adaptive clock stretching.
B. Simulation Results:
We performed simulations on 32 32 as well 64 64 bit carry-save multipliers. The vector merge adder is implemented with hybrid RCA where the middle 8-bit of the RCA (bit [12:19] for 32 bit RCA and bit [28:35] for 64-bit RCA) is accelerated up by using the KS adder. The simulation is performed using BPTM 70 nm devices using the test setup as described in Section II-B. The supply voltage scaling is done such that both conventional and hybrid multiplier maintains a yield target of 95% for short latency path and 100% for long latency path under scaled supply voltage. The power dissipation is estimated using Nanosim for a set of 200 random patterns. The simulation results are shown in Fig. 9(b) which indicates that 5%25% of extra power saving can be gained by using the hybrid multiplier. The extra area-overhead is found to be only 0.2% [Fig. 9(c)
A. Basic Idea:
The design of hybrid multiplier is based on the concept of hybrid adders. Fig. 9(a) shows the bit CSM. The first rows are carry-save stages while the final row is vector-merge stage. In this implementation, the carry-save
Fig.11. Without carry
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In this section, we discuss some of the design challenges and issues involved in designing low-power hybrid arithmetic units using adaptive clock stretching.
A. Throughput Penalty:
In order to determine the actual throughput penalty from a system level perspective, we incorporated the proposed arithmetic units in a five stage DLX pipeline. The throughput penalty was assessed by running SPEC2000 [15] benchmarks in SimpleScalar [16] simulator. The results given in Fig. 10(a) show on an average a 3.03% throughput penalty (by using 10 bit decoding) and less than 8% for 8-bit decoding. We have also done comprehensive simulations on SPEC CINT 2000 benchmarks with ref inputs in order to determine throughput loss with 8-bit input decoding. The configuration of the simulated processor is described in Table II. For applying rare two-cycle operations on adders and multipliers, we considered all instructions that use the adders and multipliers. If a long latency add operation is detected, the adder is set to be occupied for two-cycles and the results is broadcast on the operand buses at the end of second cycle. Similarly, for multiplication operation, the computation is executed in three clock cycles whereas the computation is performed and the result is broadcasted after six clock cycles for long latency operations (note that they are rare). The simulation results [shown in Fig. 10(b)] indicate a maximum throughput loss of 2%.
Fig 12.Performance versus area overhead with # of inputs to LPB (WTM 16 bits)
B. Impact of Number of Decoding Bits:

Increasing the number of decoding bits reduces the throughput penalty because the activation of the critical path can be predicted more accurately. However, the complexity and area overhead of decode logic also increases. In Fig. 11, the tradeoff between throughput penalty and area overhead for a 16 bit WTM is shown. From the graph we observe that throughput penalty decreases with increase in number of decoding bits. Therefore, we use 8-bit decoding throughout this work. Fig.13.Throughput penalty Vs. Number of inputs to LPB
E. Modifications in Design Flow:

Application of low-voltage execution units also requires modification in standard design/verification and manufacturing test process. The RTL development will require addition and cost analysis of pre-decoding logic, clock gating logic. For hybrid execution unit design the RTL should be modified to incorporate fast architecture appropriately. The timing analysis and synthesis should consider the timing of long latency as well as short latency paths to estimate the clock frequency under a yield constraint. The RTL verification requires addition of extra test patterns in delay test suite to verify decoding logic, long and short latency paths.
C. Impact of the Location of Decoding Bits:

If the decoding (for critical path prediction) is done in LSB side, the timing slack for supply scaling reduces since it is limited by the path that starts from decoded bits and end at the MSB. vice versa is true if the decoding is done on the MSB side. Therefore, to maximize the timing slack for supply scaling, we decode the middle 8-bits for critical path prediction
D.Requirement of Level Converting flops:

Note that our analysis of voltage scalable arithmetic units (standard as well as hybrid) does not consider level conversion at the low voltage/nominal voltage interface. We propose to use low overhead level converting flops [11] in order to minimize the area/power/delay overhead
VII. CONCLUSION
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[8] J. Kao, M. Miyazaki, and A. Chandrakasan, A 175-mW multiply-accumulate unit using an adaptive supply voltage and body bias architecture, IEEE J. Solid-State Circuits, pp. 15451554, 2002. [9] R. Woo, S. J. Lee, and H. J. Yoo, A 670 ps, 64 bit dynamic low power adder design, in Proc. Int. Symp. Comput. Architect., 2000, pp.128131. [10] J. Rabaey, Digital Integrated Circuits: A Design Perspective, 2nd ed.Englewood Cliffs, NJ: PrenticeHall, 2003. [11] Synopsys Design Compiler. [Online]. Available: www.synopsys.com
Variable latency functional units using adaptive clock stretching can allow aggressive scaling of supply voltage while maintaining rated frequency with little performance degradation. We developed and explored various adder and multiplier topologies/architecture that are amenable to aggressive supply voltage scaling/clock-stretching while maintaining high yield and frequency. We also proposed hybrid adder design (by mixing small amount of fast arithmetic into the slower ones) that can be utilized for improving yield or scaling the supply voltage further. We demonstrated that hybrid design can indeed make the adders supply voltage scalable with improved tolerance to process variation.
REFERENCES
[1] Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, and Kaushik Roy, Fellow, Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 9, pp. 1301 1309, oct. 2009. [2] D. Mohapatra, G. Karakonstantis, and K. Roy, Lowpower processvariation tolerant arithmetic units using input-based elastic clocking,in Proc. Int. Symp. Low Power Electronic Design (ISLPED), 2007, pp. 7479. [3] S. K. Mathew, M. Anders, B. Bloechel, T. Nguyen, R. Krishnamurthy, and S. Borkar, A 4-GHz 300-mW 64bit integer execution ALU with dual supply voltages in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 4451, Jan. 2005 [4] Y. Chen, H. Li, K. Roy, and C. Koh, Cascaded carryselect adder (C SA): A new structure for low-power CSA design, in Proc. Int.Symp. Low Power Electronic Design (ISLPED), 2005, pp. 195200. [5] V. G. Oklobdzija, B. Zeydel, H. Dao, S. Mathew, and R. Krishnamurthy, Comparison of high-performance VLSI adders in energydelay space, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 754 758, Jun. 2005. [6] H. Suzuki, W. Jeong, and K. Roy, Low power adder with adaptive supply voltage, in Proc. Int. Conf. Computer Design, 2003,pp.103-106.
[12] BPTM 70 nm: Berkeley Predictive Technology Model. [Online].Available: www.eas.asu.edu/~ptm [13] Synopsys Nanosim. [Online]. Available: www.synopsys.com [14] SPEC 2000 Benchmarks. [Online]. Available: www.spec.org [15] Simplescalar Tool Set. www.simplescalar.com [Online]. Available:
[7] J. Rabaey, Digital Integrated Circuits: A Design Perspective, 2nd ed.Englewood Cliffs, NJ: PrenticeHall, 2003.
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DESIGN OF PARALLEL MAC ARCHITECTURE BASED ON MODIFIED BOOTH ALGORITHM D.Kowsalyadevi1 K.Ayyar2
1.PG scholar in embedded system technologies 2. Assist. Professor in Electrical and Electronics Engineering
Velalar College of Engineering and Technology, Erode
Abstract In this paper, we proposed a new architecture of multiplierand-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1s-complement-based radix-2 modified Booths algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library. Index TermsBooth multiplier, carry save adder (CSA) tree, digital signal processing (DSP), Multiplier andAccumulator (MAC). I. INTRODUCTION
Because Wallace tree is to add the partial products from encoder as parallel as possible its operation time is proportional to O( ) , where is the number of inputs. It uses the fact that counting the number of 1s among the inputs reduces the number of outputs into . In real implementation, many (3:2) or (7:3) counters are used to reduce the number of outputs in each pipeline step. The most effective way to increase the speed of a multiplier is to reduce the number of the partial products because multiplication proceeds a series of additions for the partial products. To reduce the number of calculation steps for the partial products, MBA algorithm has been applied mostly where Wallace tree has taken the role of increasing the speed to add the partial products. To increase the speed of the MBA algorithm, many parallel multiplication architectures have been researched. Among them, the architectures based on the BaughWooley algorithm (BWA) have been developed and they have been applied to various digital filtering calculations. One of the most advanced types of MAC for general purpose digital signal processing has been proposed by Elguibaly [6]. It is an architecture in which accumulation has been combined with the carry save adder (CSA) tree that compresses partial products. In the architecture proposed in [6], the critical path was reduced by eliminating the adder for accumulation and decreasing the number of input bits in the final adder. While it has a better performance because of the reduced critical path compared to the previous MAC architectures, there is a need to improve the output rate due to the use of the final adder results for accumulation. An architecture to merge the adder block to the accumulator register in the MAC operator was proposed in to provide the possibility of using two separate /2-bit adders instead of one -bit adder to accumulate the bit MAC results.
With the recent rapid advances in multimedia and communication systems, real-time signal processings like audio signal processing, video/image processing, or largecapacity data processing are increasingly being demanded. The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing such as filtering, convolution, and inner products. Most digital signal processing methods use nonlinear functions such as discrete cosine transform (DCT) or discrete wavelet transform (DWT). Because they are basically accomplished by repetitive application of multiplication and addition, the speed of the multiplication and addition arithmetics determines the execution speed and performance of the entire calculation. Because the multiplier requires the longest delay among the basic operational blocks in digital system, the critical path is determined by the multiplier, in general. For high-speed multiplication, the modified radix-4 Booths algorithm (MBA) [4] is commonly used. However, this cannot completely solve the problem due to the long critical path for multiplication . In general, a multiplier uses Booths algorithm and array of full adders (FAs), or Wallace tree instead of the array of FAs., i.e., this multiplier mainly consists of the three parts: Booth encoder, a tree to compress the partial products such as Wallace tree, and final adder .
Fig.1.Basic arithmetic steps of multiplication and accumulation.
In this paper, a new architecture for a high-speed MAC is proposed. In this MAC, the computations of multiplication and accumulation are combined and a hybrid-type CSA structure is proposed to reduce the critical path and improve the output rate. It uses MBA algorithm based on 1s complement number system. A modified array structure for the sign bits is used to increase the density of the operands. A carry look-ahead adder (CLA) is inserted in the CSA tree to reduce the number of bits in the final adder. In addition, in order to increase the output rate by optimizing the pipeline efficiency, intermediate calculation results are accumulated in the form of sum and carry instead of the final adder outputs. II. OVERVIEW OF MAC In this section, basic MAC operation is introduced. A multiplier can be divided into three operational steps. The first is radix-2 Booth encoding in which a partial product is generated from the multiplicand(X) and the multiplier(Y) . The second is adder array or partial product compression to add all partial products and convert them into the form of sum and carry. The last is the final addition in which the final multiplication result is produced by adding the sum and the carry. If the process to accumulate the multiplied results is included, a MAC consists of four steps, as shown in Fig. 1, which shows the operational steps explicitly. A general hardware architecture of this MAC is shown in Fig. 2. It executes the multiplication operation by multiplying the input multiplier X and the multiplicand Y . This is added to the previous multiplication result Z as the accumulation step.
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If (2) is used, multiplication can be expressed as
If these equations are used, the afore-mentioned multiplication accumulation results can be expressed as
Each of the two terms on the right-hand side of (5) is calculated independently and the final result is produced by adding the two results. The MAC architecture implemented by (5) is called the standard design . If N-bit data are multiplied, the number of the generated partial products is proportional to N . In order to add them serially, the execution time is also proportional to N . The architecture of a multiplier, which is the fastest, uses radix-2 Booth encoding that generates partial products and aWallace tree based on CSA as the adder array to add the partial products. If radix-2 Booth encoding is used, the number of partial products, i.e., the inputs to the Wallace tree, is reduced to half, resulting in the decrease in CSA tree step. In addition, the signed multiplication based on 2s complement numbers is also possible. Due to these reasons, most current used multipliers adopt the Booth encoding. III. PROPOSED MAC ARCHITECTURE In this section, the expression for the new arithmetic will be derived from equations of the standard design. From this result, VLSI architecture for the new MAC will be proposed. In addition, a hybrid-typed CSA architecture that can satisfy the operation of the proposed MAC will be proposed.
Fig. 2. Hardware architecture of general MAC. The N-bit 2s complement binary number X can be expressed as
A. Derivation of MAC Arithmetic 1)Basic Concept: If an operation to multiply two bit numbers and accumulate into a 2 -bit number is considered, the critical path is determined by the 2 -bit accumulation operation. If a pipeline scheme is applied for each step in the standard design of Fig. 1, the delay of the last accumulator must be reduced in order to improve the performance of the MAC. The overall performance of the proposed MAC is improved by eliminating the accumulator itself by combining it with the CSA function. If the accumulator has been eliminated, the critical path is then determined by the final adder in the multiplier. The basic method to improve the performance of the final adder is to decrease the number of input bits. In order to reduce this number of input bits, the multiple partial products are compressed into a sum and a carry by CSA. The number of bits of sums and carries to be transferred to the final adder is reduced by adding the lower bits of sums and carries in
If (1) is expressed in base-4 type redundant sign digit form in order to apply the radix-2 Booths algorithm, it would be
advance within theof Engineering, Coimbatore performance will INFO Institute range in which the overall not be degraded. A 2-bit CLA is used to add the lower bits in the CSA. In addition, to increase the output rate when pipelining is applied, the sums and carrys from the CSA are accumulated
402 The second term corresponds to the lower bits and is the value that is fed back as the addition result for the sum and carry
instead of the outputs from the final adder in the manner that the sum and carry from the CSA in the previous cycle are inputted to CSA. Due to this feedback of both sum and carry, the number of inputs to CSA increases, compared to the standard design and [6]. In order to efficiently solve the increase in the amount of data, a CSA architecture is modified to treat the sign bit. 2) Equation Derivation: The aforementioned concept is applied to (5) to express the proposed MAC arithmetic. Then, the multiplication would be transferred to a hardware architecture that complies with the proposed concept, in which the feedback value for accumulation will be modified and expanded for the new MAC. First, if the multiplication in (4) is decomposed and rearranged, it becomes
Fig .4. Hardware architecture of the proposed MAC The second term can be separated further into the carry term and sum term as

If (6) is divided into the first partial product, sum of the middle partial products, and the final partial product, it can be reexpressed as (7). The reason for separating the partial product addition as (7) is that three types of data are fed back for accumulation, which are the sum, the carry, and the preadded results of the sum and carry from lower bits Thus, (8) is nally separated into three terms as
If (7) and (10) are used, the MAC arithmetic in (5) can be expressed as
Now, the proposed concept is applied to Z in (5). If Z is first divided into upper and lower bits and rearranged, (8) will be derived. The first term of the right-hand side in (8) corresponds to the upper bits. It is the value that is fed back as the sum and the carry. If each term of (11) is matched to the bit position and rearranged, it can be expressed as (12), which is the nal equation for the proposed MAC. The rst parenthesis on the right is the operation to accumulate the rst partial product with the added result of the sum and the carry. The second parenthesis is the one to accumulate the middle partial products with the sum of the CSA that was fed back. Finally, the third parenthesis ex-presses the operation to accumulate the last partial product with the carry of the CSA
Fig. 3. Proposed arithmetic operation of multiplication and accumulation.
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Fig. 5. Architecture of proposed CSA tree B. Proposed MAC Architecture If the MAC process proposed in the previous section is rearranged, it would be as Fig. 3, in which the MAC is organized into three steps. When compared with Fig. 1, it is easy to identify the difference that the accumulation has been merged into the process of adding the partial products. Another big difference from Fig. 1 is that the final addition process in step 3 is not always run even though it does not appear explicitly in Fig. 3. Since accumulation is carried out using the result from step 2 instead of that from step 3, step 3 does not have to be run until the point at which the result for the final accumulation is needed. The hardware architecture of the MAC to satisfy the process in Fig. 3 is shown in Fig. 4. The n-bit MAC inputs, X and Y, are converted into an (n+1) -bit partial product by passing through the Booth encoder. In the CSA and accumulator, accumulation is carried out along with the addition of the partial products. As a result, n-bit, S, C and Z (the result from adding the lower bits of the sum and carry) are generated. These three values are fed back and used for the next accumulation. If the final result for the MAC is needed, P[2n-1:n] is generated by adding S and C in the final adder and combined with P[n-1:0] that was already generated. C. Proposed CSA Architecture The architecture of the hybrid-type CSA that complies with the operation of the proposed MAC is shown in Fig. 5, which performs 88-bit operation. It was formed based on (12). In Fig. 5, is to simplify the sign expansion and is to compensate 1s complement number into 2s complement number. S[i ]and C[i] correspond to the ith bit of the feedback sum and carry. Z[i] is the bit of the sum of the lower bits for each partial product that were added in advance and Z[i] is the previous result. In addition, corresponds to the bit of the partial product. Since the multiplier is for 8 bits, totally four partial products are generated from the Booth encoder. In (11), and correspond to and , respectively. This CSA requires at least four rows of FAs for the four partial products. Thus, totally five FA rows are necessary since one more level of rows are needed for accumulation. For an n nbit MAC operation, the level of CSA is . The white square in Fig. 5 represents an FA and the gray square is a half adder (HA). The rectangular symbol with five inputs is a 2-bit CLA with a carry input. The critical path in this CSA is determined by the 2-bit CLA. It is also possible to use FAs to implement the CSA without CLA. However, if the lower bits of the previously generated partial product are not processed in advance by the CLAs, the number of bits for the final adder will increase. When the entire multiplier or MAC is considered, it degrades the performance. In Table I, the characteristics of the proposed CSA architecture have been summarized and briefly compared with other architectures. For the number system, the proposed CSA uses 1s complement, but ours uses a modified CSA array without sign extension. The biggest difference between ours and the others is the type of values that is fed back for accumulation. Ours has the smallest number of inputs to the final adder.
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comparison. The difference between the two is because ours carries out the accumulation by feeding back the final CSA outputs rather than the final adder results as in Fig. 6
TABLE I
TABLE II
IV. IMPLEMENTATION AND EXPERIMENT In this section, the proposed MAC is implemented and analyzed. Then it would be compared with some previous researches. The pipeline stage is defined and the performance is analyzed based on this pipelining scheme. Implementation result from each section will be compared with the standard design [6], each of which has the most representative parallel MBA architecture. A. Pipelining 1) Stage Analysis: The pipeline stages were determined based on the delay modeling obtained earlier. step 1 and step 2 in Fig. 3 that correspond to the Booth encoding and CSA operation, respectively, are set to stage 1 and step 3, which correspond to the final adder and are set to stage 2. Such pipeline stage can be organized as shown in Table III and the clock frequency is determined by this result. In Table III, it can be seen that CSA can operate at a higher clock rate in [6] compared to the proposed architecture. However, it does not mean that the overall MAC performance is better. The reason why the proposed architecture has slightly higher delay and hardware resources is that the focus of ours has been on the overall performance. This will be examined in detail in the next section. 2) Pipeline Structure and Operation: A hardware incorporates a pipelining scheme to increase the operation speed and ours did too, which is shown in Fig. 6(a), with the one from Elguibalys scheme [6] in Fig. 6(b) for the purpose of
Fig .6. Pipelined hardware structure (a)proposed (b)Standard design These two schemes are also compared in the time sequence in Fig. 7(a) and (b) for Fig. 6(a) and (b), respectively. While an accumulated result cannot be output by the method in [17] every clock period because of a structural drawback for the accumulation, ours can output a result in every clock cycle. Thus, even though our delay is a little longer than [17], as shown in Table III or Table IV, ours shows much better overall performance or the output rate. Table III
Table IV
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Fig. 7. Pipelined operational scheme (a)Standard operation (b)proposed operation [4] P. Zicari, S. Perri, P. Corsonello, and G. Cocorullo, An optimizedadder accumulator for IV. CONCLUSION high speed MACs, Proc. ASICON 2005, vol.2, As high-speed components and low power become pp. 757760, 2005. important implementation concerns in multipliers, the need to design new structures to meet these [5] A. Fayed and M. Bayoumi, A merged requirements increases. In partial product generation multiplier-accumulator for high speed signal step a new modified Booth algorithm has been processing applications, Proc. ICASSP,vol. 3, proposed. In partial product reduction step a novel pp.32123215, 2002. tree structure has been modified. In final addition step a fast adder structure using high-speed components is used. A new full adder has been presented. Parallelism has been used in this multiplier which effects on speed of whole structure. New carry save addition algorithm has been proposed. This study has decreased transistor count by 8 percent, delay time of whole architecture has reduced 10 percent and power consumption reduction is 10 percent in compare with otherprevious designs. [6] F. Elguibaly, A fast parallel multiplier accumulator using the modified Booth algorithm, IEEE Trans. Circuits Syst., vol. 27, no. 9, pp.902908, Sep. 2000. [7] K.Z. Pekmtszi, "Multiplixer-based array multipliers", IEEE Transaction on Computers, vol. 48, no. 1, pp. 15-23, Jan. 1999.
REFERENCES [1] Young-Ho Seo, Dong-Wook Kim, A New VLSI Architecture of Parallel Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm IEEE Trans. Very Large Scale Integration (VLSI) Syst., Vol. 18, No. 2, February 2010.
[8] J. Fadavi-Ardekani, MN Booth encoded multiplier generator using optimizedWallace trees, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 2, pp. 120125, Jun. 1993. [9] T. Sakurai and A. R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584594, Feb. 1990.
[2] Sumit Vaidya and Deepak Dandekar Delaypower performance Comparison of multipliers in VLSI Circuit design International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, pp.47-56 July 2010. [3] Asadee, P, Islamic Azad Univ., Pishva, Iran A new MAC design using high-speed partial product summation tree,IEEE Conference, pp.231 - 234 , Sep.2009
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DESIGN OF WIMAX TRANSCEIVER MODULE USING RS & VITERIBI

Vennilapriya.B1 M.Srinivasan2 1. PG scholar in Embedded system Technologies 2. Head of the Department in Electrical & Electronic engineering Velalar College of Engineering & Technology, Erode
ABSTRACT
Wimax standard specifies the air interface of fixed broadband wireless access (BWA) systems supporting multimedia, Internet, VoIP, satellite communication services. The MAC is structured to support multiple physical layer (PHY) specifications, each suited to a particular operational environment. For operational frequencies from 1066 GHz and 11 GHz, the PHY is based on single-carrier modulation. The objective of the thesis is to design the transceiver module of Wimax with more secure and to increase the data rate using RS and Viteribi algorithm. Wireless metropolitan area networks (WMANs) are used to convey information over relatively long distances. WLANs are connected or communicated through WMANs. These are broadband access with the maximum data rate of 120 Mbps at 10-66 GHz and 11 GHz.
technologies such as Bluetooth and IR.
Wireless MAN PHY

The WirelessMAN-SCa PHY is based on single-carrier technology and designed for NLOS operation in frequency bands below 11 GHz. For licensed bands, channel bandwidths allowed shall be limited to the regulatory provisioned bandwidth divided by any power of 2 no less than 1.25 MHz.
II TRANSMIT PROCESSING
Source data shall first be randomized, then FEC encoded and mapped to QAM symbols. QAM symbols shall be framed within a burst set, which typically introduces additional framing symbols. Symbols within a burst set shall be multiplexed into a duplex frame, which may contain multiple bursts. The I and Q symbol components shall be injected into pulse shaping filters, quadrature modulated up to a carrier frequency, and amplified with power control so that the proper output power is transmitted.
I INTRODUCTION
The main goal of this work is to learn and understand the features of the IEEE standard 802.16a and afterwards, once familiarized with this standard, to develop an OFDM 802.16a PHY layer base band implementation with the characteristics showed in such standard. Borland C is used for writing coding for the model and Real-Time Workshop and Code Composer Studio for targeting that C coding on the DSP board in order to have a better understanding of the standard and of the system performance running this model under both platforms. Wireless networks serve as the transport mechanism between devices and among devices and the traditional wired networks (enterprise networks and the Internet). Wireless networks are many and diverse but are frequently categorized into three groups based on their coverage range: Wireless Wide Area Networks (WWAN), WLANs, and Wireless Personal Area Networks (WPAN). WWAN includes wide coverage area technologies such as 2G cellular, Cellular Digital Packet Data (CDPD), Global System for Mobile Communications (GSM), and Mobitex. WLAN, representing wireless local area networks, includes 802.11, HiperLAN, and several others. WPAN represents wireless personal area network
Figure 1 Transmitter model of Wimax
SOURCE BIT RANDOMIZATION

Source bits, i.e., the original information bits prior to FEC encoding, shall be randomized during transmission.
Figure 2 Randomizer
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However, payloads that cannot be modified by burst profile changes, such as the contents of the FCH, shall not be punctured. When a source allocation does not divide into an integer number of K byte Reed Solomon code words, the last (fractional) RS code word shall be shortened to a smaller value 1 K'< K that accommodates the remainder bytes. All code words, including the shortened last codeword, shall use the R specified by the burst profile for the RS code words within that allocation.
As Figure 2 illustrates, source bit randomization shall be performed by modulo-2 addition (XORing) source (information) data with the output of a Linear-Feedback Shift Register (LFSR) possessing characteristic polynomial 1 + X14 + X15. The LFSR shall be preset at the beginning of each burst set (directly following the preamble) to the value 100101010000000, and shall be clocked once per processed bit. The LFSR is not preset between time division multiplexed allocations that may reside within a single burst. Only source bits are randomized. This includes source payloads, plus uncoded null (zero) bits that may be used to fill empty payload segments. Elements that are not a part of the source data, such as framing elements and pilot symbols shall not be randomized. Null (zero) bits used to complete a QAM symbol (when an allocation does not fill an entire QAM symbol) shall not be randomized.
Block Interleaver
Support of interleaving between the inner and outer code with a depth of NR = 10 is mandatory. Interleaving shall not be defined in the FCH burst profile. When interleaving is used, its usage and parameters shall be specified within a burst profile. The interleaver changes the order of bytes from the ReedSolomon (RS) encoder output. A de-interleaver in the receiver restores the order of the bytes prior to RS decoding. The interleaver is a block interleaver, where a table is written, i.e., filled, a byte at a time row-wise (one row per RS code word) and read a byte at a time column-wise. The number of rows, NR, used by the interleaver is a burst parameter. So that bursts are not generated that exceed an intended receivers capabilities, the largest NR supported by a terminal is communicated during SS basic capability negotiation.
FEC
Adaptive modulation and the concatenated FEC shall be supported for all other payloads. Omitting the FEC and relying solely on ARQ for error control is optional for payloads carried outside the FCH.
RS CODE
ReedSolomon code shall be derived from a systematic RS (N = 255, K = 239) code using GF. The following polynomials are used for the systematic code: Code Generator Polynomial: Field Generator Polynomial: The bit/byte conversion shall be MSB first. This RS code may be shortened and punctured to enable variable block sizes and variable errorcorrection capability, where N is the number of overall bytes after encoding, K is the number of data bytes before encoding, R = N K is the number of parity bytes. When a block is shortened to K' data bytes, the first 239-K' data bytes of the block to be encoded shall be set to zero, but shall not be transmitted. When a codeword is punctured to R' parity bytes, only the first R' of the total R = 16 parity bytes shall be transmitted. Support of shortening K of the base code to values smaller than 239 bytes while maintaining R = 16 is mandatory, and is governed by the burst profile specification for K. The capability to also puncture, such that R 16, is mandatory, and is governed by the burst profile specification for R.
Encoding for rate 3/4 16-QAM

Figure 3 illustrates the rate 3/4 pragmatic TCM encoder for 16-QAM. This encoder uses the Base line rate 1/2 binary convolutional encoder, along with two systematic bits that are passed directly from the encoder input to the encoder output. With this structure, the encoder is capable of simultaneously generating four output bits per three input bits. The sequence of arrival for the u2u1u0 input into the encoder is u2 arrives first, u1 second, u0 last. During the encoding process, the encoder generates a two-bit constellation index, b3b2, for the I symbol coordinate, and simultaneously generates another two-bit constellation index, designated b1b0, for the Q symbol coordinate. Note that whole symbols shall be transmitted, so input records of lengths divisible by three shall be fed to this encoder.
Figure Pragmatic TCM encoder for rate 16QAM
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IFFT
Inverse Fast Fourier Transform is used for infinite number of inputs. N-1 X(t) = 1/N X(n) exp ( j*2**k/N ) n=0 We use DIT(Decimation In Time Domain) approach here. Main advantage of IFFT is satisfying symmetry and periodicity property. Here Addition and multiplication are not complicated, compared to DFT and vice versa for receiver module.
III Receiver Block Diagram:

The reverse process of transmitter module is receiver module shown in below figure
FROMRFSECTION CYCLIC PREFIX REMOVAL FFT PILOT REMOVAL DEMODULATOR (QAM)
To draw trellis diagram, refer the above table. Write the all possible present state buffers (C D), then next state (C D). Now refer the above table, for zero input and the buffer values are 00 (C D) respective next state is 00 (C D). So draw a straight line from 00 of present state to 00 of next state, and above the straight line write the output value (A B) in bracket. As like the same for one input, but the line is dotted line. State Table:
DATA OUTPUT DATA DEWHITENER BITS
FEC DECODER (RS&VITERBI)
BURST ERROR DETECTOR
Figure 4 Receiver block diagram IV VITERBI DECODING EXPLANATION CONVOLUTION ENCODER BLOCK DIAGRAM:
To write the state table, refer the trellis diagram. If you see the second next state, the 00 is from 00 and 01 of the previous sate. So we can divide into two states. Write 00 in state 0 and 01 in state 1 and write the respective output (values with in bracket of the straight and dotted line) in value 0 and value 1. As like the same write for 01, 10, 11. Now the required value that is state 0 and 1, Value 0 and 1 are generated. We have to get the convolution encoder output. For that, take an example of 1010. Now give this as an input to the convolution encoder.
Now we are going to calculate the viterbi decoding process. Take the first 2 bits and do bitwise Xor with all the value 0 and value 1 binary values (see state table). And convert to decimal equivalent of Xored output. The adding value is zero for first row of value 0 and 1. Except the first row, all other row
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0 or state 1. Note: The above example is shown for only two sate buffer of convolution encoder. If its three state (000 to 111 at present state) or 6 state (000000 to 111111 at present state) buffer convolution encoder. Have to generate state 0, state 1, value 0 and value 1 for all possible of buffer and input values.
calculation of equivalent decimal values should be added with the previous minimum distance values according to the state value of the respective binary combination of value 0 or 1. The values are color of red is called as adding values which are taken from the previous min distance. FINAL CALCULATION: Xor gives Bit wise Xor, Green gives inputs to the viterbi decoder (2 bits each), Pink gives Values from value 0 and value 1 of state table, Red gives Adding value from previous minimum distance.
V CONCLUSION In this thesis, transceiver module of Wimax has been surveyed based on its data rate including various research papers. It is expected that WiMax becomes the dominant standard for Wireless MAN in the world market, at least, in fixed broadband networks. WiMax products will have to be delivered to the market needs and those for the end-users will have to be extremely easy to install. Focus is too often on technologies that Subscribers pay for services, not technologies. Technologies enable services, but should not be a burden on users. Broadband capabilities are important, but bandwidth is not the only meter to assess service. 250Mbps data rate is achieved in this thesis. VI REFERENCE [1] IEEE Standard for Local and metropolitan area networks Part 16:(2009), Air Interface for Broadband Wireless Access Systems Amendment 1: Multiple Relay Specification [2] IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Broadband Wireless Access Systems [3] IEEE Standard for Local and Metropolitan Area Networks Media Access Control (MAC) Bridges Amendment 5: Bridging of IEEE 802.16 [4] IEEE Standard for Conformance to IEEE 802.16 Part 4:(2007) Protocol Implementation Conformance Statement (PICS) Proforma for Frequencies Below 11 GHz [5] IEEE Recommended Practice for Local and Metropolitan Area Networks. Coexistence of Fixed Broadband Wireless Access Systems (2004)
For the adding value in first row of above table. See the Xored value of value 0, its 00. So by referring the state table, the respective state value of 00 of value 0 is 00. So take the value of previous min distance at 00 position (0). And for 01, its 10 the value at that position is 0. For 11 00, 10 10. Same as for value. The calculate min distance, the min distance is nothing but the minimum value of value 0 and value 1. Then name it by four positions (00, 01, 10, and 11). To find the path take the min distance values respective state value. For example in the first row min distance 1 is from value 1. So the respective state value of 00 of value 0 is 00. So the path is 0. In the third row both are same so the path can be from state
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Digital Subtraction Angiography In Heart and Brain Diagnostics Using Labview

R.Naveeth Kumar #1 P.Hari Krishnan#2 M.E (Control And Instrumentation Engg) Department of Electrical and Electronics Engineering, Anna University of technology ,Coimbatore
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#1
naveeth1@gmail.com
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Lecturer, Department of Electrical and Electronics Engineering, Anna University of technology, Coimbatore, India. techniques such as arteriography.DSA images often show motion artifacts that may hamper proper diagnosis. In order to reduce these motion artifacts, the misalignment of the successive images in the sequence needs to be determined and corrected. This alignment operation is often referred to as image registration. Many semi- or even fully automatic registration techniques have been developed over the past two decades. The X-ray images taken may either be still images, displayed on a image intensifier or film, or motion images, the images are usually taken using a technique called DSA. Images in this case are usually taken at 2 - 3 frames per second, which allows the radiologist to evaluate the flow of the blood through a vessel or vessels. This technique "subtracts" the bones and other organs so only the vessels filled with contrast agent can be seen. Cerebral angiography is a form of angiography which provides images of blood vessels in and around the brain, thereby allowing detection of abnormalities such as arteriovenous malformations and aneurysms.Typically a catheter is inserted into a large artery (such as the femoral artery) and threaded through the circulatory system to the carotid artery, where a contrast agent is injected. A series of radiographs is taken as the contrast agent spreads through the brain's arterial system, then a second series as it reaches the venous system. For some applications this method may yield better images than less invasive methods such as computed tomography angiography and magnetic resonance angiography.In addition, cerebral angiography allows certain treatments to be performed immediately, based on the its findings. If, for example, the images reveal an aneurysm, metal coils may be introduced through the catheter already in place and maneuvered to the site of aneurysm; over time these coils encourage formation of connective tissue at the site, strengthening the vessel walls. In some jurisdictions,
AbstractDigital subtraction angiography (DSA) is a new computer assisted-process which enables visualization of cerebral and artery structures after intravenous injection of contrast material. For timeresolved background-subtracted contrast-enhanced magnetic resonance angiography, the bright and the spare cerebral signal allows unique identification of contrast bolus arrival in the cerebellum. This represents an automatic filtering algorithm using such cerebral characterization for selecting cerebral and artery phase images and mask images to generate an optimal summary cerebral angiogram. Thus, the exact image cannot be obtained using only the phase images and hence the comparison of mask image with the phase image produces the subtracted angiographic images. A control action is determined to eliminate a discrepancy, if any, between the predicted position and the measured position of the bolus. Thus the relative position of the imaging device and the biological structure is adaptively adjusted according to the control action to chase the motion of the bolus. This is implemented using Image processing techniques .
I.INTRODUCTION Digital subtraction angiography is a new, and rapidly developing, technology in the field of diagnostic radiology. DSA is one of several computer-assisted radiologic tools for diagnosing conditions associated with the internal structure of blood vessels.The technique usually involves injecting contrast medium into the veins and measuring over time the changing concentration of contrast medium passing through the vascular structures of interest.Through the use of a computer, the images before the contrast injection are subtracted from those after injection to give a numerical representation of the arterial structure under study. This relatively noninvasive technique can be performed on an outpatient basis with very low risk compared to conventional and (invasive)
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cerebral angiography is required to confirm brain death. The dye material is inserted in to the brain and the X-ray images are generated with a frame rate of 2 - 3 per second. If a brain aneurysm presses on nerves in your brain, it can cause signs and symptoms. Its due to some mismatches produce across the blood flow.
Temporal subtraction, familiar to radiologists,requires an image before administration of contrast (the mask) which is then subtracted from all subsequent post-contrast images. Assuming there has been no subject motion between the two images, complete cancellation of soft-tissue and bone is achieved with this method, leaving only the iodinated blood vessels. ii.
ENERGY SUBTRACTION
Energy subtraction techniques provide soft-tissue and bone cancellation based upon the differential attenuatin of tissues as a function of xray energy.Two alternate schemes have been evaluated for energy subtraction.The first, K-edge subtraction, uses two x-ray beams directly above and below the K absorption edge of Iodine (33 keV).If the xray beams are nearly monoenergetic, then a subtraction of images obtained with the two beams will remove all structures except the iodinated vessels. iii.
HYBRID SUBTRACTION
fig 1. Digital Subtraction Angiography Schematic II. METHODS OF SUBTRACTION
Visualization of blood vessels containing dilute amounts of Radiographic contrast media requires a means of subtracting the high contrast structures from the image. Once the high contrast structures have been cancelled, the subtraction image can be enhanced using display windowing techniques routinely employed for CT images. Without some form of subtraction, these contrast enhancement techniques are ineffective, because the high contrast objects, e.g., bone/soft-tissue and air/soft-tissue interfaces will obscure the lower contrast blood vessels containing dilute iodine.There are three parameters which can be used for soft-tissue and bone cancellation: i. Time (temporal subtraction) ii. Energy (energy subtraction) iii. Hybrid (hybrid subtraction) i.
TEMPORAL SUBTRACTION
A hybrid subtraction method to reduce the motion sensitivity of temporal subtraction for intravenous arteriography is described. Hybrid subtraction uses dual-energy scanned projection radiography to provide pre- and post-contrast images with the soft tissues subtracted. These pre- and postcontrast soft-tissue-cancelled images are then subtracted. Because involuntary motion (such as swallowing or bowel peristalsis) often affects soft tissues primarily, this hybrid technique provides better visualization of carotid and abdominal arteries than temporal or dual-energy subtraction alone.
III. DIGITAL SUBTRACTION PROCESS IN IMAGE PROCESSING
i.
Image acquisition
It is the first process, it is nothing but the capturing of the image and it gives the hints regarding the origin of digital images. Generally, the image acquisition stage involves preprocessing, such as scaling, sampling and quantization. ii. Image enhancement It is among the simplest and most appealing areas of digital image processing. Basically, the idea behind enhancement techniques is to bring out detail that is obscured, or simply to highlight certain features of interest in an image. A familiar example of enhancement is when we increase the contrast of an image
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because it looks better. It is important to keep in mind that enhancement is a very subjective area of image processing
processes that output images to processes that output image attributes vii. Segmentation Procedures partition an image into its constituent parts or objects. In general, autonomous segmentation is one of the most difficult tasks in digital image processing. Almost always follow the output of a segmentation stage, which usually is raw pixel data. IV DSA METHODOLOGY
i. DIGITIZATION PROCESS
iii.
Fig 3. Artery Sample Image Image restoration
Converting an analog image into a numerical representation suitable for input into digital computer. Digitization includes two process,ADC- analog to digital converter . DAC- digital to analog converter .
It is an area that also deals with improving the appearance of an image. However, unlike enhancement, which is subjective, image restoration is objective, in the sense that restoration techniques tend to be based on mathematical or probabilistic models of image degradation. Based on human subjective preferences regarding what constitutes a good enhancement result. iv. Color image processing It is an area that has been gaining in importance because of the significant increase in the use of digital images over the Internet. Color is used as the basis for extracting features of interest in an image. v. Wavelets The foundation for representing images in various degrees of resolution. In particular, this material is used in for image data compression and for pyramidal representation, in which images are subdivided successively into smaller regions. vi. Compression The name implies, deals with techniques for reducing the storage required saving an image, or the bandwidth required transmitting it. Although storage technology has improved significantly over the past decade, the same cannot be said for transmission capacity. It deals with tools for extracting image components that are useful in the representation and description of shape. The material in this begins a transition from
Fig 4. Digital Subtraction Process ii. SUBTRACTION PROCESS
Comparison of the digitized phase image with mask image is subtraction. Finally the subtracted binary image is converted into grayscale image.
V IMPLEMENTATION IN LABVIEW
LabVIEW (short for Laboratory Virtual Instrumentation Engineering Workbench) is a platform and development environment for a visual programming language from National Instruments. The graphical language is named "G". Originally released for the Apple Macintosh in 1986, LabVIEW is commonly used for data acquisition, instrument control, and industrial automation on a variety of platforms including Microsoft Windows, various flavors of UNIX, Linux, and Mac OS X. The latest version of LabVIEW is version LabVIEW 2010.
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DIGITIZATION PROCESS
IMAQ Vision for LabVIEW is a library of LabVIEW VIs that you can use to develop machine vision and scientific imaging applications.National Instruments also offers IMAQ Vision for Measurement Studio,which includes the same imaging functions for LabWindows/CVI and other C development environments and includes ActiveX controls for Visual Basic. Vision Assistant, another software product from NI, allows you to prototype your application strategy quickly without having to do any programming. Additionally, NI offers Vision Builder for Automated Inspection, configurable machine vision software that you can use to prototype, benchmark, and deploy applications.
VI. RESULTS AND DISCUSSION VII. CONCLUSION
BEFORE SUBTRACTION PROCESS
In this system using the automatic filtering algorithm methodology is implemented, the DSA technique is used to find the abnormalities and thickness , fractures and diseases in blood vessels.In this system, the DSA subtraction algorithm methodology is implemented,the thickness of the blood vessels is in ongoing process,The medical imaging techniques plays an important role in Biomedical Engineering.The angiography techniques is used in all parts of the body.The simulation can be done through vision utilities in Labview. REFERENCES
1.Macovski A: Iodine imaging using spectralanalysis. 2. Houk TL, Kruger RA, Mistretta CA et al:Real-time digital K-edge subtraction fluoroscopy.
AFTER SUBTRACTION PROCESS
3. Brody WR, Butt G, Hall A, and Macovski A: A method for selective tissue and bone visualization . 4.Introduction to labview IMAQ Manual. 5. Brody WR: Hybrid subtraction for improved intravenous arteriography. Radiol (in press). 6. Macovski A, Brody WR, Lehmann L, et al Future trends in projection radiography. 7. A. K. Wakhloo, F. Schellhammer, J. de Vries, J. Haberstroh, and M.Schumacher, Self-expanding and balloon-expandable stents in the treatment of carotid aneurysms 8. Mayfield angiography clinical and research in Cerebral
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ENHANCEMENT OF OPTIC CUP TO DISC RATIO DETECTION IN GLAUCOMA DIAGNOSIS

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D. Sasirekha1, A. Murthi2 PG Student, Associate Professor, Department of Electrical Engineering, Government college of Engineering, Salem- 11 E- mail: rekhasasi123@gmail.com
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Abstract: Glaucoma is a major global cause of

blindness. An approach to automatically extract the main features in color fundus images are proposed in this paper. The optic cup to disc ratio (CDR) in retinal fundus images is one of the principle physiological characteristics in the diagnosis of glaucoma. The least square fitting algorithm aims to improve the accuracy of the boundary estimation. The technique used here is a core component of ARGALI (Automatic cup-to-disc Ratio measurement system for Glaucoma detection and AnaLysIs), a system for automated glaucoma risk assessment. The algorithms effectiveness is demonstrated manually on segmented retina fundus images. By comparing the automatic cup height measurement to ground truth, we found that the method accurately detected neuro-retinal cup height. This work improves the efficiency of clinical interpretation of Glaucoma in fundus images of the eye. The tool utilized to accomplish the objective is MATLAB7.5
and will affect 60 million people by 2010 [4]. The ailment is physiologically described as the degeneration of optic nerve cells, and is characterized by changes in the optic nerve head and visual field. Although Glaucomatous damage is irreversible, early detection and subsequent medical intervention by ophthalmologists is effective in slowing the progression of the disease. Figure 1 illustrates the optic nerve change along the three stages of glaucoma development. In the early stage of glaucoma, optic nerve damage starts without incurring any symptom, patients are not aware of the disease until advanced stage which is associated with total blindness. The damage caused is irreversible, but treatment can prevent progression of the disease if detected in the early stage. Thus, early detection of glaucoma is crucial.
I. INTRODUCTION
Glaucoma is a group of diseases that can damage the eyes optic nerve and result in vision loss and permanent blindness. Some of the alarming facts about glaucoma are (1) Glaucoma is the leading cause of blindness (2) There is no cure for glaucoma, with medication it is possible to halt further loss of vision (3) Everyone is at risk from babies to senior citizens[1]. According to World Health Organization, glaucoma is the second leading cause of blindness; it is responsible for approximately 5.2 million cases of blindness (15% of the total burden of world blindness) [3]
(a) Normal optic nerve (b) early glaucoma (c) Advanced glaucoma
Figure1. Stages of progressive cupping in neuro- retinal optic disc and cup area for glaucoma patient. a. Normal Stage, without any nerve damage, b. Early Stage, nerve damage starts with no vision loss, normal or high intra- ocular pressure. c. Advanced Stage, visual loss occurred.
Clinically, the diagnosis of Glaucoma can be done through measurement of CDR [2], defined as the ratio of the vertical height of the optic cup to the vertical height of
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computational cost as well as improve segmentation accuracy.
the optic disc. An increment in the cupping of ONH corresponds to increased ganglion cell death and hence CDR can be used to measure the probability of developing the disease. A CDR value that is greater than 0.65 indicates high glaucoma risk [5]. ONH assessment is manually performed by a trained specialist or using specialized and expensive equipment such as the Heidelberg Retinal Tomography (HRT) system. Thus, there remains a lack of cost effective, sensitive and precise method to screen for glaucoma. Previously, many methods have been reported for optic disc detection [6, 7], but significantly fewer methods have been presented for optic cup detection, which is much more challenging due to the reduced visibility of the optic cup within the optic disc and the high density of vascular architecture traversing the optic cup boundary. One of the earliest reported methods was based on the discriminatory analysis of color intensity [8]. Later, in [9], pixels within the retinal image were classified based on pixel features generated from stereo color retinal images. Variational level set based on pixel intensity was used to globally optimize the obtained cup contour in [10].
In this study, we aim to find an optimized solution for optic cup detection. We presented and evaluated several segmentation and boundary detection methods. A fused approach based on multimodalities including level set segmentation, convex hull and ellipse fitting boundary is proposed. Convex hull [11] is the smallest region enclosing a specified group of points. The ellipse fitting algorithm is developed to better estimate the neuro-retinal optic cup boundary. The promising result will yield a large scale clinical trial in near future. Figure2. Shows the simplified work flow of computed aided
glaucoma diagnosis through CDR measurement.
II. METHODOLOGY
A. ROI determination In order to extract the optic disc and cup, a region of interest around the optic disc must first be delineated, as the optic disc generally occupies less than 5% of the pixels in a typical retinal fundus image. While the disc and cup extraction can be performed on the entire image, localizing the ROI would help to reduce the The optic disc region is usually of a brighter pallor or higher color intensity than the surrounding retinal area. This characteristic is exploited through automatically selecting 0.5% of the pixels in the image with the highest intensity. Next, the retinal image is subdivided into 64 regions, and an approximate ROI centre is selected based on the region containing the highest number of preselected pixels. Following this, the ROI is defined as a rectangle around the ROI centre with dimensions of twice the typical optic disc diameter, and is used as the
416 E. Optic Cup Smoothing

After the cup boundary has been detected, ellipse fitting is again employed to eliminate some of the cup boundarys sudden changes in curvature. Ellipse fitting becomes especially useful when portions of the blood vessels in the neuro-retinal rim outside the cup are included with in the detected boundary. The CDR is consequentially obtained based on the height of detected cup and disc.
initial boundary for the optic disc segmentation, as shown in Figure 3.
F. Ellipse Optimization for optic disc and cup

Ellipse fitting algorithm can be used to smooth the disc and cup boundary. Ellipse fitting is usually based on least square fitting algorithm which assumes that the best-fit curve of a given type is the curve that has the minimal sum of the deviations squared from a given data points (least square error).
Figure3. Retinal fundus image with the defined ROI in the outlined rectangle
B. Optic Disc Segmentation To calculate the vertical cup to disc ratio, the optic cup and disc first have to be segmented from the retinal images. The optic disc extraction is straight forward and various approaches have been previously proposed for segmentation of the disc. In this paper, the disc boundary is detected using optimal color channel as determined by the color histogram analysis and edge analysis.
Direct Least Square Fitting Algorithm is chosen to fit the optic and cup over other popular ellipse fitting algorithms like Bookstein Algorithm, Taubin Algorithm. Instead of fitting general conics or being computationally expensive, this algorithm minimizes the algebraic distance subject to a constraint, and incorporates the ellipticity constraint into the normalization factor. It is ellipsespecific, thus the effect of noise (ocular blood vessel, C. Optic Disc Smoothing hemorrhage, drusens, etc.) around the cup area can be The disc boundary detected from the above step may not minimized while forming the ellipse. It can also be easily represent the actual shape of the disc since the boundary can solved naturally by a generalized Eigen system. be affected by a large number of blood vessels entering the In Fitting algorithm, a quadratic constraint is set on disc. Therefore, ellipse fitting is performed to reshape the the parameters to avoid trivial and unwanted solutions. obtained disc boundary. The goal is to search a vector parameter which contains the six coefficients of the standard form of a conic. D. Optic Cup Segmentation Compared to the extraction of the optic disc, cup segmentation provides an even greater challenge, as the cup-disc boundary is usually less pronounced than that of the disk region and is further compounded the increased visibility of blood vessels across the cup-disc boundary. To extract the cup from the optic disc, more robust image processing techniques are normally used to segment the cup An ellipse is a special case of a general conic which can be described by an implicit second order polynomial =0(1) with an ellipse specific constraint (2)
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applying the Lagrange multipliers we get the following conditions for the optimal solution a (3) (8)
Where a, b, c, d, e, f are coefficients of the ellipse and (x, y) are coordinates of points lying on it. The polynomial F(x, y) is called the algebraic distance of the point (x, y) to the given conic. By introducing vectors
where S is the scatter matrix of the size 66, (9)
it can be rewritten to the vector form Fa(x) = x.a = 0 (4)
in which the operator S denotes the sum
The fitting of a general conic to a set of points may be approached by minimizing the sum of squared algebraic distances of the points to the conic which is represented by coefficient a:
(10)
Next, the Eq. (8) is solved by using generalized Eigen vectors. There exist up to six real solutions, but by considering the minimization ||Da||2 subjected to the constraint (6) would yield only one solution, which corresponds by virtue of constraint, to an ellipse. G. Convex hull based Ellipse Optimization A convex hull of a set of points is the smallest convex polygon that contains every one of the points. It is defined by a subset of all the points in the original set. The convex hull of X can be described constructively as the set of convex combinations of finite subsets of points from X: that is, the set of points of the form, where n is an arbitrary natural number, the numbers tj are non-negative and sum to 1, and the points Xj are in X. It is simple to check that this set satisfies either of the two definitions above. So the convex hull Hconvex(X) of set X is:
(5)
The problem Eq.(5)can be solved by the standard least squares approach, but the result of such fitting is a general conic and it need not to be an ellipse To ensure an ellipse specificity of the solution, the appropriate constraints Eq. (2) has to be considered. Under a proper scaling, the inequality constraint in Eq. (2) can be changed in to an equality constraint fitting problem (6) can be
and the ellipse-specific reformulated as subjectto
(7)
where the design matrix D of the size N6, represents the least squares minimization of Eq. (5) and the constraint matrix C of the size 66, express the constraint of Eq.(6).the minimization problem of Eq.(7) is ready to be solved by a quadratically. First, by
If X is a subset of an N-dimensional vector space, convex combinations of at most N+1 point are sufficient in the definition above. This is equivalent to saying that the convex hull of X is the union of all simplexes with at most N+1 vertex from X.
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are calculated. It is observed that the spread of CDR errors with respect to clinical values is more spaced out for ARGALI while those based on the new algorithm cluster around the 'zero error line'. Figure 5 compares CDR result from both ARGALI and our new approach against ground truth CDR. The risk of glaucoma is accessed based on CDR value; clinically a CDR greater than 0.65 indicates glaucoma. From the plot, it is observed that, ARGALI tends to under estimate the CDR value which cause more false negative, our new algorithm doubles the chances of correct diagnosis.
In this paper, proposed a direct least square fitting ellipse optimization for optical cup detection. Figure 4 shows how convex hull was applied in our system in selecting feature points around the neuro-retina cup region. The pixel set obtained from level set method for cup region were usually segmented with the influence of the interweavement of surrounding ocular blood vessels, hemorrhages, drusens and other noises. If all those pixels were fed to ellipse fitting algorithm, they could yield an unreal cup boundary. Using feature points selected from the pixel set using convex hull to fit the ellipse cup the system could generate more realistic neuro-retinal cup.
Figure4. Ellipse fitted Optic Disc and Cup
Figure5. Detection of Glaucoma using ARGALI and new algorithm.
H. Image Analysis
To evaluate the performance of our approach, the neuro- retinal images are obtained from Singapore eye research institute. The cup to Disc ratio for each neuroretinal image was provided by the ophthalmologist using stereographic viewers and images were set as ground truth against which the performance of our proposed method was evaluated. I.
III. CONCLUSION This thesis presented and evaluated several segmentation and boundary detection methods for a more accurate estimation of neuro-retinal optic cup. A fused approach based on multimodalities including level set segmentation, convex hull and ellipse fitting boundary smoothing is proposed. Comparing with the ARGALI system, the new approach achieves a better CDR value calculation, which results to more accurate Glaucoma Diagnosis. The good performance of the new approach leads to a large scale clinical evaluation involving 15 thousand patients from Australia and Singapore and will be able to report large clinical findings in the future.
Glaucoma Diagnosis
The performance of a CDR based glaucoma diagnosis system is largely dependent on how accurate a CDR is measured. The error ranges of our new fusion algorithm and ARGALI approach are measured in the experiment. It is found that the error range of fitting algorithm is smaller. To compare the spread of the errors for the ARGALI and our new method, standard deviations for the approaches
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T. Kurihara, "Development of a simple diagnostic method for the glaucoma using ocular Fundus pictures," 27th Annual International Conference of the, Engineering in Medicine and Biology Society, 2005.
2. J. Dammas and F. Dannheim, sensitivity and

specificity of optic disc parameters in chronic glaucoma, Invest ophth Vis Sci, vol.34.pp.22462250, jun1993
3. Thylefors. B and Negrel, the global impact of

glaucoma, Bull world health organ, 72(3) :p3 23 .6 .1994
9. M. D. Abramoff, W. L. M. Alward, E. C. Greenlee,

L. Shuba, C. Y. Kim, J. H. Fingert, and Y. H. Kwon, "Automated Segmentation of the Optic Disc from Stereo Color Photographs Using Physiologically Plausible Features," Investigative Ophthalmology and Visual Science, vol. 48, pp. 1665, 2007.
4. Quigley. H. A and A. T. Broman, The number of

people with glaucoma worldwide in 2010 and 2020 Br. J. Ophthalmol 2006, 90(3):p.262-7
5. Singapore
MOH Glaucoma Clinical Practice Guideline http: //www. moh.gov. sg/ mohcorp / publications.aspx?id=16320)
10. J. Liu, D.W.K. Wong, J.H. Lim, H. Li, N.M. Tan,

Z.Zhang, T. Y Wong, R. Lavanya, "ARGALI: An Automatic Cup-To-Disc Ratio Measurement System For Glaucoma Analysis Using Level-Set Image Processing", 13 International Conference on Biomedical Engineering (ICBME2008), 2008.
6. J. Xu, O. Chutatape, E. Sung, C. Zheng, P. C. T.

Kuan. "Optic disk feature extraction via modified deformable model technique for glaucoma analysis". Pattern Recognition 40 (2007) 2063-2076, 2006.
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automated feature extraction in fundus images". In Proc. Of the 9th IEEE International Conference on Computer Vision, 2003.
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A Low Power Double-Edge Triggered Direct Data Clocked Pair Shared Flip-Flop
B.Kousalya M.E Second year, Applied Electronics, kousmail@rediffmail.com,+91-99765 44590 Guided by Mr.A.Nandhakumar, Assistant Professor, Department of Electrical and Electronics Engineering Dr.Mahalingam College of Engg & Tech., Pollachi-642 003
Abstract- In integrated circuit, power consumption is a one of the top three challenges like area, power and speed. In practice, a large portion of the on chip power is consumed by the clocking system which consists of clock distribution network and flop-flops. Various design techniques for a low power clocking system are surveyed. One of the effective methods to reduce the power consumption is double edge triggering. To this approach, we propose a novel low power flip flop with less power consumption than other flip flips. Index Terms-Flip-flop, low power, double edge triggering I.INTRODUCTION In current scenario the requirement of portable equipment is increasing rapidly like Pocket calculators, Hearing aids, Implantable pacemakers and cardiac defibrillators, Portable military equipment for individual soldiers, Wristwatches, Wireless computing etc. In order to achieve the portability we go for System-on-chip design (SoC). System-on-chip technology is the ability to place multiple function "systems" on a single silicon chip like processor, bus and other elements on a single monolithic substrate. It is integrating hundreds of millions of transistors on one chip. If density of chip goes on increasing means heat will be dissipated due to the high power consumption where packaging and cooling only have a limited ability to remove the excess heat. If we are reducing the interior power in integrated chip means the sophisticated cooling system and high cost battery requirement is reduced linearly.There is a wide selection of flip-flops in the literature [1][18]. Many contemporary microprocessors selectively use master-slave and pulsed-triggered
flip-flops [1]. Energy recovery clocked flip flops SCCER, SDER, CCER [2], used in the pipelined multipliers. Pulse triggered flip-flops could be classified into two types, implicit-pulsed and explicit-pulsed, for example, the implicit pulsetriggered data-close-to-output flip-flops (ipDCO) [3] and the explicit pulse-triggered dataclose-to-output flip-flops (ep-DCO) [3].This paper surveys various low power techniques for the clocking system in Section II. The existing flip flop CPSFF is discussed in Section III. After that we elaborate on the proposed DDCPSFF and DET-DDCPSFF in Section IV and V, then Section VI deals with the simulation result with comparison. Section VII concludes this paper. II. SURVEY OF LOW POWER DESIGN OF A CLOCKING SYSTEM There are three source of power dissipation in digital complementary metal-oxidesemiconductor (CMOS) circuit. That is static power dissipation, dynamic power dissipation and short circuit power dissipation. Dynamic and short circuit power dissipation fall under the category of Transient Power Dissipation. Static power dissipation is due to leakage currents. Power consumption is determined by several factors including frequency f supply voltage V, data activity , capacitance C, leakage and short circuit current. So the total power dissipation in CMOS circuit is expressed as [4], P=Pdyamic + Pshort circuit + Pleakage. (1)
The equation shows the total power is equal to sum of dynamic power, short circuit power and leakage power. There are various ways to lower the power consumption shown as follows.
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b) Clock Gating. When a certain block is idle, we can disable the clock signal to that block to save power. Gated master slave flip-flop was proposed in [14]. Both conditional operation and clock gating methods reduce power by decreasing switching activity. III. CLOCKED PAIR SHARED FLIP FLOP CDFF and CCFF use many clocked transistors. CDMFF[4] reduces the number of clocked transistors but it has redundant clocking as well as a floating node. To ensure efficient and robust implementation of low power sequential element, we propose Clocked Pair Shared flipflop (CPSFF[4], Fig. 1) to use less clocked transistor than CDMFF and to overcome the floating problem in CDMFF[4]. In the clocked-pair-shared flip-flop, clocked pair (N3, N4) is shared by first and second stage. An always on pMOS, P1, is used to charge the internal node X rather than using the two clocked pre charging transistors (P1, P2) in CDMFF. Comparing with CDMFF, a total of three clocked transistors are reduced, such that the clock load seen by the clock driver is decreased, resulting in an efficient design. Further the transistor N7 in the clocked inverter in CDMFF is removed. CPSFF[4] uses four clocked transistors rather than seven clocked transistors in CDMFF, resulting in approximately 40% reduction in number of clocked transistors. Furthermore the internal node X is connected to Vdd by an always on P1, so X is not floating, resulting in enhancement of noise robustness of node X. This solves the floating point problem in CDMFF. The always ON P1 is a weak pMOS transistor (length =3). This scheme combines pseudo nMOS [15] with a conditional mapping technique [16] where a feedback signals, comp, controls nMOS N1. When input D stays 1, Q=1, N5 is on, N1 will shut off to avoid the redundant switching activity at node X as well as any short circuit current. pMOS P2 should pull Q up when D transits to 1. The second nMOS branch (N2) is responsible for pulling down the output of Q if D=0 and Y=1 when the clock pulse arrives. pMOS in I1 should turn on Nmos N2 when D=0 .
1) Using a low swing voltage on the clock distribution network can reduce the clocking power consumption since power is a quadratic function of voltage. To use low swing clock distribution, the flip-flop should be a low swing flip- flop. For example, low swing double-edge flip-flop (LSDFF) [5] is a low swing flip-flop. In addition, the level converter flip-flop is a natural candidate to be used in low swing environment too. For example, CD-LCFF-ip [6], could be used as a low swing flip-flop since incoming signals only drive nMOS transistors. The low swing method reduces the power consumption by decreasing voltage in equation. 2) Using Dual Vt/MTCMOS to reduce the leakage power in standby mode. With shrinking feature size, the leakage current increases rapidly, the MTMOS technique [7] as well as transistor stacking, dynamic body biasing, and supply voltage ramping could be used to reduce leakage standby power consumption [8]. A data retention flip-flop is proposed in [9]. 3) Reducing Short Current Power: split path can reduce the short current power, since pMOS and nMOS are driven by separate signals. 4) There are two ways to reduce the switching activity: conditional operation (eliminate redundant data switching: conditional discharge flip-flop (CDFF) [10], conditional capture flip-flop (CCFF) [11]) or clock gating. a) Conditional Operation. For dynamic flip-flops, like hybrid latch flipflop (HLFF)[12], semidynamic flip-flop (SDFF) [13], there are redundant switching activities in the internal node. When input stays at logic one, the internal node is kept charging and discharging without performing any useful computation. The conditional operation technique is needed to control the redundant switching. For example, in CDFF, a feedback transistor is inserted on the discharging path of 1st stage which will turn off the discharging path when D keeps 1. Internal node will not be kept discharging at every clock cycle. In CCFF, it uses a clocked NOR gate to control an nMOS transistor in discharging path when Q keeps 1. The redundant keeps 1. The redundant switching activity is removed in both cases. This reduces the power consumption by decreasing data activity in the equation.
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data input D directly with elimination of input transmission gates and N5 to achieve the same operation. The DDCPSFF as shown in Fig.2.
Fig.1. Clocked Pair Shared flip-flop. Although P1 is always ON, short circuit only occurs one time when D makes a transition of 01, and the discharge path is disconnected after two gates delay by comp (turning off N1). After that, if D remains at 1, the discharge path is already disconnected by N1; there would be no short circuit. The clocked-pseudo-nMOS scheme is different from the general idea of conventional pseudo-nMOS logic in that we use clocked transistors in the pull down branch. P1, N1, N3, and N4 should be properly sized to ensure a correct noise margin [17]. Several low power techniques in Section II can be easily incorporated into the new flip-flop. Unlike CDMFF, low swing is possible for CPSFF since incoming low voltage clock does not drive pMOS transistors. Low swing voltage clock signals could be connected to the nMOS transistors N3 and N4, respectively. In our next section we will see modified version of CPSFF and CPSFF with double edge triggering. IV. PROPOSED DIRECT DATA CLOCKED PAIR SHARED FLIP FLOP (DDCPSFF) In above CPSFF, the Q output is mainly depends on the previous output only. When D=1,Q should be 0initially. That time the N5 is idle. When D=0,Q should be 1 initially. That time the input transmission gate is idle. Due to the noise coupling at node Q during transitions, the input transmission gate and N5 will not take correct gate input. In order to avoid this we fed the
Fig.2.Direct Data CPSFF The inverter at the output I2 and I4 also eliminated. There is no need of Q and Q_kpr feedback signals from output for this structure. When CLK and CLKDB is 1 and D=1, transistors N1, N3, N4 is switched on, P1 and N2 is switched off. Then node X will be 0. So P2 is ON,Q will be 1,when D=0,N1 is OFF, N2 is ON, P2 is OFF. The previous Q output will be discharged through N2, N3, and N4. Then Q=0. V. PROPOSED DOUBLE EDGE TRIGGERING DIRECT DATA CLOCKED PAIR SHARED FLIP FLOP (DET-DDCPSFF) The proposed flip-flop has several advantages over the conventional flip-flops. First of all, the flip-flop is triggered at both edges of the clock. We efficiently implemented dual edgetriggering operation using the pulse generator that generates a brief pulse at both clock edges as shown in Fig.3. With this design, the opposite clock edge is no longer wasted and can be used for capturing a valid input data. Thus, clock frequency can be cut in half while preserving the rate of data processing. Using lower clock frequency translates into considerable power savings for the
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That is when D is 01 transition the left hand side of the pull down network is responsible for Q output When D is 10 transition the right hand side of the pull down network is responsible for Q output.
clocked portions of the circuit as well as for the clock distribution network [18].
Fig.3. Dual pulse generator Scheme. Use of explicit pulse generator can provide some additional advantages. For example, the pulse generator may be local to each flip-flop or shared among multiple flip-flops. Then, because the entire flip-flop needs not to be duplicated, the power and area overheads can be much less than for the conventional flip-flops. Fig.5. Proposed DET-DDCPSFF. VI. SIMULATION RESULTS The simulation results were obtained from Microwind3.1.simulations in 180nm and 90nm technology. An inverter is placed after output Q, providing protection from direct noise coupling [3]. The value of the capacitance load at node Qb is 100 fF. The simulation environment is, for 180nm Vdd = 2v,clock frequency is 250Mhz(single edge triggering),clock frequency is 125Mhz(Double edge triggering),for 90nm Vdd=1v,clock frequency is 1Ghz(single edge triggering),clock frequency is 0.5Ghz(Double edge triggering). Circuits were optimized for power delay product (PDP). Delay is data to output delay (Dto-Q delay) which is the sum of the setup time and the clock to the output delay. The D-to-Q delay [20], [21] is obtained by sweeping the 0 1 and 1 0 data transition times with respect to the clock edge and the minimum data-tooutput delay corresponding to optimum set up time is recorded. Table I shows a comparison of proposed flipflop (shaded) with other flip-flops characteristics in terms of delay, total power and PDP number of transistors, number of clocked transistors in
Fig.4. Double edge Clock pulse generator. Instead of applying clock signal we can apply the clock pulse to the flip flop in order to reduce the power consumption. The double edge clock pulse generator circuit is shown in Fig.4. The proposed DET-DDCPSFF as shown in Fig.5. In above DET-CPSFF, N3 and N4 switched ON when clock pulse arrived. If D=1, N1 is ON and N2 is OFF. So Vdd is grounded through the P1, N1, N3 and N4.then X=0,P2 is switched ON and Q=1.Similiarly for D=0, X=1,N1 and P2 is OFF and N2 is ON. Then Q output is discharged through N2, N3 and N4, Q=0.
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0.09m technology. Table II shows the comparisons of flip flops in 0.18 m technology. TABLE I COMPARISONS OF FLIP FLOP (0.09m) Design Name DDCPSFF DETDDCPSFF d-CDMFF s-CDMFF CDFF No. of Tr. 12 24 35 20 28 No.of Clocked Tr. 4 2 9 7 2 DQ delay (ps) 148 187 70 59 46 Power (w) 13.88 36.55 60.7 40.2 55.3 PDP (fJ) 2.0 6.8 4.2 2.3 2.5 (b) Fig.6. Simulation wave for DDCPSFF a) 0.09m b) 0.18 m
Design Name DDCPSFF DETDDCPSFF LSDFF CCFF HLFF
TABLE II COMPARISONS OF FLIP FLOP (0.18m) No. No.of DQ Power PDP of Clocke delay (w) (fJ) Tr. d Tr. (ps) 12 4 87 93.28 8.1 24 28 26 20 2 3 5 4 148 199 188 190 103 132 185 250 15.2 26.3 34.8 47.5 (a)
(b) Fig.7. Simulation wave form for DETDDCPSFF a) 0.09 m b) 0.18 m From the Table I, DDCPSFF improves overall power consumption over d-CDMFF about 77% and over s-CDMFF about 65%.DETDDCPSFF improves overall power consumption over CDFF[16] about 33%.
(a)
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REFERENCES [1] A. Chandrakasan, W. Bowhill, and F. Fox, Design of High -Performance Microprocessor Circuits, 1st ed. Piscataway, NJ: IEEE Press,2001. [2] H.Mahmoodi,V.Tirumalashetty,Matthew Cooke and Kaushik Roy,Ultra Low Power Clocking Scheme Using Energy recovery and Clock Gating flop, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17,no. 1, pp. 3344, January. 2009. [3] J. Tschanz, S. Narendra, Z. P. Chen, S. Borkar,M. Sachdev, and V. De,Comparative delay and energy of single edge-triggered & dual edgetriggered pulsed flip-flops for highperformance microprocessors, in Proc. ISPLED, Huntington Beach, CA, Aug. 2001, pp. 207212. [4] Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, and Zhongfeng Wang,Design of Sequential Elements for Low Power Clocking System, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published. [5] C. L. Kim and S. Kang, A low-swing clock double edge-triggered flip-flop, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 648 652,May 2002 [6] P.Zhao, J. McNeely, S.Venigalla,G. P.Kumar,M. Bayoumi, N.Wang, and L. Downey, Clocked-pseudo-NMOS flip-flops for level conversion in dual supply systems, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., to be published. [7] J.Tschanz, Y. Ye, L. Wei, V. Govindarajulu,N.Borkar, S. Burns, T. Karnik, S. Borkar, and V. De,Design optimizations of a high performance microprocessor using combinations of dualVt allocation and transistor sizing, in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, Jun.2002, pp. 218219. [8] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits.Englewood Cliffs, NJ: Prentice-Hall, 2003. [9] Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, A 1-V high-speed MTCMOS circuit scheme for power-down application circuits, IEEE J. Solid-State
From the Table II, DDCPSFF improves overall power consumption over CCFF about 49% and over HLFF about 62%.DET-DDCPSFF improves overall power consumption over LCDFF [5] about 21%.
(a)
(b) Fig.8. Comparison of flip-flops with power a) 0.09 m b) 0.18 m From fig.8.DDCPSFF and DET-DDCPSFF is less power consumption than other conventional flip flops. VII. CONCLUSION In this paper we presented a variety of low power technique in addition with double edge triggering. Following the approach we proposed two low power flip-flops like DDCPSFF and DET-DDCPSFF. The above proposed flip flops can be used for variety of application like, Ring counter, Shift register, Error detector, used as a low power delay buffers and level converters etc.
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[20] V. Stojanovic and V. Oklobdzija, Comparative analysis of master-slave latches and flip-flops for high-performance and low power system, IEEE J.SolidState Circuits, vol. 34, no. 4, pp. 536548, Apr. 1999. [21] N.Weste and D. Harris, CMOS VLSI Design. Reading, MA: Addison Wesley, 2004.
Circuits, vol. 32, no. 6, pp. 861869, Jun.1997. [10] P. Zhao, T. Darwish, and M. Bayoumi, High-performance and lowpower conditional discharge flip-flop, IEEE Trans. Very Large Scale Integr.(VLSI)Syst., vol. 12, no. 5, pp. 477484, May 2004. [11] B. Kong, S. Kim, and Y. Jun, Conditionalcapture flip-flop for statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8, pp.12631271, Aug. 2001. [12] H. Partovi, R. Burd, U. Salim, F.Weber,L.DiGregorio, and D.Draper, Flow-through latch and edge-triggered flip-flop hybrid elements, in ISSCC Dig., Feb. 1996, pp. 138139. [13] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R.Wang, A. Mehta,R. Heald, and G. Yee, Semi-dynamic and dynamic flipflops with embedded logic, in Symp. VLSI Circuits, Dig. Tech. Papers, Jun. 1998,pp. 108109. [14] D. Markovic, B. Nikolic, and R. Brodersen, Analysis and design of low-energy flipflops, in Proc. Int. Symp. Low Power Electron. Des., Huntington Beach, CA, Aug. 2001, pp. 5255. [15] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits.Englewood Cliffs, NJ: PrenticeHall, 2003. [16] C. K. Teh, M. Hamada, T. Fujita, H. Hara, N.Ikumi, and Y. Oowaki,Conditional data mapping flip-flops for low-power and highperformance systems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 14, no. 12, pp. 13791383, Dec. 2006. [17] D. A. Hodges, H. G. Jackson, and R. A. Saleh,Analysis and Design of Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2004. [18] Jae-Il Kim and Bai-Sun Kong Dual EdgeTriggered NAND-Keeper Flip-Flop for High-Performance VLSI Journal of semiconductor technology and science, Vol.3, No. 2, June, 2003 [19] Enomoto, T.; Higuchi, Y.; A Lowleakage Current Power 180-nm CMOS SRAM Design Automation Conference,2008.ASPDAC 2008.Asia and South Pacific. pp.101 102, April 2008.
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LOW POWER HIGH PERFORMANCE DUAL MATCH LINE FOR MOBILE DEVICES
Mrs.S.Umaiyal1 Mrs.S.Deepa2 1.Research Scholar in Embedded Systems Technologies. 2.Asst.Professor in Electrical & Electronics Engineering Vellalar College of Engineering & Technology,Erode. AbstractNetwork security for mobile devices is in high demand because of the increasing virus count. Since mobile devices have limited CPU power, dedicated hardware is essential to provide sufficient virus detection performance.A TCAMbased virus-detection unit provides high throughput, but also challenges for low power and low cost. In this paper, an dual-port BiTCAM (unifying binary and ternary CAMs) is proposed to achieve a high-throughput, low-power, and lowcost virus-detection processor for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dual-port dynamic AND gates. The dual-port designs reduce power consumption and increase storage efficiency due to shared storage spaces. In addition, the dividable BiTCAM provides high flexibility for regularly updating the virus-database. The BiTCAM achieves a 48% power reduction and a 40% transistor count reduction compared with the design using a conventional single-port TCAM.The implemented 0.13 m processor performs up to 3 Gbps virus detection with an energy consumption of 0.44 fJ/pattern-byte/scan at peak throughput. Index TermsAssociative memories, ClamAV, content-addressable memory, dual-port match line, high speed, low power, pattern matching, PFCDPD, pseudo-footless, Snort, virus detection. these designs are not suitable for mobile devices mainly because of two drawbacks. First, due to their hardware limitation, they are aimed at data matching with only a few thousands of network patterns in SNORT [7] (an open source network intrusion prevention system). They are also not scalable to perform any antivirus scanning, since the number of virus patterns is one order larger than SNORT. The ClamAV [8] (an open source antivirus software) releases more than 20,000 virus patterns and that number is still increasing.Second, these designs store all the virus patterns in the on-chip memory for achieving high throughput.When dealing with a large number of virus patterns, these designs need a large chip area and significant power due to the enlarged size of the on-chip memory. Hence, we can use CAM-based designs to achieve higher search speed. However, traditional CAM designs can not satisfy the other requirements, including low cost, low power, and high programmability, to realize a good SoC integration. Therefore we developed a virus-detection processor for mobile applications, wherein the key component is an adaptively dividable dual-port BiTCAM (unifying binary and ternary CAMs) [9]. The BiTCAM design achieves a 48% power reduction and a 40% transistor reduction, as compared to the design using two separate single-port TCAMs. The 0.13 m virus-detection processor embedded with a BiTCAM plus a low-cost external DRAM performs up to 3 Gbps virus detection for 30K ClamAV rules at an energy cost of only 0.44 fJ/pattern byte/scan at peak throughput. II. THE VIRUS-DETECTION PROCESSOR The design considerations for a virusdetection engine in mobile devices are analyzed as follows. 1) The system throughput should reach up to 1 Gbps for supporting real-time virus detection in mobile devices adopting 4G wireless systems. 2) The scalability of handling more than ten thousands patterns is required for versatile network protection. In addition, the system must be highly flexible to accommodate the rapidly increasing new virus patterns. 3) Power consumption is the most important design consideration for mobile devices.
I.INTRODUCTION
Content-addressable memory (CAM) can be used to simultaneously compare the input datum with all the data stored in the memory. Due to the parallel operations, the CAM is useful for applications that demand high data-search speed, such as data base access [1], image processing [2], and IP address lookup [3]. Network security systems require a great amount of pattern matching operations to compare the input network packet with the pre-defined rule set for protecting the system from network attacks such as worms and viruses. Recently, several papers proposedhardwarebasedpatternmatchingapproaches[4 ]-[6]forwire-linenetwork securitysystems. However,
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The increasing virus pattern will greatly increase the power consumption and the cost of onchip CAMs. The memory design is critical for dealing with the increasingly large virus database. The key idea of our proposed virus-detection processor is to condense as much information on-chip as possible such that most of input data can be quickly scanned without further inspection. The entire virus scanning is split into two phases: fast onchip filtering by the filtering engine, and the exactlymatching with some off-chip memory accesses, as shown in Fig. 1(b). Only important filtering signatures and skip data are stored on the chip. In order to reduce the onchip memory,the filtering engine operates only on the fixed amount of the memory, including a 16-KB TCAM and a 8.5-KB SRAM.These filtering data are extracted from the entire virus database by preprocessing the 30K virus patterns released from the ClamAV. The reprocessing tool also generates a suffix pattern tree, which will be stored in the offchip memory. Because most of the input data is safe,
experimental results show that more than 80% of the data can be quickly processed by the filtering engine. The filtering engine screens impossible matches by consulting two TCAM lookup tables (named noplane and yes-plane), which are used to perform two steps of the on-chip data-scanning in Fig. 1(c) and (d). By comparing the input datum with the no-plane TCAM from the least significant bit (LSB), the engine first looks up the shift table to perform a quick shift of impossible bytes until locating a possible match, as shown in Fig. 1(c). If the input datum is matched with an entry of no-plane, the input string will be skipped according to the shift count stored in the shift SRAM.When the comparison of no-plane is missed or if the corresponding shift-count is zero, the filtering engine will enter the second step of virus detection, as shown in Fig. 1(d). Then we further look up another signature table (called the yes-plane) to eliminate any false positives by ensuring that the prefix has the same signature.The filtering engine will skip the input datum if it is mismatched with the data of the yes-plane. If a possible match is still not
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ruled out, then the exactly-matching engine performs suffix matching by making comparisons with a suffix tree stored in off-chip memory, which can hold a large number of virus patterns. The off-chip memory needs roughly 8MB to store the entire2MB virus patterns of the ClamAV. In the proposed processor, the on-chip memory takes up over 75% of the overall power consumption and shares about 80% of the transistor count of the whole chip. Hence, compressing filtering data into the on-chip memory critically determines the performance and power efficiency for virus detection. In order to further reduce the power consumption and silicon cost of the on-chip memory, we propose an adaptively dividable dual-port BiTCAM to substitute the two separate TCAM tables, so as not only to enhance the storage utilization, but also to reduce thepower consumption of the TCAM. III. THE DUAL-PORT BITCAM-BASED MEMORY BLOCK A. The Evolution Fig. 2(a) shows the evolution from a conventional single-portTCAM to a dual-port TCAM.The left part of Fig. 2(a) illustrates a design example for realizing
the memory part of the virus detection processor. It includes two single-port TCAMs and two SRAMs. One TCAM serves as the no-plane look-up table (or the shift table) and the other as the yes-plane look-up table (or the signature table). Since tail dont care bits are unnecessary in reality,the prefix of the yesplane will be aligned to the left side of the TCAM array, and the TCAM entries in the yes-plane are sorted to form a triangle. Similarly, the no-plane TCAM forms another symmetrical triangle. The noplane is matched with the bits starting from the LSB and that the yes-plane is matched with the MSBs.The ternary cells storing not only waste hardware cost but also waste energy. Our idea is to merge these two single-port TCAMs into a single rectangular dualport TCAM and concurrently match with the whole prefix. To achieve this goal we need a dual-port TCAM and two SRAMs as shown in the right part of Fig. 2(a), with a division line inserted in the dual-port TCAM array to separate the no-plane entries and the yes-plane entries.With the proposed dual-port TCAM, the ternary cells storing terms can be minimized, and consequently both the total memory capacity and the power consumption are reduced.However, the partition of two CAM entries should not be fixed because the virus-detection application demands the flexibility of updating the
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contents of the look-up tables. To satisfy this design requirement, the division line should be adaptively adjusted according to different rule sets.Fig. 2(b) shows another design example Our analysis shows that a few leading bytes in the yes-plane contain no x bits. Therefore, the ternary cells for storing those leading bytes can be replaced by binary cells for further area and power reduction, since usually a binary cell is simpler than a ternary cell [12]. Thus, we name this new design a BiTCAM,since it combines binary and ternary cells.According to the characteristics of the virus patterns in ClamAV, we obtain some rules for constructing the CAMs contents. 1) The data width of the no-plane is at most 24 bits. 2) The data width of the yes-plane is between 8 and 32 bits, and the bit width of the binary data in the yes-plane is set to 8. 3) The number of entries in the no-plane is less than 2048.Therefore, the total bit width of those entries not used by the no-plane can be fully used to store data of the yes-plane. 4) If the summation of the bit width of the yes-plane and that of the no-plane is larger than 32 for a particular entry to be inserted into the CAM array, either the data for the yesplane or that for the noplane will be cut short, depending on which solution cause less sacrifice in the filtering rate.
B.The Complete Memory Block The complete memory block is shown in Fig.3. The memory block is divided into 4 memory banks. Each bank contains one 512 32b BiTCAM, one 512 2b shift SRAM, and one 512 32b signature SRAM. The yes-plane and no-plane triangles are located on the left and the right part of the BiTCAM bank,respectively. The two SRAMs and the BiTCAM share one address decoder for reducing the hardware cost. Owing to the circuit structure, the search operation of each match-line of the yes-plane goes from the left-most CAM cell to the right, and theoutputs from the right port of the BiTCAM should be used as the word-lines for the signature-SRAM. The match result of each match-line is ORed with the corresponding output of the address decoder to become the word-line of the signature SRAM.Similarly, the search operation of the noplane begins from the right-most CAM cells, and the outputs from the left port of the BiTCAM should be used as the word-lines for the shift-SRAM.The match results are also ORed with the corresponding output of the address decoder to become the word-lines of the shift-SRAM on the left. Hit-detection circuits are added to determine any un-match cases. The symbol SC in Fig. 3 stands for the conventional 6T SRAM cell, while B and T represent 4-bit dual-port dynamic AND (DP-AND) gates for binary and ternary CAM cells, respectively. Each 32b match-line circuit is constructed with eight DP-AND gates.
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IV. THE DUAL-PORT DYNAMIC GATE AND THE MATCH-LINE SCHEME The proposed dual-port dynamic AND (DP-AND) gate (Fig.4(a)) is derived from the single-port pseudo-footless clock-and-data pre-charged dynamic (PF-CDPD) AND gate (Fig. (b)) [13], which is used to construct the PF-CDPD AND-type match circuit, a technique which leads to high speed and low power BiCAM or TCAM designs [12]. Shown as the dotted and solid lines in Fig. 4(a), the DP-AND gate has two evaluation paths sharing the same pull-down network (PDN) togenerate two outputs, out1 and out2. Actually only one output,either out1 or out2, will be determined by the logic evaluation result of the PDN
by pre-programming the set cell, a 6-T SRAM cell, once the rule set is finalized. In other words, the setcell is used to determine the division and should be initialized when the data for the CAM cells arestored. A set cell with 0 determines that the CAM cells contributing to the PDN belong to the yes-plane. Otherwise, these CAM cells belong to the no-plane. If the DP-AND is set to the yes-plane, M1 of the dynamic circuit is turned on and the comparison result of the CAM cells will be sent to out1 through M1. On the other hand, M2 will be turned off for breaking the propagation of the search result and M4 will be turned on, and out2 behaves the same as .Fig. 5(a) illustrates one row of circuitry in the memory block, and depicts the connection
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signal.The ML_no only collects the matching results of the dualport AND gates belonging to the no-plane while skipping thematching results of the dual-port AND gates belonging to the yes-plane.The dual-port AND gates belonging to the yes-plane.The dual-port match-line circuit can also be implemented as a static circuit as shown in Fig. 5(b). Evaluation results for bothIf the DP-AND is set to the yes-plane, M1 of the dynamic circuit is turned on and the comparison result of the CAM cells will be sent to out1 through M1. On the other hand, M2 will be turned off for breaking the propagation of the search result and M4 will be turned on, and out2 behaves the same as .Evaluation results for both kinds of ML circuits in 0.13 m technology are summarized in Table I. The dynamic circuit outperforms the static one both in speed and power consumption. Cost and power comparisons of on-chip memories are illustrated in Fig. 5. Design 1 uses two single-port TCAMs and two SRAMs with four their own address decoders. Design 2 has one dual-port TCAM and two SRAMs, using only one simplified address decoder (refer to Fig. 3). This work has one 2-level dual-port BiTCAM and two SRAMs with the simplified address decoder. Fig. 5(a) shows the transistor count comparison.The BiTCAM design has a 40% transistor reduction compared to two singleport TCAMs. Fig. 5(b) shows the power reduction of the CAM. One dual-port TCAM achieves 23% power reduction compared to two single-port TCAMs.When assuming a 25% occupation of binary cells, the power of a dual-port BiTCAM is further reduced to 38%. Fig. 5(c) shows the power reduction of the whole memory block.
V. CONCLUSION arrangement of two DP-AND gateslocated at both sides of the division line. ML_no and ML_yesare match-lines in each row, and they require only one clock signal. However, for ease of explanation, in Fig. 5(a), the clock signals for both match-lines are designated differently ( and).ML_yes is triggered by clock signal from the left-most DP-AND gate. This DP-AND gate belongs to the yes-plane, and its out1 will be evaluated according to the matching result of CAM cells. If matching, out1 goes high, and it will serve as the clock signal for the next DP-AND gate; if un-matching,out1 stays low, then all the right-side DP-AND gates will be kept quiet. Accordingly, signal of T3 comes from the output of its left stage, and the output of T3 becomes signal of T4 belonging to the no-plane.Afterwards, the output of each DP-AND gate functions as the output of T3 until the final matching result is generated. Similarly, the operation of ML_no is triggered by clock This paper proposed an adaptive dividable dual-port 0.13 m BiTCAM for a high-speed, low-power and low-cost virus-detection processor in mobile devices. The proposed dual-port match-line scheme reduces the transistor count by 40% and provides 48% savings in power consumption compared to thesingle-port match-line scheme. The design of the adjustable division line provides high flexibility for updating virus databases.The virus-detection processor with the embedded BiTCAM performs up to 3 Gbps virus detection for 30K ClamAV rules at an energy cost of only 0.44 fJ/pattern-byte/scan at peak throughput. REFERENCES [1] K. J. Lin and C. W. Wu, A low-power CAM design for LZ data compression, IEEE Trans. Comput., vol. 49, no. 10, pp. 11391145, 2000.
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[2] T. Ikenaga and T. Ogura, A fully parallel 1-MbCAMLSI for real-time pixel-parallel image processing, IEEE J. Solid-State Circuits, vol. 35,no. 4, pp. 536544, 2000. [3] N. F. Huang, W. E. Chen, J. Y. Luo, and J. M. Chen, Design of multifield IPv6 packet classifiers using ternary CAMs, in Proc. IEEE Int. Conf. Global Telecommunications, 2001, vol. 3, pp. 18771881. [4] Y. H. Cho and W. H. Mangione-Smith, A pattern matching coprocessor for network security, in Proc. IEEE 2005 Int. Conf. Design Automation,pp. 234239. [5] L. Tan and T. Sherwood, A high throughput string matching architecture for intrusion detection and prevention, in Proc. IEEE Int. Symp.Computer Architecture, 2005, pp. 112122. [6] M. Yadav, A. Venkatachaliah, and P. D. Franzon, Hardware architecture of a parallel pattern matching engine, in Proc. IEEE Int. Symp. Circuits and Systems, 2007, pp. 13691372. [7] Snort Users Manual 2.8.1. [Online]. Available: http://www.snort.org/ docs/snortht manuals/htmanual 281/ [8] About ClamAV. 2008 [Online]. Available: http://www.clamav.org/about/[9] C. C. Wang, C. J. Cheng, T. F. Chen, and J. S. Wang, An adaptively dividable dual-ported BiTCAM for virus detection processors in mobile devices, in IEEE Int. Solid-State Circuits Conf. Dig., 2008, pp.390391. [10] S. Wu and U. Manber, A fast algorithm for multi-pattern searching,Univ. Arizona, Report TR-94-17, 1994. [11] B. H. Bloom, Space/time trade-offs in hash coding with allowable errors, Commun. ACM, vol. 13, no. 7, pp. 422426, 1970. [12] C. C. Wang, J. S. Wang, and C. W. Yeh, High-speed and low-power design techniques for TCAM macros, IEEE J. SolidState Circuits,vol. 43, no. 2, pp. 530540, Feb. 2008. [13] J. S. Wang, H. Y. Li, C. C. Chen, and C. W. Yeh, An ANDtype match-line scheme for energy-efficient content addressable memories,in IEEE Int. Solid-State Circuits Conf. Dig., 2005, pp. 464610. [14] TSMC 0.13 mLogic 1P8M Salicide CU FSG 1.2V/3.3V Process Documents,Taiwan Semiconductor Manufacturing Co., Ltd..
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A LOW POWER DESIGN SRAM USING SELF-CONTROLLABLE VOLTAGE LEVEL (SVL) TECHNIQUE S.CHINNU KANCHAN schinnu90@yahoo.co.in B.DEEPAN RAJ deepanraj4590@gmail.com S.A.ASWATHI aswathi.s.a@gmail.com S.BALAKRISHNAN krishsbk@gmail.com
SNS COLLEGE OF TECHNOLOGY COIMBATORE-35

examine the effects of the SVL circuit on the PST of storage circuits.
ABSTRACT A low leakage power is designed in 180-nm CMOS process. The stand-by leakage power of a SRAM bit memory cell array incorporating a newly-developed leakage current reduction circuit called a Self-controllable Voltage Level (SVL) circuit was only 3.7nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V . On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area. Using this technique the power can be saved and the life of battery is increased.
INTRODUCTION
Battery-driven portable systems need low leakage power techniques. Two well-known techniques reduce leakage power (PST). One is to use a multi -threshold-voltage CMOS (MTCMOS) [3]. It effectively reduces PST by disconnecting the power supply with high Vt MOSFET switches. However, there are serious drawbacks with the use of this technique, such as the fact that both memories and flip-flops based on this technique cannot retain data. The other technique involves using a variable threshold-voltage CMOS (VTCMOS) [4] that reduces PST by increasing the substrate-biases. This technique also faces some serious problems, such as a large area penalty and a large power penalty due to the substrate-bias supply circuits. To solve the abovementioned drawbacks, a small leakage current reduction circuit called a Self-controllable Voltage Level (SVL) circuit has been developed that not only significantly decreases PST, but also retains data during a stand-by period. We applied this technique to a 1K-bit 180-nm SRAM that could potentially be used in future multimedia mobile applications to
FIG .1. Leakage current reduction circuit called SELF- CONTROLLABLE VOLTAGE LEVEL.
CIRCUIT DESIGN, FABRICATION AND CHARACTERISTICS

The SVL circuit consists of an upper SVL (U-SVL) circuit and a lower SVL (L-SVL) circuit (Fig. 1), where a single inverter has been used as the load circuit. The SVL circuit shown in Fig. 2 is applied to the SRAM memory cell array. The U-SVL
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circuit is constructed of a wide channel pull-up pMOSFET switch (pSW) and multiple nMOSFET resistors (nRSm; m=1, 2, ) connected in series. Similarly, the L-SVL circuit incorporates a wide channel pull-down nMOSFET switch (nSW) and multiple series-connected pMOSFET resistors (pRSm). While the load circuit is active (i.e., CLB=0 and CL=1), both the pSW and nSW are turned on, but the nRS1 and pRS1 are turned off. Therefore, the U-SVL and L-SVL circuits can supply a maximum supply voltage VD (=VDD) and a minimum ground level voltage VS (=VSS=0), respectively, to the active load circuit. Thus, the operating speed of the load circuit can be maximized. When the load circuit is in stand-by (i.e., CLB=1 and CL=0), all the nRSm and pRSm switches are turned on, and both the Psw and nSW are turned off.
(vn+vp). Decreasing Vds will decrease the effect of the drain-induced barrier lowering (DIBL) so that the leakage currents decrease even more. In addition, the SVL circuit not only reduces the Vgd of the cut-off MOSFETs, but also reduces the Vgc of the turn-on MOSFETs. Decreasing Vgd reduces the GIDL currents of the cutoff MOSFETs and decreasing Vgc decreases the gatequantum-tunneling leakage currents of the turn-on MOSFETs. Therefore, the total leakage current of the load circuit will greatly decrease.
SRAM DESIGN PERFORMANCE
AND
We fabricated SRAMs with a 1K-bit (8bx8Wx16W) memory-cell array incorporating an SVL circuit with an m of 1 or 2 using 180-nm CMOS technology. A photograph of the SRAM LSI chip is shown in Fig. 3.
FIG .2. Circuit diagram of SRAM with 1K-bit memory-cell array incorporating SVL circuit with m of 2.
FIG. 3. 180-nm CMOS LSI that includes SRAMs with 1K-bit memory-cell array incorporating SVL circuit.
Thus, the U-SVL and L-SVL circuits respectively generate a slightly lower supply voltage VD (=VDDvn<VDD) and a relatively higher ground-level voltage VS (=vp>0V), where vn and vp are the total voltage drops of all nRSm and all pRSm, respectively. Thus, the back-gate biases (VBGs) {i.e., source voltages (Vs)} of both the cut-off pMOSFETs and the nMOSFETs in the stand-by load circuit are increased and are given by vn and -vp, respectively. The increase in VBGs will increase the Vts of the cut-off MOSFETs. Therefore, the leakage currents of the cut-off MOSFETs decrease. Furthermore, the increase in Vs increases the "write" operating margin [5]. Similarly, the Vdss of the cutoff MOSFETs decreases and becomes VDD-
The channel widths of the pMOSFETs and nMOSFETs in the memory cells are 2.5 micro m and 1.25 micro m respectively, those of the pSW and nSW are 320 micro m, and those of the pRSm and nRSm are 1.25 micro m. Figure 4 shows the simulated voltage levels at various nodes in the SRAM with the 1K-bit memory-cell array incorporating the SVL circuit with an m of 2. As shown in Fig. 4(a), the SVL circuit supplies a lower VD (1.03V) and relatively higher VS (0.35V) to the memory cell array, and retains the memory cell data during stand-by. When CL goes to a high level, VD increases to VDD (1.8V), while VS decreases to VSS (0V), so the SRAM becomes active within about 600 psec. Figure 4(b) shows
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the row address (ADR) and word-line voltage (VW) waveforms, and Fig. 4(c) shows the output datum (do=1) waveform. The read access time of the new SRAM is 536.9 psec, namely, almost the same as that (535.5 psec) of the conventional 1K-bit SRAM.
incorporating an SVL circuit with an m of 2. Figures 6 (a), (b), (c), and (d) are the 100-MHz clock (clk), Read/Write control signal (WE), "write data" (dis) and "read data" (dos), respectively. The active power (PAT) of an SRAM with a 1K-bit memory-cell array based on the SVL circuit with an m of 2 at a clock frequency (fc) of 200MHz and a VDD of 1.8V was 3.295mW, which was almost the same as that (3.296mW) of a conventional 1Kbit SRAM. Table 1 summarizes the characteristics of the 1K-bit, 180-nm CMOS SRAMs.
FIG. 4. Simulated waveforms at several nodes in SRAM with 1K-bit memory-cell array with the SVL circuit (m=2). Figure 5 depicts the measured stand-by power (PSTm1) of a 1K-bit memory-cell array based on an SVL circuit with an m of 1, that (PSTm2) of a 1K-bit memory-cell array incorporating an SVL circuit with an m of 2, and that (PST con) of the conventional memory cell array. Figure 5 also plots the stand-by power ratio. PSTm2 is drastically reduced to 3.7nW, which is namely 5.4% of the PST con (=69.1nW) at VDD=1.8 V. FIG. 6. Measured waveforms at various nodes in 180-nm SRAM with 1K-bit memory-cell array incorporating SVL circuit with m of 2 (fc=100MHz, VDD=1.8V, and VSS=0V).
SOFTWARE USED
TANNER EDA version 7.0 software tool and 180-nm CMOS process is used .The 180 nm indicates the gate length of the MOSFET. By reducing the gate length of the device, the power reduced. We have implemented the Self-Controllable Voltage Level technique to the 1-bit of SRAM cell. The SRAM cell used is 6T .The Schematic diagram of the SRAM cell of 6T is drawn in the S-edit using the browser icon. The browser icon gives the components like N-MOSFET, PMOSFET, POWER SUPPLY, and GROUND. In addition, wires, input, output is used from the icons in the left side of the S-edit page. The circuit is being fully designed .Figure .7. Shows the schematic diagram of conventional SRAM without the SVL .And the output waveforms are generated by inserting commands to the input and output nodes used in the schematic diagram. In addition, the file is simulated and the waveforms are viewed. Here we simulate to see the power and voltage waveform of the input used in the schematic diagram.
FIG . 5. Measured stand-by leakage power (PST) as function of supply voltage (VDD). Figure 6 shows the measured waveforms at various nodes of an SRAM with a 1K-bit memory-cell array
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FIG. 7. Schematic diagram of conventional SRAM in TANNER software . In addition, figure .8. Shows the output waveforms generated in TANNER .The waveform is in four parts (i.e.) two inputs bit line (BL) and word line (WL) waveforms, which are given with the Bit streams. In addition, two outputs voltage and power, which is in mille watts? In addition, the T-SPICE generates the power results also in non-graphical data. The power consumed by conventional SRAM is 25mWatts for one cell
FIG .9. Schematic diagram of SRAM with SVL incorporated in TANNER software.
FIG.10. shows the output waveforms (Voltage and Power) of SRAM incorporating SVL.
CONCLUSION
Hence, by using the SVL technique it is proved that the power consumption can be reduced. Since one bit cell incorporated with SVL and without SVL shows the good change in the power consumption. When this efficient technique is applied to 1kb of SRAM that is 1024 cells, it shows drastic changes in the power consumption. The measured stand-by leakage power of the 1K-b SRAM memory cell array significantly decreased to 5.4% that of the conventional SRAM memory cell array, while the speed degradation and area overhead were negligible and the "write" operating margin was increased. We conclude that the developed SRAM incorporating the SVL circuit, which can retain data even
FIG . 8. shows the output waveforms (Voltage and Power) of the conventional SRAM.
Now the SRAM cell is implemented by incorporating the SVL technique and the output waveforms are generated with both voltage and power waveforms, which is in microwatts. Figure.9 shows the schematic diagram of the SRAM with SVL incorporated in it.
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in stand-by, will play a major role in future deep sub100-nm CMOS SRAMs.
REFERENCES
[1] A low-leakage current power 180-nm CMOS SRAM. T.Enomoto and Y.Higuchi.,IEEE Jour of solid state circuits,June.2008. [2] A Self-Controllable-Voltage-Level (SVL) Circuit for Low-Power, High-Speed CMOS Circuits Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano, and Tomochika Harada Chuo University, Faculty of Science and Engineering,2002,Tokyo, Japan enomoto@ise.chuo-u.ac.jp [3] S. Mutoh et al., A 1V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application, Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC96), FA 10.4, pp. 168 169, 438, Feb. 1996. [4] T. Kuroda et al., A 0.9-V, 150-MHz, 10-mW, 4-mm2 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme, IEEE Jour. of Solid-State Circuits, vol. 31, no. 11, pp. 1770-1779, Nov. 1996. [5] H. Mizuno and T. Nagano, Driving source-line cell architecture for sub-1-V high-speed low-voltage applications, IEEE Jour. Of Solid-State Circuits, vol. 31, no. 4, pp. 552-557, April. 1996.
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Image Segmentation by Using Fuzzy Measures

S.Deiva Santhalyn Mercy #1 P.Hari Krishnan#2 #1M.E (Control And Instrumentation Engg) Department of Electrical and Electronics Engineering, Anna University of technology ,Coimbatore
1
mercy_ice5@yahoo.com
#2
Lecturer, Department of Electrical and Electronics Engineering, Anna University of technology, Coimbatore, India.
2
hariora@yahoo.com texture, and so forth. The edge-based segmentation techniques such as Canny edge detector, active contour, and edge following emphasize on detecting significant gray-level changes near object boundaries. The advantage of the region-based segmentation is that the segmented results can have coherent regions, linking edges, no gaps from missing edge pixels, and so on. However, its drawback is that decisions about region memberships are often more difficult than those about edge detections. The edgebased segmentation can simplify the analysis by drastically minimizing the amount of pixels from an image to be processed, while still preserving adequate object structures. The drawback of the edge-based segmentation is that the noise may result in an erroneous edge. II. THRESHOLDING TECHNIQUES The various existing forms of the image segmentation can be recognized using various techniques like Otsus technique, Kittler and Illingworths minimum error thresholding Method, Fuzzy C-means clustering etc.. When going in deep discussion several changes been analysed among the above methods. Otsus technique is based on discrimination analysis, in which the optimal threshold value calculation is based on the minimization of the weighted sum of the object and background pixels within-class variances. In Kittler and Illingworths minimum error thresholding method, it is assumed that the image can be characterized by a mixture distribution of object and background pixels. Jawahar propose a fuzzy thresholding scheme based on Fuzzy C-means clustering. The problem of fuzzy clustering is that of partitioning the set of n sample points into classes. The algorithm is an iterative optimization that minimizes one cost function. Kapur propose a method based on the previous work of Pun that first applied the concept of entropy to thresholding. This method interprets the image object and background as two different information sources. When the sum of the object and background entropies reaches its maximum, the image is said to be optimally thresholded. i. Global Thresholding When we consider beam thresholding, it can only threshold out the worst nodes of a cell. It cannot threshold out an entire cell, even if there are no good
AbstractIn image analysis, image thresholding which is used for separating the object from the background is one of the most common applications. In contrast to this, here image segmentation scheme has been processed based on thresholding by means of fuzzy set theoretical measure. The threshold is calculated by measuring the index of fuzziness of background and object sets. Typical computer vision applications usually require an image segmentationpre-processing algorithm as a first procedure. At the output of this stage, each object of the image, represented by a set of pixels, is isolated from the rest of the scene.The purpose of this step is that objects and background are separated into non overlapping sets. Usually, this segmentation process is based on the image gray-level histogram. In that case, the aim is to find a critical value or threshold. I. INTRODUCTION Image segmentation has become an indispensable task in many image and video applications. Typical computer vision applications usually require an image segmentation-pre-processing algorithm as a first procedure. At the output of this stage, each object of the image, represented by a set of pixels, is isolated from the rest of the scene. The purpose of this step is that objects and background are separated into non overlapping sets. Usually, this segmentation process is based on the image gray-level histogram. In that case, the aim is to find a critical value or threshold. Through this threshold, applied to the whole image, pixels whose gray levels exceed this critical value are assigned to one set and the rest to the other. For a well-defined image, its histogram has a deep valley between two peaks. Around these peaks the object and background gray levels are concentrated. Thus, to segment the image using some histogram thresholding technique, the optimum threshold value must be located in the valley region. Image segmentation is an important signal processing tool that is widely employed in many applications including object detection, object-based coding, object tracking, image retrieval, and clinical organ or tissue identification. To accomplish segmentations in these applications, the methods can be generally classified as region-based and edge-based techniques. The region-based segmentation techniques such as semi supervised statistical region refinement, watershed, region growing, and Markov-random-field parameter estimation focus on grouping pixels to become regions which have uniform properties like greyscale,
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nodes in it. To remedy this problem, a novel thresholding technique, global thresholding is introduced.
max P(L) > max P(L)
(1)
Now, the hard part is determining P(L), the probability of a node sequence. Unfortunately, there is no way to do this efficiently as part of the intermediate computation of a bottom-up chart parser. We will approximate P(L) as follows: P(L)= P( (2)
Fig 1. Global thresholding motivation The key insight of global thresholding is due to Rayner and Carter (1996). Rayner et al. noticed that a particular node cannot be part of the correct parse if there are no nodes in adjacent cells. In fact, it must be part of a sequence of nodes stretching from the start of the string to the end. In a probabilistic framework where almost every node will have some (possibly very small) probability, we can rephrase this requirement as being that the node must be part of a reasonably probable sequence. The Figure 1 shows an example of this insight. Nodes A, B, and C will not be thresholded out, because each is part of a sequence from the beginning to the end of the chart. On the other hand, nodes X, Y, and Z will be thresholded out, because none is part of such a sequence. Rayner et al. used this insight for a hierarchical, nonrecursive grammar, and only used their technique to prune after the first level of the grammar. They computed a score for each sequence as the minimum of the scores of each node in the sequence, and computed a score for each node in the sequence as the minimum of three scores: one based on statistics about nodes to the left, one based on nodes to the right, and one based on unigram statistic. It is needed to extend the work of Rayner et al. to general PCFGs, including those that were recursive. Therefore differs from theirs in many ways. Rayner et al. ignore the inside probabilities of nodes; while this may work after processing only the first level of a grammar, when the inside probabilities will be relatively homogeneous, it could cause problems after other levels, when the inside probability of a node will give important information about its usefulness. On the other hand, because long nodes will tend to have low inside probabilities, taking the minimum of all scores strongly favors sequences of short nodes. Furthermore, their algorithm requires time O( ) to run just once. This is acceptable if the algorithm is run only after the first level, but running it more often would lead to an overall run time of O( ). Finally, we hoped to find an algorithm that was somewhat less heuristic in nature. Our global thresholding technique thresholds out node N if the ratio between the most probable sequence of nodes including node N and the overall most probable sequence of nodes is less than some threshold, Tg. Formally, denoting sequences of nodes by L, we threshold node N if
The most important difference between global thresholding and beam thresholding is that global thresholding is global, any node in the chart can help prune out any other node. In stark contrast, beam thresholding only compares nodes to other nodes covering the same span. Beam thresholding typically allows tighter thresholds since there are fewer approximations, but does not benefit from global information. ii. Otsus Technique Otsus thresholding technique is based on a discriminant analysis which partitions the image into two classes C and C1 at gray level t such that C ={ 0,1, 2,,t} and , C1 ={ t +1,t + 2,L-1} , where L is the total number of the gray levels of the image. Let the number of pixels at the ith gray level be n be the total number of pixels in a given image. The probability of occurrence of gray level i is defined as: (3) Gray distribution can be described not only by gray mean, but also by gray variance. So we consider whether we can use the average variance to replace the average mean in Otsu method. The image variance reflects image uniformity; the variance is small inside of the objects and background. But the variance of edge and its neighbourhood changes acutely. So it is reasonable to use the average variance instead of the average of the foreground and background means in Otsu method. iii. Fuzzy C Means Fuzzy c-means (FCM) is a method of clustering which allows one piece of data to belong to two or more clusters. This method was developed by Dunn in 1973 and improved by Bezdek in 1981 and it is frequently used in pattern recognition. Fuzzy C means is a method of clustering which allows one pixel to belong to one or more clusters. The FCM algorithm attempts to partition a finite collection of pixels into a collection of C fuzzy clusters with respect to some given criteria. Fuzzy C-means Algorithm is based on minimization of the following objective function J (U, (4)
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cluster I,
u is between 0 and 1, is the centroids of is the Euclidean distance between ith data point, m [1,] is a weighting
centroids and function.
Below given are some of the characteristics of FCM By iteratively updating the cluster centers and the membership grades for each data point, FCM iteratively moves the cluster centers to the "right" location within a data set. Performance depends on initial centroids. For a robust approach there are two ways which is described below. i. Using an algorithm to determine all of the centroids. (for example: arithmetic means of all data points) ii. Run FCM several times each starting with different initial centroids. III . FUZZY MEASURES i. Fuzzy Set Theory Fuzzy set theory assigns a membership degree to all elements among the universe of discourse according to their potential to fit in some class. The membership degree can be expressed by a mathematical that assigns, to each element in the set, a function membership degree between 0 and 1. Let X be the universe (finite and not empty) of discourse and an element of X . A fuzzy set in is defined as A= {( (5)
Fig.2 Histogram and functions for subsets Both membership functions could be seen, simultaneously, in Fig 2 The S -function in the right side of the histogram and the Z-function in the left. The method incorporates fuzzy concepts that are more able to deal with object edges and ambiguity and avoids the problems involved in finding the minimum of a function. However, it has some limitations concerning the initialization of the seed subsets. To achieve an automatic process these limitations must be overcome. In order to implement the thresholding algorithm on a basis of the concept of similarity between gray levels, Tobias and Seara made the assumptions that there exists a significant contrast between the objects and background and that the gray level is the universe of discourse, a 1-D set, denoted by X . The purpose is to split the image histogram into two crisp subsets, object subset O and background subset F, using the measure of fuzziness previously defined. The initial fuzzy subsets, denoted by B and W , are associated with initial histogram intervals located at the beginning and the end regions of the histogram. The gray levels in each of these initial intervals have the intuitive property of belonging with certainty to the final and subsets object or background. For dark objects B W . These initial fuzzy subsets,W and B, are modeled by the S and Z membership functions, respectively. ii. Measure Of Fuzziness A reasonable approach to estimate the average ambiguity in fuzzy sets is measuring its fuzziness. The fuzziness of a crisp set should be zero, as there is no ambiguity about whether an element belongs to the set or not. If the set is maximally ambiguous and its fuzziness should be maximum.
The S-function is used for modeling the membership degree. This type of function is suitable to represent the set of bright pixels and is defined as = [0] ,at x a = [2{ }],at a x b }],at b (6)
= [1-2 { = [1] at x
where b= (1/2)(a+c).The S-function can be controlled through parameters and the parameter is called .The higher the the crossover point where gray level of a pixel (closer to white), the higher membership value and vice versa. The S-function is used to represent the dark pixels and is defined by an expression obtained from Zfunction as follows:
Fig. 3 Typical shape of the S function
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The Otsu Threshold Segmentation uses an automated mechanism to select a threshold value to divide the image into sets of pixels. It is not sure that whether it tries to maximize the between class variance or minimize the within class variance (both operations usually result in similar segmentations). Since it is an automated method, there is no opportunity for the user to define the intensity ranges manually. The "Inside Value" and "Outside Value" are used to establish what is the foreground and background values in the (binary) thresholded image. The "Connected Component Parameters" use different strategies to define how pixels must touch in order to be considered from the same object. Face connected means the pixels have to be adjacent in the same row (or column, etc.). Other strategies allow pixels to be diagonal to each other and be considered the same object. These options have only minor effects on segmentations unless you have very thin structures which are not horizontal/vertical. In this case, it is best not use the face connected strategy. The result of the connect component step is a set of individually labelled objects. iv. Edge Detection A point is being an edge point if its twodimensional first-order derivative is greater than a specified threshold. A set of such points that are connected according to a predefined criterion of connectedness is by definition an edge.In practice, optics, sampling, other image acquisition imperfections yield edges that are blurred. The slope of the ramp is inversely proportional to the degree of blurring in the edge. The thickness of edge is determined by the length of the ramp.First-order derivatives of a digital image are based on various approximations of the 2-D gradient. Secondorder derivative is defined as digital approximations to the Laplacian of a 2-D function. The first derivative can be used to detect the presence of an edge at a point in an image. Similarly, the sign of the second derivative can be used to determine whether an edge pixel lies on the dark or light side of an edge v. Indexed Images An indexed image consists of an array and a colormap matrix. The pixel values in the array are direct indices into a colormap. By convention, this documentation uses the variable name X to refer to the array and map to refer to the colormap. The colormap matrix is an m-by-3 array of class double containing floating-point values in the range [0,1]. Each row of map specifies the red, green, and blue components of a single color. An indexed image uses direct mapping of pixel values to colormap values. The color of each image pixel is determined by using the corresponding value of X as an index into map. vi. Truecolor Images A truecolor image is an image in which each pixel is specified by three values, one each for the red, blue, and green components of the pixels color. MATLAB store truecolor images as an m-by-n-by-3 data
Degrees of membership near 0 or 1 indicate lower fuzziness, as the ambiguity decreases. Kaufmann is introduced an index of fuzziness (IF) comparing a fuzzy set with its nearest crisp set. A fuzzy set A* is called crisp set of A if the following conditions are satisfied: < 0.5 (8)
This index is calculated by measuring the normalized distance .Between A and A* defined as [ |] (9)
where is the number of elements in A, . Depending if K=1 or 2, the index of fuzziness K is called linear or quadratic. Such an index reflects the ambiguity in a set of elements. If a fuzzy set shows low index of fuzziness there exists a low ambiguity among elements. iii. Fuzzy Thresholding A fuzzy set is a class of points possessing a continuum of grades of membership where there is no sharp boundary between elements that belong to this class and those that do not . We can express this grade of membership by a mathematical function called membership function or characteristic function pA( .
Fig.4 Multimodal image histogram. To obtain the threshold with the proposed method, we start by defining two crispy sets as shown in Fig 4.We know that the gray level in each set precisely defines both the object and the background sets. Such sets are respectively associated to the gray-level intervals x[191 and [x,xi,]. Xj and Xi, are the initial and final gray-level limits for the crispy sets, respectively. For each set, it is computed the membership function ( )= S(x| a,b,c) a=2b c (10) (11)
Next, we must assign the gray levels in the fuzzy interval of the histogram to one of the two initial crispy sets according to an allocation rule. Such rule is based on the measurement of the index of fuzziness on the image graylevel histogram. We use this index to reflect the degree of membership of each gray-level in the fuzzy interval.
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V. TABULATION IMG NO. 1. 2. 3. MIN mu 0.007 0.027 1.511 MAX mu 48.72 52.07 95.70 MIN SIGMA 2B 0.6117 2.284 1.946 MAX SIG. 2B 2.760 3.35 6.583
THRES HOLD VAL.
array that defines red, green, and blue color components for each individual pixel. IV IMPLEMENTATION IN MATLAB Image segmentation using Otsu thresholding is developed to bring an impressive OTSU(I,N) segments. The image I into N classes by means of Otsu's N thresholding method. OTSU returns an array IDX containing the cluster indices from 1 to N of each point. IDX = OTSU(I,N) (12)
67 79 121.03
VI. CONCLUSION Compared to other thresholding techniques it is suggested that the proposed method will be a good alternative to deal with multimodal histograms. It is particularly made for real-time applications because histogram-segmentation based methods are simpler and therefore faster than the other ones. REFERENCES [1] A. S. Pednekar and I. A. Kakadiaris, Image segmentation based on fuzzy connectedness using dynamic weights, IEEE Trans. Image Process., vol. 15, no. 6, pp. 15551562, Jun. 2006. [2] S. Sahaphong and N. Hiransakolwong, Unsupervised image segmentation using automated fuzzy c-means, in Proc. IEEE Int. Conf. Computer and Information Technology, Oct. 2007, pp. 690694. [3] O. J. Tobias, R. Seara, and F. A. P. Soares, Automatic image segmentation using fuzzy sets, in Proc. 38th Midwest Symp. Circuits and Systems, 1996, vol. 2, pp. 921924. [4] O. J. Tobias and R. Seara, Image segmentation by histogram thresholding using fuzzy sets, IEEE Trans. Image Process., vol. 11, 2002. [5] C. V. Jawahar, P. K. Biswas, and A. K. Ray, Investigations on fuzzy thresholding based on fuzzy clustering, Pattern Recognit., vol. 30, no 10, pp. 1605 1613, 1997. [6] K. S. Chuang, H. L. Tzeng, S. Chen, J. Wu, and T. J. Chen, Fuzzy c-means clustering with spatial information for image segmentation, Comput. Med. Imag. Graph., vol. 30, no. 1, pp. 915, 2006. [7] L. K. Huang and M. J. J. Wang, Image thresholding by minimizing the measures of fuzziness, Pattern Recognit., vol. 28, no. 1, pp. 4151, 1995. [8] H. R. Tizhoosh, Image thresholding using type II fuzzy sets, Pattern Recognit., vol. 38, pp. 23632372, 2005 [9] N. Otsu, A threshold selection method from gray level histograms, IEEE Trans. Syst., Man, Cybern., vol. SMC-9, pp. 6266, 1979. [10] A. Kaufmann, Introduction to the Theory of Fuzzy Subsets. New York: Academic, 1975, vol. I.
IDX = OTSU(I) uses two classes N=2, default value and [IDX, sep] = OTSU(I,N) also returns the value (sep) of the separability criterion within the range [0 1]. Zero is obtained only with data having less than N values, whereas one optimal value is obtained only with N-valued arrays.It should be noticed that the thresholds generally become less credible as the number of classes N to be separated increases and if I is an RGB image, a transform is first performed on the three R,G,B channels.It is done by using the image processing tools of matlab. INPUT IMAGE
IMAGE AFTER GREY CONVERSION
OUTPUT SEGMENTED IMAGE
The segmentation is then carried out on the image component that contains most of the energy. It is made that as such an input image when given for segmentation is first converted to grey image and then a segmented image has been obtained as an output as a result.
LOW-POWER D-BCT DECODER FOR WI-MAX USING NEURAL NETWORKS

Gayathiri.S1 S.Saravanan2
1. PG Scholar in Embedded System Technologies 2.Asst.Professor in Electrical & electronics Engineering Velalar college of Engineering & Technology, Erode
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Abstract -The convolution turbo code (CTC) has large

memory power consumption. To reduce the power consumption of the state metrics cache (SMC), lowpower memory-reduced trace back maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the trace back MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed trace back computation requires no complicated reversion checker, path selection, and reversion flag cache. MAP decoders are necessary components of powerful iterative decoding systems such as Turbo codes. For double-binary (DB) MAP decoding, radix-2*2 trace back structures are introduced to provide a trade off power consumption. Trace back MAP decoding: In this, the trace back MAP decoding is proposed to trace the state metrics back by accessing the difference metrics. Trace back convolutional decoding: In the conventional path, the state metrics computed by the natural recursion processor (NRP) in the natural order are stored in the SMC. These two trace back structure, MAP decoding structure achieve power reduction of the state metrics cache. Artificial intelligence technique called Neural network algorithm which is proposed to reduce the power consumption of D-BCT decoder and achieves a better performance in terms of power, latency, etc., as compared to existing methods.
low logic overhead in the L-MAP and (E)ML-MAP. Fig.1.1 illustrates the decoding paths of the conventional and traceback computation. In the conventional path, the state metrics computed by natural recursion processor (NRP) in the natural order are stored in the c. Then, the state metrics are read out to compute log-likelihood ratio (LLR) in the reverse order. In the traceback path, the difference metrics are stored in the SMC . Then, the state metrics are traced back in the reverse order with the stored difference metrics. Instead of storing all state metrics, the size of metrics memory can be reduced by access the difference metrics. 1. Block Diagram of Conventional Path In the conventional path as shown in figure 1.1 and figure 1.2, the state metrics computed by the natural recursion processor (NRP) in the natural order are stored in the SMC.
1. Introduction
Binary convolutional turbo code (CTC) proposed in 1993 has been proved that it can get a high coding gain near the Shannon capacity limit. In 1999, the non-binary CTC was introduced to have superior coding gain. In recent years, the double-binary CTC was adopted in the advanced wireless communication standards, such as DVB-RCS, and WiMAX. The reduction of the CTC in bit error rates is achieved at the expense of intensive computations involved in the iterative turbo decoding steps. The iterative turbo decoding is composed of soft-input softoutput (SISO) decoding algorithms. A powerful SISO algorithm is the maximum a posteriori probability algorithm (MAP). Because of additive forms of the log-MAP (LMAP) and Max-log-MAP (ML-MAP), they have been widely used in MAP algorithms. An enhanced Max-logMAP (EML-MAP) has been proposed to have much better coding gain than the ML-MAP. Without massive mathematical approximations, the L-MAP however has the significant correction performance than the (E) ML-MAP. The memory organization of the metrics in MAP algorithms is critical. For binary CTC decoders, some previous works have been proposed to reduce power consumptions based on decreasing size or accesses of the memory. The reverse calculations with a flag memory and reversion checkers are proposed. The reversion checkers prolong the decoding critical path or cycles. Besides, the reverse calculation only works in (E)ML-MAP. Our previous work was proposed to trace the metrics back. The traceback calculation works with
Fig. 1.1 Conventional Path block diagram Then, the state metrics are read out to compute the a posteriori log-likelihood ratio (LLR) by the log-a posteriori module (LAPO) in the reverse order. Iterative decoding of convolutional turbo code (CTC) has large memory power consumption.
Fig. 1.2 Conventional decoding procedures 1.1 1.1.1 Architecture of Conventional Traceback Method Introduction
Viterbi Algorithm (VA) with high constraint length K is widely used error detection / correction scheme such as GSM, the voice channels of 3G and IEEE 802.11a wireless LAN. The well-known VA has been described in literature extensively. The data path of the Viterbi Decoder (VD) is composed of three major components: Branch Metric Calculation Unit (BMU), Add Compare Select (ACS) and Survivor Memory Unit (SMU). ACS attracts most of the research efforts in the field of VD since the existence of feedback loop of the butterfly-like processor makes ACS unit the bottleneck of
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popped out of the LIFO, is 4L. A key observation is that every decision bit in the survivor memory written by the WR will be read by TB and DC respectively. In other words, every decision bit in the survivor memory will be read two times. The redundant memory read operations are the main optimization target our proposed architecture try to address. 1.2 Traceback MAP Decoding Approach 1.2.1 Introduction
speed of the whole VD system. However, it has been shown that SMU contributes over half of the power consumption and energy due to the extensive large memory access operations. Two basic approaches used to record survivor paths are register exchange and traceback in SMU of VD [3]. Up to now, only VDs with K 5 implemented using register exchange have been reported in literature. Generally, all the VDs with conventional traceback approach employ some variations of the kpointer traceback architecture. Here k refers to the number of the read pointers to access the survivor memory. The classical implementation of the trace back scheme is based on the property of unification. That is, if we follow all survivor sequences back M stages, they all merge to the same state. Similarly, if we choose an arbitrary state at stage X and trace back to X M L stages, we will reach the same maximum likelihood correct state.
Fig. 1.3 Architecture of conventional traceback approach 1.1.2 Survivor Path Memory
Fig. 1.4 Traceback Path Block Diagram To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback DB MAP decoding is proposed. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. In the traceback path unit as shown in figure 1.4, the difference metrics computed by the NRP are stored in the SMC. Then, the state metrics are traced back with the stored difference metrics by the traceback recursion processor (TRP) in the reverse order. The power consumption of the SMC can be reduced by accessing the difference metrics because the number of stored metrics is lower. The computational power of TRP is small, and the overall memory size and power consumption of the traceback path is reduced. 1.2.2 Pre-Traceback Algorithm Description The main task of the TR in conventional traceback approach is to get the initial start state for the DC through a recursive M shift and survivor memory read operations. For simplicity, we let the traceback length M = L. At time instant L + M, for i N = {0, 1, 2,. ,. ,., ., ., . i ,m}, where N is the set of trellis state and m = 2K1 , S kL+M will converge to the maximum likelihood state SKLmaxlike. Furthermore, during the time interval [kL, (k +1)L], for i N, we refer the pre state of i at the time instant kL as the target trace back state. Naturally, the goal of TR which starts at time instant (k+1) L is to locate the target traceback state at time instant kL, which is S n=S n1 d n,i>>1} (1.2) represents the decision bits of Here, dni state i at time instant n. The exponential number, {dni, i >> 1}, represents the index number of the temporal adjacent pre state. The operation defined in equation 1.2 implies a multiplex select operation. It is apparent that the pretraceback operation defined in equation 1.2 is performed in the forward direction opposed to the conventional traceback operation which is done in backward direction. According to the unification property of the trellis graph, if L is set large enough, the pointer register S should point to the same state S(k+1)L = SkLmaxlike (1.3) which is the target track back state and the start state of the DC. As soon as WR complete L + 1 columns of decision bit update, the target traceback state of the last column is available at the same time. Hence, the corresponding DC can be performed from the target traceback state which is estimated by the prei i { i
The survivor path memory can be regarded as a circular 4 blocks of memory with L columns each as shown in figure 1.3. Three operations decision-vector write, traceback-read and decode-read work in parallel to manipulate the decision bits vectors in different memory banks: Decision bit-write (WR) writes the updated decision bit vectors from ACS unit into the survivor memory in an increased memory address order. Tracebackread (TB) recursively estimates the previous state Sn-1 according to the current state Sn and the associated decision 8 bit d n. For radix-2 applications, the estimation rule can be described as follows: 8 Sn-1= {d n, Sn >> 1} (1.1) The initial state is arbitrary according to the unification property and the recursion will be repeated for consecutive L iterations. The decode-read (DC) performs the similar read operation as the traceback operation defined by equation 1 except that the initial state is the output state estimated by TB in the last L time slot. Every L time interval, the TB begins the trace back read from an arbitrary state, and the DC starts with the state determined by the TB process in the last L time interval. Since the decoded bits generated by the DC are in the reverse order, a simple two- stack Last-In-First- Out (LIFO) scheme is used to perform bits order reversal. Each stack with a size of L depth, DC process pushes the reversal decoded bits stream into one stack while the decoded bits stored in the other stack are popped. Hence, the overall latency of traceback method, which is the time delay between the writing of the decision bit of WR process and the time when the corresponding bit is
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traceback operation directly. In our proposed pre-traceback approach, pre-traceback and DC are done in forward direction and backward direction respectively whereas in the conventional approach TB and DC are both done in backward direction. In summary, compared to the conventional traceback scheme which is based on three types of memory access operations (WR, TB and DC), only two types of operations are necessary in the pre-traceback approach, WR and DC: Decision bit-write (WR): In addition to update decision bit vectors in the survivor memory, the pointer register are also updated as described in equation 4.2. The update of the survivor memory and the pre-traceback of the pointer register are done in parallel. Decode-read (DC) process performs two steps of operation: First, select an arbitrary state and look for the target traceback state in the pointer register. Second, from the start state, performs the iterative read operation for decoding. 1.2.3 Pre-Traceback Architecture The survivor memory is divided into three banks, with L columns for each bank, as shown in Figure 1.5. Only two types of operations: WR and DC work in parallel to access the survivor memory concurrently. In addition to the pointer register mentioned in the above section, another register is used to store the intermediate DC start state, which is simply referred to as DC start register. WR updates the decision vector columns in an increasing order. Correspondingly, the pointer register is updated based on the general description in equation 4.2. However, as we only need to know the target traceback state L stages before, the operation of pre-traceback is based on the block with the size of L. It should be noted that at time instant kL, where k = {1, 2, }, pretraceback for the time interval [(k 1)L, kL] and [kL,(k + 1)L] is overlapped. A simple trick is employed with the aim to share the pointer register as well as overcoming the problem of overlap. It is apparent to observe that at time instant kL, for the pre-traceback operation at time interval [kL, (k + 1)L], the ith pointer register should always be initialized as i. So by just plugging the initial state number into equation 2 at time instant kL + 1, the pointer register between the two blocks can be shared. The target traceback state in the pointer register is shifted into DC start register at every kL time instant. Specifically, the operation of the pointer registers can be summarized as follows: i Sni = i n , i>>1
{d i {d i }
Fig. 1.5 Pre-Traceback Architecture Diagram Compared to the conventional traceback approach, the proposed pre-traceback approach has 25% improvement in both memory size efficiency and latency reduction. Although a similar size and latency can also be achieved with the conventional traceback scheme, it must involve some form of dedicated clocking design strategies. Table1 1.1 Size and Latency of Traceback and PreTraceback Architecture Survivor Memory Path 4L 3L Decoding Latency
Traceback Pre-Traceback
4L 3L
Specifically, in [3], read pointer must work 3 times faster than write pointer and there is a stringent constraint on the phase relationship between the write pointer and the read pointer. This obviously improves the design efforts compared to the proposed pre-traceback approach which adopts a simple clocking strategy that the read and write pointers work at the same frequency. 1.2 Path History (PH) Memory
Path History Memory is used in Viterbi algorithm to find the survivor path. The contents of this memory are updated on each stage L of the trellis which allows reconstructing the survivor path. There are 8 ACS units in the array that output 8 decision bits per clock cycle. These decision bits (survivor states) are saved in the PH RAM. Total size of the PH RAM is given by: Size of PH RAM = (2L-1/2M) x WL x total windows (1.5) Where WL (Window Length) is 5-6 times the constraint length. Lis the constraint length and M=3 for 8 ACS units. The total processing of states (2L-1 states) is done by a smaller de Bruijin graph of 2M states. For example in equation 4.5, the size of the PH RAM for constraint length 9 (as in 3GPP) will be: Size of PH RAM = 32 x 54 x 4 = 6912 x 8 bits. There is 8K (2K x 8) of output RAM available in turbo decoding array. This is reused for PH memory and shown in figure 1.6
, if n=1 , if n = KL+1 where K=1,2,. . (1.4)
Sn-1 n , i>>1} , Otherwise At each kL time instant, with an initial start state determined by pointer registers, DC begins a consecutive memory read operation with a decreasing address. A LIFO is also required to perform the bit reverse order. The overall latency including LIFO is only 3L opposed to 4L in the conventional approach. A simple architectural comparison is summarized in Table 1.1.
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Memory and counts down by 1. The decrement in count provides jump of one segment length. Reverse processor B1 and B2 share the same counter and shifter. Reconfigurable trace back processing is explained with examples of 3GPP and GSM in table 1.2. Let U4-U3_U2_U1_U0 are outputs of buffers B1B2_B3_B4 and C6_C5_C4_C3_C2_C1_C0 are the outputs of the 6 bit down counter. Output of the arithmetic shifter with zero shift is 0_0_0_0_C6_C5_C4_C3_C2_C1_C0. Table 1.3. Tri state buffer controls for reconfigurable traceback processing B1 B2 B3 B4 B5 B6 B7 B8 GSM On On On On On Off On On 3GPP Off Off Off Off Off On Off Off
Fig. 1.6 2Kx4 identical path history RAMs, Segmentation and mappings shown for different standards. Each block of 2K RAM is used to store one window length (WL) of decision bits. These RAMs are segmented by total states of the trellis. For example, for 256 states there are 256 decision bits. Therefore the RAMs will be divided into 32x8 wide segments. The total number of segments will be equal to one window length (constraint length x 6 = 54 for 3GPP). Figure 1.6 and table 1.2 show these mappings and segmentation for various standards. PH memory is read by trace back processors as they calculate the survivor path in the reverse traversing of the trellis. Table 1.2 Memory utilization for different standards Standard Constant Length Memory Utilization for 2k RAM=WL x Segment Size 54x32=1728x8 Bits
The contents of the read register for 3GPP using the controls in table 4.3 will be 0 0 C6 C5 C4 C3 C2 C1 C0 U1 U0
By a similar reasoning the read register contents for GSM are: C5 C4 C3 C2 C1 C0 U4 U3 U2 U1 U0
W- CDMA(Japan) CDMA 2000 UMTS GSM PDC IS-95,IEEE 802.16 IS-54
5 7 6
30x2= 60x8 Bits 42x8=336x8 Bits 36x4=144x8 Bits

Figure 1.9 Traceback processing Virtual Silicon 2K x 8 synchronous (separate read and write port) macro RAMs were used for Path history memory consuming 110 uW/MHz/Port. The decoder consumes 69mw at 20MHz occupying 2.824 mm2 area. 2. Proposed Neural network structure Artificial neural networks (ANN) have been used successfully in pattern recognition problems, function approximation, control, etc. Their processing capabilities are based on a parallel architecture. There are different kinds of electronic implementations of ANN: digital, analog, hybrid, and each one has specific advantages and disadvantages depending on the type and configuration of the network, training method and application. For digital implementations of ANN there are different alternatives: custom design, digital signal processors, programmable logic. Among them, programmable logic offer low cost, powerful software development tools and true parallel implementations. Field programmable gate arrays (FPGA) are a family of programmable logic devices based on an array of configurable logic blocks (CLB), which give a great flexibility in the development of digital ANNs. The backpropagation algorithm , is one of the most useful algorithms of ANN training. In this, the neuron implementation for the in topologies that are suitable for this
1.3
Reconfigurable Trace Back Processing
The input/output state connections for the ACS blocks are explained in figure 1.7. Total number of states = 2 a+1.
Fig. 1.7 Next and Previous state calculation for all Trellises There are two reverse processors B1 and B2 (dummy) working in parallel, each accessing separate PH RAM. B2 calculations initialize the start state of B1 To get the survivor path, we have chosen the trace back technique as register exchange in not preferred for large constraint lengths. As explained above, the previous trellis path stage SL-1 is given by the current path state SL according to the following update. SL-1 = [SL<<1,D] which corresponds to a left shift of the current state introducing the value of surviving bit D in the vacant position. This is also shown by D1-D7 in figure 1.9. Survivor bit is selected by multiplexer M1 from the data bus of PH Memories. The select control to this multiplexer is provided by D1, D2, D3 outputs. 6 bit Down Counter is initialized with the last address of PH
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2.2 Sigmoid Activation Function Hardware Design A very important part of neuron implementation is activation function hardware design. One of the most frequently used activation function in backpropagation neural networks applications is the hyperbolic tangent (tanh) sigmoid function (refered to as "tansig" in Matlab), and is given as: F(n)=(en-e-n)/(en+e-n) (2.2) This function is not suitable for direct digital implementation as it consists of an infinite exponential series. Many implementations use a lookup table for approximation. However the amount of hardware required for these lookup tables can be quite large especially if one required a reasonable approximation . A simple second order nonlinear function exists which can be used as an approximation to a sigmoid function . This nonlinear function can be implemented directly using digital techniques. The following equation is a second order nonlinear function which has a tanh-like transition between the upper and lower saturation regions : 1 for L n f(n) = f`(n) for L < n < L (2.3) -1 for n -L where L depends on the level of saturation of the function and f n'( ) is defined by f`(n) = n( - theta*n ) for 0 n L n( +theta*n), LZO
algorithm. The tanh sigmoid activation function is also implemented. The neuron is then used in a multilayer neural network. For the implementation, VHDL language was used. VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware description language which simplifies the development of complex systems because it is possible to model and simulate a digital system form a high level of abstraction and with important facilities for modular design. The purpose of this work is to suggest and analyze several neuron implementations, show a way for the integration and control of the neurons within a neural network, and describe a way to implement a simple feedforward neural network trained by BP algorithm using XC3S500E Xilinx FPGA. 2.1 Neuron Implementation The common mathematical model of a neuron is shown in Fig. 2.1
Fig. 2.1 Mathematical model of artificial neuron. The neuron output can be written as: a = f ( j=1 R wj Pj ) (2.1) where pj are inputs, wj are weight coefficients, f activation function, and a neuron output. Two distinct neuron implementation were designed using 8-bit and 12-bit binary MAC (multiply accumulate) circuits. The sigmoid activation function is used for implemented neurons in hidden layer, and linear activation function is used for output layer neuron. For all neurons ( 8bit and 12-bit), the product of signed input ( 4-bit / 8-bit) and signed weight ( 4-bit) form a signed result (8-bit/ 12bit). These products value are accumulated into activation state. The final output value is obtained by applying the activation function. The weight coefficients are stored in a ROM within neurons. Referring to Fig. 2.2, the MAC unit which accepts a serial processing of weights and parallel inputs pairs, each pair is multiplied together and a running total is recorded. An index control module controls the multiplexing order. Once all input pairs have been processed, the final sum is passed through the activation function to produce the neurons output. The main advantage of serial processing is the small constant area required, regardless of topology, to implement one MAC and some routing for one input and one weight contained in the weight ROM module. The obvious disadvantage is the processing speed. If the network involves a large number of inputs, serial processing will suffer from slow processing.
(2.4)
where and theta are parameter for setting the slop and gain. Fig.2.3 shows the comparison between the sigmoid defined by equation 2.2 and the hardware approximation defined by equations 2.3 and 2.4.
Fig.2.3 Real tanh sigmoid activation function and hardware approximation For an 8-bit neurons, figures 2.4 and 2.5 show the time diagrams for implementing two neurons, one with approximated tanh sigmoid activation function and the other with linear activation function. The RTL (register transfer level) hardware circuits for implementing the two neurons are shown in figures 2. 6 and 2.7, leading to different hardware complexity and different operating speeds.
Fig. 2.2 Neuron structureserial processing
Fig.2.4 Time diagram of implementing an 8-bit artificial neuron with approximated tanh sigmoid activation function
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Table 2.1 Comparative data for implemented 8-bit artificial neurons Neuron Type Tanh Linear sigmoid
Device Utilization .
No. of slices (4656) No. of registers No. of 4 input LUTS(9312) No. of bonded IOBs(232) No. of multiplier(20) No. of GCLKs(24) 50 14 94 21 3 1 18 7 30 21 2 1
Fig.2.5 Time diagram of implementing an 8-bit linear artificial neuron
Time Summary . Max path delay Max operating frequency
24.8 nsec 40.3 MHz
12.7nsec 78.7 MHz
2.4 Neural Network Simulation and Implementation Results The architecture of feedforward neural network used in this work is 3-3-1 (input, hidden, output) layers. It is shown in Fig.2.8.
Fig.2.8 Two layer feedforward (BP) neural network architecture of dimension 3-3-1 (referred to nntool matlab schematic notation)
Fig.2.6 RTL hardware schematic circuit for implementing tanh sigmoid artificial neuron
The network is composed of three input , the hidden layer with three sigmoid neurons, and the output layer with single linear neuron. All neurons in the same layer are handled in parallelism. It fully uses the parallel, quick characteristic of the FPGA. Considering the tradeoff area and speed in the design of the chip, the parallel inputs of every neuron from the previous layer are sent to the multiplication and accumulated to the activation function. The principle diagram of the top level and RTL level neural network design is shown in Fig.2.9 (a ,b, and c).
Fig.2.7 RTL hardware schematic circuit for implementing linear artificial neurons 2.3 Comparison Results Table 2.1 gives performance and resource use summary for the two implemented 8-bit neurons. As it can be seen, the linear neuron require very few hardware resource in comparison with tanh sigmoid nonlinear neuron. The operation speed in all cases gives a good results and shows the advantages of using FPGAs in neural realization.
(a)
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summary gives a good results and shows the advantages of using FPGAs in neural realization.
Fig.2.10 Time diagram for (3-3) single layer tanh sigmoid neural network (assumed has identical performance to hidden layer).
(b)
Fig.2.11 Time diagram for (3-3-1) feedforward BP neural network. 2.5 Conclusions Construction solutions for implementation of neural networks using FPGAs are described. The main purpose of this research was to design and implement single neuron in the domain of speed and hardware complexity, and to suggest a solution for connecting neurons into a multilayer feedforward BP neural network. An important part of this work was the hardware implementation for the approximation of sigmoid activation function. Since the more advanced families of FPGAs can contain more than 100,000 CLB (configurable logic block), then it is clear that we can implement a network with an interesting number of neurons working in parallel in just a single chip. On the other hand, using hardware description, such as VHDL, represent a very practical option when dealing with complex systems. Finally, we can say the FPGAs constitute a very powerful option for implementing ANNs since we can really exploit their parallel processing capabilities. References: [1] C.-H. Lin, C.-Y. Chen, and A.-Y. Wu, Highthroughput 12-mode CTC decoder for WiMAX Standard, accepted for publication in Proc. IEEE VLSIDAT 2008, Hsinchu, Taiwan, April 23-25, 2008. [2] C.-H. Lin, C.-Y. Chen, and A.-Y. Wu, An- Yeu Wu, Low-Power Memory-Reduced Traceback MAP decoding for Double Binary Convolutional Turbo Decoder, IEEE Trans. On Circuits and System Society, vol. 56, p. 1005-1016, May 2009.
(c) Fig.2.9 (a) Top level diagram of implementing 3-3-1 feedforward neural network, (b) RTL level circuit diagram of implementing hidden layer, (c) RTL level circuit diagram of implementing output layer. Where p1 , p2 , p3 is the 4-bit input signals to hidden layer neurons. The 4-bit nine weights coefficients are stored in a ROM within neurons. The tanh sigmoid activation function of hidden neuron is implemented as VHDL package code according to kwan approximation. The 8-bit outputs of hidden layer neurons 1 2 3 a ,a ,a are applied as input to output layer neuron. The output signal out _ rdy is applied as start signal to output layer in _rdy. The clk signal drive both network layers. The three 4-bit weights coefficients of output layer are also stored in a ROM within output neuron . The overall network 12-bit output is a. To validate the performance of the neural network, we establish the test-bench considering the actual situation of the neural network operation. The test-bench adopting three type of input signal vectors, and the weight coefficient of hidden and output layers are stored in ROMs. The simulative results ( time diagram) of the hidden layer and overall neural network are shown in figures 2.10 and 2.11 respectively. As a result of synthesis and implementation of multilayer feedforword neural network on a Xilinx xc3s500 FPGA device. The device utilization summary and timing
[3] Yao Gang, Arslan, T.; Erdogan, A.t., An Efficient Pre-Traceback Approach for Viterbi Decoding in Wireless IEEE International Symposiun On Communication, Circuits and Systems, Vol. 6, pp. 5441 5444, July 2005. [4] Ahmed, I.; Arslan, T. ,A Reconfigurable Viterbi Traceback for Implementation on Turbo Decoding Array, IEEE International SOC Conference, pp. 107-108, January 2007. [5] M.Hagan , H . Demuth , M. Beele , " Neural Network Design" , University of Colorado Bookstore, 2002, ISBN : 0- 9717321- 0-8. [6] R. Omondi, C. Rajapakse," FPGA Implementation of Neural Networks", Springer U.S., 2006,ISBN 10-0-38728485-0. [7] O. Maischberger ,v. Salapura , " A Fast FPGA Implementation of a General Purpose Neuron ", Technical University , Institute of in formatik , Austria , 2006. [8] D. L. Berry, "VHDL programming by examples", McGraw-Hill, fourth edition, 2002. [9] Pavlitov K., Mancler O., " FPGA Implementation of Artificial Neurons" , Electronics, No.9 September , 2004 , pp . 22-24. [10] J. Blake , L. McDaid , " Using Xilinx FPGAs to Implement Neural Networks and Fuzzy Systems" , Faculty of Eng . , University . of Ulster , Magel college , Northland Rd . Derry , 2005. [11] Kwan , H.K. , " simple sigmoid . like activation function suitable for digital hardware implementation" , Electronic Letters , V.28 , July , 1992 , pp. 1379 1380 . [12] Xilinx , XST User Guide , Xilinx Inc . 2003.
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OPTIMIZED THRESHOLD IN IMAGE SEGMENTATION USING FUZZY MEASURES

Nishamary.p1 S.Saravanan2 1.PG scholar in Embedded System Technologies 2.Asst.professor in Electrical And Electronics Engineering Velalar College of Engineering and Technologies,Erode
AbstractIn this paper, an optimized threshold in image segmentation based on a fuzziness measure is presented. This work is an improvement of an existing method. Using fuzzy logic concepts, the problems involved in finding the minimum of a criterion function are avoided. Similarity between gray levels is the key to find an optimal threshold. Two initial regions of gray levels, located at the boundaries of the histogram, are defined. Then, using an index of fuzziness, a similarity process is started to find the threshold point. A significant contrast between objects and background is assumed. Histogram equalization is used in small contrast images. The peformance measure is calculated and compared with the existing methods. Index TermsFuzzy measures, fuzzy sets, image segmentation, index of fuzziness, threshold. I. INTRODUCTION In computer vision, segmentation refers to the process of partitioning a digital image into multiple segments (sets of pixels, also known as super pixels). The goal of segmentation is to simplify and/or change the representation of an image in to something that is more meaningful and easier to analyze. Image segmentation is typically used to locate objects and boundaries ( lines, curves, etc.) in images. More precisely, image segmentation is the process of assigning a label to every pixel in an image such that pixels with the same label share certain visual characteristics [1]. The result of image segmentation is a set of segments that collectively cover the entire image, or a set of contours extracted from the image. Each of the pixels in a region are similar with respect to some characteristic or computed property, such as color, intensity, or texture. Adjacent regions are significantly different with respect to the same characteristic. Segmentation based on gray level histogram thresholding is a method to divide an image containing two regions of interest: object and background. In fact, applying this threshold to the whole image, pixels whose gray level is under this value are assigned to a region and the remainder to the other. Histograms of images with two distinct regions are formed by two peaks separated by a deep valley called
bimodal histograms. In such cases, the threshold value must be located on the valley region. When the image histogram does not exhibit a clear separation, ordinary thresholding techniques might perform poorly. Fuzzy set theory provides a new tool to deal with multimodal histograms. It can incorporate human perception and linguistic concepts such as similarity, and has been successfully applied to image thresholding [2]. The remainder of this paper is organized as follows. In Section II, a background review on thresholding methods is presented. A general description of the fuzzy set theory and indexof fuzziness measuring is presented in Section III. The existing method is described in Section IV. The proposed method is presented in SectionV. Limitations and detected problems of the existing method are also discussed. SectionVI shows comparative results to illustrate the effectiveness of the proposed approach and Section VII presents the final conclusions. II. THRESHOLDING ALGORITHMS We categorize the thresholding methods in six groups according to the information they are exploiting. These categories are [17] : 1.Histogram shape-based methods, where, for example, the peaks, valleys and curvatures of the smoothed histogram are analyzed. 2. Clustering-based methods, where the gray-level samples are clustered in two parts as background and foreground (object) or alternately are modeled as a mixture of two Gaussians. 3.Entropy-based methods result in algorithms that use the entropy of the foreground and background regions, the cross-entropy between the original and binarized image, etc. 4. Object attribute-based methods search a measure of similarity between the gray-level and the binarized images, such as fuzzy shape similarity, edge coincidence,etc. 5. The spatial methods use higher-order probability distribution and/or correlation between pixels 6. Local methods adapt the threshold value on each pixel to the local image characteristics.
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THRESHOLDING SIMILARITY
BASED
ON
ATTRIBUTE
These algorithms select the threshold value based on some attribute quality or similarity measure between the original image and the binarized version of the image. These attributes can take the form of edge matching, shape, compactness, moments, connectivity, texture, or stability of segmented objects.Tsai considers the graylevel image as the blurred version of an ideal binary image. The thresholding is established so that the first three gray-level moments match the first three moments of the binary image. Hertz and Schafer consider a multi thresholding technique where a thinned edge field, obtained from the gray-level image E(gray), is compared with the edge field derived from the binarized image E(binary). Murthy and Pal were the first to discuss the mathematical framework for fuzzy thresholding, while Huang and Wang proposed an index of fuzziness by measuring the distance between the gray-level image and its crisp (binary) version. Russ has noted that experts in microscopy subjectively adjust the thresholding level at a point where the edges and shape of the object get stabilized. III. GENERAL DEFINITIONS A. Fuzzy Set Theory Fuzzy set theory assigns a membership degree to all elements among the universe of discourse according to their potential to fit in some class. The membership degree can be expressed by a mathematical function that assigns, to each element in the set, a membership degree between 0 and 1. Let X be the universe (finite and not empty) of discourse and an elementof X. A fuzzy set A in X is defined as A= (1)
Fig. 1. Typical shape of the S-function.
Fig. 2. Histogram and the functions for the seed subsets
The S-function is used for modeling the membership degrees. This type of function is suitable to represent the set of bright pixels and is defined as (x)=S (x;a,b,c)
Where b = (1/2) (a+c). The S-function can be controlled through parameters a and c . Parameter b is called the crossover point where . The higher the gray level of a pixel (closer to white), the higher membership value and vice versa. A typical shape of the Z-function is presented in Fig.1. The Z-function is used to represent the dark pixels and is defined by an expression obtained from function as follows : (3) Both membership functions could be seen, simultaneously, in Fig.2. The S-function in the right side of the histogram and the Z- function in the left. B. Measures of Fuzziness A reasonable approach to estimate the average ambiguity in fuzzy sets is measuring its fuzziness. The fuzziness of a crisp set should be zero, as there is no ambiguity about whether an element belongs to the set or not. If , the set maximally ambiguous and its fuzziness should be maximum. Degrees of membership near 0 or 1 indicate lower fuzziness, as the ambiguity decreases.
(2)
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A fuzzy set is called crisp set of A if the following conditions are satised :
(4)
This index is calculated by measuring the normalized distance between A and dened as (5) where n where A,K [1, ]. Depending if k= 1 or 2, the index of fuzziness is called linear or quadratic. Such an index reects the ambiguity in a set of elements. If a fuzzy set shows low index of fuzziness there exists a low ambiguity among elements. IV. EXISTING METHOD This work is an improvement of an existing method based on a fuzziness measure to nd the threshold value in a gray image histogram[4],[5]. The method incorporates fuzzy concepts that are more able to deal with object edges and ambiguity and avoids the problems involved in nding the minimum of a function. However, it has some limitations concerning the initialization of the seed subsets. To achieve an automatic process these limitations must be overcome. In order to implement the thresholding algorithm on a basis of the concept of similarity between gray levels, Tobias and Seara made the assumptions that there exists a signicant contrast between the objects and background and that the gray level is the universe of discourse, a 1-D set, denoted by X. The purpose is to split the image histogram into two crisp subsets, object subset O and background subset F, using the measure of fuzziness previously dened. The initial fuzzy subsets,denoted by B and W, are associated with initial histogram intervals located at the beginning and the end regions of the histogram. The gray levels in each of these initial intervals have the intuitive property of belonging with certainty to the nal subsets object or background. For dark objects B is the subset of O and W is the subset of F or light objects W is the subset of F and B is the subset of O. These initial subsets W and F are modified by S and Z membership functions. These subsets are a seed for starting the similarity measure process. A fuzzy region placed between these initial intervals is dened as depicted in Fig. 2. Then, to obtain the segmented version of the gray level image, we have to classify each gray level of the fuzzy region as being object and the background. The classication procedure is done by adding to each of the seed subsets a gray level xi picked from the fuzzy region. Then, by measuring the index of fuzziness of the subsets B {xi} and W {xi}, the gray level is assigned to the subset with lower index of fuzziness (maximum similarity). Applying this procedure for all gray levels of the fuzzy region, we can classify them into object or background subsets. Since the method is based on measures of index of fuzziness, these measures need to be normalized by first computing the index of fuzziness of the seed subsets and calculating a normalization factor according to (6) Where and are the IFs of the subsets W and B, respectively.This normalization operation ensures that both initial subsets have identical index of fuzziness at the beginning of the process. It is a necessary condition since the method is based in the calculation of similarity between graylevels Fig.3 illustrate how the normalization works. For dark objects, the method can be described as follows. 1. Compute the normalization factor . 2. For all gray levels xi in the fuzzy region compute and 3. If W is lower than , then xi is included in set F, otherwise is xi included in set O. For light objects the method performs similarly except for the set inclusion in step3. In this case, if lower than , then xi is included in set O,otherwise xi is included in set F.
Fig. 3. Normalization step and determination of the threshold value
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V. PROPOSED METHOD The concept presented above sounds attractive but has some limitations concerning the initialization of the seed subsets. In [5] these subsets should contain enough information about the regions and its boundaries are defined manually. The proposed method in this paper aims to overcome some of the limitations of the existing method. In fact, the initial subsets are defined automatically and they are large enough to accommodate a minimum number of pixels defined at the beginning of the process. This minimum depends on the image histogram shape and it is a function of the number of pixels in the gray level intervals [0, 127] and [128, 255] . It is calculated as follows: (7)
Where P1 [0,1] and h(xi) denotes the number of occurrences at gray level xi . Equation (7) can be seen as a special case of a cumulative histogram. However, in images with low contrast, the method performs poorly due to the fact that one of the initial regions contains a low number of pixels. So, previous histogram equalization is carried out in images with low contrast aiming to provide an image with significant contrast. Histogram equalization is as a contrast enhancement technique with the objective to obtain a new enhanced image with an uniform histogram. This can be achieved by using the normalized cumulative histogram as the grey scale mapping function. If the number of pixels belonging to the gray level intervals [0,127] or [128,255] is smaller than a value Pmin and M, N are the defined by Pmin=P2MN, where P2 dimensions of the image, the image histogram is equalized. Equalization is carried out using the concept of cumulative distribution function. The probability of occurrence of graylevel in an image is approximated by
Fig. 4. Test images and the corresponding ground-truth images.
A. Calculation of Parameters P1 and P2 To obtain the parameters P1and P2 a statistical approach is used. Parameters P1 and P2 are concerned with the number of pixels of the initial intervals and histogram equalization, respectively.As the parameters are not mutually related, the statistical study is made independently. In this study, 30 test images are used. To determine the P1 parameter the images in the data base presenting a significant contrast are used. Such images exhibit a significant distribution of pixels gray levels over the interval [0,255] and it is not necessary an histogram equalization. For each image, the parameter P1 is chosen to ensure that both the IFs of the subsets W and B provide an increasing monotonic behavior.
(8)
For discrete values the cumulative distribution function is given by
(9) Thus, a processed image is obtained by mapping each pixel with level in the input image into a corresponding pixel with level in the output image using (9).
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TABLE I MINIMUM VALUES OF P(%)
TABLE III PERFORMANCE OF INDIVIDUAL METHODS (%)
TABLE II MINIMUM VALUES OF P(%)
the images with low contrast and parameter P1 calculated earlier, are used. These images present a small contrast with most pixels concentrated in half side of the histogram. For these images, the minimum number of pixels in the gray level intervals [0,127] or [128,255] that ensures the convergence of the method is obtained by trial and error and the parameter P2 is calculated. With these minimum values, Table II is constructed and the mean and standard deviation are also calculated.In this work, the value of P2=20% is used. VI. EXPERIMENTAL RESULTS In order to illustrate the performance of the proposed methodology,14 images are randomly selected from our original 30 images database. A manually generated ground-truth image has been defined for each image and used as a gold standard. Original images and their gold standard are illustrated in Fig. 4. Results are compared with two well established methods: the Otsus technique (OTSU) [13] and Fuzzy C-means clustering algorithm (FCM)[6]. In this way, a comparison between fuzzy and non fuzzy threshold algorithms is carried out and the resultsof the three techniques are presented in Fig.5. Performance is obtained by comparing the gold standard image with the corresponding image provided by the three different methods. To measure such performance, a parameter, based on the misclassification error, has been used. Thus
If P2 is too high, the fuzzy region between the initial intervals is too small and the values of gray levels for threshold are limited. On the other hand, if P1 is too low, the initial subsets are not representative and the method does not converge. With these minimum values of that ensure the convergence, Table I is constructed and the mean( and the standard deviation( ) are calculated. After analysis of the results, the mean value of P1= 39.64% is adopted. To determine the value of the
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seed intervals. Method convergence depends on the correct initialization of these initial intervals. After calculating the initial seeds a similarity process is started to find the threshold point. This property of similarity is obtained by calculating an index of fuzziness. Histogram equalization is carried for low contrast images to increase the performane. To measure the performance of the proposed method the misclassification error parameter is calculated. For performance evaluation purposes, results are compared with two well established methods: the Otsus technique and the Fuzzy C-means clustering algorithm. After results analysis we can conclude that the proposed approach presents a higher performance for a large number of tested images. REFERENCES
[1] W. K. Pratt, (2001) Digital Image Processing, .third ed. New York: Wiley. [2] A. S. Pednekar and I. A. Kakadiaris, (2006)Image segmentation based on fuzzy connectedness using dynamic weights, IEEE Trans. ImageProcess., vol. 15, no. 6, pp. 15551562, Jun. [3] S. Sahaphong and N. Hiransakolwong, (2007)Unsupervised image segmentation using automated fuzzy c-means, in Proc. IEEE Int. Conf. Computerand Information Technology,, pp. 690694. [4] O. J. Tobias, R. Seara, and F. A. P. Soares, (1996)Automatic image segmentation using fuzzy sets, in Proc. 38th Midwest Symp. Circuits andSystems, vol. 2, pp. 921924. [5] O. J. Tobias and R. Seara, (2002)Image segmentation by histogram thresholding using fuzzy sets, IEEE Trans. Image Process., vol. 11, . [6] C. V. Jawahar, P. K. Biswas, and A. K. Ray, (1997)Investigations on fuzzy thresholding based on fuzzy clustering, Pattern Recognit., vol. 30, no. 10, pp. 16051613. [7] K. S. Chuang, H. L. Tzeng, S. Chen, J. Wu, and T. J. Chen, (2006)Fuzzyc-means clustering with spatial information for image segmentation,Comput. Med. Imag. Graph., vol. 30, no. 1, pp. 915, . [8] L. K. Huang and M. J. J. Wang, (1995),Image thresholding by minimizing the measures of fuzziness, Pattern Recognit., vol. 28, no. 1, pp. 4151,.. [9] H. R. Tizhoosh,(2005) Image thresholding using type II fuzzy sets, Pattern Recognit., vol. 38, pp. 23632372. [10] A. Rosenfeld and P. de la Torre, (1983),Histogram concavity analysis as an aid in threshold selection, SMC, vol. 13, no. 3, pp. 231 235. [11] J. S. Wezka and A. Rosenfeld, (1979),Histogram modification for threshold selection, IEEE Trans. Syst., Man, Cybern., vol. SMC-9, pp. 3852. [12] T. Ridler and S. Calvard, (1978),Picture thresholding using an iterative selection method, IEEE Trans. Syst., Man, Cybern., vol. SMC-8, pp.630632, [13] N. Otsu,(1979), A threshold selection method from gray level histograms, IEEE Trans. Syst., Man, Cybern., vol. SMC-9, pp. 6266. . [14] J. Kittler and J. Illingworth, (1986)Minimum error thresholding, Pattern Recognit., vol. 19, no. 1. [15] J. N. Kapur, P. K. Sahoo, and A. K. C.Wong, (1985)A new method for graylevel picture thresholding using the entropy of the histogram, Graph. Models Image Process., vol. 29, pp. 273285. [16] T. Pun, (1980)A new method for gray-level picture thresholding using the entropy of the histogram, Signal Process., vol. 2, no. 3, pp. 223237. [17] M. Sezgin and B. Sankur, (2004)Survey over image thresholding techniques and quantitative performance evaluation, J. Electron. Imag., vol. 13, no. 1, pp. 146165.
Fig 5:
Fig.5. Results of three algorithms.for each image , from left to right :otsustechnique, fuzzy c-means algorithm, and final improved method.
100
(10)
where BO and FO are, respectively, the background and foreground of the original (ground-truth) image, B T and FT are the background and foreground pixels in the resulting image, respectively, |.| and is the cardinality of the set. This parameter varies from 0% for a totally wrong output image to 100% for a perfectly binary image. The performance measure for every algorithm is listed in Table III. Mean and standard deviation are also presented. The methods indicated by IM1 and IM2 represent the improved method without and with histogram equalization, respectively. After comparing results, the improved method with histogram equalization provides, in general, satisfactory results with particular attention in images with imprecise edges. VII. CONCLUSION In this paper, an optimized threshold in image segmentation based on index of fuzziness measure is presented. This work overcomes some limitations of an existing method concerning the definition of the initial
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ROBUST DE-NOISING WITH EXTRACTION OF P-WAVE, T-WAVE, R-PEAK AND QRS COMPLEX IN NORMAL ELECTROCARDIOGRAM AND ANALYSIS WITH THE ABNORMAL ELECTROCARDIOGRAM USING WAVELET TRANSFORMS
R.VINOTH KUMAR1 , P.HARI KRISHNAN2
1 2
Pg Student, Department of Electrical and Electronics, Anna University of Technology,Coimbatore.
Assistant Professor, Department of Electrical and Electronics, Anna University of Technology,Coimbatore.
e-mail: enginevinoth@gmail.com
Abstract- This paper deals with the study and analysis

of ECG signals using wavelet transform. Wavelet Transform provides more reliable and efficient localization in both the time and frequency. Discrete Wavelet Transform (DWT) is used in the ECG signal feature extraction. First step is the de-noising of the ECG signals by removing the corresponding wavelet coefficients at higher scales. Second step is the application of the robust method in extracting P- wave, T-wave, R peak and QRS complex from an ECG signal. In the final step, the analysis of the different abnormal signals with that of the normal signal is done using suitable wavelet tool. Keywords- Electrocardiogram, P- wave, T-wave, R peak and QRS complex, Wavelet Transforms, DWT.
I. INTRODUCTION
The ECG is nothing but the recording of the hearts electrical activity. The deviations in the normal electrical patterns indicate various cardiac disorders. Cardiac cells, in the normal state are electrically polarized. Their inner sides are negatively charged relative to their outer sides. These cardiac cells can lose their normal negativity in a process called depolarization, which is the fundamental electrical activity of the heart. This depolarization is propagated from cell to cell, producing a wave of depolarization that can be transmitted across the entire heart. This wave of depolarization produces a flow of electric current and it can be detected by keeping the electrodes on the surface of the body. Once the depolarization is complete, the cardiac cells are able to restore their normal polarity by a process called repolarization. This is also sensed by the electrodes [1]. The earlier method of ECG signal analysis was based on time domain method. But this is not always sufficient to study all the features of ECG signals. So, the frequency representation of a signal is required. To accomplish this, FFT (Fast Fourier Transform) technique is applied. But the
Unavoidable limitation of this FFT is that the technique failed to provide the information regarding the exact location of frequency components in time. As the frequency content of the ECG varies in time, the need for an accurate description of the ECG frequency contents according to their location in time is essential. This justifies the use of time frequency representation in quantitative electro cardiology. The immediate tool Available for this purpose is the Short Term Fourier Transform (STFT). But the major drawback of this STFT is that its time frequency precision is not optimal. Hence we opt a more suitable technique to overcome this drawback. Among the various time frequency transformations the wavelet transformation is found to be simple and more valuable [2]. The wavelet transformation is based on a set of analyzing wavelets allowing the Decomposition of ECG signals in a set of coefficients. Each analyzing wavelet has its own time duration, time location and frequency band. The wavelet coefficient resulting from the wavelet transformation corresponds to a measurement of the ECG components in this time segment and frequency band.
II. THEORY
Normally, the frequency range of an ECG signal is of 0.05100 Hz and its dynamic range of 110 mV. The ECG signal is characterized by five peaks and valleys labelled by the letters P, Q, R, S, T. In some cases we also use another peak called U. The performance of ECG analyzing system depends mainly on the accurate and reliable detection of the QRS complex, as well as T- and P-waves. The P-wave represents the activation of the upper chambers of the heart, the atria, while the QRS complex and T-wave represent the excitation of the ventricles or the lower chamber of the heart. The detection of the QRS complex is the most important task in automatic ECG signal analysis. Once the QRS complex has been identified a more detailed examination of ECG signal including
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the heart rate, the ST segment etc. can be performed [3]. In the normal sinus rhythm (normal state of the heart) the P-R interval is in the range of 0.12 to 0.2 seconds. The QRS interval is from 0.04 to 0.12 seconds. The Q-T interval is less than 0.42 seconds and the normal rate of the heart is from 60 to 100 beats per minute. So, from the recorded shape of the ECG, it can be said whether the heart activity is normal or abnormal. Amplitude P-wave 0.25 mV R-wave 1.60 mV Q-wave 25% R wave T-wave 0.1 to 0.5 mV Duration P-R interval: 0.12 to 0.20 s Q-T interval: 0.35 to 0.44 s S-T interval: 0.05 to 0.15 s P-wave interval: 0.11 s QRS interval: 0.09 s The normal value of heart beat lies in the range of 60 to 100 beats/minute. A slower rate than this is called bradycardia (Slow heart) and a higher rate is called tachycardia (Fast heart). If the cycles are not evenly spaced, an arrhythmia may be indicated. If the P-R interval is greater than 0.2 seconds, it may suggest blockage of the AV node. Certain disorders, involving heart valves cannot be diagnosed from ECG. Other diagnostic techniques such as angiography and echocardiography can provide information not available in ECG. Each action potential in the heart originates near the top of the right atrium at a point called the pacemaker or sinoatrial (SA) node. The wave generated by action potential, terminates at a point near the center of the heart, called the atrioventricular (AV) node. The horizontal segment of this waveform preceding the P-wave is designated as the baseline or the isopotential line. The P-wave represents depolarization of the atrial musculature. The QRS complex is the combined result of the repolarization of the atria and depolarization of the ventricles, which occur almost simultaneously. The T-wave is the wave of ventricular repolarization, where as the U-wave, if present is generally believed to be the result of after potentials in the ventricular muscle. So, the duration amplitude and morphology of the QRS complex is useful in diagnosing cardiac arrhythmias, conduction abnormalities, ventricular hypertrophy, myocardial infection and other disease states . Figure 1. A typical normal ECG waveform
III. WAVELET TRANSFORM

The Wavelet Transform is a time-scale representation that has been used successfully in a wide range of applications, in particular signal compression. Recently, wavelets have been applied to numerous problems in Electrocardiology, including data compression, analysis of ventricular late potentials, and the detection of ECG characteristic points. The Wavelet Transformation is a linear operation that decomposes the signal into a number of scales related to frequency components and analyses each scale with a certain resolution. The WT uses a short time interval for evaluating higher frequencies and a long time interval for lower frequencies. The wavelet transform is a convolution of the wavelet function (t) with the Signal x(t) . Orthonormal dyadic discrete wavelets are associated with scaling Functions (t) . The scaling function can be convolved with the signal to produce Approximation coefficients S. The discrete wavelet transform (DWT) can be written as (1) choosing an orthonormal wavelet basis we can reconstruct the original [5]. The approximation coefficient of the signal at the scale m and location n can be written as (2) But the discrete input signal is of finite length N. So the range of scales that can be investigated is 0 < m < M. Hence a discrete approximation of the signal can be written as By
(3)
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detail that is missed by other wavelet algorithms, like Haar wavelet algorithm. Even if a signal is not represented well by one member of the Daubechies family, it may still be efficiently represented by another.
where the mean signal approximation at scale M is X M(t) = SM,n M,n(t) and detail signal approximation corresponding to scale m, for finite length signal is given by (4)
IV. METHODOLOGY
The signal approximation at a specific scale is a combination of the approximation and detail at the next lower scale. xm(t) = xm-1(t) dm(t) (5)
REMOVAL OF THE NOISE Baseline Drift Removal

Baseline wandering is one of the noise artifacts that affect ECG signals. We use the median filters (200-ms and 600-ms) [5] to eliminate baseline drift of ECG signal. The process is as follows The original ECG signal is processed with a median filter of 200-ms width to remove QRS complexes and P waves. The resulting signal is then processed with a median filter of 600-ms width to remove T waves. The signal resulting from the second filter operation contains the baseline of the ECG signal. By subtracting the filtered signal from the original signal, a signal with baseline drift elimination can be obtained. After removing baseline wander, the resulting ECG signal is more stationary and explicit than the original signal. However, some other types of noise might still affect feature extraction of the ECG signal. In order to reduce the noise many techniques are available like Digital filters, Adaptive method and Wavelet Transform thresholding methods. Digital filters and Adaptive methods can be applied to signal whose statistical characteristics are stationary in many cases. However, for non stationary signals it is not adequate to use Digital filters or Adaptive method because of loss of information. To remove the noise, we use Discrete Wavelet transform. This first decomposes the ECG signal into several subbands by applying the Wavelet Transform, and then modifies each wavelet coefficient by applying a threshold function, and finally reconstructs the denoised signal. The high frequency components of the ECG signal decreases as lower details are removed from the original signal. As the lower details are removed, the signal becomes smoother and the noise disappears since noises are marked by high frequency components picked up along the ways of transmission. This is the contribution of the discrete Wavelet Transform where noise filtration is performed implicitly. In order to extract information from the ECG signal, the raw ECG signal should be processed. ECG signal processing can be roughly divided into two stages by functionality: Pre-processing and Feature Extraction as shown
WAVELET SELECTION
The use of the Wavelet Transform has gained popularity in time-frequency analysis because of the flexibility it offers in analyzing basis functions. The selection of relevant wavelet is an important task before starting the detection procedure. The choice of wavelet depends upon the type of signal to be analyzed. The wavelet similar to the signal is usually selected. The are several wavelet families like Harr, Daubechies, Biorthogonal, Coiflets, Symlets, Morlet, Mexican Hat, Meyer etc. and several other Real and Complex wavelets. However, Daubechies (Db4) Wavelet has been found to give details more accurately than others [. Moreover, this Wavelet shows similarity with QRS complexes and energy spectrum is concentrated around low frequencies. Therefore, we have chosen Daubechies (Db4) Wavelet for extracting ECG features in our application. The Daubechies Wavelet is shown in Fig. 4.
Figure 2. Daubechies wavelet Daubechies [4] wavelet is chosen although the Daubechies algorithm is conceptually more complex and has a slightly complicated computations, yet this algorithm picks up minute
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The energy decreases if the scale is larger then 24. The energy of motion artifacts and baseline wander (i.e., noise) increases for scales greater then 25. Therefore, it can be choosed to use characteristic scales of 21 to 24 for the wavelet. The detection of the QRS complex is based on modulus maxima of the Wavelet Transform. This is because modulus maxima and zero crossings of the Wavelet Transform correspond to the sharp edges in the signal. The QRS complex produces two modulus maxima with opposite signs, with a zero crossing between them shown in Fig. 4. Therefore, detection rules (thresholds) are applied to the Wavelet Transform of the ECG signal. The Q and S point occurs about the R Peak with in 0.1second. The left point denoted the Q point and the right one denotes the S point. Calculating the distance from zero point or close to zero of left side of R Peak within the threshold limit denotes Q point. Similarly the right side denotes the S point.
in Fig. 3.
ECG SIGNAL
PRE PROCESSING
R PEAK AND QRS COMPLEX
IDENTIF ICATION
T WAVE DETECTION
P WAVE DETECTION
Figure 3. Structure of ECG signal processing Feature Extraction is performed to form distinctive personalized signatures for every subject. The purpose of the Feature Extraction process is to select and retain relevant information from original signal. The Feature Extraction stage extracts diagnostic information from the ECG signal. The Pre-processing stage removes or suppresses noise from the raw ECG signal.
A. Pre-processing
ECG signal mainly contains noises of different types, namely frequency interference, baseline drift, electrode contact noise, polarization noise, muscle noise, the internal amplifier noise and motor artifacts. Artifacts are the noise induced to ECG signals that result from movements of electrodes. One of the commonest problems in ECG signal processing is baseline wander removal and noise suppression.
Figure 4. Maxima, Minima and Wavelet crossing at scale 2. Most of the energy of the QRS complex lies between 3 Hz and 40 Hz. The 3-dB frequencies of the Fourier Transform of the wavelets indicate that most of the energy of the QRS complex lies between scales of 23 and 24, with the largest at 24. The energy decreases if the scale is larger then 24. The energy of motion artifacts and baseline wander (i.e., noise) increases for scales greater than 25. Therefore, we choose to use characteristic scales of 21 to 24 for the wavelet to detect QRS complex . The Q and S waves are high frequency and low amplitude waves and their energies are mainly at small scale. So, the detection of these waves is done with WT at lowscale. The onset and offset of the QRS complex are detected by using scale 22. From the modulus maximum pair of the R wave, the beginning and ending of the first modulus maxima before and after the modulus maximum pair are detected within a time window. These correspond to QRS onset and offset points.
B. Detection of R peak and QRS

In order to detect the peaks, specific details of the signal are selected. The detection of R peak is the first step of feature extraction. The R peak in the signal from the Modified Lead II (MLII) lead has the largest amplitude among all the waves compared to other leads. The QRS complex detection consists of determining the R point of the heartbeat, which is in general the point where the heartbeat has the highest amplitude. A normal QRS complex indicates that the electrical impulse has progressed normally from the bundle of His to the Purkinje network through the right and left bundle branches and that normal depolarization of the right and left ventricles has occurred. Most of the energy of the QRS complex lies between 3 Hz and 40 Hz .The 3-dB frequencies of the Fourier Transform of the wavelets indicate that most of the energy of the QRS complex lies between scales of 23 and 24, with the largest at 24.
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signs are -/+. When there is only one modulus maxima present, the + sign indicates a T wave that consists only in a ascending. When the sign is -, we see a T wave formed by an descending. The zero crossing between the modulus maxima pair corresponds to the peak of the T wave.
C. Detection of P and T waves 1) P wave detection

The P wave generally consists of modulus maxima pair with opposite signs, and its onset and offset correspond to the onset and offset of this pair. This pair of modulus maxima is searched for within a window prior to the onset of the QRS complex. The search window starts at 200 ms before the onset of the QRS complex and ends with the onset of the QRS complex. The modulus maxima is a point where Wf (23 , ) is at maximum (the slope of Wf (23 , ) will equal be zero). The zero crossing between the modulus maxima pair corresponds to the peak of the P wave .
4) Onset and Off set of T wave

The T wave has characteristics similar to the P wave. The modulus maxima correspond to the maximum slopes between the onset of the T peak, and the offset of the T peak. The search for the onset of the T wave is carried out between the first modulus maxima corresponding to the T wave and the QRS offset. The detection procedure is the same as that for the P wave, except that the search window follows the QRS complex. The T wave onset is considered to be same as the offset of proceeding QRS complex.
2) Onset and Off set of P wave

To find the onset, a backward search is made from the point of modulus maxima that is on the left of the zero crossing, to the start of the search window, until a point is reached where Wf (23 , ) becomes equal to or less than 5% of the modulus maximum. This point is marked as the onset of the P wave. Similarly a forward search is made from the point of modulus maxima that is on the right of the zero crossing, to the end of search window, until a point is reached where Wf (23 , ) becomes equal to or less than 5% of the modulus maximum (modulus minimum). This point is marked as the offset of the P wave.
V. WAVELET ANALYSIS
The wavelet analysis of ECG signal is performed using MATLAB software. MATLAB is a high performance; interactive system which allows to solve many technical computing problems. The MATLAB software package is provided with wavelet tool box. It is a collection of functions built on the MATLAB technical computing environment. It provides tools for the analysis and synthesis of signals and images using wavelets and wavelet packets within the MATLAB domain. The normal ECG wave form and the waveforms with abnormalities are shown in Figures 5,6 and 7.
3) T wave detection
A normal T wave and its transform clearly display a modulus maxima pair with opposite signs [6]. The T wave is found at the zero-crossing between the two modulus maxima. The T waves energy is mainly preserved between the scales 23 and 24. Therefore it was more appropriate to turn away from the dyadic scales and to choose the scale 10 for the WT. The next step consists of the search for modulus maxima. At scale 10 we analyzer a signal and search for modulus maxima larger than a threshold . This threshold is determined by using the Root Mean Square (RMS) of the signal between two R-peaks. When there are two or more modulus maxima with the same sign, the largest one is selected. After finding one or more modulus maxima, it is possible to determine the location and character of the T wave. The first situation occurs when there is a modulus maxima pair with opposite signs. This indicates a small hill when the signs are +/- and a small inverted hill when the
Figure 5. Normal sinus rhythm.
Figure 6. Sinus tachycardia.
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Transformation is worth investigating in P- and Twave recognition. Wavelet technique can be used in identification of the ECG changes resulting from acute coronary artery occlusion and are able to identify specific detailed time frequency Components of ECG signal, which are sensitive to transient ischemia and eventual restoration of electrophysiological function of the myocardial tissue. The practical benefit of the wavelet based ECG approach is that T-wave abnormalities can be assessed without the need for T-wave end point identification. The wavelet transformation is a new promising technique in non-invasive electro cardiology providing improved methods for late potential detection. It can be observed that the peaks of QRS complexes flatten and P- and T-waves containing lower frequencies become more visible. At the same time the details at lower scales constitutes the higher frequencies of the signal. The benefit of the wavelet transformation lies in its capacity to highlight the details of the ECG signal with optimal time frequency resolutions. Since the application of wavelet transformation in electro cardiology is relatively new field of research, many methodological aspects (Choice of the mother wavelet, values of the scale parameters) of the wavelet technique will require further investigations in order to improve the clinical usefulness of this novel signal processing technique. Simultaneously diagnostic and prognostic significance of wavelet techniques in various fields of electro cardiology needs to be established in large clinical studies.
Figure 7. Sinus bradycardia. The commonly known abnormalities are considered and the waveforms corresponding to these abnormalities are loaded in to wavelet tool box and the coefficients plots are compared with those of Normal ECG. Different standard wavelets have been tried and Daubechies wavelet (db10) was found to be the most suitable for the analysis of ECG signals. Different abnormalities result in different changes in the coefficients. From the results of the wavelet toolbox the following observations were made and shown in Table 1.
S.NO 1 2 3 4 5 6 7 8
NAME OF ABNORMALITY DEXTROCARDIA TACHYCARDIA BRADYCARDIA HYPERKALEMIA MYOCARDIAL ISCHAEMIA HYPERCALCAEMIA SINOATRIAL BLOCK SUDDEN CARDIAC DEATH
CHARACTERIS -TIC FEATURES INVERTED PWAVE R-R INTERVAL < 0.6 s R-R INTERVAL > 1s TALL T-WAVE AND ABSENCE OF P-WAVE INVERTED TWAVE QRS INTERVAL < 0.1 s COMPLETE DROP OUT OF A CARDIAC CYCLE IRREGULAR ECG
REFERENCES
[1] L. Cromwell, F.J. Weibell, E.A. Pfeiffer (2005) Biomedical Instrumentation and Measurements, Prentice Hall of India, New Delhi. [2] C.S. Burrus, R.A. Gopinath, H. Guo, (1997) Introduction to Wavelets and Wavelet Transforms, a Primer, Prentice Hall Inc. [3] C. Li, C. Zheng (1993) Proc. Annual Int. Conf. IEE Eng. in Med. & Biol. Soc., San Diego, California, 330331. [4] I. Daubechies (1992) Ten Lectures on Wavelets, CBMS-NSF Lecture Notes nr. 61, SIAM, Philadelphia. [5] P. de Chazal, C. Heneghan, E. Sheridan, R.Reilly, P. Nolan, M. O'Malley, Automated Processing of the Single-Lead Electrocardiogram for the Detection of Obstructive Sleep Apnoea, IEEE Trans. Biomed. Eng., 50(6): 686-689, 2003. [6] Cuiwei Li, Chongxun Zheng, and Changfeng Tai, Detection of ECG Characteristic Points using Wavelet Transforms, IEEE Transactions on Biomedical Engineering, Vol. 42, No. 1, pp. 21-28, 1995.
Table 1. Various abnormalities and their characteristic features
VI. CONCLUSION
One of the crucial steps in the ECG analysis is to accurately detect the different waves forming the entire cardiac cycle. Especially the wavelet
465
Runtime Partial Reconfiguration of FIR Filter

M. Mubarak Ali M.Tech(VLSI) PG Scholar, SASTRA University Thanjavur INDIA
Abstract- This paper presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters using Xilinx FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This FIR filter design method shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.
I. INTRODUCTION
R. Arun, M.Tech(VLSI) PG Scholar, SASTRA University

Thanjavur INDIA
II. RECONFIGURABLE FIR FILTER DESIGN
FIR filters are employed in the majority digital signal processing (DSP) based electronic systems. The emergence of demanding applications (image, audio/ video processing and coding, sensor filtering, etc.) in terms of power, speed, performance, system compatibility and reusability make it imperative to design the reconfigurable architectures. This paper presents a partially reconfigurable FIR filter design that targets to meet all the objectives(low-power consumption, autonomous adaptability/reconfigurability, fault-tolerance, etc.) on the FPGA. FPGAs are programmable logic devices that permit the implementation of digital systems. They provide an array of logic cells that can be configured to perform a given functionality by means of a configuration bitstream. Many of FPGA systems can only be statically configured. Static reconfiguration means to completely configure the device before system execution. If a new reconfiguration is required, it is necessary to stop system execution and reconfigure the device it over again. Some FPGAs allow performing partial reconfiguration, where a reduced bitstream reconfigures only a given subset of internal components. Dynamic Partial Reconfiguration (DPR) allows the part of FPGA device be modified while the rest of the device (or system) continues to operate and unaffected by the reprogramming [1]. Module-based partial reconfiguration was proposed by Xilinx [3][4]. And now many researchers have been proposed many partial reconfiguration methods (JBits, PARBIT, etc) [1][2]. The modular design flow allows the designer to split the whole system into modules.
The FIR filter computes an output from a set of input samples. The set of input samples is multiplied by a set of coefficients and then added together to produce the output as shown in Fig. 1. Implementation of FIR filters can be undertaken in either hardware or software [5]. A software implementation will require sequential execution of the filter functions. Hardware implementation of FIR filters allows the filter functions to be executed in a parallel manner, which makes improved filter processing speed possible but is less flexible for changes. Thus, reconfigurable FIR filter offers both the flexibility of computer software and the ability to construct custom high performance computing circuits. Fig. 2 shows the partial reconfigurable m n order FIR filter, which consists of m n order filter modules and right side module. These FIR filter is consisted of m filter modules, which connected by bus macros on FPGA. And each filter module consists of n/2 reconfigurable multiply-accumulate (rMAC) unit, which includes the serial-to-parallel register to get coefficient inputs in serial.
Fig 1: n-tap transposed FIR filter
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processing, 20-tap FIR filter is composed by partial reconfiguration of module1 showing Fig. 3(b). Final Module Assemble: In the phase, designer assembles on system from partially generated modules. All partial modules generated in active module implementation step are combined to the top-level module.
III. EXPERIMENT AND RESULT
Fig 2: Block diagram of (a) partial reconfigurable m n order FIR filter, (b) reconfigurable multiply-accummulate (rMAC) modules
II. IMPLEMENTATION This section describes the implementation method of 20-tap FIR filter, which is reconfigured partially from 12-tap FIR filter. The whole system is implemented on a Xilinx Virtex2p30 FPGA device. A. HDL Coding and Synthesis This step is composed to following two phase: Top Module Design: In this phase, designer must consider each sub-module interconnection, area assignment and bus macro assignment. Reconfigurable Sub-module Design: This phase is same to traditional HDL design method. But designer must consider input and output assign rule for partial reconfiguration. B. Module-Based Design Modular Design Implementation step comprises following three phase: 1) Initial budget phase, 2) Active module implementation, 3) Final assembly. Initial Budget: In this phase, the team leader assigns top-level constraints to the top-level design. Top-level constraint needs to area constraint and bus-macro assignment. This step is as sequence of top module design. In this step, designer must do bus macro manual setting, sub module area constraint by using floor planner and top module IOB assignment. Bus macro is limited by target size. Through equation (1), designer can estimate maximum usable bus macro. Active Module Implementation: In this phase, the team members implement the reconfigurable modules. That is, partially reconfigurable sub-modules are generated by top module and .ucf file. Each sub-module generates a partial bit stream during this step. Fig. 3 shows a post-PAR placement and routing) diagram. Through n-order filter module1 is reconfigured to bypass module and module2 is reconfigured to 4-tap module on 12-tap FIR filter while other module is
The partial reconfiguration of reconfigurable symmetric transposed FIR filters was implemented on Xilinx Virtex2pro FPGA device using test environment shown in Fig. 4[6]. XUPV2P FPGA test board and Agilent logic analyzer were used for board level verification. And configuration bitstream download is operated by Xilinx Platform Cable USB and IMPACT. For dynamic partial reconfiguration experiment, the partial reconfigurable module1 and module2 were reconfigured bypass module and 4-tap module respectively while other areas of modules remain operational. For verification, we have performed following two methods. First, 12-tap and 20-tap FIR filters before/after partial reconfiguration have been simulated to verify the output results on FPGA test board using Xilinx ChipScope Pro Analyzer. Second, each module has been assigned by identification number such as bypass=00, 2-tap=01, 4-tap=10, 6-tap=11, and then during the partial reconfiguration process the waveform of logic analyzer shows the change of identification number to verify the partial reconfiguration of FIR filter. Because most of modules are operating except reconfigured module, module identification number is changed continuously. After completing DPR, the waveform shows the output change from 3D(111101) to 31 (110001). This result shows that module2 is reconfigured partially from 6-tap module to bypass module. And measured reconfiguration time shows about 112.5 ms. Otherwise, the full reconfiguration is processed after FPGA reset. Measure reconfiguration time is about 3.05 s. Thus the reconfiguration time of DPR FIR filter is reduced about 1/30 compared to full reconfiguration of FIR filter. For performance comparison, we have implemented FIR filter using variable multipliers, multiplexer.
Fig 3: Simulated Waveform for FIR Filter
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IV CONCLUSION
In this paper, we present a reconfigurable FIR filter design using dynamic partial reconfiguration, which has area efficiency, flexibility and configuration time advantage allowing dynamically inserting and/or removing the partial modules. The proposed method produces a reduction in hardware cost and allows performing partial reconfiguration, where a reduced bit stream reconfigures only a given subset of internal components. In the future, self-reconfigurable hardware platform using microcontroller unit and configuration memory will be promising solution for automatic partial reconfiguration of digital circuit in the run-time environment.
REFERENCES [1]. Mesquita, D., Moraes, F., Palma, J., Moller, L., Calazanas, N.: Remote and Partial Reconfiguration of FPGAs: tools and trends. International Parallel and Distributed Processing Symposium,(2003). [2]. Raghavan, A. K., Shutton, P.: JPG-A partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs. Proc. Of the International Parallel and Distributed Processing Symposium, (2002) [3]. Xilinx Inc.: XAPP 290: Two flows for Partial Reconfiguration: Module Based or Difference Based. www.xilinx.com, Sept. (2004) [4]. Xilinx Inc.: Development System Reference Guide. www.xilinx.com. [5]. Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays. Springer, (2001). [6]. Xilinx: Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs. Xcell Journal, Xilinx, Fall (2004)
468
Software Power Estimation for Microcontroller Instruction Set

M.Mohamed Asan Basiri
II M.E - Embedded System Technologies Anna University of Technology Coimbatore Coimbatore, Tamilnadu asanbasiri@gmail.com
Mr.N.Kumaresan M.E.,
Lecturer, Department of ECE, Anna University of Technology Coimbatore Coimbatore, Tamilnadu
Abstract - Low power consumption is becoming a critical factor for System-on-a-Chip designs. System level power estimation for SoCs has gained importance with the increase of SoC design complexity. This paper presents a high-level power estimation methodology for microcontrollers in the context of digital SoCs. It is based on System TLM (Transaction Level Modeling) models including a cycle accurate ISS (Instruction Set Simulator) for simulation performance aspects and on fast characterization from gatelevel implementations for accuracy aspects. The experiments show that for average power estimation and power curve estimation, an excellent accuracy has been reached and for a family of high performance, integrated, 32-bit embedded RISC processor ARM 7 TDMI. Keywords - ARM 7 TDMI, circuit state overhead, clock driven sampling circuit, energy driven sampling circuit, instruction base cost, instruction set simulator, system on chip, transaction level modeling.
A software energy estimation model is presented for a family of high performance, integrated, 32-bit embedded RISC processors. This model is significantly less complex than other models, and yet is demonstrated to accurately predict energy consumption to within 8% with 99% confidence based on physical measurements. Factors such as operating frequency, source/destination registers, and operand values are explored. In view of this model, previously proposed optimizations are evaluated for potential energy savings. II BASIC ENERGY MODEL The used energy model of this approach was mainly based on two factors:1) instruction base cost (BC), which is the energy consumed during execution of an instruction, and 2) circuit state overhead (CSO) cost, which describes the energy consumed by the circuit switching activity between two consecutive instructions. As shown in Fig. 1, a linear addition of all cost factors gives an estimation of the consumed energy during the execution of the program. The cost factors are extracted by average measurements of the current drawn by the processor as it repeatedly executes short instruction sequences. To determine the BC of an instruction, a sequence with always the same instruction was used. A loop with several pairs of two instructions minus the BC of each instruction gives the CSO costs of this pair. To overcome the huge characterization effort, several authors presented techniques for minimizing the required measurements by grouping the instructions depending on the functional unit used by the instructions. A modern microprocessor like the 486DX2 is an extremely complex system consisting of several interacting functional blocks. However, this internal complexity is hidden behind a simple interface its instruction set. Thus to model the energy consumption of this complex system, it seemed intuitive to consider individual instructions. Each instruction involves specific processing across various units of the CPU. This can result in circuit activity that is characteristic of each
I INTRODUCTION The power consumption of digital embedded systems is one of the key constraints in the design process. To meet this constraint and to fulfill the requirements requested by the user, energy optimizations of software and hardware are necessary at every stage of the design process. In the case of mobile devices, such user requirements can be, for instance, a higher computational power while having the same budget of energy to not decrease the battery lifetime of the device. However, other benefits of power-aware systems such as lesser cooling efforts become more and more important for customers. To meet those tight design constraints, the energy dissipation in hardware and software has to be minimized at early stages in the design flow. In the modern literature, the term software energy consumption is defined as the amount of energy consumed by a processor during the execution of certain software. According to this definition, a soft ware energy estimation has to be made by an estimation of the energy dissipation caused by the processor on which this software runs. Therefore, to allow parallel hardware and software development, accurate energy models of processors are needed.
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enough not to cause any cache misses. Only the target instructions should execute on the CPU during the experiment and thus system effects like multiple timesharing applications and frequent interrupts cannot be allowed. B .Circuit State Overhead The switching- activity in a circuit is a function of the present inputs and the previous state of the circuit. Thus, it can be expected that the actual energy cost of executing an instruction in a program may be different from the instruction's base cost. This is because the previous instruction in the given program and in the program used for base cost determination may be different. For example, consider a loop of the following pair of instructions: XOR BX,1 ADD AX,DX The base costs of the XOR and ADD instructions are 319.2 and 313.6. The expected base cost of the pair, using the individual base costs would be their average, i.e. 316.4 while the actual current is 323.2. It is greater by 6.8. The reason is that the base costs are determined while executing the same instruction again and again. Thus each instruction executes in what we expect is a context of least change. At least, that is what the observations consistently seem to indicate. When a pair of two different instructions is considered, the context is one of greater change. The cost of a pair of instructions is always greater than the base cost of the pair and the difference is termed as the circuit state overhead. As another example, consider the following sequence of instructions. The base cost and the number of cycles of each instruction is listed alongside. The measured cost was 332.8 (avg. current over 10 cycles) Using base costs we get (309.6+313.6+400.2 x2+308.3 x3+306.5 x3)/10 = 326.8,the circuit state overhead is thus 6.0. It is possible to get a closer estimate if we consider the circuit state overhead between each pair of consecutive instructions. III ENERGY ESTIMATION MODEL To facilitate the portability to other architectures, the energy estimation model has to be as generic as possible. For that reason, a new model has been developed that is a combination of an instruction-level energy model and a data-dependent. The total energy Etotal consumed by a program is the sum over all clock cycles Ntotal of the energy consumption per cycle Ecycle.
instruction and can vary with instructions. This intuition was the starting point for the empirical study that led to the development of the final instruction-level energy model. Under this model each instruction in the instruction set is assigned a fixed energy cost called the base energy cost. The variation in base costs of a given instruction due to different operand and address values is then quantified.
Fig.1 Basic software energy estimation model
The base energy cost of a program is based on the sum of the base energy costs of each executed instruction. However, during the execution of a program, certain inter-instruction effects occur whose energy contribution is not accounted for if only base costs are considered. The first type of inter instruction effect is the effect of circuit state. The second type is related to resource constraints that can lead to stalls and cache misses. The energy cost of these effects is also modeled and used to obtain the total energy cost of a program. The instruction-level energy model described here is based on actual measurements and evolved as a result of extensive experimentation. It is comprehensive and provides all the information needed to evaluate programs in terms of their energy costs. A. Base Energy Cost The base cost for an instruction is determined by constructing a loop with several instances of the same instruction. The average current being drawn is then measured. This current multiplied by the number of cycles taken by each instance of the instruction is proportional to the total energy. While this method seems intuitive if the CPU is executing only one instruction at a given time, most modern CPUs, including the 486DX2 are processing more than one instruction at a given time due to pipelining. However, the following discussion shows that the concept of a base energy cost per instruction and its derivation remains unchanged. Care should be taken in designing the experiments used to determine the base costs. The size of the loop has to be large enough to minimize the effects of the branch statement at the bottom of the loop and small
The energy per clock cycle can further be decomposed into four parts: 1) instruction-dependent energy dissipation Ei; 2) data-dependent energy dissipation Ed;
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processors.
3) energy dissipation of the cache system Ec; 4) the dissipation of all external components Ee, including the bus system, memories, and peripherals,
A. Characterization System After defining the energy estimation model, all needed cost factors of the processor have to be estimated. For each cost factor, a dedicated test bench has to be written, and the current consumption during its execution on the processor has to be measured. To reach an accurate estimation, several hundreds of such characterization steps are required. This leads to a very time-consuming procedure where errors are easily introduced. Therefore, an automated characterization is absolutely essential. For that matter, we have implemented an automated characterization system. The following figure depicts an overview of the tool for automated instruction set characterization. Every characterization step is controlled by a graphical user interface implemented in LabView. First, the information about the processors architecture has to be loaded in the form of a detailed instruction set description. The test bench generator creates all the required assembly programs to characterize all BC and CSO factors for the instructions defined by the description file. The generation of additional test benches to characterize the influence on power dissipation of data dependence, like different operand addresses or values, can be forced by a welldefined data-dependent XML file. Afterward, these test benches are compiled by an architecture-dependent compiler, and the executable programs are loaded one by one on the processor. During the execution of these programs, the processor sets a trigger signal to indicate that the initialization has been completed, and the execution of the characterization code starts. This signal triggers the digitizer, which samples the output of a dedicated power measurement circuit. One of the key requirements for the tool was easy portability to other architectures. For that reason, a modular design of the characterization system has been chosen. To keep the effort of an integration into a new processor tool flow as small as possible, all functions accessing the compiler, the linker, and the processor communication device have been encapsulated into interface modules. Therefore, only these modules have to be adapted to the new architecture. Since the creation of test benches is a platform-specific task, the test bench generator also has to be implemented in a generic way. To provide all required information about the new processor, a dedicated instruction set description file has been defined. The format of this XML-based instruction set description file allows an easy adaptation to the instruction set of most of the modern
Fig. 2 Characterization system overview
After the data acquisition step, software filters eliminate spikes in the current profile. The measurement evaluation and analysis step extracts the cost factors for each characterization test bench and stores them into an energy database. B. Measurement Circuit In the course of implementation of the characterization system, a new energy measurement technique for digital processors has also been developed. This measurement method is based on a current mirror in the power supply line of the processor. To reduce measurement errors introduced by spikes in the instantaneous current profile of digital systems, a dedicated-hardware-based current integration technique has been developed instead of measuring the output current by means of a shunt resistor, as in the below diagram. This novel measurement technique supports two types of energy samplings: 1) clock-driven sampling 2) energy-driven sampling. Clock-driven sampling accurately records the power profile cycle. This method is needed for the characterization of complex operations like branch instructions with delay slots. In such cases, the desired processor state occurs only during one single clock cycle. For all other instructions, the more accurate energy-driven sampling is used. In this case, it is not possible to assign exactly one energy value to each clock cycle because the sampling rate only depends on the current drawn by the processor. This section depicts the usage of the introduced energy estimation model characterized for a MIPS smart
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states. Afterward, the same procedure starts with the discharged capacitor.
card processor in a software-based power profile optimization technique. Since smart cards are powered by an RF field, the average current drawn by the processor has to be minimized to prevent system failures. To evaluate the impact of the power profile on the RF powered energy source, a model of this source, as described in above, has been stressed with the evaluated power profile. The aim of the optimization was to reduce the average current drawn by a software program by means of nonfunctional instructions (NFIs). NFIs are instructions that have no impact on the internal registers of the processor (for instance, NOPs). They can therefore be inserted at any position in a program without changing its behavior. Thus, a minimization of the average current can be reached by inserting NFIs with low-power consumption into instruction sequences that draw a higher current. 1. Clock Driven Sampling Circuit As mentioned above, the clock-driven sampling records the consumed average power given by P =Idd.Vdd during each processor cycle. Since the supply voltage Vdd of processors is constant, the power only depends on the average current Idd. An average measurement of the current can be done by the circuit shown in the following fig. Whereas one capacitor of the circuit is charged with an exact copy of Idd, the other one is discharged over the resistor R. At the end of each clock cycle, the voltage VC on the charged capacitor is sampled, and the capacitors are switched. Assuming that the delay time of the switches is much less than the clock period, the integration interval is given by 1/Fclk, and the average current can be calculated as follows: Idd= VC C Fclk. Rbias in the following fig. is used for biasing purposes. An offset dc value due to Rbias has to be subtracted from the measured value. The switch control circuit delays the processor clock for at least one switch delay. This causes a start of current integration just a tick before the processor clock rises. The reason for this short forward shift of the integration interval is that most of the energy in synchronous circuits is consumed during signal transitions at the beginning of each clock cycle. At the end of a clock period, the processor is in a stable state and consumes only leakage power. Since leakage currents of complimentary metal oxide semiconductor circuits are very small, errors caused by the switching capacitors are minimized. 2. Energy Driven Sampling Circuit The second measurement technique is based on the same principle as the clock-driven sampling described in the previous section. It differs only in the switch control. As shown in the following fig, a comparator compares the voltage VC across the charged capacitor to a precise reference voltage Vref. If VC exceeds Vref , a flip-flop changes this state, and a trigger pulse is generated, which leads to a change in the switch
Fig. 3 Clock driven sampling circuit
Fig. 4 Energy driven sampling circuit
The trigger pulse indicates that the charged capacitor has accumulated a charge of QC =C.Vref , during which time the processor has consumed an energy of E = QC . Vdd. The power profile of the processor can be derived from the time between every pair of Tpulses Tpulse. Because of delays in the switch control circuit, a constant delay Tdelay has to be subtracted from Tpulse to get the right time during which the energy E has been consumed. The average power P between two pulses can be calculated as P =E / (Tpulse - Tdelay). IV RESULT LabVIEW (short for Laboratory Virtual Instrumentation Engineering Workbench) is a platform and development environment for a visual programming language from National Instruments. The graphical language is named "G". Originally released for the Apple Macintosh in 1986, LabVIEW is commonly used for data acquisition, instrument control, and industrial automation on a variety of platforms including Microsoft Windows, various flavors of UNIX, Linux, and Mac OS X. The
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V CONCLUSION AND FUTURE WORK This project is used for estimating power and energy using a constant parameter for power consumption. This model is accurate to within 8% with 99% confidence. We analyzed energy consumption of the ARM7TDMI core in terms of opcodes, register numbers, register values, instruction fetch addresses, data fetch addresses, and the immediate operands in each pipeline stage, respectively. The aim of the optimization was to reduce the average current drawn by a software program by means of nonfunctional instructions (NFIs). NFIs are instructions that have no impact on the internal registers of the processor (for instance, NOPs). They can therefore be inserted at any position in a program without changing its behavior. Thus, a minimization of the average current can be reached by inserting NFIs with low-power consumption into instruction sequences that draw a higher current. In this project, we have presented an environment for automated instruction set characterization of embedded processors based on physical measurements. After a survey of the underlying energy model, the characterization system has been described in detail. This is followed by the introduction into two novel power measurement techniques. At the end, the performance of those power sampling techniques has been depicted, and the simulation result of this approach to ARM 7 TDMI processor has been discussed. The future work of this project is to estimate the power consumption of the ARM 9 TDMI processor instructions. REFERENCES
[1] Manuel Wendt, Matthias Grumer, Christian Steger, Member, IEEE,Reinhold Weiss, Member, IEEE, Ulrich Neffe, and Andreas Muehlberger (2010),Tool for Automated Instruction Set Characterization for Software Power Estimation, vol 59, no. 11.
latest version of LabVIEW is version LabVIEW 2010, released in August 2010. A. Current Estimation Using Clock Driven Circuit
Fig. 5 Current estimation using clock driven circuit for load instruction
B. Current Estimation Using Energy Driven Circuit
[2] Choi Y, Lee I, Cho Y, Joo Y, Lim H, and Chang (2004),Webbased energy exploration tool for embedded systems, IEEE Des.Test.Comput., vol. 21, no. 6, pp. 572586. [3] Dragic M.S and Margala M (2003), A versatile built-in CMOS sensing device for digital circuit parametric test, IEEE Trans. Instrum. Meas., vol. 52, no. 6, pp. 17561764. [4] Flinn J and Satyanarayanan M (1999), PowerScope: A tool for profiling energy usage of the mobile applications, in Proc. 2nd IEEE WMCSA, pp. 110115. [5] Nikolaidis S and Laopoulos T (2002), Instruction-level power consumption estimation of embedded processors for low-power applications, Comput. Stand. Interfaces, vol. 24, no. 2, pp. 133 137. [6] Russell J.T and Jacome M.F (1998), Software power estimation and optimization for high performance, 32-bit embedded processors, in Proc. ICCD:VLSI Comput. Processors, pp. 328333. Fig. 6 Current estimation using energy driven circuit for load instruction [7] Tiwari I, Malik s, and Wolfe A(1994), Power analysis of embedded software:A step towards software power minimization, in Proc. IEEE/ACM ICCAD, pp. 384390.
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Zig Bee based Monitoring of Leg Ulcers

M.dhivya #1, A.Sugantha priyan #2
Department of electrical and electronics engineering, Anna university of technology, Coimbatore, India
2
sugan.eee@gmail.com
Abstract - Chronic ulcers or leg ulcers are wound which stands for long time. This kind of ulcers cant be cured in a normal type. This ulcer mostly affects the elder and paraplegic patients. Owing to this leg ulcer 1% of world population is affected and also 4% of cost spent up by annual budget of National Health Service in U.K. So there is a need to develop a device that able to monitor the patients to care on the wound management under medical counsellor. A new wireless wound mapping device is to be develop, which is based on electrical impedance spectroscopy and involves the multi frequency characterization of the electrical properties of wound tissue under an electrode array also with wireless feature. A main advantage of this wireless wound mapping device is the inclusion of the transducer array into the dressings will protect the ulcer from disturbance and contamination. Also it supports to the healing process, while monitoring the ulcer. The wireless transmission helps to telewound monitor.
Key words Chronic ulcers, impedance spectroscopy, remote wound monitoring
or may take years to do so. These ulcers cause physical stress and financial burden on patients and the entire healthcare system. Unfortunately, this chronic wound does not respond to existing treatments. Research is required to enhance cost effective alternatives, which supports wound healing, reduce pain and improve the quality of life of patients. To reduce the hospital costs the patient has to be discharge as quickly as possible. But to this long term chronic wounds extends this nursing time. So there is a need to monitor the patient remotely. II. ULCER ASSESSMENT TECHNIQUES Recording wound area and volume is a routine part of patient Assessment and provides information about the healing process. This entire collection of wound parameter data helps to identifying short and long-term goals of care and to determine appropriate interventions at each stage. To make this process as cost effective, patients take care on the monitoring of wound parameters. An objective need is to make the healthcare professional to advise the patient on necessary dressing changes, changes in treatment, or if necessary, intervene more directly. By this the patients can get the treatment and assessment from their home itself. It reduces the cost of the nursing time and also will improve their self confidence and quality of life. Tracing wound size is an important part of health care system. Because wounds initial size affect the apparent healing rates. The surface area (S) and its area to perimeter ratio (S/P) are useful to document healing process. An assessment of these parameters is done by computerized planimetry of digital images using suitable software. This helps in plotting healing rate against initial wound area which supports to know the progress of treatment and care. The parameters to be measured woundrelated parameters are Wound volume, Wound area, Maximal wound depth and wound margin. Direct method is inexpensive and convenient although it is time consuming process. In this method uses the invasive technique which may
1. INTRODUCTION Chronic ulcers or pressure ulcers are wounds that cant be cured in the normal type. These wounds do not heal at an early stage of the healing process. If the wounds doesnt show any sign of improvement then this is known as chronic. This ulcer affects mostly to the elder persons over 60 years in age and also affects 25 percent of spinal cord injured persons, paraplegic patients at some stage in their lives. An estimated 1% of the population in industrial countries suffer from this pressure ulcer and the treatment costs up to 2 million a year. It adds the costs up to 4% of the total National Health Service budget in 2004 in U.K also $10 billion is spent each year in the care of leg ulcers in world wide. Much of this cost should be preventable. More than 90% of the cost of treatment is the cost of nurse time. Pressure ulcers are a painful and serious outcome of a failure of routine medical and nursing care. In this leg ulcer the balance between production and degradation is lost and degradation plays a large role. Pressure ulcers may never cure
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III. PROPOSED TECHNIQUE In order to measure ulcers and other wounds conveniently and effectively, a non disruptive 3-D technique is required, preferably operated by means of a small handheld device, which can be used with little training, or more optimally, remotely/ automatically operated, and viewed by a clinician. One technique which could potentially provide non disruptive 3-D measurements is electrical impedance spectroscopy. It is based on the measurement of the tissue impedance and could enable the investigator to not only measure wound area and depth but also to precisely assess the wound brink, and after some calibration measurements, establish the type of tissue present, all without removing the dressing, and thus, avoiding interfering with wound healing. Electrical impedance spectroscopy involves the characterization and analysis of electrical properties of tissue over a range of frequencies and has been used by the authors to characterize and map wounds. A. Impedance Basics: Skin impedance is measured over a range of frequencies, and a suitably large frequency range should be used to encompass the important features, typically 10 Hz to 1 MHz. In the initial measurements, in order to speed up the many measurements required to produce a map of the wound. A more limited range between 11 Hz and 1 kHz was used. The measured impedance data can be displayed in two major ways:
disrupt the healing and lead to contamination. Also the healthy tissues may affect by spreading wound fluid by the invasive technique. In the indirect method the wound parameters are measured with non invasive technique. So there is no harm to the wound. mostly the method follows the counting squares and scaled photograph method. In counting squares the small squares were drawn on the transparency film and it is placed over the wound and the outline is traced. It gives the length and width of wound. but the wound depth cannot be find by this method. Photographic technique is also like the previous method. The reliability of these techniques was based on the investigator. Ruler technique gives the parameters about width and length. But it should be applied only if the wounds are in regular shape. The noncontact photographic technique (planimetry) wipes out the risk of contamination and disturbance to the wounds. The equipment is bulky and costly. Also the results vary depends upon the camera angle.
Fig. 1 Visit rack from Smith and Nephew The traced transparent film is attached to the electrical clipboard. By this the parameters are obtained. In all the above method gives the data only about the length and width but about the wound depth. Normally the wound depth is measured by inserting a cotton swab in the deepest part of the wound. It would be done many times that will lead to pain full and contamination. Personal digital assistant (PDA)-powered laser digitizer is a recent method. Images of wounds are obtain and recorded. Then it is transferred to electronic patient file. This also depends on camera angle. To date no technique is available that can be readily performed by the patient or his family that would enable them to take a more active role in wound management.
i. ii.
Plotting the imaginary impedance versus the real resistance in the form of a complex impedance plot (see Fig.2). In the form of a Bode diagram.
Usually displays the logarithm of the magnitude of the impedance as a function of the logarithm of the frequency and the same for the phase angle. Both plots enable the investigator to determine equivalent model variables, and therefore, to identify/characterize the tissue type present or the thickness of the tissue under study.
Fig.2 Complex impedance plot
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capacitance and the centre of impedance arc is depressed below the real axis. RP varies considerably between different individuals and under different circumstances. It is basically the current bypassing the capacitive epidermal layers, largely traversing through skin appendages. This parallel resistance varies over time, with sweating and skin preparation. C. Mapping System: A new device has been developed by the authors called ImpediMap, based on impedance spectroscopy, addressing many of the issues outlined earlier. It is targeted at the monitoring of chronic wounds, but could also be utilized in helping to prevent the formation of ulcers as well as in the study of acute wounds or burns. The initial prototype can be seen in Fig. 4 with further improvements presently being developed.
B. Impedance Model: The complex impedance plot for measured skin impedance generally has the form of a depressed semicircular arc (see Fig.2). Cole equation, for such electrical behaviour observed for a wide range of biological tissues. (1) Where R0 = resistance at 0 Hz and R= resistance at infinitely high frequency. The exponent is a descriptor of the level of depression of the observed impedance arc (see Fig. 3) (2)
Fig.3 Equivalent circuit of wound impedance In order to analyze the measured impedance, a simple equivalent circuit model is often used, which was derived from the original Lapicque model, and adapted by Cole and Fricke. The outer, dry epidermis shows capacitive behaviour at high frequencies. At low frequencies, however, only resistive properties can be measured for this layer. This has lead to the modelling of the epidermis by a resistor Rp in parallel with a capacitor C. Underneath the epidermis lie the moister dermal layers. Currents can flow through these layers relatively unimpeded and they are therefore represented by a small resistance Rs in series with the aforementioned parallel circuit. It has been observed, however, that the phase angle of the capacitive element of the circuit, although constant over a considerable range of frequencies, is not the expected 90 of an ideal capacitor. This has lead to the use of an empirical constant-phase element, as shown in Fig. 4, which has a phase angle typically between 45 and 90. The constant phase element can be described as follows. ZCPA = K (j) (3) (4) If = 1, = 90, the capacitive element is a true capacitance and the arc has its centre on the x-axis. If is less than unity, as is generally the case, < 90, the capacitive element is not an ideal Fig.5 Envisaged use of a PDA device Skin re-grows the skins parallel resistance RP increases dramatically so much that it was quickly difficult to measure accurately within the frequency range chosen. There was a major difference in the Fig.4 Electrode array An array of electrodes is embedded in a sterile carrier dressing and the tissue impedance underlying each of the individual electrodes is measured by the associated system and the data presented to the clinician in a range of formats to provide information concerning the wound and the healing progress in terms of, for example, wound size/volume and wound severity. Simplistically, intact skin has a high impedance, whereas an open wound has a very low impedance, the latter largely due to the resistance Rs , of the underlying dermis. Maps with pixels of varying resistance/impedance are produced to show the shape and size of the wound, and to establish the degree of healing, all without removing the dressing (see Fig. 5).
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battery powered to ensure patient safety. Discreet frequencies between 11 and 935 Hz were initially chosen for early trials. The more and lower the frequencies used in the measurement, the longer the total measurement time will be for the multi electrode array.
magnitude of the impedance for an open wound and that of even only partially re-grown skin. IV. HARDWARE MODEL The hardware structure (Fig. 6) is used to measure the signal from transducer. The device is
Zig bee Fig.6 Hardware overview of the wound-mapping system Healing progress in terms of, for example, wound size/volume and wound severity. The measurement current is achieved by a voltagecontrolled Current source, chosen to restrict the A current-to-voltage converter is used to output current to a safe limit, i.e., 10 A (rms). The convert the applied current through the electrodeoutput signal from the voltage controlled current skin impedance into a voltage to be measured. This source is then switched to the electrode array via a voltage is later amplified by a second stage to bank of multiplexers. An instrumentation amplifier ensure that good use is made of the A/Ds range measures the voltage between each electrode under (5 V). Digital Signal Processing is used in a wide test and reference electrode. The output signal from range of applications including: the instrumentation amplifier is fed into an Telecommunications, Data communications, amplifier/filter stage for further conditioning. The Wireless communications, Image enhancement and skin impedance sensing electrodes are use to processing. measure the growth of the skin. An array of electrodes is embedded in a sterile carrier dressing and the tissue impedance underlying each of the individual electrodes is measured by the associated system and the data presented to the clinician in a range of formats to provide information concerning the wound and the In fact, by wireless communication, the user interface sends measured data and information on the metrological characteristics of the system to a DSP. The best solution has been obtained after a redesign of the measurement system by using wireless modules to remotely transmit data to the DSP board, reducing possible damages or interferences during the computational process.
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ultrasound and photography, Skin Res. Technol., vol. 9, pp. 116121, 2003. 8. T. A. Krouskop, R. Baker, and M. S. Wilson, A noncontact wound measurement system, J. Rehabil. Res. Dev., vol. 39, pp. 337345, 2002. 9. H. A. Thawer, P. E. Houghton, M. G. Woodbury, D. H. Keast, and K. E. Campbell, A comparison of computer-assisted and manual wound size measurement, Ostomy Wound Manage., vol. 48, pp. 4653, 2002. 10. British Standard: Medical electrical equipment. Part 1: General requirements for safety Collateral standard Safety requirements for medical electrical systems, British Standard Institute, London, U.K., 2001. 11. N. Cullum, E. A. Nelson, K. Flemming, and T. Sheldon, Systematic reviews of wound care management: (5) beds; (6) compression; (7) laser therapy, therapeutic ultrasound, electrotherapy and electromagnetic therapy,Health Technol. Assess., vol. 5, pp. 1221, 2001. 12. A. H. Lackermeier, A novel multichannel Impedance analyser for the in vivo investigation of the electrical properties of human skin during transdermal drug delivery, Ph.D dissertation, University of Ulster,Belfast, 2000. 13. D. C. Salter, Examination of stratum corneum hydration state by electrical methods, in Skin Bioengineering, vol. 26, P. Elsner, A. O. Barel, E. Berardesca, B. Gabard, and J. Serup, Eds. Basel, Switzerland: Karger, 1998, pp. 3847. 14. L. L. Baker, S. Rubayi, F. Villar, and S. K. DeMuth, Effect of electricalStimulation waveform on healing ulcers in humans with spinal cord injuries, Wound Repair Regen., vol. 4, pp. 72 79, 1996. 15. E. T. McAdams and J. Jossinet, Tissue impedance a historical overview, Physiol. Meas., vol. 16, pp. A1A13, 1995. 16. B. Rigaud, L. Hamzaoui, N. Chauveau, M. Granie, J. P. S. Dirinaldi, and J. P. Morucci, Tissue characterization by impedance a multifrequency approach, Physiol. Meas., vol. 15, pp. A13A20, 1994. 17. E. T. McAdams, A. H. Lackermeier, and J. Jossinet, AC impedance of the hydro gel-skin interface, in Proc. 16th Annu. Int. Conf. IEEE Eng. Med. Biol. Soc. Eng. Adv.: New Oppor. Biomed. Eng. (Cat. no.94CH3474-4), 1994, pp. 870871. 18. A. Stefanovska, L. Vodovnik, H. Benko, and R. Turk, Treatment of chronic wounds by means of electric and electromagnetic fields. II: Value of FES parameters for pressure sore treatment, Med. Biol. Eng. Comput., vol. 31, pp. 213220, 1993. 19.J. W. Griffin, E. A. Tolley, R. E. Tooms, R. A. Reyes, and J. K. Clifft, A Comparison of photographic and transparency-based methods for measuring wound surface-area, Phys. Ther., vol. 73, pp. 117122, 1993 20. C. Majeske, Reliability of wound surface-area measurements, Phys. Ther., vol. 72, pp. 138141, Feb. 1992. 21. E. T. McAdams and J. Jossinet, The importance of electrode-skin impedance in high resolution electrocardiogram, Automedica, vol. 13, pp. 187208, 1991. 22. C. Gabrielli, Use and applications of electrochemical impedance techniques schlummberger technical report, Schlummberger, Hague, The Netherlands, Rep. 12860013, 1990. 23. E. T. McAdams and J. Jossinet, Electrode-skin impedance in impedance tomography, in Proc. Meeting Electr. Impedance Tomogr., 1990, pp. 14 19. 24. Grimnes, Impedance measurement of individual skin surface electrodes, Med. Biol. Eng. Comput., vol. 21, pp. 750 755, 1983. 25. D. C. Salter, A study of some electrical properties of normal and pathological skin in vivo, Ph.D. dissertation, University of Oxford, Oxford, 1981.
ZigBee is rapidly becoming the standards of choice for low data rate wireless applications. IEEE 802.15.4 defines a robust radio (PHY) and medium access control (MAC) layer. ZigBee supports star, mesh and cluster-tree topologies. Unlike Bluetooth or wireless USB devices, ZigBee devices have the ability to form a mesh network between nodes. By this wireless technique the data is transfer to clinician from patients home. V. CONCLUSION The existing wound measurement methods were studied and the problems are manifested. By using a non disruptive 3-D technique, A zig bee enabled wireless device is plan to develop that will enable clinicians to monitor wound healing without disturbing, the wound-healing process. A non disruptive 3-D technique is nothing but a electrical impedance spectroscopy. According to this if the skin re-grows, the skins parallel resistance RP increases dramatically. The recorded data can then be sent to the clinician through wireless transmission if a result exceeds the boundaries. This will enable patients and their families to optimally manage the ulcers themselves under the guidance of a clinician. The correlation between the parameters, reepithelialisation rate is expected to be 95%. The vision for the future is to greatly miniaturize the device and the electrodes (increasing their number/density) and to incorporate a wireless transmitter into the electrode array/ dressing, thus enabling the use of a PDA or similar device to display and store the recorded data. VI. REFERENCE
1. Remote wound monitoring of chronic ulcers, Sonja A. Weber, Niall Watermen, Jacques Jossinet, vol 14, no 2, march2010. 2. Visitrak Wound Measurement System, Smith and Nephew Healthcare, Hull, U.K., 2008. 3. Aranz Medical Silhouette Wound Imaging, Measurement and Documentation Solution, Aranz Medical Ltd., Christchurch, New Zealand, 2006. 4. T. A. Mustoe, Understanding chronic wounds: A unifying hypothesis on their pathogenesis and implications for therapy, Amer. J. Surg., vol. 187, pp. S65S70, May 2004. 5. G. Bennett, C. Dealey, and J. Posnett, The cost of pressure ulcers in the U.K, Age Ageing, vol. 33, pp. 230235, May 1, 2004. 6. M. Flanagan, Wound measurement: Can it help us to monitor progression in healing?, J. Wound Care, vol. 12, pp. 189194, 2003. 7. M. Dyson, S. Moodley, L. Verjee,W. Verling, J.Weinman, and P.Wilson,Wound healing assessment using 20 MHz
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LOW POWER DESIGN BASED ON VARIABLE INPUT DELAY CMOS LOGIC

Miss kamali.B1 Mr. P.Rajasekaran2 1. PG scholar in Embedded system Technologies 2. Lecturer in Electrical & Electronic engineering department Velalar College of Engineering & Technology, Erode
AbstractWe propose a new complementary metaloxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized permanently on series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on non critical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. I. INTRODUCTION Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The power consumption of these circuits has two components. The dynamic power is consumed only when the circuit performs a function and signals change. Leakage or static power is consumed all the time, i.e., even when the circuit is idle. It is unnecessary and one would like to eliminate it. But there are practical difficulties. Because the advanced CMOS technologies have higher leakage, this component has received much attention. The ways to reduce leakage work at the transistor design and manufacturing process levels. On the other hand, we realize that the dynamic power cannot be eliminated completely because it is caused by the computing activity. It can, however, be reduced by circuit design techniques.
Whenever a logic gate changes state, power is consumed. The state change can be due to the essential logic value changes as well as due to glitches. The latter are not necessary and their elimination is the subject of this paper. II. PRESENT CONTRIBUTION We describe the formulation of an LP using variable input-output gate delay model with an overall delay constraint. This is a variation of the minimum dynamic power LP described in previous publications. In speed-critical designs, the critical path delay should not exceed some given value we will refer to as maxdelay. If the delay requirement is stringent, then the circuit designed using the minimum dynamic power LP may not meet the specification. In such cases, we provide the designer with another version of the LP in which, the design is optimized by adding buffers at selected nets in addition to the input delay elements. We call this the delay specification LP. We describe three possible ways of implementing the variable- input delay gate and its application to low power design. The technique for the sizing of the new gates and delay elements is also discussed in recent publications. Our technique reduces glitches in the circuit thereby reducing. It is true that the quantities and may not be completely independent and reducing alone can potentially increase. Other power reduction techniques such as and can be used in conjunction with the present technique to improve the design quality. Note that these techniques reduce and do not change the power saving from our technique which primarily targets. III. SOLUTION CURVES Let us consider the solution space explored by the proposed LP and the previous LP techniques. Consider the illustration of Fig. 1.1. The solid curve shows the power-delay tradeoff in previous methods with conventional gate design. The circuit designs given by the points on this curve are the fastest minimum power circuits for. If we increase and use
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the proposed delay specification LP, the power delay curve shifts to one of the dotted curves shown in the figure. For a given maxdelay the point on a dotted curve is the solution with minimum dynamic power for the corresponding.
the design consumes less power for the same maxdelay as shown by the dotted-line curves. However, every technology has some maximum and it is difficult to construct gates with any higher delay variability. The limiting power delay tradeoff curve is labeled with. IV. PROPOSED GATE DESIGN Our focus here is on independently changing the delays of interconnects leading to a gate inputs without inserting any gates or buffers, which might consist of their own pull-up and pull-down paths and node capacitances. As described above, it is advantageous to design a gate with differing delays along different input-output paths through the gate. In other words, it is advantageous to design gates with , such that fewer buffers will be needed to high meet the delay specification. We call such a gate variable input-delay gate. In this section, we propose a transistor level implementation of the gate and its characteristics. Consider a two-input NAND gate shown in Fig. 1.2. Suppose, the delay of path 1 to is and that of 2 to 3 is . Then 3 (1) (2) Where and are the input capacitances seen is the series
Fig. 1. Power delay curve and delay specification LP The maximum allowed for the technology is given by . The region of feasible implementations is shown as the shaded region in the figure. Every point in the shaded region is a possible minimum dynamic power solution for a given and a given maxdelay requirement. The lower boundary of this region represents zero-buffer designs. If the gate input to output delay variability is allowed to increase indefinitely, all glitch suppression conditions would be satisfied without increasing the critical path delays. The point in Fig. 1.1 has the same speed as the original circuit prior to power minimization. Any increase in dynamic power over this minimum is caused by the delay buffers inserted to satisfy the technology limit on the allowable. The delay specification LP proposed in this paper effectively exploits the power-delay solution space. Note that for any given maxdelay, the delay specification LP solution consumes less power than the solution. In the proposed delay specification LP, if we use the conventional logic gates, i.e., , we get the same design as obtained by previous methods . This design will be buffer-less only if some large maxdelay was specified. If we use nonzero, the power delay tradeoff curve shifts down to one of the dotted curves shown in Fig. 4. This is because the design with delay specification LP requires fewer buffers than the previous technique (shown by the solid curve) and hence consumes less power. Thus, by increasing for a design, we reduce the power consumption of any given solution from the solid curve to one of the dotted curves for the same maxdelay. As the delay variability upper bound is increased to a higher value,
at the inputs of the gate and
resistance of the ON transistors in the previous stage. A conventional CMOS gate is characterized by a single delay normally assigned to the output. We examine the following four different implementations.
Fig. 2. A conventional 2-input CMOS NAND gate Input capacitance manipulation is the technique is increased without altering . by which
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This is achieved by increasing the sizes of the transistors connected to input 1 such that . Now the delays are, (3) (4) (5) The problem with this implementation is that the resistances of ON transistors in the series path are interrelated and hence the output delay is also altered. The formulation becomes nonlinear. Resistance with a single nMOS pass transistor can be added in series to the path in which extra delay is desired. This scheme is shown in Fig. 1.3. (a) and (b). This nMOS transistor is always ON and hence adds a series resistance to the path 1 to 3. Fig. 4. Always-on CMOS transmission gate This does not degrade the signal but has the disadvantage that it adds an additional transistor. Moreover, gate leakages of the two devices of the CMOS transmission gate can provide power to ground paths. We should point out that the delays obtained either by single nMOS transistor or by the CMOS transmission gate are static. Resistance with a feed through resistive cell is a technique of adding the resistance using a polysilicon serpentine resistor overlaid with silicide blocking. This is the standard way of creating a resistance in an analog circuit. The advantage of these cells is continuous controllability of resistance rather than the discrete control provided by transistors. We did not use this method because of its large area overhead. A. Design Issues Fig. 3. Always on nMOS pass transistor The delays are ) (6) (7) (8) The resistance can be controlled by changing the size of the nMOS transistor Resistance with a CMOS pass transistor (transmission gate) can be added to introduce the extra resistance in the path as shown in Fig. 1.4. (a) and (b) The inserted CMOS pass transistor contains both nMOS and pMOS transistors that are always ON. We selected the single nMOS pass transistor for our design. Some of the underlying reasons are low area overhead, simplicity of integrating it in the a cell library, and the ease of incorporating it in circuitlevel simulation. A previous paper has discussed the CMOS transmission gate delay element and reported that it provides good delay controllability but has poor signal integrity. Since we did not require a standalone delay element, the delay producing transistors were integrated with logic gates whose input delays and output signal integrity are locally analyzed and adjusted. There are several design issues regarding this variable input delay gate design. The delay along a path is varied by changing the series resistance, which is a function of the length of the transistor/transmission gate and hence the delay along the line can be altered by changing the length of the extra transistor/ transmission gate. This transistor cannot be infinitely long because that would increase the voltage drop across it and cause signal integrity issues at the output of the gate. Hence there is a realistic limit to the length of the transistor added and this determines the maximum differential delay that can be added. Raja et al.
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describe this as the gate differential delay upper bound in their low power design. This parameter is related to the technology the gate is implemented in and is called the feasibility condition. Our design analysis determined a of 10 delay units for the 0.25m fabrication process we used. The delay unit is the minimum gate delay for the technology and is the delay of an inverter feeding into another inverter of the same size. The logic 1 state is degraded by the threshold voltage of nMOS transistor. If the signal does not drive the transistors in the logic gate into cutoff, there will be increased leakage. This problem can be alleviated by using a CMOS transmission gate instead of a single transistor. The effect of increased leakage is shown in the results section. The placement of the series transistor with respect to the routing capacitance also needs to be examined. If the routing capacitance is small it does not matter where the transistor is placed in the path. V. RESULTS In this section, we present an application of the new gate design in implementing custom circuits for minimum dynamic Power. Unoptimized Example Circuit Assume that the delays of all gates are the minimum allowed by the technology through sizing of transistors in gates appropriately. We observe that the differential delay, at gates 5 and 6, exceeds the inertial delay and we expect potential glitches. The circuit was simulated for rising signals at all three inputs using Spectre analog simulator from Cadence. The results are shown in Fig. 8. As expected, gates 5 and 6 transition 2 and 3 times, respectively. Buffer Optimized Circuit The buffer optimization using conventional gates requires the use of one buffer for the circuit to operate at the same speed . The optimized circuit with the buffer is shown in Fig. 5. It is implemented using two CMOS inverters and has an overall delay of 2 delay units.
The buffer optimized circuit was simulated for the same vector-pair as the unoptimized circuit. As expected, the optimization eliminated all glitches as shown in Fig. 8. However, the buffer optimization requires that the transition of input 1 should pass through the buffer. This increases the total number of transitions in this Circuit. Low-Power Design with Proposed Gate. When variable input-delay gates are used, the optimized circuit is shown in Fig. 6. We have used the single nMOS transistor implementation here but any of the proposed designs could have been used. We have used the single nMOS transistor implementation here but any of the proposed designs could have been used
Fig. 6. Proposed input delays Circuit-level simulation for the same vector pair is shown in Fig. 7. The glitches at the outputs of gates 5 and 6 are eliminated in this optimized design as well. Circ uit Logic activity Gate transi tions 5 Reduc tion 37.5% Energy consumed Tota Redu l ction Leakage Vec tor 000 Vec tor 111 60.7 pA
550 31.3 fJ % 62.5% 300 62.5 38.1 Fig 6 3 fJ % pA Table.1. Values of Design of example circuits A. Energy Consumption Fig 5
Fig. 5. Two-inverter delay buffer
During the simulation for the three circuits described above, we measured the supply current for the given input vectors and computed the energy. The results are shown in Table I. The simulations were done with Spectre analog simulator from Cadence . As recorded in the table, the unoptimized circuit consumes 800 fJ, the buffer optimized circuit consumes 550 fJ and the new variable-input delay gate circuit consumes 300 fJ. The new gate design achieves substantially higher power saving than the
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buffer optimized design. The total power obtained from the simulator includes the short circuit and leakage components as well. Table I also shows a good correlation between the reduction in the number of transitions and power saving. The power savings of the optimized circuit are due to the following two reasons: Glitches have been removed, which makes the proposed example circuit save power over the unoptimized circuit; B. Leakage Current The introduction of an nMOS pass transistor degrades the signal at the gates of the transistors. This increases the leakage current of the circuit and may even drive the transistors out of cutoff. The current flowing in the steady state is called the quiescent current and is due to the leakage through OFF transistors. The quiescent current is a function of the input vectors at the primary inputs (PIs) of the circuit. To analyze the relative effect, we simulated circuits with a pair of input vectors allowing the transients to completely settle down following each vector. The three circuits simulated for leakage were the unoptimized circuit of Fig. 2, the optimized circuit of Fig. 7, and another optimized circuit obtained by replacing the nMOS pass transistors in Fig. 7 with CMOS transmission gates. This increase is not due to the degradation of the signal but is due to the leakage path added from to through the sidewall capacitance. This is a very minor increase for the 0.25- m fabrication technology but further analysis needs to be done for more recent technologies. C. Benchmark Circuits We optimized several ISCAS85 benchmark circuits for dynamic power. The results in Table II compare the designs done with the new variableinput delay gates to original versions of circuits and those optimized using conventional gates. For each method, two optimized designs were created, one where no increase in the overall delay (maxdelay) was permitted and the other where the overall delay was allowed to increase to twice that of the original design. The original designs were optimized not for power but for speed in the given 0.25- m CMOS technology. Each design had the smallest possible delays along critical paths as well as all other paths in the given technology. We analyzed the circuit at the logic level assuming that it is possible to design such unit or constant delay gates, i.e., gates sized to feed the fan-outs. For each circuit, first an original version (not optimized for glitch removal) was created as a reference. This version used the fastest gates
available in our 0.25- mCMOS technology. These gates have larger transistors and typically consume more power.
Fig. 7. Benchmark circuit These vectors were generated for complete or almost complete stuck-at fault coverage. It is assumed that such vectors provide appreciable logic activity and hence a reasonable estimation of power. Power estimation for all other designs was similar but used the delays obtained from the LP. Next, we redesigned the circuits with variable-input delay gates described in previous sections. An LP determined the input and output delays for all gates under an input differential delay constraint. Each circuit was designed for two overall delays, 1 and 2, respectively, normalized with respect to the corresponding reference design. To meet the maxdelay constraint, some circuits used delay buffers. But in most cases no buffers were required. In the linear program optimization, an upper bound is used on the input differential delay that can be achieved. This upper bound is a technology parameter and is determined through actual design and simulation of gates. When the circuit topology requires very large differential delays, delay buffers must be used to satisfy the glitch removal conditions. The linear program, however, keeps the number of such buffers to a minimum. D. Chip Design and Total Power We did the physical design of the ISCAS85 benchmark circuit c7552. First, an unoptimized design was created. This circuit contained 3827 gates and was implemented with 15 512 transistors. We used gates with smallest size transistors as compared to the fastest gates used in the original design of the previous subsection. The unoptimized circuit, therefore, is slower but consumes less power. Its physical layout was done by the Cadence layout editor. We redesigned the circuit using the proposed variable input delay gates and that design contained
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1435 nMOS transmission gates and one delay buffer, requiring 1439 extra transistors. A third design using the conventional CMOS gates was also implemented. It required 366 delay buffers or 1464 extra transistors added to the unoptimized version.
REFERENCES 1. V. D. Agrawal, Low power design by hazard filtering, in Proc. 10th Int. Conf. VLSI Des., Jan. 1997, pp. 193197. 2. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, Digital circuit design for minimum transient energy and a linear programming method, in Proc. 12th Int. Conf. VLSI Des., Jan. 1999, pp. 434439. 3. A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design: Circuits and Systems. Boston, MA: Kluwer, 1995. 4. M. Berkelaar, Statistical delay calculation, in Proc. Workshop Notes Int. Workshop Logic Synth., Lake Tahoe, CA, May 1997, pp. 2.1.12.1.4. 5. M. Berkelaar, Statistical delay calculation: A linear time method, in Proc. IEEE Int.Workshop Timing Issues Specif. Synth. Digit. Syst., Dec. 1997, pp. 1524. 6. M. Berkelaar, P. Buurman, and J. Jess, Computing entire area/power consumption versus delay trade-off curve for gate sizing using a piecewise linear simulator, IEEE Trans. Circuits Syst., vol. 15, no. 11, pp. 14241434, Nov. 1996. 7. M. Berkelaar and E. Jacobs, Using gate sizing to reduce glitch power, in Proc. ProRISC Workshop Circuits, Syst., Signal Process., Mierlo, The Netherlands, Nov. 1996, pp. 183188. 8. M. Berkelaar and E. T. A. F. Jacobs, Gate sizing using a statistical delay model, in Proc. Des. Autom. Test Eur. Conf., Paris, France, Mar. 2000, pp. 283 290. 9. M. Berkelaar and J. A. G. Jess, Transistor sizing in MOS digital circuits with linear programming, in Proc. Eur. Des. Autom. Conf., Mierlo, The Netherlands, Mar. 1990, pp. 217221. 10. M. T. Bohr, R. S. Chau, T. Ghani, and K. Mistry, The high-k solution, IEEE Spectrum, vol. 44, no. 10, pp. 2935, Oct. 2007.
Fig. 8. Simulated output In Fig.8 the variable-input delay gate design saves 58% average and 66% peak power. In comparison with the conventional CMOS gate design using 366 delay buffers, the variable-input delay gate design consumed about 17% less average power. These power savings, though appreciable, are lower. VI. CONCLUSION The novelty of our work is in: 1) finding the best combination of path balancing and hazard filtering by linear programming to minimize the hardware and timing penalties; 2) formulating the linear program with reduced-complexity (linear in circuit size) constraint set so large circuits can be designed; and 3) using a two-step solution where gate delays are first found by the linear program and then implemented at the transistor-level so that the size-delay nonlinearity is locally (not globally) dealt with. These variations make delays vary over a range rather than being static numbers. This can be accounted for in our technique during the LP stage, where the constraints can be modified to incorporate the maximum gate delay value in the latest time of arrival constraints and the minimum gate delay values in the earliest time of arrival constraints. One such analysis has been recently reported . It is possible to reduce the hardware overhead of delay buffers by customizing the optimization to a subset of highly probable or worst-case vectors.
11. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and MixedSignal VLSI Circuits. Boston, MA: Springer, 2000. 12. Cadence Design Systems, San Jose, CA, Affirma analog environment reference, 2003.
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SIGNAL PROCESSING WITH SENSOR MEASUREMENTS

R.SENTHIL KUMAR (Asst Prof of Dept EEE) SRM UNIVERSITY (rskrren@yahoo.co.in) SARAVANAN.S (sathyasara18@gmail.com) R.V.SANDIP (sandiprudraraju2@gmail.com) S.SAIKUMAR (saikumar.kumar08@gmail.com) VIJAY SRIDHAR (sputnik3389@gmail.com)
ABSTRACT-In Signal Processing various advancements have been undergone to solve inference problems such as detection, classification, estimation and filtering. In this paper we have taken an initiative to solve these and to produce exact signals as that of the original. High speed sensors enable the recovery of sparse signals from a small set of non-adaptive, linear measurements. If properly chosen, the number of measurements can be much smaller than the Nyquist rate samples. Despite the intense focus on signal recovery, many signal processing problems do not even require full signal recovery. In supporting this statement we have theoretically proved the recovery of signals from its sparse measurements using sensor techniques.
Such constraints are actually obeyed on natural classes of signals and images; this is the primary reason for the success of standard compression tools based on transform coding . To fix ideas, we mention two simple examples of constraint. Bounded Variation model for images: Here image brightness is viewed as an underlying function ( , )on the unit square0 , 1, which obeys (essentially) | | . The digital data of interest consist of = pixel samples of produced by averaging over 1 1 pixels. We take a wavelet point of view; the data are seen as a superposition of contributions from various scales. Let ( )denote the component of the data at scale, and let denote the orthonormal basis of wavelets at scale, containing 3 4 elements. The corresponding coefficients obey ( ) 4 Bump Algebra model for spectra. Here a spectrum (e.g., mass spectrum or magnetic resonance spectrum) is modelled as digital samples (f(i/n))of an underlying function on the real line which is a superposition of so-called spectral lines of varying positions, amplitudes, and line widths. Formally ( )/ . ( )= Here the parameters are line locations , are amplitudes/ polarities, and are line widths, and g represents a line shape, for example the Gaussian, although other profiles could be considered. We assume the constraint where | | , which in applications represents an energy or total mass constraint. Again we take a wavelet viewpoint, this time specifically using smooth wavelets. The data can be represented as a superposition of contributions from various scales. Let( ) denote the component of the spectrum at scale j and let( ) denote the orthonormal basis of wavelets at scale, containing j elements. ( ) The corresponding coefficients again obey . .2 While in these two examples, the constraint appeared, other constraints with 0 < 1can appear naturally as well; p<1see below. For some readers, the use of norms with may seem initially strange; it is now well understood that the norms with such small p are natural mathematical measures of sparsity. As P decreases below 1, more and more sparsely is being required. Also, from this viewpoint, a constraint based on p=2 requires no sparsely at all. Note that in each of these examples, we also allowed for separating the object of interest into sub bands, each one of which obeys a constraint. In practice, in the following we stick with the view that the object of interest is a coefficient vector obeying the constraint, which may mean, from an application viewpoint that our methods correspond to treating various subbands separately, as in these examples. The key implication of the constraint is sparsely of the transform coefficients. Indeed, we have trivially that, if denotes the vector with everything except the largest coefficients set to. , ( + 1) for = 0,1,2, ,,with a constant , depending only on (0,2).Thus, for example, to approximate with error , we need to keep only the ( ) biggest terms in .
INTRODUCTION: From DSP to CSP IN recent decades, the digital signal processing (DSP) community has enjoyed enormous success in developing algorithms for capturing and extracting information from signals. Signal processing has moved from the analog to the digital domain. Digitization has enabled the creation of sensing and processing systems that are more robust, flexible, cheaper and, therefore, more ubiquitous than their analog counterparts. In this paper, we design compressed data acquisition protocols which perform as if it were possible to directly acquire just the important information about the signals/imagesin effect, not acquiring that part of the data that would eventually just be thrown away by loss compression. As a result of this success, the amount of data generated by sensing systems has grown from a trickle to a torrent. We are thus confronted with the following challenges: 1) Acquiring signals at ever higher sampling rates 2) Storing the resulting large amounts of data 3) processing/analyzing large amounts of data. Thus, in recent years, the signal processing community has also begun to address the challenge of signal acquisition more directly by leveraging its successes in addressing the second two. In particular, compressive sensing (CS) has emerged as a framework that can significantly reduce the acquisition cost at a sensor. A signal that can be compressed using classical methods such as transform coding can also be efficiently acquired via a small set of non-adaptive, linear, and usually randomized measurements. Transform Compression Background: Our treatment is abstract and general, but depends on one specific assumption which is known to hold in many settings of signal and image processing: the principle of transform sparsity. We suppose that the object of interest is a vector which can be a signal or image with m samples or pixels, and that there is an orthonormal basis ( : = 1, , )for which can be, for example, an orthonormal wavelet basis, a Fourier basis, or a local Fourier basis, depending on the application. (As explained later, the extension to tight frames such as curvelet or Gabor frames comes for free.) The object has transform coefficients = ( , ) and these are assumed sparse in the sense that, for some 0 < < 2and for some > 0. ( | | ) .
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Related Work: In this paper, we consider a variety of estimation and decision tasks. The data streaming community, which is concerned with efficient algorithms for processing large streams of data, has examined many similar problems over the past several years. In the data stream setting, one is typically interested in estimating some function of the data stream (such as a norm, a histogram, or a linear functional) based on sketches, which in many cases can be thought of as random projections. For a concise review of these results, see. The main differences with our work include the following: 1) Data stream algorithms are typically designed to operate in noise-free environments on man-made digital signals, whereas we view compressive measurements as a sensing scheme that will operate in an inherently noisy environment; 2) Data stream algorithms typically provide probabilistic guarantees, while we focus on providing deterministic guarantees; and 3) Data stream algorithms tend to tailor the measurement scheme to the task at hand, while we demonstrate that it is often possible to use the same measurements for a variety of signal processing tasks. There have been a number of related thrusts involving detection and classification using random measurements in a variety of settings. For example, in scarcity is leveraged to perform classification with very few random measurements, while in, random measurements are exploited to perform manifold-based image classification. In, small numbers of random measurements have also been noted as capturing sufficient information to allow robust face recognition. However, the most directly relevant work has been the discussions of classification in and detection in .We will contrast our results to those of, below. This paper builds upon work initially presented in. Mysteries: Because of the indirect manner by which the KGG result implies we really do not learn much about the phenomenonof interest in this way. The arguments of Kashin, Garnaev,and Gluskin show that there exist near-optimal dimensional subspaces for the Kolmogorov widths; they arise as the nullspaces of certain matrices with entries 1entries which are known to exist by counting the number of matrices lacking certain properties, the total number of matrices with 1entries, and comparing. The interpretability of this approach is limited. The implicitness of the information operator is matched by the abstractness of the reconstruction algorithm. Based on OR/IBC theory we know that the so-called central algorithm is optimal. This algorithm asks us to consider, for given information , = ( ),the collection of all objects x which could have given rise to the data ( )= : ( )= , Defining now the center of a set S center( ) = ( ) , ( ) the central algorithm is = and it obeys, when the information
than quantized measurements. Classical sampling theory dictates that, in order to ensure that there is no loss of information, the number of samples M should be as large as the signal dimension N. The CS theory, on the other hand, allows for M<<N as long as x the signal is sparse or compressible. To understand how many measurements are required to enable the recovery of a signal x, we must first examine the properties of that guarantee satisfactory performance of the sensing system. In Cands and Tao introduced the restricted isometric property (RIP) of a matrix and established its important role in CS. First define to be the set of all K-sparse signals, i.e. ( )| = : := | Where denotes the set of indices on which is nonzero. We say that a matrix satisfies the RIP of order if there exists a constant, such that (1 ) holds for all. In other words, is an approximate isometry for vectors restricted to be K-sparse? It is clear that if we wish to be able to recover all Ksparse signals x from the measurements, y then a necessary condition on is that for any pair , with. Equivalently, we require, ( ) > 0which is guaranteed if satisfies the RIP of order with constant. Furthermore, the RIP also ensures that a variety of practical algorithms can successfully recover any compressible signal from noisy measurements. The following result makes this precise by bounding the recovery error of x with respect to the measurement noise and with respect to the distance from to its best K-term approximation denoted = [Cands]: Suppose that satisfies the RIP of order 2K with isometry constant. < 2 1Given measurements of the form, = + where ,the solution to subject to subject to = arg obeys + where =4

=2
Note that in practice we may wish to acquire signals that are sparse or compressible with respect to a certain spar city basis, i.e., = where is represented as a unitary matrix and. In this case, we would require instead that satisfy the RIP, and the performance guarantee would be on Before we discuss how one can actually obtain a matrix that satisfies the RIP, we observe that we can restate the RIP in a more general form. Let (0,1)and , be given. We say that a mapping is a -stable embedding of( , ) if (1 (1 + ) ) for all and . A mapping satisfying this property is also commonly called bi-Lipschitz. Observe that for a matrix , satisfying the RIP of order 2K is equivalent to being a -stable embedding of ( , ) or of ( , 0 ) Furthermore, if the matrix satisfies the RIP of order 2K then is a -stable embedding of( ( ), ( )) or( ( ), 0 ) where . ( ) = : . Random Matrix Constructions : We now turn to the more general question of how to construct linear mappings that satisfy for particular sets U and V. While it is possible to obtain deterministic constructions of such operators, at present the most efficient designs (i.e., those requiring the fewest number of rows) rely on random matrix constructions. We construct our random matrices as follows: given M and N, we generate random MN matrices by choosing the entries as independent and identically distributed (i.e.) random variables. We impose two conditions on the random distribution. First, we require that the distribution yields a matrix that is norm-preserving, which requires that 1 ( )= Second, we require that the distribution is a sub-Gaussian distribution, meaning that there exists a constant C > 0such that
is optimal,
= , ( ) ; This abstract viewpoint unfortunately does not translate into a practical approach (at least in the case of the, , ( ), 0 < < 1The set ( ) , ( ) is a section of the ball, , = ( )and finding the center of this section does not correspond to a standard tractable computational problem. Moreover this assumes we know and which would typically not be the case. COMPRESSIVE MEASUREMENTS AND EMBEDDINGS: Compressive Sensing and Restricted Isometrics STABLE
( )
In the standard CS framework, we acquire a signal via the linear measurements = where is an MN matrix is the vector of representing the sampling system and measurements y. For simplicity, we deal with real-valued rather
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for all . This says that the moment( ) generating function of our distribution is dominated by that of a Gaussian distribution, which is also equivalent to requiring that the tails of our distribution decay at least as fast as the tails of a Gaussian distribution. Examples of sub-Gaussian distributions include the Gaussian distribution, the Rademacher distribution, and the uniform distribution. In general, any distribution with bounded support is sub-Gaussian. The key property of subGaussian random variables that will be of use in this paper is that for any , the random variable is highly concentrated about ; that is, there exists a constant c>0 that depends only on the constant C in such that Pr 2 where the probability is taken over all MN matrices . Stable Embeddings: We now provide a number of results that we will use extensively in the sequel to ensure the stability of our compressive detection, classification, estimation, and filtering algorithms. We start with the simple case where we desire a -stable embedding f (u,v), where and
| |
Potential Applications: To see the potential implications, recall first the Bump Algebramodel for spectra. In this context, our result says that, for a spectrometer based on the information operator it is really only necessary to take measurements to get an accurate reconstruction of such spectra, rather than the nominal measurements. However, they must then be processed nonlinearly.Recall the Bounded Variation model for images. In that context, a result says that for a specialized imaging device based on a near-optimal information operator it is really only to take measurements to get an accurate reconstruction of images with m pixels, rather than the nominal m measurements. The calculations underlying these results will be given below, along with a result showing that for cartoon-like images (which may model certain kinds of simple natural imagery, like brain scans), the number of measurements for an m -pixel image is only . . INFORMATION: Consider information operators constructed as follows. With the orthogonal matrix whose columns are the basis elements , and with certain n -by- m matrices obeying conditions specified below, we construct corresponding information operators . Everything will be completely transparent to the choice of orthogonal matrix and hence we will assume that is the identity throughout this section. In view of the relation between Gelfand n-widths and minim ax errors, we may work with n -widths. Let ker denote as usual the nullspace . We define the width of a set relative to an operator . , sup . In words, this is the radius of the section of X cut out by the null spaceker . In general, the Gelfand n-width is the smallest value w of obtainable by choice of . is an , : is an matrix. We will show for all large n and m the existence of by n matrices m where. , , , with C dependent at most on p and the ratio . Conditions CS1-CS3: In the following, with 1, , let denote a sub matrix of obtained by selecting just the indicated columns of . .We let denote the range of in . Finally, we considera family of quotient norms on .; with denoting the norm on vectors indexed by 1, / subject to. These describe the minimal -norm representation of V achievable using only specified subsets of columns of .We define three conditions to impose on an matrix ,indexed by strictly positive parameters , and 1 3, and . CS1: The minimal singular value of exceeds 0 log Uniformly in .| | CS2: On each subspace we have the inequality . , log Uniformly in .| | CS3: On each subspace log Uniformly in . | | CS1 demands a certain quantitative degree of linear independenceamong all small groups of columns. CS2 says that linear combinations of small groups of columns give vectors that look much like random noise, at least as far as the comparison of and norms is concerned. It will be implied by a geometric ,
and
| |
arefinite sets of points in
RN. In the case where u=v, this is essentially the Johnson Linden Strauss (JL). Lemma 1: Let u and v be sets of points in RN. Fix ,(0,1). Let be an MN random matrix with i.e. entries chosen from a distribution satisfying. If then with probability exceeding,1- , is a stable embedding of (u,v) . Proof: To prove the result we apply to the| || | vectors corresponding to all possible . By applyingthe union bound, we obtain that the probability of not holding is bounded above by .2| || | By requiring2| || | and solving M for we obtain the desired result. We now consider the case where is a Kdimensional subspace of RN and v={0}Thus, we wish to obtain a thatnearly preserves the norm of any vector. At first glance,this goal might seem very different than the setting for Lemma1, since a subspace forms an uncountable point set. However,we will see that the dimension K bounds the complexity of thisspace, and thus it can be characterized in terms of a finite numberof points. Lemma 2: Suppose that is a K-dimensional subspace of RN. Fix , (0,1). Let be an MN random matrix withi.i.d. entries chosen from a distribution satisfying . If 2 then with probability exceeding 1 , is a -stable embedding of. , 0 Sketch of Proof: It suffices to prove the result for satisfying, 1, since is linear. We consider a finite sampling of points of unit norm and with resolution onthe order of /14. One can show that it is possible to construct such a with.| | 42 Applying Lemma 1 and setting M to ensure a /2 -stable embedding of, , 0 we can use simple geometric arguments to concludethat we must have a stable embedding of , 0 for every satisfying 1. We now observe that we can extend this result beyond a singleK-dimensional subspace to all possible K-dimensional subspacesthat are defined with respect to an orthonormal basic,i.e., .
| || |
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with , Recalling, | | In short, with
fact: every slices through the ball in such a way that the resulting convex section is actually close to spherical. CS3 says that for every vector in some , the associated quotient norm is never dramatically smaller than the simple norm on . It turns out that matrices satisfying these conditions are ubiquitous for large n and m when we choose the and properly. Of course, for any finite n and m , all norms are equivalent and almost any arbitrary matrix can trivially satisfy these conditions simply by taking very small and , very large. However, the definition of very small and very large would have to depend on n for this trivial argument to work. We claim something deeper is true: it is possible to choose and independent of n and of . Consider the set Of all n * m matrices having unit-normalized columns. On this set, measure frequency of occurrence with the natural uniform measure (the product measure, uniform on each factor ). Theorem: Let , be a sequence of problem sizes with n , and ~ , 0 .and 1 . There exist 0and >0depending only on A and so that, for each 0the proportion of all n*m matrices satisfying CS1CS3 with parameters and eventually exceeds 1The proof will show that the proportion of matrices not satisfying the condition decays exponentially fast in n . For later use, we will leave the constants and implicit and speak simply of CS matrices, meaning matrices that satisfy the given conditions with values of parameters of the type described by this theorem, namely, with and not depending on n and permitting the above ubiquity. Near-Optimality of CS Matrices: We now show that the CS conditions imply near-optimalityof widths induced by CS matrices. Theorem: , be a sequence of problem sizes with n and ~ . . Consider a sequence of n by matrices , obeying the conditions CS1CS3 with and positive and independent of n . Then for each 0,1 , there is , , , , , , so that for Let
,
. ,and invoking CS1 we have
/log
/ . / /log /log

The theorem follows with

,
ALGORITHMS: Given an information operator , we must design a reconstruction algorithm which delivers reconstructions compatible in quality with the estimates for the Gelfand n widths. As discussed in the Introduction, the optimal method in the OR/IBC framework is the so-called central algorithm, which unfortunately, is typically not efficiently computable in our setting. Feasible-Point Methods: Another general abstract algorithm from the OR/IBC literature is the so-called feasible-point method, which aims simply to find any reconstruction compatible with the observed information and constraints. As in the case of the central algorithm, we consider, for given information , the collection of all objects which could have given rise to the information . .
,
In the feasible-point method, we simply select any member of by whatever means. One can show, adapting standard , OR/IBC arguments as show in the following. Lemma: Let where
.
and
is an optimal .
, ,
log
information operator, and let be any element of , Then for 0 1 2 . , In short, any feasible point is within a factor two of optimal. Proof:
Proof: Subject to Consider the optimization problem 0 , 1 Our goal is to bound the value of
/
log / Choose so that 0= . Let J denote the indices of the /log largest values in . Without loss of generality suppose coordinates are ordered so that J comes first among them m entries, and partition , . Clearly
1while, because each entry in is at least as big as any entry in gives 1 . , . A similar argument for approximation gives, in case p<1 / 1 . , . Now
: , sup Now clearly, in the special case when is only known to lie in and is measured, the mini max error is ,
We first justify our claims for optimality of the centralalgorithm, and then show that a feasible point is near to thecentral algorithm. Let again denote the result of the centralalgorithm. Now : , sup ,
0 . Hence, with , we have .As and| | /log , we can invoke CS3, getting . . / On the other hand, again using and| | /log , . invokeCS2,getting Combining these with the above
exactly . Since this error is achieved by , thecentral algorithm for each such , the minimax error over all is achieved by the central algorithm. This minimax error is sup : . , . , Now the feasible point obeys ; hence, ,
But the triangle inequality gives ,
. hence,
as
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2 , More generally, if the information operator is only near optimal, then the same argument gives 2 , , .A popular choice of feasible point is to take an element ofleast norm, i.e., a solution of the subject to problem where here is the vector of transform coefficients,. A nice feature of this approach is that it is not necessary to know the radius R of the ball . ; the element of least norm will always lie inside it. For later use, call the solution. , By the preceding lemma, this procedure is near-minimax: With where for given0 1andR>0 ,
,
2 sup
2
,
with immediate extensions to We conclude that , as was to be proven. Proof of Theorem :
Secondly, the entropy numbers obey. . , At the same time, the combination of Theorems shows that , Applying now the Feasible Point method, we have 1 2 , ,
,
for all R
Proof of Theorem: Before proceeding, it is convenient to prove Theorem. Note that the case p1 is well known in OR/IBC so we only need to give an argument for p<1 (though it happens that our argument works for as well). The key point will be to apply the p-triangle inequality Valid for 0 1; This inequality is well known in interpolation theory through Petre and Spars work, and is easy to verify directly. Suppose without loss of generality that there is an optimal subspace Vn, which is fixed and given in this proof. As we just saw sup : , , , . Now , , 0 so clearly . Now suppose without loss of generality that attain the radius bound, i.e., they satisfy and for they , satisfy
,
Now is an opportune time to prove Theorem. We note that in the case of 1 . The argument is the same for0 1, and we simply repeat it. Suppose that x=0, and consider the adaptively constructed subspace according to whatever algorithm is in force. When the algorithm terminates, we have an n-dimensional information vector 0 and a subspace Vn0, consisting of objects which would all give that information vector. For all objects in Vn0, the adaptive information therefore turns out the same. Now the minimax error associated with that information is exactly radius inf
;but this cannot be smaller than

,
.
,
The result follows by comparing with .
with
ESTIMATIONWITH COMPRESSIVE MEASUREMENTS: Problem Setup and Applications: While many signal processing problems can be reduced to a detection or classification problem, in some cases we cannot reduce our task to selecting among a finite set of hypotheses. Rather, we might be interested in estimating some function of the data. In this section we will focus on estimating a linear function of the data from compressive measurements. Suppose that we observe and wish to estimate , from the measurements y, where is a fixed test vector. In the case where is a random matrix, a natural estimator is essentially the same as the compressive detector.
Then define _ 2 Set. = T By the p-triangle inequality and so Hence So

,
However, to and
, ,
belongs
_ 2
,
0 .
,
Hence,
_ 2
Proof of Theorem: We are now in a position to prove Theorem of the Introduction. First, in the case p =1, we have already explained in the Introduction that the theorem of Garnaev and Gluskin implies the result by duality. In the case 0<p<1 , we need only to show a lower bound and an upper bound of the same order. For the lower bound, we consider the entropy numbers, defined as follows. Let X be a set and let , be the smallest number such that an -net X for can be built using a net of cardinality at most 2n. From Carls theoremthere is a constant c>0so that the Gelfand n-widths dominate the entropy numbers. . , ,
Suppose we have set | | of | |linear functions we would like to estimate from y. Example applications include computing the coefficients of a basis or frame representation of the signal, estimating the signal energy in a particular linear subspace, parametric modeling, and so on. One potential estimator for this scenario, which is essentially a simple generalization of the compressive detector in , is given by
for. 1,2, , | | While this approach, which we shall refer to as the orthogonalized estimator, has certain advantages, it is also enlightening to consider an even simpler estimator, given by , We shall refer to this approach as the direct estimator since it
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eliminates the orthogonalization step by directly correlating the compressive measurements with . CONCLUSION: In this paper, we have taken some first steps towards a theory of signal processing by showing that sensor measurements can be effective for a variety of detection, classification, estimation, and filtering problems. We have provided theoretical bounds backed up by experimental results that indicate that in many applications it can be more efficient and accurate to extract information directly from a signals sensor measurements than first recover the signal and then extract the information. It is important to reemphasize that our techniques are universal and agnostic to the signal structure and provide deterministic guarantees for a wide variety of signal classes. In the future we hope to provide a more detailed analysis of the classification setting and consider more general models, as well as consider detection, classification, and estimation settings that utilize more specific models, such as sparsity or manifold structure.
REFERENCES: 1) E. Candies, compressive sampling, in Proc. Int. Congr.Math, Madrid,Spain,Aug 2006. 2) R. Walden, Analog-to-digital converter survey and analysis, IEEE J.Sel.Areascommun, vol17, no.4, pp.539-550, April 1999. 3) Y. Meyer, Wavelets and operators . Cambridge, U.K. : Cambridge Univ. Press 1993. 4) sparse components of images and optimal atomic decomposition, constructive Approx.vol.17, pp.353-382,2001. 5) E. J. Cands, Robust Uncertainty Principles and Signal Recovery, presented at the 2nd Int. Conf. Computational Harmonic Anaysis, Nashville, TN, May 2004. 6)E. J. Cands and T. Tao, Near-optimal signal recovery from random projections: Universal encoding strategies, Applied and Computational Mathematics, Calif. Inst. Technol., Tech. Rep., 2004. 7)J. Tropp and A. Gilbert, Signal recovery from random information via orthogonal matching pursuit, IEEE Trans. Inf. Theory, vol. 53, no. 12, pp. 46554666, Dec. 2007. 8)D. Needell and R. Vershynin, Uniform uncertainty principle and signal recovery via regularized orthogonal matching pursuit, Found. Comput. Math., vol. 9, no. 3, pp. 317334, Jun. 2009. 9)T. Blumensath and M. Davies, Iterative hard thresholding for compressive sensing, Appl. Comput. Harmon. Anal., vol. 27, no. 3, pp. 265274, Nov. 2009. 10) J. Treichler, M. Davenport, and R. Baraniuk, Application of compressive sensing to the design of wideband signal acquisition receivers, in Proc. U.S./Australia Joint Work. Defense Apps. Signal Process. (DASP), Lihue, HI, Sep. 2009
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EEG Analysis of Hearing Impaired Children
R.Dhivya II Year M.E (Applied Electronics) Dr.MCET Pollachi. r.dhivyathulasi@gmail.com

Abstract Normal audible frequency of human being ranges from 20Hz to 20KHz. Inability of perceiving these frequency range is called hearing impairment. In our brain there are four lobes frontal, parietal, occipital and temporal. Each lobe is responsible for specific function of our body. According to this fact, temporal lobe is responsible for auditory sensation. EEG is the electrical activity of the brain. It is received from the four lobes of brain. Thus analyzing the EEG we can find the temporal lobe dysfunction. In this proposed work we are going to find out which filter is suitable for filtering of an EEG. We have used matlab for the eeg data analysis. Keywords EEG, hearing impairement
Mr.S.Thiruvenkadam Assistant Professor(SS) Department of EEE, Dr.MCET,Pollachi.
Zoological Gardens, to high-frequency sounds. Hearing is one of the five sensors of humans body. The audible sounds frequencies for human being are ranged from 20 Hz to 20 kHz. Its generally accepted that humans cannot perceive sounds in the frequency range above 20 kHz. Furthermore, humans brain is divided into four main lobes: frontal lobe, parietal lobe, occipital lobe and temporal lobe . Each lobe of the brain has specific function i.e responsible for particular activity of our human body. The temporal lobe will respond to hearing ability of human. The electricity activity produced by the brain when human exposed to a sound will be collected by the electrodes which are placed on the scalp. Measuring EEG signals is not an intrusive procedure; it causes no pain and has been used routinely for several decades
I.INTRODUCTION Electroencephalographic (EEG) has become an important technology in todays medication world. An EEG (electroencephalogram) is a measurement of time-varying potential differences that reflect the electrical activity of (for instance) the human brain. The Electroencephalogram is used for clinical and research purposes. The EEG technology is used to capture the electrical activities of humans brain by placing electrodes on scalp. There are a number of benefits for using EEG in neuroscience research. First, the EEG is noninvasive to the research subject and the subject to hold still is perhaps less stringent than in functional magnetic resonance imaging (fMRI). Second, EEG records spontaneous brain activity and it capable of detecting changes in electrical activity in the brain on a millisecond time scale. The first systematic study of high frequency hearing was conducted by Francis Galton in the second half of the 19th century. Using a high-frequency whistle attached to his cane and operated by a rubber bulb, Galton observed the unconditioned responses of animals, including those of the London
Fig.1
Location of Temporal lobe in Brain
Hearing impairment or hard of hearing or deafness refers to conditions in which individuals are fully or partially unable to detect or perceive at least some frequencies of sound
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which can typically be heard by members of their species. Hearing sensitivity is indicated by the quietest sound that an individual can detect, called the hearing threshold. In the case of people and some animals, this threshold can be accurately measured by a behavioral audiogram. Infant's cry is a multimodal behavior that contains a lot of information about the infant, particularly, information about the health of the infant. Infant's cry [2] is a multimodal and dynamic behavior with a lot of information in its acoustic signal. The pioneers of studying on infant's cry were Wasz-Hockert and et al. in Scandinavia in the 1960s. An infant's cry contains a lot of information about the baby, as hunger, pain, sleepiness or boredom. But eeg will give more information than a sound while considering the hearing impairement.
optimum filter to reduce the artifacts in the Electroencephalogram by comparing filters previously used in this field of study.
II. METHODOLOGY Source EEG data is taken from seven year old boy. He is partially hearing impaired. Data can also be downloaded from the medical databases. Patient is asked to take rest for few minutes before going to record the EEG, this work is based on the partially hearing impaired children. EEG provides cognitive underpinnings of various brain process , reasoning,learning, perception building and emotion arousals. Interpretation of psychophysical data from impaired hearing individuals on intensity discrimination tasks has been confounded by the fact that some impaired individuals performance is near-normal in quiet, whereas for others, the difference limen is elevated. It has been observed that a subjects discrimination abilities may be related to the underlying audiogram configuration, which is often dependent on the type of physiological damage that has occurred. This suggests that data be grouped and analyzed according to the type of hearing loss. Physiological signals are in the range of few micro volts to several volts. But that range is not enough to process these signals. So amplification is done within the EEG machine. The EEG software should have the file exporting (convert to another file format) character. In this study we have considered only the temporal lobe waves, since temporal lobe is responsible for auditory sensation. Generally there are three types of brain waves will appear depending on the human activity. A. File Convertion The data can be in any format. Mostly it will be in EDF (European Data Format) or text format. We have downloaded the data from physionet medical database. Some text files with ascii format can be loaded directly in matlab. But EDF files have to be converted to matlab readable formate . So we used EDF to text converter. Then the data is loaded into matlab and processed.
Fig. 2 Placement of Electrodes for EEG measurement In this proposed work we are going to analyse the EEG of hearing impaired children. Since there is a relationship between temporal lobe and auditory system. A few years [1] before theoretical analysis of normal and abnormal hearing have been done. Hearing disorder identification based on infants cry also an research field [2]. There are several techniques available to determine the hearing ability level. Some of the techniques are auditory brain stem response (abr) test, otoacoustic emissions (oae) test, tympanometry. But these tests will creat some irritation to the children while doing the test. But EEG is not such a case. EEG examination for the hearing indentification is a rearch field [3]. We are trying to determine the
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B. Domain Convertion Physiological signals in time domain wont give required information to analyse the Elecroencephalogram. EEG consists of a wave that varies in time, much like a sound signal, or a vibration. As such, it contains frequency components that can be measured and analyzed, and these frequency components have interesting and valuable properties. The rhythm can only be shown clearly in frequency domain. A fast Fourier transform (FFT) is an efficient algorithm to compute the discrete Fourier transform (DFT) and its inverse. There are many distinct FFT algorithms involving a wide range of mathematics, from simple complex-number arithmetic to group theory and number theory. An FFT computes the DFT and produces exactly the same result as evaluating the DFT definition directly; the only difference is that an FFT is much faster. (In the presence of round-off error, many FFT algorithms are also much more accurate than evaluating the DFT definition directly). So the brain signals will be digitised using Fast Fourier Transform (FFT) function available in Matlab.
Fig 4 . FFT of original EEG FFT is an efficient algorithm to compute the discrete Fourier Transform (DFT) and its inverse.In Fig.4 the result of FFT process and the brain signals are in discrete form are shown .Among several EEG electrodes , four electrodes T3,T5 and T4,T6 are temporal lobe electrodes. Here we have considered any one temporal lobe electrode (T3 or T4 or T5 or T6) at a time to determine the hearing ability level. The data we used is large, the full data cant be showed in this paper . So in Fig.3 upto 150 values only showed. C. Filtering Physiological signals have to filtered before processing. Because all physiological signals will be corrupted by some biological artifacts. Electroencephalogram may also affected by ECG (Electrocardiogram), EMG (Electromyogram) and EOG (Electrooculogram).But EOG effect will be more sensitive compared to other artifacts. Many experiments have been done to reduce the artifacts approximately from 1980s.Filtering have been done in some years before [4] using adative noise cancellation method .
Conventional filtering cannot be applied to eliminate the artifacts because EEG signal and artifacts have overlapping spectra. An adaptive process, in which the transfer function H(z) is adjusted according to an optimizing algorithm. The adaptation is directed by the error signal between the primary signal and the filter output.
Fig 3 Original EEG Signal from one temporal electrode
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EOG is the most wanted disturbance to be reduced. So in our proposed work we concentrated on that. IV. APPLICATIONS Analysis of the EEG can be extended to find out the hearing ability of the partially hearing impaired children. This can also be extended to completely hearing impaired children. REFERENCES
[1]. Lisa G. Huettel, Member- IEEE, and Leslie M.
Fig 5. Adaptive Filter The most used optimizing criterion is the Least Mean Square algorithm. This algorithm is an application scheme widely used in practice due to its simplicity. Usually, FIR filters are used in this process because they are simple and stable. The objective of an adaptive filter [3] is to change the coefficients of the linear filter, and hence its frequency response, to generate a signal similar to the noise present in the signal to be filtered. The adaptive process involves minimization of a cost function, which is used to determine the filter coefficients. The adaptive filter adjusts its coefficients to minimize the squared error between its output and a primary signal. In case of nonstationary circumstances, the coefficients will change with time, according to the signal variation, thus converging to an optimum filter. The
Collins, Member- IEEE A Theoretical Analysis of Normaland Impaired-Hearing Intensity Discrimination IEEE Transactions on Speech and audio processing,Vol12, N0:3.May2004.Pg323,325,328,331.
[2].Mahmoud Mansouri Jam, Hamed Sadjedi Identification of Hearing Disorder by Multi-Band Entropy Cepstrum Extraction from Infant's Cry,IEEE Transactions on Signal processing-2009.
[3]. R. Sudirman (IEEE member), S. C. Seow, Electroencephalographic Based Hearing Identification using Back-Propagation Algorithm, IEEE Conference-2009.
Recursive least squares (RLS) adaptive filter is an algorithm which recursively finds the filter coefficients that minimize a weighted linear least squares cost function relating to the input signals. This in contrast to other algorithms such as the least mean squares (LMS) that aim to reduce the mean square error. In the derivation of the RLS, the input signals are considered deterministic, while for the LMS and similar algorithm they are considered stochastic. Compared to most of its competitors, the RLS exhibits extremely fast convergence. The Normalised least mean squares filter (NLMS) is a variant of the LMS algorithm that solves this problem by normalising with the power of the input. In this work we are going to use adaptive normalized least means square filter. We are going to use some other filters to compare the results.
[4].Christopher J. James, Martin T. Hagan, Richard D. Jones,MPhilip J. Bones*, and Grant J. Carroll, Multireference Adaptive Noise Canceling Applied to the EEG, IEEE Transactions on biomedical engineering, vol. 44, no. 8, august 1997
III. CONCLUSION We are trying to find the filter which is suitable for the EEG analysis. EEG data without artifact or with minimum artifact will be an effect basis for any futher analysis. Particularly
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TRANSMISSION REDUCTION ALGORITHM FOR WIRELESS SENSOR NETWORKS Deepa.K 1, Sathish kumar.M 2 1 PG Scholar Embedded System Technologies 2 Associate Professor Department of Electrical and Eletronics Engineering Velalar College of Engineering and Technology ABSTRACT
Wireless sensor network (WSN) consists of a large number of sensor nodes which are limited in battery power and communication range. The use of WSN for environment monitoring applications will require reliable delivery of sensed information with low power consumption. Sensor association rules, which are a kind of behavioral pattern that aims to capture the temporal relations between sensor nodes, has proven to be a promising tool for improving wireless sensor network (WSN) performance and its quality of service (QoS) by participating in the resource management process and by compensating for the undesired effects of wireless communication. To prepare the data needed for generating sensor association rules, each sensor node should monitor its activity over time and inform the sink about the time in which events are detected. However, without an efficient extraction mechanism, this process is costly, giving the limited resources of sensor nodes. This proposed mechanism network data reduction algorithm(DRA) is used to reduce the amount of sensor behavioral data by removing the some of data redundancies. Hence increases the energy efficiency in wireless sensor networks. Intex terms- wireless sensor networks(WSN),Data Reduction Algorithm(DRA),Power consumption,Performance 1. INTRODUCTION Advances in wireless technologies and microelectronic devices have led to the development of sensor nodes that are capable of sensing, processing, and transmitting data [2], [3]. This new trend in sensor technology led the design of wireless sensor networks (WSNs). A WSN consists of several sensor nodes that are designed to sense the environment around them and send, in cooperation with each other, detected events to a wellequipped node referred to as the sink. WSNs have proven their success in a variety of applications, particularly those that require fine-grained monitoring of physical environments that are subject to critical conditions, such as fire, toxic gas leaks, and explosions [2], [3], [6]. Guarantee an acceptable level of quality for events delivery, a new class of fast, reliable, and fault-tolerant protocols for WSN need to be developed [4]. However, the distributed nature and the limited resources of sensor nodes (e.g., energy, communication, and computation [2], [3]), as well as the unreliability of wireless communication increase the possibility of errors, lost messages, delays in data delivery, and losses of functionality. These factors are potentially devastating to the performance and the overall quality of service (QoS) of WSNs [4], [7], [8], [15], [16]. Recently, the knowledge discovery process, which is a wellknown process in traditional database systems used to extract patterns from data [24], [25], has shown to be a promising tool to improve WSN performance and its QoS [5]. Knowledge discovery in WSN (KDW) has been used to extract the following two types of information (knowledge): 1) patterns about the surrounding environment, which are extracted from the data reported by sensor nodes [26][29], and 2) behavioral patterns about sensor nodes, which are extracted from meta-data describing sensors behaviors [1].Sensor association rules is among the earliest behavioral patterns generated from WSNs [1]; it aims to capture the temporal relations between sensor nodes based on common intervals of their activities. An example of sensor rule is (s1 s2=> s3 ,90%, ), which translates to, if events from sensors s1 and s2 are received, then there is a 90% chance of receiving an event from sensor s3 within units of time. Formulating sensor association rules entails the following tasks: 1) preparing meta- data describing sensors behaviors and 2) finding patterns of sensors that detect events within the same time interval. 2.ASSOCIATION RULES Let S ={s1 s2 s3.sm } be set of sensors in a particular sensor networks. We assume that time slot is divided into equal time slots as {t1,t2. . . . tn} such that ti+1-ti = For all 1 < i < n where is the size of each time slots, and T_his = tn t1 represents the historical period of behavioral data during the process of data extraction. We also refer to P = {s1 s2 s3. . .sk} S as a pattern of sensors. Definition 2.1: A sensor database DS of behavioral data is defined to be a set of epochs in which each epoch is a couple E (Ets, P), where P is a pattern of sensors that report events within the same time slot. Ets is the epochs time slot. Table I shows an example of a behavioral database that consists of four epochs. The first tuple in the database encodes the fact that each sensor (s1,s2 and s3 ) detected at least one event within time slot number 1. For simplicity, we refer to the time slot by an integer number rather than the actual time. TABLE 1 ts 1 2 3 4 P s 1 s2 s3 s1s2 s3 s2 s1 s2 s3 s4
Definition 2.2: Let P1 be a pattern of sensor nodes such that P1 S. We say that an epoch E (Ets,P) supports P1 if P1 P. Definition 2.3: The frequency of pattern P1 in DS is defined as the number of epochs in DS that supports P1, i.e.
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P, E DS}| . additional storage space to store behavioral data during the given historical period. The extraction process starts when the sink diffuses the mining parameters to all nodes in the network. These parameters include the minimum support, the time slot size, and the historical period (see Section II). Upon receiving the mining parameters, each sensor establishes a local buffer B of size (T _his/): one for each time slot. The buffer entry of slot ti is refereed by B (ti ). Initially, all bit entries in the buffer are not set yet. After that, sensors keep track of the time, and at the end of each time slot, each sensor checks for any detected event within this time slot. If there is such an event, the bit entry corresponding to this time slot is set. At the end of the historical period, each sensor examines its local buffer. If the number of set bits is greater than or equal to the given minimum support, the node will establish a message (or a series of messages depending on the packet size) containing the sensor identifier and the time slot numbers in which the corresponding bits are set. 4. IN NETWORK DATA GENERATION MECHANISM To prepare the data needed to generate sensor-association rules, each sensor node should monitor its activity over time and inform the sink about the time slots in which events were detected. The following two main algorithms have been proposed to govern the interaction between the sensor nodes and the sink [1]: 1) direct reporting and 2) distributed extraction. Although the distributed extraction mechanism achieves a good reduction in the number of messages compared with direct reporting, the process of collecting sensor behavioral data is still a costly process due to the limited resources of sensor nodes. However, there is high redundancy among sensors data behaviors (i.e., several sensor nodes share the same time slot numbers in which their events were detected); this redundancy can be removed, thus reducing the size and number of messages needed to report behavioral data. Traditional data-aggregation techniques (e.g., sum, average, and count) are unsuitable for use with sensor data behavior. In this section, we propose a data gathering algorithm that uses an in-network reduction technique to reduce the amount of behavioral data that need to be sent to the sink. The proposed in-network data reduction is implemented on top of a data gathering tree, which we refer to as a minimum nodes data gathering tree (MNDGT) and in cooperation with the distributed extraction mechanism. The MNDGT takes in consideration that not all sensor nodes are going to participate in formulating the sensor association rules, and it is constructed in such a way that those nodes that will participate in formulating sensor association rules are included, plus the nodes that are needed to maintain the minimum distance to the sink. 4. A. PRELIMINARY In this section, we provide the key definitions pertaining to the construction of the MNDGT, which is the tree structure used to route the sensor behavioral data to the sink. The network architecture is assumed to consist of a set of n sensor nodes, i.e., S = {s1 , s2 , . . . , sn }. Time is divided into equal sized slots of size each (among the mining
F req(P1 , DS) = |{E(Ets , P )|P1
Sometimes we refer to the value F req (P1, DS) b y frequency of P1 or support of P1. In this paper, we will not consider how sensor association rules are generated; instead, we focus on how the data required for the mining process are extracted. 3. RELATED WORK Association rules is the data-mining technique that is concerned with discovering the correlations between the objects that co-occur in the same context. Association rules have been used in different domains, such as business analysis [9] and medical applications [10]. In WSNs, association rules have been used to generate patterns pertaining to the sensor nodes and their underlying domain. In this section, we review some of the attempts that have been proposed to use association rules with sensor networks. Loo et al. [11] study the problem of mining associations between sensors values in data streams generated from sensor nodes in a particular WSN. Their technique depends on a data model that stores data reported from sensor nodes and presenting it in a way that facilitates the adaption of a loose counting algorithm [12] that does a one-pass analysis of the data. In this data model, sensors are assumed to take values from a finite discrete number of values. A quantization method is applied for the continuous values. Rmers approach took into consideration the distributed nature of WSNs and proposed an in-network data mining technique to discover the frequent patterns of events with certain spatial and temporal properties. In this approach, each sensor node is aware of the events that are within a certain distance from itself (this distance may be a Euclidean distance or number of hops). The sensor then collects these events and applies a mining algorithm to discover the pattern that satisfies a given parameters. Rmers mining parameters approach includes minimum support S, minimum confidence C, maximum scope, and maximum history. Every node in the network collects the events from the neighbors within the maximum scope and keeps a history of their events for duration of the maximum history. In [1], Boukerche and Sa sensor-association rules as an attempt to extract a pattern regarding the sensor nodes, rather than the area monitored by the WSN. The main difference between sensor association rules and the other techniques is that the data used in the mining process are behavioral data (i.e., meta-data describing the nodes activities), and they differ from the sensed data reported by the sensor nodes (see Section II for more details). In their paper, the following two main approaches for extracting sensor behavioral data from WSNs have been proposed: 1) direct reporting and 2) distributed extraction [1].Direct reporting is an ad hoc solution for extracting the behavioral data. This mechanism makes no assumptions about the capabilities of sensor nodes. Each sensor reports its behavioral data to the sink (i.e., a notification message to the sink if an event was detected within the current time slot), even if it is not participating in formulating the association rules Distributed extraction is designed to put more computational load on the sensor nodes by equipping each sensor with
Each active node scans its candidate parents set and chooses the node with the highest frequency to be its parent. Then, the parent is informed of the nodes decision by sending a build message that carries the nodes identifier. Other kinds of nodes that send build messages are called mandatory nodes. A node is mandatory in the MNDGT if it is inactive and has received a build message. The mandatory nodes are necessary to guarantee that each node can reach the sink with the minimum number of hops. Each parent node maintains a list of its children for further communication. Fig.1. shows the MNDGT for the network in Nodes s3 a n d s10 are mandatory nodes s3 received a build message from s4, and s10 r e c e iv ed a build messages from nodes s13a n d s14. Fig. 3 shows the format of the Definition 4.1: Let si be a sensor node in the set S. construction and build messages. AS(si ) = {t1 , t2 , . . . , tm } such that m (T _his/) and B(tj ) = 1 for all 1 j m is then defined as the activity set of sensors si. . Definition 4.2: si , 1 i n is defined as an active node if |AS(si )| min_sup; otherwise, it is deemed inactive. parameters provided by the user). The in-network reduction mechanism follows the same strategy in distributed extraction to profile sensor behavior [1]. Each sensor has a buffer B o f size (T _his/) one entry for each time slot sensors that control their activities by keeping track of the time, and at the end of the current time slot, each sensor sets the buffer entry corresponding to its slot if an event has been detected during this time. The behavior data of a sensor are ready to be routed to the sink by the end of the historical period, which will take the structure of a set that contains the slot numbers in which the sensor detected events; we refer to this set as the activity set of the sensor. Definition 4.3: N L(si ) is the set of all neighbors of node si that are within its radio transmission. Definition 4.4: Candidate parents of node si , i.e., CP (si ), is the set of nodes in the set N L(si ) that are at the minimum
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distance, in number of hops, from the sink. 4.B.MINIMUN PROCESS NODE DATA GATHERING
The MNDGT construction process starts at the end of the historical period. We assume that each node has prior knowledge about the mining parameters (min_sup, , and T _his) and that it has already prepared its activity set. The sink begins with broadcasting a construction message that consists of the following three fields: 1) sender identifier; 2) hop count; and 3) frequency. The hop count indicates the distance from the sender to the sink. Frequency is the cardinality of the senders activity set. Each node in range of the sink will receive the construction message, update its candidate parents set, and rebroadcast the construction message to its neighbors after it modifies the sender field, the hop count, and the frequency fields. The candidate parents of node x is the set of nodes that are the closer to the sink than node x and which can be used as gateways. Initially, the candidate parents set of the node is empty, but once a message from a node that is closer to the sink than the node in question is received, the sending node is added to the candidate parents set, along with its frequency. Later, if the node receives a construction message from another node that happens to be closer to the sink than any of the other nodes in the candidate set, the closest node is added to the candidate parents set, the old candidates are removed, and a new construction message is broadcasted. It may be that more than one node in the candidate parents set are at an equal distance (same hop count) from the sink. The next step in the MNDGT construction process is determining the links between the nodes (i.e., the actual parents).
Fig. 1.1 MNDGT example - construction phase.

5. NETWORK DATA REDUCTION The MNDGT presented in Section IV-B is used to route the activity sets from the sensor nodes to the sink. However, with-
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out any reduction mechanism, these nodes serve as mere routers for the messages. In this section, we present an in-network reduction mechanism to be integrated with MNDGT to remove some of the redundancy in the activity sets (i.e., sensor nodes may share some elements in their activity sets) while they are being routed to the sink. Recall that a sensor activity set consists of the time slot numbers where the sensor detected events. Sensors data activities differ from other data, and they are not feasible to apply the standard aggregation functions to reduce the amount of the data. However, there is a possible way that can be used to eliminate the redundancy between the activity sets. If we can find a set that is common among a number of activity sets, we will refer to this set as a reference set. The difference operation is applied to the activity set and the reference set, and the results of the difference operation are sent to the sink: the number and size of messages are reduced. To increase the possibility of reduction, the sensors are partitioned into different groups, with each group sharing one reference set. One possible way of partitioning the sensor nodes is to use the structure of MNDGT: by having a node and its children share the same reference set and having each node in the group participate in formulating the reference set. The definition of participation and reference sets is recursive, so we have to take into account the concept of reference sets. 6.PERFORMANCE EVALUVATION A. In-Network Data Reduction Evaluvation Compare the performance of the in-network reduction mechanism with the direct reporting and the distributed extraction mechanisms. The compression is based on a simulator that has been built using Matlab version 7.4.0.287 [34]. In this simulator, 1000 sensor nodes have been deployed in a grid of 450 m 450 m. Each sensor is 15 m away from any other sensor. Fig.2.shows the total number of messages versus support values for historical period of 10 days. As we can see in these figures, the total number of messages for direct reporting is constant for all the support values. This is due to the way that this mechanism reports the activity sets: Each sensor sends its data without knowing if it will participate in formulating the sensor association rules and, thus, the great number of useless messages. For distributed extraction, an equal number of messages is generated in comparison to direct reporting at low support values. However, the total number of messages decreases as the support values increase. The decrease in the number of messages in distributed extraction is due to local decision making by the node based on the cardinality of the local buffer. For in-network data reduction, results show that it outperforms both its counterparts by achieving better message reduction than them (the amount of the reduction is 10%30% of messages achieved by distributed extraction and 10%70% of messages achieved by direct reporting). The in-network mechanism shows the following two areas of optimization to reduce number of messages: 1) the same as in distributed extraction, based on the cardinality of sensor
Fig.2.Total number of messages versus minimum support for 10 days buffer, and 2) the removal of some of the redundancy in the activity sets. Although we have chosen a sufficient enough density factor for event generation, we will get an approximate reduction using lower density factors. This is explained by having the parent node and its children share the same reference set, which is big enough due to the spatial correlation between sensor nodes. Another factor that affects the total number of messages in all three mechanisms is the length of the historical period, as we can see in Fig.2. The total number of messages is doubled for the three techniques for the historical period of 10 days B. Energy Consumption
Fig..3.Average energy consumption per node (M in_sup= 50%). Fig.3.shows the average energy consumption per node for minimum support to be 50% and 90%. In these figures, distributed extraction consumes less energy than direct reporting, for a support value of 50%, and even a better reduction at a support value of 90%. In-network reduction technique outperforms both direct reporting and distributed extraction for support values of 50% and 90%. Energy reduction ranges between 30% (at a minimum support value of 50%) and 70% (at a maximum support value of 90%) of the average energy consumed by distributed extraction and ranges between 50% (at a minimum support value of 50%) and 90%(at a maximum support value of 90%) of the average energy consumed by direct reporting. Furthermore, it can be seen that the energy consumption for the in-network and distributed- extraction techniques decreases at a minimum support value of
90% compared with when the minimum support value is 50% (due to the lower number of active nodes). Another important result that can be deduced from these figures is the amount of energy consumed by each node in in-network reduction, which ranges between 0 and 14 J for a support value of 0%, between 0 and 9 J for a support value of 50%, and between 0 and 2 J for a support value of 90%. The amount of energy in current sensor nodes can accommodate the implementation of the innetwork reduction technique in WSNs because it consumes a low percentage of the sensors energy.
INFO Institute of Engineering, Coimbatore
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[15] K. Akkaya and M. Younis, A survey of routing protocols in wireless sensor networks, Elsevier Ad Hoc Netw. J., vol. 3, no. 3, pp. 325349, 2005. [16] K. Rmer, F. Mattern, and E. Zurich, The design space of wireless sensor networks, IEEE Wirel. Commun., vol. 11, no. 6, pp. 5461, Dec. 2004. [17] U. Lee, B. Zhou, M. Gerla, E. Magistretti, P. Bellavista, and A. Corradi, MobEyes: Smart mobs for urban monitoring with a vehicular sensor network, IEEE Wirel. Commun., vol. 13, no. 5, pp. 5257, Oct. 2006. [18] W. R. Heinzelman, A. Chandrakasan, and H. Balakrishnan, Energyefficient communication protocol for wireless microsensor networks, in Proc. 33rd Hawaii Int. Conf. Syst. Sci., Jan. 2000, pp. 80208030. [19] S. Madden, M. J. Franklin, J. M. Hellerstein, and W. Hong, TAG: A Tiny AGgregation service for ad-hoc sensor networks, ACM SIGOPS Oper. Syst. Rev., vol. 36, no. SI, pp. 131146, Dec. 2002.
7. CONCLUSION
In this paper, we have introduced an in-network reduction mechanism to reduce the amount of the behavioral data, which are extracted from a WSN, needed to generate sensor associtation rules. Performance evaluation has been provided to compare the in-network reduction with the direct-reporting and distributed-extraction mechanisms [1], and results have shown better performance of the in-network technique in terms of energy consumption and number of messages needed to report the behavioral data REFERENCES.
[1] A. Boukerche and S. Samarah, A novel algorithm for mining association rules in wireless ad hoc sensor networks, IEEE Trans. Parallel Distrib. Syst., vol. 19, no. 7, pp. 865877, Jul. 2008. [2] F. Zhao and L. J. Guibas, Wireless Sensor Networks: Information Processing Approach. San Mateo, CA: Morgan Kaufmann, 2002. [3] I. F. Akyildiz, W. Su, Y. Sankarasubramaniam, and E. Cayirci, Wireless sensor networks: A survey, Comput. Netw., vol. 38, no. 4, pp. 393422, Mar. 2002. [4] A. Boukerche, R. W. Pazzi, and R. B. Araujo, A fast and reliable protocol for wireless sensor networks in critical conditions monitoring applications, in Proc. 7th ACM Int. Symp. Model., Anal. Simul. Wireless Mobile Syst., Venice, Italy, Oct. 2004, pp. 157164. [5] P.-N. Tan, Knowledge discovery from sensor data, Sensors, vol. 23, no. 3, pp. 1419, 2006. [6] C. Y. Chong and S. Pumar, Sensor networks: Evolution, opportunities, and challenges, Proc. IEEE, vol. 91, no. 8, pp. 12471256, Aug. 2003. [7] A. Boukerche, F. H. Silva, R. B. Araujo, and R. W. Pazzi, A low latency and energy aware event ordering algorithm for wireless actor and sensor networks, in Proc. 8th ACM Int. Symp. Model., Anal. Simul. Wireless Mobile Syst., 2005, pp. 111117. [8] C. S. R Murthy and B. S. Manoj, Ad Hoc Wireless Networks Architecture and Protocols. Englewood Cliffs, NJ: PrenticeHall, 2004. [9] R. Agrawal, T. Imielinski, and A. Swami, Mining association rules between sets of items in large databases, in Proc. ACM SIGMOD Conf. Management Data, Washington, DC, May 1993, pp. 207216. [10] C.Ordonez, C. Santana, and D. Braal, Discovering interesting association rules in medical data, in Proc. ACM SIGMOD Workshop Res. Issues Data Mining Knowl. Discovery, Dallas, TX, 2000, pp. 7885. [11] K.K.Loo, I.Tong B.Kao and D.Chenung Online algorithms for mining inter-stream associations from large sensor networks, in Proc. 9th PAKDD, Hanoi, Vietnam, May 2005, pp. 143149. [12] G. S. Manku and R. Motwani, Approximate frequency counts over streaming data, in Proc. 28th Int. Conf. Very Large Data Bases, Hong Kong, Aug. 2002, pp. 346357. [13] K. Romer, Distributed mining of spatio-temporal event patterns in sensor networks, in Proc. Euro-Amer. Workshop Middleware Sens. Netw./DCOSS, San Francisco, CA, Jun. 2006, pp. 103116. [14] R. Agrawal and R. Srikant, Fast algorithms for mining association rules, in Proc. 20th Int. Conf. Very Large Data Bases, Santiago de Chile, Chile, Sep. 1994, pp. 487499.
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WAVELET BASED MULTILEVEL IMAGE RESTORATION
S.Karthika,PG scolar,Dept of EEE, Dr.Mahalingam College of Engineering and Technology,Pollachi-642003, karthiskt6@yahoo.com. J.Amudha , Asst.Prof, EEE (PG), Dr.Mahalingam College of Engineering and Technology,Pollachi-642003.
AbstractWe present a multilevel extension of the popular thresholded Landweber algorithm for wavelet-regularized image restoration that yields an order of magnitude speed improvement over the standard xed-scale implementation. The method is generic and targeted towards large-scale linear inverse problems, such as 3-D deconvolution microscopy. The algorithm is derived within the framework of bound optimization. The key idea is to successively update the coef cients in the various wavelet channels using xed, subbandadapted iteration parameters (step sizes and threshold levels). The optimization problem is solved ef ciently via a proper chaining of basic iteration modules. The higher level description of the algorithm is similar to that of a multigrid solver for PDEs, but there is one fundamental difference: the latter iterates though a sequence of multiresolution versions of the original problem, while, in our case, we cycle through the wavelet subspaces corresponding to the difference between successive approximations. This strategy is motivated by the special structure of the problem and the preconditioning properties of the wavelet representation. We establish that the solution of the restoration problem corresponds to a xed point of our multilevel optimizer. We also provide experimental evidence that the improvement in convergence rate is essentially determined by the (unconstrained) linear part of the algorithm, irrespective of the type of wavelet. Finally, we illustrate the technique with some image deconvolution examples, including some real 3-D uorescence microscopy data.
portraits) the imaging system introduces a slight distortion. Often images are slightly blurred and image restoration aims at deblurring the image. Causes For Image Degradation Image may be degraded due to various phenomena like: Motion blur Improper focusing of Camera during image acquisition. Atmospheric turbulence Noise In cases like motion blur, it is possible to come up with an very good estimate of the actual blurring function and "undo" the blur to restore the original image. In cases where the image is corrupted by noise, the best we may hope to do is to compensate for the degradation it caused. Image degradations can be classified into several categories, among which point degradations (or, noise) and spatial degradations (or, blurring) are most common in applications. Other types of degradations involve chromatic or temporal effects.
Example images :
1 INTRODUCTION Image restoration is a process of recovering or restoring an original image from its observed but degraded version. The purpose of image restoration is to restore a degraded/distorted image to its original content and quality. In many applications (e.g., satellite imaging, medical imaging, astronomical imaging, poor-quality family
Figure. 1 (a). Original Image
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set, allowing the deconvolution to be performed.
2.EXISTING SYSTEM
Introduction Inverse problems arise in various imaging applications such as biomicroscopy, medical imaging or astronomy. An increasingly important issue for reconstruction and restoration tasks is the mass of data that is now routinely produced in these fields. The instrumentation typically allows for high-dimensional and multimodal imaging, fostering the evolution of experimental practices towards more quantitative and systematic investigations. This trend will arguably persist over the forthcoming years, and, as a result, computation time will remain a serious bottleneck for restoration methods, despite the progress of computer hardware. In this context, advanced (nonlinear) restoration methods that were developed for traditional 2-D imaging cannot be applied directly; larger-scale problems require more efficient algorithmic implementations.
Figure. 1 (b). Degraded image due to motion blur
Some Methods Available For Restoring The Image Inverse Filter An inverse filter is a linear filter whose point-spread function is the inverse of the blurring function. The advantage of the inverse filter is that it requires only the blur PSF as a priori knowledge, and that it allows for perfect restoration in the case that noise is absent. Wiener Filter Image restoration is implemented using wiener filtering, which provides us with the optimal trade-off between de-noising and inverse filtering. The result is in general better than with straight inverse filtering. Wavelet Restoration Wavelet based algorithms are implemented to restore the image. The image restoration contains two separate steps: Fourier-domain inverse filtering and wavelet-domain image denoising. Blind Deconvolution Blind deconvolution is a deconvolution technique that permits recovery of the target scene from a single or set of "blurred" images in the presence of a poorly determined or unknown point spread function (PSF). [1] Regular linear and nonlinear deconvolution techniques utilize a known PSF. For blind deconvolution, the PSF is estimated from the image or image
Iterative Algorithm Problems
For
Linear
Inverse
In several imaging inverse problems, it may be of interest to encourage the solution to have characteristics which are most naturally expressed by the combination of more than one regularizer. The resulting optimization problems can not be dealt with by the current state-of-the-art algorithms, which are designed for single regularizers (such as total variation or sparseness-inducing penalties, but not both simultaneously). In this method, an iterative algorithm is introduced to solve the optimization problem resulting from image (or signal) inverse problems with two (or more) regularizers. The new algorithm is illustrated in a problem of restoration of group sparse images, i.e., images displaying a special type of sparseness in which the active pixels tend to cluster together.
Thresholded Landweber Algorithm This is a variational deconvolution algorithm that minimizes a quadratic data term subject to a regularization on the -norm of the wavelet coefficients of the solution. We will primarily be interested in the subspace structure of the wavelet
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representation. The tree-structure of the wavelet transformthat is, the embedding of the underlying scaling-function subspaceswill become important for the algorithmic considerations. Given an estimate of the minimizer of C(w), say Wold we define
by temporarily moving up to the next finer scalingfunction subband. UpdateLevel : Recursive procedure which updates the subbands at coarser scales by calling itself step size times. Then updates the subbands at scale by calling (the number of updates before and after a recursive call are fixed by and , respectively). Note that the procedure must compute the current residual for the scalingfunction subband at scale before calling itself. This is either done by applying the correction principle in the opposite direction (from the wavelet subbands to the scaling-function subband), or by going to the next finer scale using UpdateResidual . MLTL: Main routine that performs initialization tasks followed by several iterations of the update procedure. One may devise even more general e.g. full multigrid schemes by adapting this routine. Numerical Experiments Asymptotic Convergence
This functional has three important characteristics. 1) When ,W = Wold takes the same value as C(w) 2) For all other values of A(w) , is an upper-bound of C(w), 3) A(w)admits a minimizer with a closed-form expression.
3 .PROPOSED SYSTEM Multilevel Thresholded Landweber Algorithm General Multilevel Scheme We provide a pseudo-code description of a method that is strongly inspired by the multigrid paradigm. However, there is one fundamental difference: traditional multigrid schemes typically cycle through nested subspaces corresponding to increasingly coarse discretizations of the original inverse problem. In the present context, we successively update the wavelet subbands at every scale; that is, we reinterpret the different scales of the wavelet transform as a multilevel representation of the inverse problem. The corresponding subspaces are not nestedthey contain the oscillating components corresponding to the difference between successive coarse-level approximations. Incidentally, early attempts to apply the multigrid paradigm to image-restoration problems remained relatively unsuccessful because they were concentrating on slowly oscillating components. The different modules of multilevel scheme are as follows: UpdateResidual : Updates the residual for the subbands at scale (if needed). Uses the correction principle if the wavelet subbands have not been modified so far. Otherwise, the update is performed
We then used this reference to compare the asymptotic behavior of the TL and MLTL algorithms. To this end, we performed a series of experiments where the algorithms are applied to the minimization of (1) and initialized with the measurement . Although the asymptotic convergence rates that are presented here may not be directly relevant to practical situations, they give a quantitative indication of the acceleration potential of the MLTL algorithm. Our asymptotic study required several thousand iterations of the TL and MLTL algorithms in various configurations, which is why we resorted to a small-scale problem. Computation Time This type of assessment is most relevant in practical situations, but it depends on computer hardware parameters. Therefore, it is provide a comparison with the standard TL algorithm. We first simulated the effect of a defocusing blur on a 512 512 test image. We used a standard diffractionlimited point spread function (PSF) model for widefield fluorescence microscopy. We restored this simulated measurement using the TL and MLTL algorithms. Both were initialized with the measurement. We used a separable orthonormalized cubic spline wavelet basis with four decomposition levels. CONCLUSION Previously available methods have essentially consisted in alternating between a Landweber
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iteration and a wavelet-domain soft-thresholding operation. While having the advantage of simplicity, they are known to converge slowly. By expressing the cost functional in a Shannon wavelet basis, we are able to decompose the problem into a series of subband-dependent minimizations. In particular, this allows for larger (subbanddependent) step sizes and threshold levels than the previous method. This improves the convergence properties of the algorithm significantly. We demonstrate a speed-up of one order of magnitude in practical situations. This makes waveletregularized deconvolution more widely accessible, even for applications with a strong limitation on computational complexity. We present promising results in 3-D deconvolution microscopy, where the size of typical data sets does not permit more than a few tens of iterations.
[7]
W. L. Briggs and V. E. Henson, Wavelets and multigrid, SIAM J. Sci. Comput., vol. 14, no. 2, pp. 506510, Mar. 1993.
[8] S. Mallat, A theory for multiresolution signal decomposition: The wavelet representation, IEEE Trans. Pattern Anal. Mach. Intell., vol. 11, no. 7, pp. 674693, Jul. 1989.
REFERENCES [1] Cdric Vonesch and Michael Unser, A Fast Multilevel Algorithm for WaveletRegularized Image Restoration, IEEE TRANSACTIONS ON IMAGE PROCESSING, VOL. 18, NO. 3, March 2009 [2] C. Vonesch and M. Unser, A fast thresholded Landweber algorithm for waveletregularized multidimensional deconvolution, IEEE Trans. Image Process., vol. 17, no. 4, pp. 539549, Apr. 2008 [3] P. Sarder and A. Nehorai, Deconvolution methods for 3-D fluorescence microscopy images, IEEE Signal Process. Mag., vol. 23, no. 3, pp. 3245, May 2006. I. Daubechies, M. Defrise, and C. De Mol, An iterative thresholding algorithm for linear inverse problems with a sparsity constraint, Commun. Pure Appl. Math., vol. 57, no. 11, pp. 14131457, Aug. 2004.
[4]
[5] M. A. T. Figueiredoa and R. D. Nowak, An EMalgorithm for waveletbased image restoration, IEEE Trans. Image Process., vol. 12, no. 8, pp. 906916, Aug. 2003 [6] R. D. Nowak and M. A. T. Figueiredo, Fast wavelet-based image Deconvolution using the EM algorithm, presented at the 35th Asilomar Conf. Signals, Systems and Computers, Pacific Grove, CA, Nov. 2001
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Adaptive Neuro Fuzzy Control of Flexible Joint Robot Manipulator

P. Hari Krishnan#1, A. Johnson Antony#2
#1
Lecture, Department of electrical and electronics engineering, Anna University of technology, Coimbatore, India.
#2
Department of electrical and electronics engineering , Anna University of technology, Coimbatore, India.
2
johnson.vlb@gmail.com
AbstractThis paper aims to advance methodologies to optimize fuzzy logic controller parameters via neural network and use the neuro-fuzzy scheme to control flexible robot manipulators. The dynamics of robot manipulators are highly nonlinear with strong couplings existing between joints and are frequently subjected to structured and unstructured uncertainties. The increased complexity of the dynamics of robots manipulator considering joint elasticity makes conventional model-based control strategies complex and difficult to synthesize. This paper presents investigations into the development of neuro Fuzzy control for position and velocity control of a flexible joint manipulator. To study the effectiveness of the controllers, a Neuro Fuzzy Controller is developed for tip angular position control of a flexible joint manipulator. This is then extended to incorporate a neuro fuzzy Controller for velocity error reduction of the flexible joint system. Simulation results of the response of the flexible joint manipulator with the controllers are presented in time domains. The performances of the neuro fuzzy control schemes are examined in terms of input tracking capability, level of vibration reduction and time response specifications. Key words flexible structure, Manipulator, neuro-fuzzy control, Uncertain system.
applications. The control issue of the flexible joint is to design the controller so that link of robot can reach a desired position for track a prescribed trajectory precisely with minimum vibration to the link. In order to achieve these objectives, various methods using different technique have been proposed. However, controlling such systems still faces numerous challenges that need to be addressed before they can be used in abundance in everyday real-life applications. The severe nonlinearities, coupling stemming from the manipulators flexibility, varying operating conditions, structured and unstructured dynamical uncertainties, and external disturbances, are among the typical challenges to be faced with when dealing with such often ill-defined systems Industrial robot manipulators are mainly positioning and handling devices. The essential problem in controlling robots is to make the manipulator follow a desired trajectory. In general degree of freedom rigid robot manipulator is characterized by nonlinear, dynamic, coupled differential equations. The problem of controlling robot manipulators still offers many practical and theoretical challenges due to the complexities of the robot dynamics and the requirement to achieve high precision trajectory tracking in the cases of high velocity movement and highly varying loads. This paper presents investigation into the development of adaptive neuro fuzzy control for trajectory tracking of tip angular position and vibration control of flexible joint manipulator. Initially a adaptive neuro fuzzy Control is developed for trajectory tracking of tip angular position. The performances of the composite control schemes are examined in terms of input tracking capability, level of vibration reduction and time response specifications. The rest of the paper is structured as follows: Section II provides a brief description of the flexible joint manipulator system considered in this study. In Section III, we introduce a number of soft computing-based controllers. The design of the proposed controller is detailed in Section IV. In Section V, simulation results are reported and discussed. We conclude with a few remarks and suggestions for further studies pertaining to this important, yet complex, control problem.
I INTRODUCTION In most existing robotic manipulators, maximizing stiffness to minimize vibration and achieve good position accuracy of robotic manipulators is a key element in their design. This high stiffness is achieved by using heavy material and a bulky design. Hence, the existing heavy rigid manipulators are shown to be inefficient in terms of power consumption and operational speed. In order to improve industrial productivity, reducing the weight of the arms and increasing their speed of operation are required. Therefore, flexible-joint manipulators have received a thorough attention lately, thanks to their lightweight, lower cost, larger work volume, better manoeuvrability, higher operational speed, power efficiency, and larger number of applications. Flexible-joint manipulators have received a thorough attention lately thanks to their light weight, high maneuverability, flexibility, high power efficiency, and large number of applications. However, controlling such systems still faces numerous challenges that need to be addressed before they can be used in abundance in everyday real-life
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Given the desired trajectories qd and qd, we aim to design a control law m which ensures that the manipulators position q and velocity q track their desired trajectories under unknown dynamics and in the presence of external disturbances. The proposed controller uses q, q, and as systems measurable states, and the manipulators parameters M(q), C(q, q), G(q), Jm, fl, fm, dl, and dm are assumed to be unknown. B. Friction Modeling The complexity of system is increased even further by adopting a highly nonlinear a priori unknown friction model that is composed of Coulomb, viscous, and static friction terms. The model of such memory less friction operating along a displacement x is described by (4) where Fc, Fv, and Fs are the Coulomb, viscous, and static friction parameters, respectively, and s is the rate of decay of the static friction term. This friction model is used to represent friction at each joint of the manipulator. C. Dynamic Modelling of the Robot A schematic diagram of the robot is given in Fig. 2 The mass and elastic properties of the link are assumed to be distributed uniformly along the link. The flexible link is taken to be an Euler Bernoulli beam. Represent the angular position of the equivalent rigid link with respect to the fixed frame of reference XY. D represents the linear displacement of the tip relative to the equivalent rigid link. Assuming small deflections of the link, an approximate linear time invariant dynamic model can be derived using Lagrangian formulation and the dynamic equations represented in matrix form as Where q is the vector of generalized coordinates. T , M is the mass matrix, C is the damping matrix, K is the stiffness matrix, and F=[T 0]T. T is the input torque applied at the joint. The variable (=D/L) approximately represents the slope at the free end of the flexible link. The dynamic model can be represented in state space form as y=Cx where by (5) (6)
II. FLEXIBLE-JOINT MANIPULATOR DYNAMICS A. Flexible-Joint Manipulator Modeling
Fig.1. Flexible-joint model Typically, a flexible joint can be modeled as shown in Fig. 1. The actuator is coupled to a flexible transmission through an r : 1 reduction gear. The transmission is directly linked to the load (e.g., manipulator link).Consider a robot manipulator with n revolute flexible joints. Using EulerLagrange formulation and neglecting gyroscopic effects, the dynamic equations of the manipulator can be written as (1)
(2) (3) Where vector of links positions; vector of motors positions; manipulators positive definite inertial matrix; C(q, q) Rnn matrix of Coriolis and centrifugal terms; G(q) Rn vector of gravitational torques; Jm Rnn motors diagonal inertial matrix; t Rn vector of transmission torques; m Rn motors generalized torque vector (control input); fl Rn load friction vector; fm Rn motors friction vector; dl Rn loads unmodeled dynamics and external disturbance vector; dm Rn motors unmodeled dynamics and external disturbance vector; K Rnn diagonal matrix of joints stiffness coefficients; r R gear ratio. q Rn Rn M(q) Rnn
and the matrices A, B, and C are given (7)
(8) (9)
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In order to achieve accurate trajectory tracking and good control performance, a number of control schemes have been developed. Amongst these, Adaptive Neuro-Fuzzy System has provided best results for control of robotic manipulators as compared to the conventional control strategies.ANFIS is a fuzzy inference system implemented in the framework of adaptive networks. By using a hybrid learning procedure, the ANFIS can construct an input-output mapping based on both human knowledge (in the form of fuzzy if-then rules) and stipulated input-output data pairs. The hybrid learning algorithm identifies the membership function parameters of single-output, Sugeno type fuzzy inference systems (FIS). A combination of least mean squares (LMS) and backpropogation gradient descent methods are used for training FIS membership function parameters to model a given set of input/output data. The parameters associated with the membership functions change through the learning process. The training process stops whenever the designated epoch number is reached or the training error goal is achieved. The nonlinearity prevailing in the arm dynamics induces high uncertainty in the performance of the robotic manipulators under conventional control strategies. The use of the intelligent systems such as neural networks and fuzzy control has provided better results. But a combination of such intelligent systems, like, neuro-fuzzy or ANFIS provides even better results than just neural networks. A. ANFIS architecture For simplicity, we assume the fuzzy inference system under consideration has two inputs x and y and one output z. Fig. 3 Depicts the structure of Adaptive neuro fuzzy controller below:
where the matrices I2x2 , I4x4 , 02x2 and 02x1 are the 2x2 identity matrix, the 4x4 identity matrix, the 2x2 matrix of zeros, and the 2x1 matrix of zeros, respectively.
Fig.2. Schematic diagram of the flexible link robot arm III. SOFT-COMPUTING-BASED CONTROL In spite of the recent advances in the area of nonlinear control systems, the common point still shared by the vast majority of conventional control techniques is their dependence on precise mathematical models of the systems to be controlled for them to provide satisfactory performance. In real life, and due to the typical high nonlinearities within the dynamics of flexiblejoint manipulators, deriving a precise model for such systems could be a difficult undertaking. Although conventional adaptive control strategies, such as in sliding mode controllers, compensate for the systems parametric uncertainties, they are still vulnerable in the face of unstructured modeling uncertainties. Expert controllers based on tools of soft computing, on the other hand, may not have such a limitation. In fact, computational intelligence tools, in general, have been credited in a number of applications to provide satisfactory results in the face of relatively large
magnitudes of noise in the input signals, of dynamically variable parameters, and in the lack of a precise mathematical model of the system in hand.
IV ADAPTIVE NEURO FUZZY CONTROL In recent years, intelligent control in general, and neuro-fuzzy control in particular, have been quite inspiring paradigms for real-time control applications. Neuro-control based artificial neural networks, having the ability to learn from input-output non-linear functions, are good candidates for solving complex nonlinear control problems. Neurons are basically non-linear elements; hence, neural networks are basically non-linear systems which can be used to learn and solve non-linear control problems that are usually too difficult for traditional and conventional control methods to handle. Using the inverse model as the main block in the neuro-control approach is one of the most widely applied schemes.
Fig.3. Structure of neuro fuzzy controller B. Hybrid Learning Algorithm The hybrid learning algorithm used in adaptive neuro fuzzy system is combination of least mean square back propagationgradient descent methods. Least Mean Squared Algorithm: This is the most elementary algorithm used for updating parameters to give adaptive response. The basic steps involved in this algorithm can be summed up as:
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calculate the difference between the data value and the model prediction at several different places (this is called the error) square the error to make all values positive (square) calculate the average (mean square) find the model alternative that gives the smallest error (least mean square)
To understand the hybrid learning algorithm better, we consider an illustration wherein the adaptive filter adjusts its coefficients to minimize the error between its output and that of an unknown system. V. SIMULATION RESULTS AND DISCUSSION Experimental Setup To demonstrate the performance of the proposed controller, a set of numerical experiments is carried out on a single link flexible-joint manipulator. The manipulators dynamics in terms of its physical parameters is defined by M(q) = I, C(q, q) = 0, and G(q) = mgl sin(q), where m is the links mass, g is the gravity constant, and l is the links length. Table I summarizes the manipulators physical parameters along with their respective values. The stiffness coefficient and gear ratio are assumed to be K = 5 N m/rad and r = 1.
Fig.5(b). Controllers response Position error.
Fig 5 (c) Motors velocity versus manipulators velocity.
Fig.4. Manipulators position and velocity reference signals.
Fig 5(d) Manipulators velocity error. VI CONCLUSION The development of neuro fuzzy control techniques for position and velocity error reduction of a flexible joint manipulator has been presented. The proposed control schemes have been implemented and tested. The control strategy is based on a neuro fuzzy control approach while taking into account the actuators relative stability criterion by introducing a trade-off between the actuators internal stability and the links position. The performances of the control
(a) Fig.5(a). Controllers response. Desired and estimated manipulators positions.
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schemes have been evaluated in terms of input position and velocity error reduction at the resonance modes of the manipulator. Acceptable performance in input position and velocity control has been achieved with proposed control strategies. The work thus developed and reported in this paper forms the basis of design and development of hybrid control schemes for input position and velocity error reduction of multi-link flexible manipulator systems and can be extended to and adopted in practical applications. REFERENCES [1]. Y. Pan, U. Ozguner, and O. H. Dagci, Variablestructure control of electronic throttle valve, IEEE Trans. Ind. Electron., vol. 55, no. 11, pp. 38993907, Nov. 2008. [2]. A. Chatterjee, R. Chatterjee, F. Matsuno, and T. Endo, Augmented stable fuzzy control for flexible robotic arm using LMI approach and neurofuzzy state space modeling, IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 12561270, Mar. 2008. [3]. L. Sweet and M. Good, Redefinition of the robot motion-control problem, IEEE Control Syst. Mag., vol. 5, no. 3, pp. 1825, Aug. 1985. [4]. B. Armstrong and C. C. de Wit, Friction modeling and compensation, in The Control Handbook, vol. 77. Boca Raton, FL: CRC Press, 1996, pp. 1369 1382. [5]. H. Olsson, K. Astrom, C. C. de Wit, M. Gafvert, and P. Lischinsky, Friction models and friction compensation, Eur. J. Control, vol. 4, no. 3, pp. 176195, 1998. [6]. S. Katsura and K. Ohnishi, Force servoing by flexible manipulator based on resonance ratio control, IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 539547, Feb. 2007. [7]. D. Seidl, S.-L. Lam, J. Putman, and R. Lorenz, Neural network compensation of gear backlash hysteresis in position-controlled mechanisms, IEEE Trans. Ind. Appl., vol. 31, no. 6, pp. 14751483, Nov./Dec. 1995.
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DATA DRIVEN QUALITY PREDICTION IN A REFINING PROCESS USING ADVANCED OPTIMIZATION TECHNIQUE P.HARI KRISHNAN #1, V G HARI HARA SUDHAN #2
#1
Lecturer, Dept. of electrical and electronics engineering, Anna university of technology Coimbatore, Coimbatore. hariora@yahoo.com M.E.(C&I) Dept. of electrical and electronics engineering, Anna university of technology Coimbatore, Coimbatore. deenaeie@gmail.com
#2
Abstract In petrochemical industries, the product quality reflects the commercial and operational performance of a manufacturing process. However, the real time measurement of product quality is generally time consuming. Online prediction of product quality is readily available like frequent process measurements and is beneficial in terms of operation and quality control. A soft sensor technology using Differential evolution (DE) is developed for quality prediction based on fault analysis in the primitive methodology implemented in the process and available lab measurements. Thus the performance of the proposed soft sensor approach to measure and analyse the quality of the process is to be determined. Keywords differential evolution, quality prediction, refining process INTRODUCTION The petrochemical industry, especially refining industry is characterized as a highly complex process operated through a modern control system. Advanced process control is widely used to improve efficiency, optimize the process operation and produce products with specified quality. In refinery both lab and online analyzer measurements are available for measuring product quality. The drawbacks of lab/analyzer measurements include slow, infrequent and sometimes un reliable; the more accurate lab measurement is even slower (time delay of hours) and less frequent (about one or two samples per day). Thus a direct sensing control strategy is not tenable. Reliable online prediction of quality would be extremely beneficial in this environment; the real time information about the effect of operational parameters on the product quality would allow control room personnel to make timely adjustment to the process to keep the control variables within limits. Such prediction is based on the ability to correlate the effect of process
variables on the product quality. First principles based physicochemical models are difficult to develop for large scale real life process due to their inherent complexity. This motivates data driven models. Hence knowledge in process variables along with its limits is of considerable importance. The widespread use of distributed control system (DCS) has allowed refiners to increase the number of measurements and actuators on the process. The integration of process historians with DCS provides a wealth of process data that can be exploited to extract information. In the case of complex systems where the process mechanism is not well understood, empherical models developed by system identification techniques are used to derive the correlation among variables. Among the techniques, neural network (NN) technology and multiple linear regressions have been widely employed to develop such data-driven models. NNs are a powerful tool for non linear system identification. They have been applied in a variety of applications such as process control, signal processing, pattern recognition, and process monitoring. Recently, it has been reported that neural net-based models have been used in refinery industry for quality prediction. Many advantages can be identified from their applications to inferential modelling. They can easily learn the nonlinear relationship among the variables and approximate it to the desired degree. PRE PROCESSING OF DATA Data collection Property predictors are modelled from historical process and lab data. The process data may come from a data historian or an information system, it may come from a SCADA package historian, or it may be made up of sets of data that were periodically downloaded from a DCS historian. Typically data collection is an iterative exercise, where a first dataset is modelled and then more data are collected to improve the
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essential step in soft sensor development. In the univariate approach, outliers are detected based on visualization together with the six-sigma rule. Xi is labeled as an outlier based on a six-sigma threshold if
accuracy or range of the property predictor that results. Data pre-processing The quality of the predictor data X is very important in PLS regression models. Suitable pretreatment of X is sometimes crucial for the resulting model; often it may mean the difference between success and failure. Industrial data offers unique challenges due to its quality while an ideal dataset would contain process information as much as possible, little noise and no outliers, the contrary is, in fact, most common in industrial situations. Missing data points are also very common in industrial practice and with no readily apparent pattern. These data quality issues need to be carefully addressed prior to the modelling step. We have followed the following steps to improve data quality. i. All process data were checked visually at first. Anything that appeared suspicious from a process point-of-view was doublechecked and carefully considered to determine if they should be removed. In the refinery process, missing data points not only exist in predictor data but also in the predicted quality data. For instance, in the current work, one of the quality streams is measured in the analytical lab and at irregular intervals (the average is one measurement every eight hours).
ii.
where is the mean of data sequence and is the standard deviation, based on the normal distribution assumption of data. Unfortunately, this procedure fails in both theory and industrial practice because the outliers tend to inflate the variance estimation, resulting in too few outliers being detected. Even though robust outliersresistant estimates such as median absolute deviation have been developed, they are applicable only to univariate data. Since variables in a refinery process are usually not independent on one another, univariate outlier detection may not be effective and can result in masking and swamping effects, where outliers are incorrectly identified as normal samples, or normal samples classified as outliers. We have developed a multivariate analysis scheme based on DE for abnormal sample detection and elimination. High leverage points are those that are outliers with respect to the independent variables. Influential points are those that when deleted cause large changes in the parameter estimates. Although an influential point will typically have high leverage, a high leverage point is not necessarily an influential point. On the other hand, once the coefficients in DE model are available, the prediction of the predicted variables based on the model can be obtained. The residuals are the difference between the known values and predicted ones, and are an indication of the fit of the -value of a sample. The residual versus leverage plot thus allows identification of unusual, harmful samples. Generally, the decision to classify a sample as an outlier is made based not only on the statistics but also on process knowledge and the experience of the user. DIFFERENTIAL EVOLUTION Based on the process analysis, the proceeding is based on an emerging evolutionary technique called as DE. DE is a relatively new EA and it has been gaining popularity during previous years. Several extensions of DE for multi-objective optimization have already been proposed. Some basic approaches just convert MOOPs to singleobjective forms and use DE to solve. The first version of a Generalized DE extended DE for constrained multi-objective optimization and was obtained by modifying the selection rule of the basic DE. The key parameters of control are NP
This resulted in a large number of constant (missing) recordings of the predicted quality. To overcome this, the time of new quality measurements were carefully noted and only the corresponding process variable values were selected for data construction and validation. The predictor data were then obtained only from high-quality samples. If missing elements exist in a small block of the predictor dataset, interpolated values based on neighbouring observations may be inserted. In the case of a large block corrupted with missing data, the entire block was not included in the training set. Outliers Outliers, which can be simply regarded as the data points that are not consistent with the bulk of data, are common in industrial data set. A soft sensor derived by PLS or other methods may deteriorate significantly even with a single outlier. Therefore, outlier detection constitutes an
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Caustic solution of low strength and demulsifier are also added after the pressure control value of the Desalter. Caustic solution is added to control PH of the brine solution. Demulsifier addition helps better separation of brine water from crude oil. Crude after getting pre-heated to 100-150 Deg.c depending on crude characteristics enters the desalter through a mixing valve. This valve helps in mixing effectively the water and crude oil and thus ensuring that the salts present in crude oil get dissolved in water. The pressure drop across this valve will determine the degree of mixing. In desalter, the emulsion formed by mixing crude oil with water is resolved by introducing it into a high voltage electric field. The action of the electric field coagulates the dispersed water phase and gravity causes the water droplets to form and collect in the bottom of the vessel. The water which contains the various impurities removed from the crude is continuously discharged in to the effluent stream. Clean desalted crude flows from the top of the desalter. Crude oil from preheating exchangers is further heated up to a temperature of desired vaporization. These heaters may be to cylindrical or rectangular shape having a convection and radiant section. Crude feed to heater flows in multi passes. The no of passes is decided on the basis of crude quantity being processed. Flow in each pass is controlled. The pressure drop across each coil is a measure of coke formation in the tubes. In some of the furnaces a portion of the convection section may used for steam generation. The heat carried away by the flue gas is utilizing for preheating the air in the air preheater before being finally released to atmosphere. The crude after gaining heat is taken to the crude distillation column in a partially vaporised form. Crude distillation column has to section. Feed coming from the heater enters the flash zone of the column just above the stripping zone. In the distillation column bottom substantial quantity of steam is introduced to strip off lighter fractions. This also helps in vaporization of hydrocarbon by lowering of partial pressure. Stripped vapour and vaporized fractions of crude rise through the upper section and separated in to overhead and side stream products. Depending on the composition of the crude overhead vapour will be totally on partial condensed. The condensed liquid is partially used as reflux to control the top temperature and balance flows as feed top stabilizer section. If the overhead vapours cannot be condensed to bring down its dew point temperature.
the population size, CR the crossover constant, F the weight applied to random differential. The basic idea in the selection rule was that the trial vector was selected to replace the old vector in the next generation if it weakly constraintdominated the old vector. There was no sorting of non-dominated vectors during the optimization process or any mechanism for maintaining the distribution and extent of the solution. Also, there was no extra repository for non-dominated vectors. Still, GDE was able to provide a surprisingly good solution but was too sensitive for the selection of the control parameters. Later on GDE was modified to make a decision based on the crowdedness when the trial and old vector were feasible and nondominating each other in the objective function space. This improved the extent and distribution of the solution but slowed down the convergence of the overall population because it favoured isolated vectors far from the Pareto front before all the vectors were converged near the Pareto front. DE seems to be an inspiration from both Genetic Algorithms and Evolutionary Strategies combined with a geometrical searching principle. Genetic Algorithms blows the pattern structure along with its mutation and crossover concepts, while Evolutionary Strategies introduce the ideas of self-adaptation based on a geometrical manipulation of individuals. Different points of view and different adaptation models have been proposed to keep up the needed exploration level in order to avoid either stagnation or premature convergence. Besides, there were attempts to empirically estimate a valid range of control parameters and their sensibility for a set of commonly used benchmarks. PROCESS DESCRIPTION The following process deals with the extraction of diesel. Crude oil stored in offsite oil storage tanks is pumped to the atmospheric section by crude oil charge pumps. The crude is pre-heated in exchange to an optimal desalting temperature of 100 150 Deg.c. The heating medium used in these exchangers will normally consist of product and pump streams drawn from the top portion of the atmospheric and Vaccum distillation tower. The heating medium may also consist of other products coming out after the first state heat recovery. Apart from heat recovery the reason why crude is desalter? Crude before getting preheats and sent to desalter is injected either with hot condensate recovered from the process or boiler feed water. This wash water is to leach out the salts that are present in the crude oil. All desalters require usually2.5 to 6 percent volume of wash water to the crude charge stream.
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f = -20.3125x1+27.8178x2+1.1914x3-0.755x4-
Products like heavy naphtha, kerosene, diesel etc., are withdrawn as side draw offs and further steam stripped in individual strippers to remove the lighter ends. Reduced crude oil from the bottom of the column is sent as feed to Vaccum section. Bottom, middle and top pump around refluxes are withdrawn from different trays, cooled and returned to the column to remove the heat and maintain the desired temperature profile in the column. PROBLEM FORMULATION The quality of the diesel is well estimated using parameter prediction. There are various methods in determining the quality of the diesel. One such methodology is recovery process. In this process the diesel is evaporated at 370 Deg.c and is then collected through condensation process. The volume of the source and collected diesel is compared. The deviation is proportional to the presence of other ingredients. In order to reduce other ingredients online control of parameter is implemented. The various parameters affecting the quality of the diesel are as follows
0.9507x5+0.6592x6+0.7956x7-0.3325x8+0.6414x90.08310-0.6629x11-0.3609x12-0.711x13 Where, x1 Over flash rate x2 Column top pressure x3 Column flash zone pressure x4 Column flash zone temperature x5 diesel stripper bottom temperature x6 Column top temperature x7 Bottom pump around draw temperature x8 Middle pump around draw temperature x9 Heavy naphtha draw temperature x10 Top pump around draw temperature x11 Top pump around return temperature x12 Middle pump around return temperature x13 Bottom pump around return temperature The various constraints involved in diesel quality include volume of the distillation column and out flow rate of diesel from the column. The minimum constraints required for formulating the problem is given by a) Fractionating column capacity 1138.48lb/hr 20.3125x1+27.8178x2+1.1914x3+0.755x4+0.9507x5 +0.6592x6+0.7956x7+0.3325x8+0.6414x9+0.08310+ 0.6629x11+0.3609x12+0.711x13 1138.48 b)Out flow of diesel 180 metric tonne/hr (30% of feed rate) -20.3125x1+27.8178x2+1.1914x3-0.755x40.9507x5+0.6592x6+0.7956x7-0.3325x8+0.6414x90.08310-0.6629x11-0.3609x12-0.711x13 180 RESULT AND CONCLUSION Table 1 presents the comparison between lab measurement and estimated values along with absolute error value The error analysis between lab measurements and predicted value is given as follows Rec @ 370 deg c ABS LAB ESTIMATE ERROR ERROR 86 91 91 91 89.37 89.25 88.78 90.85 -3.37 1.75 2.22 0.15 3.37 1.75 2.22 0.15
.fig 1 Structure of fractionating column The objective function for the quality of the diesel is given by
512
89 92 86 97
87 94 92 88 93 93 94 93 91 91 94 92 95 93 94 94 96 89 90 92 92 92 95 86 91 90 91 93 90 92 91 93 91 91 93 96 96 91 92 90 88 90
89.35 91.77 90.10 90.04 90.91 93.22 93.52 93.82 91.81 92.82 93.41 92.24 91.83 91.51 91.35 92.85 95.84 91.75 92.45 93.28 90.79 92.15 90.07 90.84 91.40 90.62 93.19 91.67 90.68 92.20 90.65 90.68 91.78 92.79 92.89 96.62 94.97 91.27 90.64 89.10 90.15 89.13
-2.35 2.23 1.90 -2.04 2.09 -0.22 0.48 -0.82 -0.81 -1.82 0.59 -0.24 3.17 1.49 2.65 1.15 0.16 -2.75 -2.45 -1.28 1.21 -0.15 4.93 -4.84 -0.40 -0.62 -2.19 1.33 -0.68 -0.20 0.35 2.32 -0.78 -1.79 0.11 -0.62 1.03 -0.27 1.36 0.90 -2.15 0.87
2.35 2.23 1.90 2.04 2.09 0.22 0.48 0.82 0.81 1.82 0.59 0.24 3.17 1.49 2.65 1.15 0.16 2.75 2.45 1.28 1.21 0.15 4.93 4.84 0.40 0.62 2.19 1.33 0.68 0.20 0.35 2.32 0.78 1.79 0.11 0.62 1.03 0.27 1.36 0.90 2.15 0.87
90.54 92.12 88.80 92.90
-1.54 -0.12 -2.80
1.54 0.12 2.80
4.10 4.10 TOT ERROR 75.83 AVG ERROR 1.52 Differential evolution exhibits difficulties in dealing with equality constraint problems but in general, they are the most efficient in terms of function evaluations. Future work will address the comparison of DE with adaptive random search algorithms, as well as the treatment of equality constraints. REFERENCES [1]. [1] L. Fortuna, S. Graziani, A. Rizzo, and M. G. Xibilia, Soft Sensors for Monitoring and Control of Industrial Processes. New York: Springer, 2007. [2]. [2] D Simon, Optimal State Estimation: Kalman, H Infinity, and Nonlinear Approachesa. New York: Wiley, 2006. [3] G. Martin, G. Barber, Z. Friedman, and E. Bullerdiek, Refining andpetrochemical property predictions for distillation, fractionation and crude switch, in Proc. 000 Comput. Conf., Chicago, IL, Nov. 13 15, 2000, 13 pages. [4] N. Bonavita and T. Matsko, Neural network technology applied to refinery inferential analyzer problems, Hydrocarbon Engineering, Dec. 1999 [Online].Available:ttp://library.abb.com/gl obal/scot scot267.nsf/veritydisplay/1e9fce2471d1a9 3385256f9b005b9d1a/ $File/NN_for_Refineries.pdf, Last accessed date: 21 July 2009 [5] J. Liu, R. Srinivasan, and P. N. S. Guru, Practical challenges in development data-driven soft sensors for quality prediction, ESCAPE-18, pp. 961 966. Singleand Multiple-Objective Optimization with DifferentialEvolution and Neural NetworksMan Mohan Rai*NASA Ames Research Center, Moffett Field, CA-94035, USA Optimization Of Thermal Cracking Operation Using Differential Evolution B.V. Babu* And Rakesh Angira Department Of Chemical Engineering Birla Institute Of Technology & Science Pilani - 333 031.
[3].
[4].
[5]. [6].
[7].
[8].
[9].
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MODEL BASED PREDICTIVE CONTROL FOR MEMBRANE BIOREACTOR IN SEWAGE WATER TREATMENT
P.HARI KRISHNAN #1, D.DEENA #2
#1
Lecturer, Dept. of electrical and electronics engineering, Anna university of technology Coimbatore,Coimbatore. hariora@yahoo.com #2 M.E.(C&I) Dept. of electrical and electronics engineering, Anna university of technology Coimbatore,Coimbatore. deenaeie@gmail.com
Abstract:- Membrane bioreactors (MBR) for wastewater treatment, which have increasingly been employed for the last 15 years and which play an important role in wastewater treatment. It is the continuation of the fundamental contribution of sewage water treatment, which is extended and complemented in various aspects. In this project an advanced control approach is made to bring desired purification for sewage water. The major challenge in controlling MBR is the large amount of uncertainty present in the process models, in the unknown inflow conditions, and in the limited measurement information. Hence, controller development is driven by the necessity to structure uncertainty, to attenuate its harmful effects, and to exploit it wherever possible. Such a control method is model based predictive controller. The frame work for the model-based control of membrane bioreactors (MBR) is developed, which aims at the economical optimization of MBR operation Keywords: MBR, NMPC, Optimization. I. INTRODUCTION Water is a global resource indispensable for life on earth. Its responsible and sustainable use and reuse is a major challenge of the 21st century. The increasing world population and industrialization lead to a rising demand for potable and process water, and in many areas existing supplies are diminishing at critical rates. Untreated wastewater threatens intact biological systems by introducing large amounts of nutrients, toxic or endocrines species, heavy metals and other harmful components. For these reasons efficient water
treatment and reuse have become decisive social and economical issues. In many countries legal limits on the effluent concentrations of selected components are tightened, e. g. by the European Water Framework Directive issued in 2000. Strict effluent constraints however together with increasing wastewater loads demand efficient treatment processes. At the same time the increasing privatization of wastewater treatment facilities requires a stronger focus on their economic performance. This context provides the motivation for the control approach presented here. MBR combine classical biological wastewater treatment with subsequent membrane filtration. The membrane unit separates the biomass of the biological treatment from the water. MBR offer high effluent quality, reliable biomass separation and small space requirements. These properties make them an appealing alternative especially when effluent constraints are tight, when space is limited and when existing plants need to be upgraded. In general, however MBR operating costs are higher than those of conventional wastewater treatment plants (WWTP), which employ sedimentation basins for the biomass separation a large potential to increase the economic feasibility of MBR lies in the improvement of their operational policy. Until today only simple control strategies have been employed Advanced control approaches frequently used in the chemical process industry have not been applied to MBR due to the large uncertainty in the biological and the filtration processes, in the inflow prediction, and in the limited measurement information. While this is not different from the obstacles in regular WWTP operation, the increased
515
complexity of MBR requires efficient online control to exploit their full potential. Hence, this project focuses on the process control of MBR. It aims at bringing advanced approaches from many research areas as e.g. control and optimization together to provide a capable, flexible and generic control architecture which takes the characteristics and peculiarities of MBR and MBR operation into account. Due to the process complexity modelbased control approaches are proposed. Time and unit scale separation are performed to obtain sub problems of lower complexity for different disturbance dynamics and for both the biology and the membrane system. For each of them suitable models, problem formulations, and efficient solution algorithms need to be formulated. The coordination between the sub problems on different time scales and between the units must be considered.
to level out peaks in the inflow rate and concentrations. Mechanical units such as sieves and sand filters remove coarse particulate matter and fat. The subsequent biology is typically divided into two zones, the denitrification and nitrification which can each comprise one or several basins. Here the biological reactions take place, turning the contaminants into biomass, carbon dioxide and gaseous nitrogen. The nitrification basin is aerated to provide dissolved oxygen. Sludge can be withdrawn from the bottom of the basin. A recirculation stream transports sludge from the nitrification back to the denitrification. Finally, a membrane unit separates the inert as well as the biologically active particulate matter from the product water. The product water is withdrawn, while the particulate matter is retained in the system. In the configuration shown here the membrane unit requires an additional air stream, whose function is discussed later. In the following II. PROCESS DESCRIPTION OF sections, the main process are units storm water MEMBRANE BIOREACTOR tank, mechanical cleaning, biology, and membrane Wastewater treatment in day today life is a system are discussed. pressing need in view of decreasing surface water resources and falling groundwater levels. Increasing water consumption mandates the intensified reuse of water and has leaded to increasingly strict legislative limits on effluent concentrations. In consequence, wastewater treatment has become a large industry with high annual product volume and financial investments (Gray, 2004). Economical pressure calls for efficient process solutions. Membrane bioreactors (MBR) are one promising technology in this context (Wintgens et al., 2005). MBR combine two technologies to efficiently and reliably purify wastewater up to high quality standards: traditional biological treatment to remove carbon, nitrate, phosphorus compounds and subsequent membrane filtration to separate the biomass and other particulate matter from the purified water. Although each MBR has its unique properties, there are main design features which are common to most plants. Wastewater enters the Fig. 1 Process Diagram for MBR. plant and is temporarily stored in a storm water tank
516 with high process complexity, and Consider past, present, and predicted future process behaviour. The process dynamics are very stiff and recalling the cyclic behaviour of the filtration system there are considerable structural differences between the operation of the biology and of the membrane system. It is therefore expected to be highly impractical or even impossible to describe the entire system with one model so an alternative approach is to divide the MBR control problem into several sub problems, which can be approached with tailored methods[6]. The key idea of the latter is to separate the disturbance and process dynamics according to their relevant time scales and to assign them to different interrelated operational layers. IV. SCHEMATIC CONTROLLER FLOW DESCRIPTION FOR THE PROCESS PLANT
Finally, the MBR process as a whole is considered, highlighting its characteristics in comparison to conventional wastewater treatment plants (WWTP) and the couplings between the biological and the membrane system, the development of advanced model-based control approaches for MBR is motivated. III. MODEL-BASED CONTROL OF MBR Efficient control of membrane bioreactors (MBR) is a challenging task. The uncertainty in the process kinetics and mechanisms, the stiff process dynamics, the lack of meaningful and reliable online measurements, the highly dynamic and uncertain inflow and the hardly understood relationships between the biology and the filtration system pose significant difficulties. The objective of advanced control approaches for MBR is to realize a reliable and cost efficient purification of wastewater up to specified standards in spite of these challenges. State-of-the-art of MBR control is based on the experience in controlling conventional biological treatment plants. The MBR biology is controlled in the same fashion as regular biology, though partly at different set points, e. g. at higher biomass concentrations. Typical control schemes are PID type control of the dissolved oxygen or ammonia concentrations. The membrane system is operated according to the set points suggested by the manufacturer or by experienced operators. Fixed set points for the controlled variables are common, with some variation to meet the required net flux[6]. The main challenge is to deal on the one hand with the high uncertainty and stiff dynamics of the two complex systems and on the other hand with their interaction. Given this situation together with the high number of controlled and manipulated variables, constraints and objectives a model-based approach to the problem seems inevitable. Model-based control approaches offer the advantage that they Can accommodate process and input constraints, Can incorporate economic objectives in addition to set point control, Can deal
Fig. 2 Schematic Controller Flow Diagram of Process Plant On the left and right of Fig.2 the control system for the biology and the control system related to the membrane unit are depicted respectively. Various coordinators are suggested between the two systems. The vertical axis represents the time scales on which the control layers operate, starting with the slowest dynamics from above. The operational layers depicted in Fig.2 are planning/scheduling, dynamic real-time optimization (D-RTO), non-linear model predictive control (NMPC), base control, and state and parameter estimation.
517 been merged into a dynamic predictive scheduling layer. On this new layer the scheduling of operational strategies (objectives and constraints) is solved simultaneously with the D-RTO problem. In this project, a framework for the modelbased control of membrane bioreactors (MBR) is developed, which aims at the economical optimization of MBR operation[2]. It is the continuation of the fundamental contribution of Cruse (2006), which is extended and complemented in various aspects. Hence, controller development is driven by the necessity to structure uncertainty, to attenuate its harmful effects, and to exploit it wherever possible. Planning is understood as strategic decision making for the operation of one or several plants e. g. based on long-term predictions of market prizes or customer demand. Scheduling on the other hand is concerned with the fulfillment of fairly specific production requirements on a shorter time horizon (Shah, 1998). In both approaches, discrete decisions are made concerning e.g. investments, the employment of certain units or pipelines or the sequencing of production campaigns. In D-RTO, optimal set points or set point trajectories for the manipulated and the controlled variables of the associated process are computed. Obviously planning, scheduling, and set point optimization are interrelated, while the degree of interdependency is specific to each considered process. Uncertainty is a major challenge to all scheduling approaches. It can be shown that nominally optimal solutions yield suboptimal or even infeasible solutions when realized under uncertainty. Uncertainty is mostly related to the model structure, the model parameters, and disturbances. V.SIMULATION RESULTS AND DISCUSSION The Extended Kalman Filter is employed to provide initial state estimates at each LTV-MPC optimization. It is assumed that in each basin the concentrations of oxygen, ammonia, nitrate, alkalinity, solids, chemical oxygen demand (COD),
The base control and the estimation layers are connected to the controlled unit, which can be the real plant or a plant simulation layer [2]. On the planning/scheduling layer fundamental planning decisions about the operation of the plant are made (Shah, 1998). This layer determines the objectives as well as the path inequality constraints and equality (eq) and inequality () endpoint constraints of process operation . The objectives may e. g. include economical and ecological objectives, and the constraints may refer to effluent concentration limits or tank holdups. Based on the information from the planning/scheduling layer, the optimal trajectories of the inputs and outputs are computed on the DRTO layer by solving a non-linear, constrained, dynamic optimization problem. Accordingly, complex models with good predictive capabilities have to be employed. If the inputs were implemented as such, plant model mismatch and disturbances would inevitably lead to divergence of the optimal () and the real (y) output trajectories. Typically the computation of the DRTO problem is too demanding to be performed on the time scale of these disturbances. Hence the NMPC layer is required for adequately fast responses. In NMPC, an optimization problem is solved again, but now the objective is not an economical one anymore, but the minimization of the difference between the optimal and the real input and output trajectories. The model employed on the NMPC layer may be of less complexity, as the prediction horizon is smaller and the model only needs to be accurate in the subspace around the real and optimal trajectories. The NMPC layer provides corrected inputs u. If the process deviates too far from the optimal solution, the NMPC layer will not be able to realize the desired behaviour anymore, therefore periodic or intelligently triggered updates of the D-RTO trajectory are required. However, MBR plants possess unique features, which allow simplifying the concept at some points and requiring extensions at others. With respect to the biology, the planning/scheduling and the D-RTO layers have
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filtered COD, and biological oxygen demand (BOD) are measurable and that the measurements of the inflow rate and inflow concentrations are perfect. Gaseous nitrogen is neither measurable nor observable, but since it does not influence any reaction its estimate is not relevant for the process prediction [1]. A measurement noise of 2% is introduced, and no process noise is assumed. No constraints on the outputs, inputs, or states are formulated. It is constant at 520m3/d. In the same diagram the input trajectory as computed by the NMPC (LTV-MPC) layer for the undisturbed process is depicted. It stays close to the reference trajectory. The deviations are caused by the variations in the state estimates [1]. A measurement noise of 2% is introduced, and no process noise is assumed. No constraints on the outputs, inputs, or states are formulated. The three weighting matrices Q, R, and S was formulated. The weighting matrix R, which penalizes input deviations, is set to zero. The matrices Q and S are set to the identity matrix. The inputs u are scaled to values around 1[1]. They comprise the permeate flow rate ZP , the aeration kla, the recycle flow rate ZND, and the sludge withdrawal ZS, The reference trajectory of the permeate flow rate ZP is shown in figure. It is constant at 520m3/d. In the same diagram the input trajectory as computed by the NMPC (LTV-MPC) layer for the undisturbed process is depicted
Fig.3b Reference profiles of the DPS layer and LTV-MPC profiles for the permeate flow ZP for r the disturbed process. The Fig.3b shows the effect of the process disturbance on the performance variables in case no LTV-MPC control is applied. Both concentrations deviate significantly from their reference profiles, and especially the ammonia concentration exhibits a steep increase.
Fig.3a Reference profiles of the DPS layer and LTV-MPC profiles for the permeate flow ZP for the undisturbed process.
Fig.4 Reference profiles of the DPS layer and obtained profiles for the effluent concentrations of ammonia cN,SNH for undisturbed process
519 set points for unknown inflow conditions together by optimizing set point values. This set point value should match the bioreactor operational strategy that may provide a capable and flexible operation. This controller operation is expected to get more efficient filtration of sewage water which can be reused. REFERENCES 1. An integrated process of jet loop bioreactor and ultra-filtration membrane used for wastewater treatment in Shanghai, China 2. Naundordf E A, Subramanian D, Pabiger Nl. Biological treatment of wastewater in the compact reactor. Chem Eng Process, 1995, 19: 229-234. 3. Xiufen Li, Fangshu Gao, Zhaozhe Hua, et.a!. Treatment of synthetic wastewater by a novel MBR with granular sludge developed for controlling membrane fouling. Separation and Purification Technology, 2005 (46): 19-25 4. Xiang Zheng, Junxin Liu. Dyeing and printing wastewater treatment using a membrane bioreactor with a gravity drain. Desalination, 2006(190): 277-286 5. Guglielmi, G.: 2002, Membrane bioreactors for municipal wastewater treatment, PhD thesis, Università di Trento, Italy. 6. Gujer, W., Henze, M., Mino, T. and van Loosdrecht, M.: 1999, Activated sludge model no.3, Wat. Sci. Tech. 39(1), 183193. 7. Hamaker, H. C.: 1937, The London-Vander-Waals-Attraction between sperical particles,
Fig. 5 Reference profiles of the DPS layer and obtained profiles for the effluent concentrations of ammonia cN,SNH (top) for the process with no tracking control, The LTV-MPC trajectory of the permeate flow rate is shown on the right of Fig3b. During the first day the concentration profiles and the permeate flow rate match the reference profiles closely due to the absence of disturbances. When the disturbance appears after approximately 1 day, the permeate flow is gradually decreased. This increases the hydraulic residence time of the system and enables the biology to treat the increased amount of ammonia and nitrate. The other input variables are adapted as well (not shown). As a result, the profiles of the ammonia and nitrate concentrations are forced back to their reference profiles. The ammonia concentration profile exhibits a noticeable deviation from the reference profile when the disturbance occurs, but the deviation is small compared to the offset observed in the uncontrolled case (Fig.4 ). The tracking of the reference trajectories is nearly perfect when perfect knowledge of the states is assumed (not shown). The offset observed is hence rather related to the challenging state estimation task than the LTV-MPC controller VI. CONCLUSION This Non-Linear Model based Predictive Controller methodology to MBR in sewage water treatment brings an efficient controlling strategy to the entire plant by automatic rescheduling of their
520
ROBOTIC SURVEILLANCE FOR PATIENT CARE IN HOSPITALS

D.Sudarvizhi Assistant Professor Department Of Biomedical Instrumentation Engg Avinashilingam Deemed University For Women Coimbatore Aamani Janga Pre-final year Department Of Biomedical Instrumentation Engg Avinashilingam Deemed University For Women Coimbatore janga.aamani@gmail.com Aleena Mary Cherian Pre-final year Department Of Biomedical Instrumentation Engg Avinashilingam Deemed University For Women Coimbatore aleenakanianthra@rediffmail.com
sudarvizhi.durai@gmail.com
Actuation ABSTRACT: In a hospital setting, automation of patient care to some extent will go a long way in reducing work load on staff and in increased efficiency of performance. A robot can be especially used in the following areas like high risk areas like radiology department, drug delivery to patients in ICU and general wards and many such areas like this for the surveillance purpose. The manipulator and the programming determine the function of the robot. Purpose of these robots is not to replace nurses but to help them so that they can spend more time with patients Key words - surveillance , automation INTRODUCTION: ROBOTICS: Robotics is the science and technology of robots, their design, manufacture, and application. Robotics requires a working knowledge of electronics, mechanics and software, and is usually accompanied by a large working knowledge of many subjects. The structure of a robot is usually mostly mechanical and can be called a kinematic chain (its functionality being akin to the skeleton of the human body). The chain is formed of links (its bones), actuators (its muscles) and joints which can allow one or more degrees of freedom. Robots used as manipulators have an end effector mounted on the last link. This end effector can be anything from a welding device to a mechanical hand used to manipulate the environment. COMPONENTS OF ROBOTS: The actuators are the 'muscles' of a robot; the parts which convert stored energy into movement. By far the most popular actuators are electric motors, but there are many others, some of which are powered by electricity, while others use chemicals, or compressed air. Manipulation Robots which must work in the real world require some way to manipulate objects; pick up, modify, destroy or otherwise have an effect. Thus the 'hands' of a robot are often referred to as end effectors while the arm is referred to as a manipulator. Most robot arms have replacable effectors, each allowing them to perform some small range of tasks. Some have a fixed manipulator which cannot be replaced, while a few have one very general purpose manipulator, for example a humanoid hand Locomotion Rolling Robots Waking Robots Control The mechanical structure of a robot must be controlled to perform tasks. The control of a robot involves three distinct phases - perception, processing and action (robotic paradigms). Sensors give information about the environment or the robot itself (e.g. the position of its joints or its end effector). Using strategies from the field of control theory, this information is processed to calculate the appropriate signals to the actuators (motors) which move the
521 time to alert security staff who can then ask the relevant individual to verify his identity at the entrance of a hospital building In terms of surveillance, the moving robots equipped with a camera and microphone are an ideal opportunity to provide information for the security system of the hospital. Face recognition and person tracking systems will be used to improve the hospital security. GENERAL BLOCK DIAGRAM:
mechanical structure. The control of a robot involves path planning, pattern recognition, obstacle avoidance, etc. The robot's computer controls everything attached to the circuit. To move the robot, the computer switches on all the necessary motors and valves. Most robots are reprogrammable-To change the robot's behavior, you simply write a new program to its computer. Dynamics and kinematics The study of motion can be divided into kinematics and dynamics. Direct kinematics refers to the calculation of end effector position, orientation, velocity and acceleration when the corresponding joint values are known. PATIENT CARE: In a hospital setting, automation of patient care to some extent will go a long way in reducing work load on staff and in increased efficiency of performance. A robot can be especially used in the following areas: high risk areas like radiology department drug delivery to patients in ICU and general wards Transport of x ray films and other such items to prevent unnecessary exposure of working personnel Automated robots have been used in certain hospitals for patient care in psychiatric wards too, with good results.
PC
Transmit ter circuit
Receiver circuit
Robot actuation mechani sm
PC siderobot side PC SIDE BLOCK DIAGRAM:

Microcontroll er Encoder
RS 232
PC
Transmitter
CCD camera tuner card CCD camera receiver
SURVEILLANCE: With the increased traffic of electronic patient data travelling in and out of surgeries and hospitals, there has been a need for investment in robust and wellresourced network infrastructures. Enabling pro-active surveillance: In the integrated world an alarm could trigger a camera to begin recording if an unauthorized person has entered a restricted section of the car park for example. Cameras could track that same individual into the hospital. Suddenly proactive surveillance becomes a realistic possibility as there is sufficient DESCRIPTION: The PC side of the block diagram has a personal computer connected to a microcontroller through RS 232 serial interface. The PC and the microcontroller control the signals to be sent to the robot. Signals to be transmitted are encoded, and transmitted via a 433 MHz AM transmitter. The PC also receives the images transmitted by the CCD camera from the robot, through a receiver, which is connected to the PC by a tuner card.
522 8 Bit CPU optimized for control applications Extensive Boolean processing(Single-bitLogic) capabilities. On - Chip Flash Program Memory On - Chip Data RAM Bi-directional & Individual Addressable I/O Lines Multiple 16-Bit Timer/Counters Full Duplex UART MultipleSource /Vector /Priority InterruptStructure On - Chip Oscillator and Clock circuitry. On - Chip EEPROM SPI Serial Bus Interface Watch Dog Timer
ROBOT SIDE BLOCK DIAGRAM:

PC
side
receiver
decoder
Micro controle
Buffer
Camera motion
rackcontroller
Motor controller
Motor controller
Motor1 CCD camera transmitter
Motor 2
rack
Wheel
Wheel
TRANSCEIVER MODULE: Transmitter A transmitter is a device which generates high frequency power, which, by means of a suitable antenna, is radiated through space, or through conductors or through obstructive media, such as walls and glass. It may be modulated with information. This modulation of information may be received and demodulated in a receiver, where the combination of a transmitter and receiver is known as radio system. Receiver RF receiver at 433 MHz frequency is used at the robot side for reception of transmitted signals. It is responsible for demodulation, that is, separation of modulating signal from carrier signal. SOFTWARE DETAILS: MICROCONTROLLER PROGRAMMING: The microcontroller (Atmel 89S51) used in the robot and the PC circuits has been programmed using assembly level language. This language offers a varied range of addressing modes, bit and byte addressable instructions and is extermely easy to use and understand. User interface is programmed using visual basic software. Visual basic (VB) is a third generation event-driven programming language and associated development environment from microsoft. It enables
DESCRIPTION: The robot side consists of a 433 MHz AM receiver which receives the signals transmitted from the PC side. These are then decoded and passed on to the microcontroller. As per the signals received, the microcontroller can selectively activate the stepper motors actuating the wheels, the rack assembly or the CCD camera head. Thus, motion and action of the robot can be easily controlled from the PC station. CCD camera transmitter mounted on a stepper motor shaft captures images and transmits them to the CCD camera receiver at the PC circuit.
MICROCONTROLLER: Introduction to ATMEL Microcontroller The major Features of 8-bit Micro controller ATMEL 89S51:
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the rapid application development (RAD) of garphical user interface (GUI) application. FLOWCHART:
START
INITIALIZE PORT
DRIVE WHEEL SMs FORWARD
S
KEY IS PRESSE D? STOP KEY IS PRESS
Robot reciever circuit

FORWARD KEY IS PRESSED?
REVERSE KEY IS PRESSED
DRIVE WHEEL SMs REVERSE
STOP KEY IS PRESSED?
PC transmitter circuit S
524 CONCLUSION: Automation of hospital services has progressed today to a stage where entire units and wards are now being operated using remote control tchnology. From space sations on the moon to U. S. missions on Antarctica, robots have changed the face of modern medicine especially in fields like radiation therapy, high precision surgeries and medical imaging. Our robot aims to fulfil basic requirements of a hospital, reducing the work load on staff and thus directing human resources to where they are needed the most. Development of solar driven devices, nano technology and low cost components in the coming years are sure to make this robot a reality and necessity in every hospital. FUTURE SCOPE: The future scope of development in our robot can be summarised in the following points: Control using voice and image recognition Biometric sensors for security and confidential access Artificial intelligence incorporated into robots Superior actuation and manipulation mechanisms
Monitor Display
REFERENCES: CCD camera 1.Sukal,T.M;Dewal,J.P.A;Ellis,M.D,Robotic system for quantification of upper limb work area following stroke,IEEE Transactions on systems and cybernetics-Vol-III-Issue 12 2.Mokhtar,M;Timmis,J;Tyrrell,A.M;Ran Bi.Artificial lymph node architecture for homeostasis in collective robotic systems,IEEE Transactions on artificial robotic systems-Vol-IIIssue 4,Pg 404-408 3.J.Kovecses;J.C.Piedboeuf;C.Lange Dynamics modeling and simulation of constrained robotic systems.IEEETrransactions on robotics and automation-Vol -15-Issue 4
CCD camera receiver
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Application of Intelligent Systems in Model Order Reduction

S.Priya Mr.K.Ramesh2 1. PG Scholar in Embedded System Technologies 2. Asst.Professor in Electrical and Electronics Engineering Velalar College of Engineering and Technology Erode.
INTRODUCTION ABSTRACT: A Rule-based approach for formulating a second order

MIMO model for a given absolutely stable higher order MIMO system in transfer function matrix form is proposed. This paper presents a Rule-based approach for the formulation of a second order MIMO model for a given absolutely stable linear time invariant higher order MIMO system, either continuous or discrete. The Higher order system convert into second order MIMO Model. So we are using this Kernel. The kernel of our methodology is the proposed Rule-base for modifying the characteristics of a second order system. This is based on the GA for second order systems. The rules are applied one by one to alter the characteristics of the initially formulated second order approximant in an iterative manner to evolve a better second order model. The proposed methodology selects the second order model that closely matches the characteristics of the given higher order system. The cumulative error index computed with the integral square error of the second order approximant and the higher order system is used as the indicator for decision making. The algorithm requires the higher order MIMO system to be represented in the form of a transfer function matrix.
Model Order Reduction (MOR) has become an established technique to analyze and compress modeling information on linear circuits and systems. Reduction of high order systems to lower order models has been an important subject area in control engineering for many years. Reduction of high order systems to lower order models has been an important subject area in control engineering for many years. The mathematical procedure of system modeling often leads to detailed description of a process in the frequency domain lead to high order transfer functions to lower order systems for analysis and design purposes. Some of the reasons for using reduced-order models of high-order linear systems could be as follows: (i) (ii) (iii) (iv) to have a better understanding of the system, to reduce computational complexity, to reduce the hardware complexity, to make feasible controller design.
Bosley and Lees [1] and others have proposed a method of reduction based on the fitting of the time moments of the system and its reduced model, but these methods have a serious disadvantage that the reduced order model may be unstable even though the original high order system is stable. To overcome the stability problem, Hutton and Friedland [2], Appiah [3] and Chen et. al. [4] gave different methods, called stability based reduction methods which make use of some stability criterion. Other approaches in this direction include the methods such as Shamash [5] and Gutman et. al. [6]. These methods do not make use of any stability criterion but always lead to the stable reduced order models for stable systems. Some combined methods
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are also given for example Shamash [7], Chen et. al. [8] and Wan [9]. In these methods the denominator of the reduced order model is derived by some stability criterion method while the numerator of the reduced model is obtained by some other methods [6, 8, 10]. The optimization-based reduced-order modeling has already been suggested in the work [11-13] in which the numerator coefficients are computed by minimizing the integral square error (ISE) between the step responses of the original and the reduced system while the denominator polynomial is obtained by using existing orderreduction technique. The genetic algorithm (GA) is a popular optimization technique in the science and engineering nowadays. Genetic Algorithm (GA) technique appeared as a promising algorithm for handling the optimization problems. GA can be viewed as a general-purpose search method, an optimization method, or a learning mechanism, based loosely on Darwinian principles of biological evolution, reproduction and the survival of the fittest [14]. GA maintains a set of candidate solutions called population and repeatedly modifies them. At each step, the GA selects individuals from the current population to be parents and uses them to produce the children for the next generation. In general, the fittest individuals of any population tend to reproduce and survive to the next generation, thus improving successive generations. However, inferior individuals can, by chance, survive and also reproduce. GA is well suited to and has been extensively applied to solve complex design optimization problems because it can handle both discrete and continuous variables, non-linear objective and constrain functions without requiring gradient information [1519]. In this paper the methods for order reduction of large scale linear systems are presented. In this method, the optimization techniques are employed for the order reduction where both the numerator and denominator coefficients of ROM by minimizing an Integral Squared Error (ISE) criterion. The obtained results are compared with a recently published conventional method to show their superiority.
STATEMENT OF THE PROBLEM

Let the model (r order system and its reduced ) be given by the transfer functions:
Where
are scalar constants
The objective is to find a reduced order reduced model R(S) such that it retains the important properties of G(S) for the same type of inputs.
REDUCTION METHOD
Balanced model truncation via square root method returns a reduced order model GRED of G and a struck array red info containing the error bound of the reduced model and Hankel singular values of the original system. The error bound is computed based on Hankel singular values of G. For a stable system these values indicate the respective state energy of the system. Hence, reduced order can be directly determined by examining the system Hankel SV's,. With only one input argument G, the function will show a Hankel singular value plot of the original model and prompt for model order number to reduce. This method guarantees an error bound on the infinity norm of the additive error || G-GRED || for well-conditioned model reduced problems:
The input arguments of balancmr is G = LTI model to be reduced (without any other inputs will plot its Hankel singular values and prompt for reduced order) ORDER = (Optional) an integer for the desired order of the reduced model, or optionally a vector packed with desired orders for batch runs.
ALGORITHM
Given a state space (A, B, C, D) of a system and k, the desired reduced order, the following steps will produce a similarity transformation to truncate the original state space system to the order reduced model.
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1. Find the SVD of the controllability and observability grammians
chromosome representation, selection function, the genetic operators, initialization, termination and evaluation function. Brief descriptions about these issues are provided in the following sections. A. Chromosome representation Chromosome representation scheme determines how the problem is structured in the GA and also determines the genetic operators that are used. Each individual or chromosome is made up of a sequence of genes. Various types of representations of an individual or chromosome are: binary digits, floating point numbers, integers, real values, matrices, etc. Generally natural representations are more efficient and produce better solutions. Realcoded representation is more efficient in terms of CPU time and offers higher precision with more consistent results. B. Selection function To produce successive generations, selection of individuals plays a very significant role in a genetic algorithm. The selection function determines which of the individuals will survive and move on to the next generation. A probabilistic selection is performed based upon the individuals fitness such that the superior individuals have more chance of being selected. There are several schemes for the selection process: roulette wheel selection and its extensions, scaling techniques, tournament, normal geometric, elitist models and ranking methods. The selection approach assigns a probability of selection Pj to each individuals based on its fitness value. In the present study, normalized geometric selection function has been used. In normalized geometric ranking, the probability of selecting an individual Pi is defined as: In normalized geometric ranking, the probability of selecting an individual Pi is defined as = = where, q = probability of selecting the best individual r = rank of the individual (with best equals 1) P = population size C.Genetic operators The basic search mechanism of the GA is provided by the genetic operators. There are two basic types of operators: crossover and mutation.
2. Find the square root of the grammians (left/right eigenvectors) 1/2 1/2 3. Find the SVD of
4. Then the left and right transformation for the final order reduced model is
5. Finally = The general form of second order system transfer function is represented as
Here The adjustable variables are , , .
OVERVIEW OF GENETIC ALGORITHM

Genetic algorithm (GA) has been used to solve difficult engineering problems that are complex and difficult to solve by conventional optimization methods. GA maintains and manipulates a population of solutions and implements a survival of the fittest strategy in their search for better solutions. The fittest individuals of any population tend to reproduce and survive to the next generation thus improving successive generations. The inferior individuals can also survive and reproduce. Implementation of GA requires the determination of six fundamental issues:
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These operators are used to produce new solutions based on existing solutions in the population. Crossover takes two individuals to be parents and produces two new individuals while mutation alters one individual to produce a single new solution. The following genetic operators are usually employed: simple crossover, arithmetic crossover and heuristic crossover as crossover operator and uniform mutation, non-uniform mutation, multi-non-uniform mutation, boundary mutation as mutation operator. Arithmetic crossover and non-uniform mutation are employed in the present study as genetic operators. Crossover generates a random number r from a uniform distribution from 1 to m and creates two new individuals by using equations:
improvement in the best solution over a specified number of generations or target value for the objective function. Evaluation functions or objective functions of many forms can be used in a GA so that the function can map the population into a partially ordered set. The computational flowchart of the GA optimization process employed in the present study is given in Fig. 1.
Start
Specify the parameters for GA
Generate initial population
Arithmetic crossover produces two complimentary linear combinations of the parents, where r = U (0, 1):
Find the fitness of each individual in the current population
Yes
Non-uniform mutation randomly selects one variable j and sets it equal to a non-uniform random number. Gen=Gen+1 Gen.>Max. Gen.? Stop
= where, = r1, r2 = uniform random nos. between 0 to 1. G = current generation. Gmax = maximum no. of generations. b = shape parameter. D.Initialization, termination and evaluation function An initial population is needed to start the genetic algorithm procedure. The initial population can be randomly generated or can be taken from other methods. The GA moves from generation to generation until a stopping criterion is met. The stopping criterion could be maximum number of generations, population convergence criteria, lack of
No Apply GA Operators: selection, crossoverand mutation
Fig.1 Flowchart of genetic algorithm
NUMERICAL EXAMPLE
To demonstrate the accuracy and usefulness of the proposed method, one numerical example is taken from the literature and the second-order reduced model is obtained using the suggested algorithm. Let us consider the system described by the transfer function:
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The reduced order model employing square root balanced truncation method technique is obtained as follows:
REFERENCES:
1. M. J. Bossley and F. P. Lees, A survey of simple transfer function derivations from high order state variable models, Automatica, Vol. 8, pp. 765-775, 1978. 2. reducing order of linear time- invariant systems, IEEE Trans. Auto. Control, Vol. 20, pp 329-337, 1975. 3.R. K. Appiah, Linear model reduction using Hurwitz polynomial approximation, Int. J. Control, Vol. 28, no. 3, pp 477-488, 1978.
The step response for the higher order model and reduced order model is represented in Fig.2
Step Response 4
3.5
2.5 Amplitude
1.5 higher order model 1 reduced model
0.5
4.T. C. Chen, C. Y. Chang and K. W. Han, Reduction of transfer functions by the stability equation method, Journal of Franklin Institute, Vol. 308, pp 389-404, 1979.
10 12
6 Time (sec)
Fig.2.Step response for higher order model and reduced order model
5. Y. Shamash, Truncation method of reduction: a viable alternative, Electronics Letters, Vol. 17, pp 97-99, 1981. 6. P. O. Gutman, C. F. Mannerfelt and P. Molander, Contributions to the model reduction problem, IEEE Trans. Auto. Control, Vol. 27, pp 454-455, 1982. 7. Y. Shamash, Model reduction using the Routh stability criterion and the Pade approximation technique, Int. J. Control, Vol. 21, pp 475-484, 1975. 8. T. C. Chen, C. Y. Chang and K. W. Han, Model Reduction using the stability-equation method and the Pade approximation method, Journal of Franklin Institute, Vol. 309, pp 473-490, 1980. 9. Bai-Wu Wan, Linear model reduction using Mihailov criterion and Pade approximation technique, Int. J. Control, Vol. 33, pp 1073-1089, 1981. 10. V. Singh, D. Chandra and H. Kar, Improved Routh-Pade Approximants: A Computer-Aided Approach, IEEE Trans. Auto. Control, Vol. 49. No. 2, pp292-296, 2004. 11. S. Mukherjee and R. N. Mishra, Reduced order modelling of linear multivariable systems using an error minimization technique, Journal of the Franklin Institute, vol. 325, no. 2, pp.
COMPARISON METHODS
The performance comparison of the proposed algorithm for order reduction techniques is given in Table I. The comparison is made by computing the error index known as integral square error ISE in between the transient parts of the original and reduced order model, is calculated to measure the goodness/quality of the [i.e. the smaller the ISE, the closer is R(s) to G(s) , which is given by:
Where y(t) and
) are the unit step
responses of original and reduced order systems for a second- order reduced respectively.
CONCLUSION:
In this paper, the square root balanced model truncation method for reducing a high order large scale linear system into a lower order system have been proposed. Genetic algorithm method based square root balanced is employed for the order reduction where both the numerator and denominator coefficients of reduced order model are obtained by minimizing an Integral Squared Error (ISE) criterion.
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235245, 1988.
12. G. Parmar, R. Prasad, and S. Mukherjee, Order reduction of linear dynamic systems using stability equation method and GA, International Journal of Computer, Information, and Systems Science, and Engineering, vol. 1, no. 1, pp. 2632, 2007. 13. S. S. Lamba, R. Gorez, and B. Bandyopadhyay, New reduction technique by step error minimization for multivariable systems, International Journal of Systems Science, vol. 19, no. 6, pp. 9991009, 1988. 14. D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, AddisonWesley, 1989. 15. S.Panda and N.P.Padhy, Comparison of Particle Swarm Optimization and Genetic Algorithm for FACTS-based Controller Design, Applied Soft Computing. Vol. 8, Issue 4, pp. 1418-1427, 2008. 16. S.Panda and N.P.Padhy, Application of Genetic Algorithm for PSS and FACTS based Controller Design, International Journal of Computational Methods, Vol. 5, Issue 4, pp. 607-620, 2008. 17. S.Panda and R.N.Patel, Transient Stability Improvement by Optimally Located STATCOMs Employing Genetic Algorithm International Journal of Energy Technology and Policy, Vol. 5, No. 4, pp. 404-421, 2007. 18. S.Panda and R.N.Patel, Damping Power System Oscillations by Genetically Optimized PSS and TCSC Controller International Journal of Energy Technology and Policy, Inderscience, Vol. 5, No. 4, pp. 457- 474, 2007. 19. S.Panda and R.N.Patel, Optimal Location of Shunt FACTS Controllers for Transient Stability Improvement Employing Genetic Algorithm, Electric Power Components and Systems, Taylor and Francis, Vol. 35, No. 2, pp. 189-203, 2007.
531
AUTOMATION IN TEXTILE LOOMS USING DIGITAL SIGNAL PROCESSOR

S.Arunmozhi., 2nd Year M.E, Dr.Mahalingam College of Engineering And Technology,Pollachi. arunmozhis.me@gmail.com Ms.J.Amutha.,M.E.,(Ph.D)., Assistant professor, Dr.Mahalingam College of Engineering And Technology,Pollachi.
Abstract This paper gives a clear solution for the current existing problem in Textile Industries. Nowadays, Weaving industries in India prefer auto looms like Rapier Loom, Somet Loom, Saurer Loom to increase the production and to reduce the manual work. Printed and Embroidery fabrics have emerging trend in the market. Industries use a sheet with holes to print a design to the fabric. But this can be automated by our project which uses DSPIC33FJ256MC710. The image of the designs are scanned through image Processing and this can be stored in a 2GB memory card. An LCD is used to display the image of the fabric. In the parts where the designs are needed can be identified and monitored through the LCD. Now the program has been done Using Micro Basiks software describing the parts to print the design. The design can be printed simultaneously in all the parts wherever the design is needed without sheets. This reduces the manual work to print design. Up to 26 designs can be stored in the Memory card. This overcomes the problem of damage in printing while using sheet with holes. This application saves power and minimizes power failure problems. Keywords: Rapier loom Somet Loom, Saurer Loom DSP, weft I. INTRODUCTION Types of Looms: Back strap loom Warp weighted loom Tapestry Frame Loom Handloom Haute lisse and basse lisse looms Power looms Rapier Loom Somet Loom Saurer Loom Air-jet Loom Water-jet Loom
Of the above types, most of the industries prefer Rapier looms, Somet Looms and Saurer Looms because of its salient features and cost. Salient Features of looms: High quality weaving machine suitable for the production of high quality fashion fabrics of natural and synthetic yarns at low cost. Sturdy Machine Frame and Unique drive resulting minimum maintenance. The main parts run in antifriction bearing. Rigid well designed beat-up gives excellent fabric. PLC base control panel. Stable weft insertion. Versatile Fabric weaving upto 500gsm. Unique drive gives lowest maintenance.
In India, we have lot of textile industries which produces yarn and different varieties of fabric, and weaving industry produces the final product of fabrics. Most of the industries uses auto looms for manufacturing the fabric. These industries use traditional mechanisms for the production of fabrics .The produced fabrics need different types of designs that makes it suitable for the current trends. The designs that are printed need automation to increase production and manual work. The advancements in technology and increase in the demand for fabrics indicate that it has to be modernized with the recent trends.
II. PROBLEM FORMULATION
The main problem in textile industries is that they use a sheet with holes to print a design to the fabric. While using this technique there is lot of problems formed like All manual work
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Want to remove the sheet paper after printing Huge time This can be automated to reduce all the above mentioned problems III. THE SUMMARY OF MECHANISM
potential to reduce power consumption in electric motors and power supplies. The DSP processor is a 100 Pin chip which consists of some special features such as Industrial temperature range (-40C to +85C), High-Performance DSCPU (Digital Signal Central Processing Unit), Modified Harvard
1.
The function of the system
According to the requirement of textile industries, the main functions of the loom controller are as follows: Automatically printing the design Print the design in the fabric by the usage of memory card. To overcome the damage of the fabric during the power failure problems. 2. The whole structure of the mechanism
architecture, Low-power, high-speed Flash technology, fully static design and Low-power consumption. Product highlight: Ram size: 30 kb Flash size (bytes): 256 kb Number of I/O lines: 85 Speed: 40 MHz Supply voltage: 3 to 3.6 v It controls the entire loom operation and automates the design printing process. It also enables the transfer of designs to the fabrics using LCD monitor 2. Power supply unit The supply unit gives all the inputs that the driver circuit and the processor needs. The board mainly gives the supply of +3V for DSP core, +12V for Metal sensors, +5V for communicating IC and 240V ac as the input to the mechanism. The step down transformer is used to step down 240V ac into +13.5V and +24V for two sections. The former for bridge diode and the later for dc-dc converter. 3. Metal Sensor
This mechanism consists of DSP IC 33FJ256 MC710 (16 bit DSP controller with high processing speed and needs +3V supply), MAX232 (need +5V supply), Buffer ICs such as 74HC573, 74HC14 and METAL sensor (need +12V supply), LED(2*16),LCD and a 2 GB memory card. The loom produces pulse signal which is given as input to PIC 16F86A .The MAX 232 is used for communication between the controllers and transforms the signal to the controller. The controller is programmed using Micro Basiks software that enables it to do all the actions. IV. HARDWARE OF THE CONTROLLER The hardware part (shown in the figure 3) mainly consists of DSP core, Power supply unit, Metal sensor and driver circuit. The main purpose of the DSP core is to automate and control the loom operation. The function of driver circuit is to make required transformations of the input signal that helps to operate the DSP core. 1. Processor area (DSP) A digital signal controller (DSC) can be thought of as a hybrid of microcontrollers and digital signal processors (DSPs). Like microcontrollers, DSCs have fast interrupt responses, offer controloriented peripherals like PWMs and watchdog timers, and are usually programmed using the C programming language, although they can be programmed using the device's native assembly language. On the DSP side, they incorporate features found on most DSPs such as singlecycle multiply-accumulate (MAC) units, barrel shifters, and large accumulators. DSCs are used in a wide range of applications, but the majorities go into motor control, power conversion, and sensor processing applications. Currently DSCs are being marketed as green technologies for their
The metal sensor is connected to the fingers of the loom which senses the printing operation of fabric with that particular design and enables the controller to proceed with the next step automatically. The metal sensor needs +12V supply. 4. Driver circuit The driver circuit (used to drive the controller) along with its basic components consists of buffer IC such as 74HC573, 74HC14 for the signal transformation is used give the efficient control to the Loom. The potentiometer is used for adjusting the fluctuations in the LCD display. The tandulum is for reducing noise 10ns faster when compared to disc capacitor. To control the heat dissipation, heat sink is used +12V constant output is produced by the regulator IC7812 and that of +5V output is produced by LM317.
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Figure 4 DSP Based Textile Auto Loom Model
Figure3.Hardware part of DSP based Textile loom controller

IV. SOFTWARE OF THE CONTROLLER The software part of the controller is associated with DSPIC33FJ256MC710 and PIC16F86A 1. DSPIC33FJ256MC710 design The DSP processor is programmed with Micro Basiks software. Image processing is used to scan the designs that has to be printed in the fabric and that is feeded in the memory card. The designs that has to be printed at specific locations can be monitored using LCD and can be printed in the fabric simultaneously in all the places that needs the design. The micro controller codings helps to design DSPIC33FJ256MC710 module. The steps that has to be performed is designed efficiently which enables to do all the operations needed by the loom to automate the process. This DSP core controls the overall process. 2. PIC16F86A design
i) Edit ii) File select iii) Run iv) Reset Edit option is used to enter the desired colour, Number of designs that is needed in that colour, Cramping and fringes. After the file is selected, run the program using the given option. Every time the program can be reseted.File select is used to set the repeat count that has to be printed repeatedly in the fabric.
V. HARDWARE MODULE Using this hardware 26 designs, 99 steps, can be performed for a single fabric design shown in figure 4. VI. CONCLUSION & FUTURE SCOPE
This IC is programmed with Microprocessor Lab which helps in the transformation of signals.This can also be programmed with Micro Code Studio Plus. 3. Keypad Design Module
The keypad design module consists of four options which is from DSPIC33FJ256MC710
The looms can be automated reducing manual work and wastage of fabrics. DSP core controls the process. Implementation of this proved that production can be increased in a low cost loom which is mostly used in textile (weaving) industries. This has wide future all over the nation. For future development it working under a process to increase number of designs to high level By using this mechanism the production can be increased in ordinary auto looms than jet looms. This overcomes the problem of damage in printing while using sheet with holes. This application saves power and minimizes power failure problems.. It also has the advantage of low power consumption.
535
NANO GENERATORS- A GENERATOR OF GREENARY

S.Saravanakumar, spkssaravanan@gmail.com SNS College of Engineering ABSTRACT The magic of nanotechnology has spread all over the world and recently many nano robots has been created which is a sign of promising future. But providing electric source to these robots is problem because if we use a normal battery as source of electricity then the size of nano robot will increase and the advantage of nano technology will be lost. But this problem can we removed by the introduction of nano generators. The nano generators are very small in size it does not need petrol or diesel like other generators for its mechanical movement instead even a small finger movement of our body will be enough to produce a considerable amount of electricity required. This generators work on the principle of piezoelectric effect, this could play INTRODUCTION The one of the most vital application of nanotechnology is in the making of nano generators. The one of the important advantage of nano generators is that it is eco-friendly. In this presentation we will see about methodology through which this nano generators produces electricity Nanogenerators The diagram above shows a nano generator which is used to produce electricity when a mechanical energy is given to nano wires and which in turn produces electricity due to its special property of piezo-electric effect. This generator is called as nano generator because the components used in the construction of this generator are of size 10^-9m. There are many generators which produce electricity through various methods but probably nano generator is first of its kind which produces electricity by various muscular activity. Basically nanogenerators produce current by bending and then releasing a vital role in medical field for example when a nano sensor is implanted under the skin to keep a check on blood pressure then it needs certain amount of electricity for its function, here we can not use battery cause it is a toxic material instead we can use nano generator which will produce electricity due to flow of blood which gives it a mechanical force. Here the nano generator is made of zinc oxide which is not toxic material. As you see compared to other generator it is compact in size due to which we have three main advantages. The first is reduction in cost, second is need of less space and the last but not least it is eco friendly. G.Yadav yadaveee@gmail.com
zinc oxide nanowires -- which are both piezoelectric and semiconducting. The nano generators use the very small piezoelectric discharges created when zinc oxide nanowires are bent and then released. By building interconnected arrays containing millions of such wires, we can produce enough current to power nanoscale devices.
536 The nano generators apart from producing electricity is also used in the field of medical electronics to detect and cure certain cancer cells, So let us get down and bath in the complete knowledge of nano generators.
THE PIEZOELECTRIC EFFECT To understand the concept of nanogenerators in detail we must under go the study of piezo electric effect in detail. Which plays a very vital role in this concept .A piezoelectric substance is one that produces an electric charge when a mechanical stress is applied.
Production Of Piezo Electric Effect
In order to produce the piezoelectric effect, the polycrystal is heated under the application of a strong electric field. The heat allows the molecules to move more freely and the electric field forces all of the dipoles in the crystal to line up and face in nearly the same direction (Figure 2).
The figure shown above is the example of piezo electric effect, as you see when a mechanical stress is given then electricity is produced and the voltmeter is connected with it in order to measure the current produced in it. This is also vice versa i.e when a mechanical stress is given then it leads in the production of electricity.
The piezoelectric crystal bends in different ways at different frequencies. This bending is called the vibration mode. The crystal can be made into various shapes to achieve different vibration modes. To realize small, cost effective, and high performance products, several modes have been developed to operate over several frequency ranges.
Proceedings of PEID-2011 INFO Institute of Engineering, NANO WIRES- ZINC Coimbatore OXIDE
Flexing the nanowires through vibration (like sound waves) produces a current in the wire. When the wire bends far enough to touch a discharge electrode, the current is transferred. So, the more the nanowire gets bent or vibrated, the more current it produces. The nano wire used here in nano generator is zinc oxide
537 It works on low frequency and is a flexible material. Real advantage of this technology is that the nanowires can be grown easily on a wide variety of surfaces, and the nanogenerators will operate in the air or in liquids once properly packaged. Property of zinc oxide In its natural state, ZnO is unintentionally doped to n-type by naturally occurring oxygen vacancies, however, and as with all wide-band gap semiconductors, it is hard to dope it away from its natural state. You need to introduce ptype impurities, But effective dopants tend to take up residence at a deep level in the material and become hard to activate. Making of zinc oxide To make the p-type ZnO nanowires, we doped ZnO crystals with phosphorus pentoxide using a chemical-vapor-deposition technique, simpler and less expensive than the MOCVD technique used to fabricate GaN LEDs. Adding phosphorus atoms to the ZnO crystal structure leads to p-type semiconducting materials through the formation of a defect complex that increases the number of holes relative to the number of free electrons.
A scanning-electron micrograph reveals uniform diameters and smooth surfaces in p-type ZnO nanowire arrays. ]
Reason for Choosing Zinc Oxide The ZnO nanowires are piezoelectric - they generate an electric current when subjected to mechanical stress.
electrode coated with 200 nm thick Pt film. Here the Pt coating enhances the conductivity of electrode, and also creates a Schottky contact at the interface with ZnO. The ZnO nanowires are grown on either GaN substrates or sapphire substrates that are covered by a thin layer of ZnO film, which served as a common electrode for directly connecting the nanowires with an external circuit. The density of the nanowires is 10/m^2, and the height and diameter are 1.0 m and 40 nm, respectively. The array of aligned ZnO nanowires are covered by a zigzag, (001) orientated Si With the ultrasonic wave being turned on and off regularly, The current jump is about 0.15 nA. The resistance of the entire
538 At present case, the power output of single nanowire is far below than that of the wire driven by an AFM tip, due to the difference of the bended amplitude. However, there is a group army of ZnO nanowires now, the power output simultaneously harvested from the group nanowires is much intense.
nanogenerator was very stable during these two periods (R = 3.560 0.005 k). This stability indicates that the current jump could not be due to the variation in resistance, as caused by the vibration of the nanowires, suggesting that the obtained current signal was created by the nanogenerator.
BASIC OPERATION Well let us now see the basic operation of nano polymer substrate. A layer of zinc oxide is generator i.e. to say how does really it works. grown on top of substrate to collect the current. With help of schematic diagram shown below it The researchers also fabricate silicon will be a lot easier for us now to know its zig-zag electrodes, which contain thousands operation in depth. of nanometer-scale tips made conductive by a platinum coating. The electrode is then lowered on top of the nanowire array, leaving just enough space so that a significant number of the nanowires are free to flex within the gaps created by the tips. Moved by mechanical energy such as waves or vibration, the nanowires periodically contact the tips, transferring their electrical charges. By capturing the tiny amounts of current produced by hundreds of nanowires kept in motion, the generators produce a direct current output in the nano-Ampere range. Now basically to produce electricity we need generator and generator needs an mechanical source to produce the electricity in the same manner even the nano generator needs an mechanical source and we can give mechanical source such as ultrasonic waves, mechanical vibration or blood flow.Based on arrays of vertically-aligned zinc oxide nanowires that move inside a novel zig-zag plate electrode, the nanogenerators could provide a new way to power nanoscale devices without batteries or other external power sources. The nanogenerators take advantage of the unique coupled piezoelectric and semiconducting properties of zinc oxide nanostructures, which produce small electrical charges when they are flexed. Fabrication begins with growing an array of verticallyaligned nanowires approximately a half-micron apart on gallium arsenide, sapphire or a flexible
PROTOTYPE OF NANO GENERATOR
The diagram above is a prototype of dc nano generator Our estimation is that our nanogenerator could produce as much as 4 watts per cubic centimeter based on a calculation for a single nanowire. That would be enough to power a broad range of nanometer-scale defense, environmental and biomedical applications, including biosensors implanted in the body, environmental monitors and even nanoscale robots. Actually the nanogenerator could harvest power from just one nanowire at a
539 grown to approximately the same length about one micron there is some variation. Wires that are too short cannot touch the electrode to produce current, while wires that are too long cannot flex to produce electrical charge. Providing power for nanometerscale devices has long been a challenge. Batteries and other traditional sources are too large, and tend to negate the size advantages of nanodevices. And since batteries contain toxic materials such as lithium and cadmium, they cannot be implanted into the body as part of biomedical applications. Because zinc oxide is non-toxic and compatible with the body, the new nanogenerators could be integrated into implantable biomedical devices to wirelessly measure blood flow and blood pressure within the body and they could also find more ordinary applications
time by dragging the tip of an atomic force microscope (AFM) over it. Made of platinumcoated silicon, the tip served as a Schottky barrier, helping accumulate and preserve the electrical charge as the nanowire flexed and ensuring that the current flowed in one direction.With its multiple conducting tips similar to those of an AFM, the new zig-zag electrode serves as a Schottky barrier to hundreds or thousands of wires simultaneously, harvesting energy from the nanowire arrays. Producing the top electrode as a single assembly sets the stage for scaling up this technology,We can now see the steps involved in moving forward to a device that can power real nanometer-scale applications. Before that happens, additional development will be needed to optimize current production. For instance, though nanowires in the arrays can be .
Nanogenerators- Electricity Produced By Hamster In the existing world where the shortage of nonrenewable source is creating a lot of trouble to man kind, there like a super hero hamster comes to our rescue. Recently it has been found that with application of certain jackets even the hamster can produce sizable electricity by its movement. The nanogenerator power is produced by the piezoelectric effect, a phenomenon in which certain materials such as zinc oxide wires produce electrical charges when they are bent and then relaxed. The wires are between 100 and 800 nanometers in diameter, and between 100 and 500 microns in length. o make their generators, some research team encapsulated single zinc oxide wires in a flexible polymer substrate, the wires anchored at each end with an electrical contact, and with a Shottky Barrier at one end to control current flow. Role of Hamster They then attached one of these single-wire generators to the joint area of an index finger, or combined four of the singlewire devices on a yellow jacket worn by the hamster. The running and scratching of the hamster and the tapping of the finger flexed the substrate in which the nanowires were encapsulated, producing tiny amounts of alternating electrical current. Integrating four
The hamster uses nano-generators to produce the suitable electricity needed for us. The basic principle behind the nano generators is given below. Principle
Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore nanogenerators on the hamsters jacket generated up to 0.5 nanoamps; less current was produced by the single generator on the finger.
Some estimates that powering a handheld device such as a Bluetooth headset would require at least thousands of these single-wire generators, which could be built up in three-dimensional modules. Beyond the finger-tapping and hamster-running, Wang believe his modules could be implanted into the body to harvest energy from such sources as muscle movements or pulsating blood vessels. In the body, they could be used to power nanodevices to measure blood pressure or other vital signs. OUT PUT OF NANO GENERATOR
540 glucose sensor implanted under the skin of the arm. Such a sensor would transmit blood sugar readings to a wrist watch. It is very economical since the nano wires used in this are very cheap. A array of nano wire can be used to run a medical implant. This does not causes any pollution to environment, since like other generators it does not uses the petrol, diesel or kerosene instead it uses mechanical movement of our body as a input to generate electricity. The implanting of nanogenerators with in our body can detect and help us to remove various cancer cells.
CONCLUSION Now after bathing in the knowledge of nano generators you might have understood the vital role which has to be played by nano generators in the near future to avoid the shortage of electricity. In order to meet the demand of electricity and mainly to get eco friendly we have only one and the best choice as nano generators. After studying this presentation you might have also noted that not only this is used to produce electricity but can also play a vital role in medical field. So I would like this wonderful presentation with a note that Nano generators are biggest not in size but in its applications
The above diagram shows the output of a nano generator. In the lab, some researchers aimed an ultrasound source at their nanogenerator to measure current output over slightly more than an hour. Though there is some fluctuation in output, the current flow was continuous as long as the ultrasonic generator was operating. To rule out other sources of the current measured, the researchers substituted carbon nanotubes which are not piezoelectric for the zinc oxide nanowires, and used a top electrode that was flat. In both cases, the resulting devices did not produce current. APPLICATIONS It can be used in defense system because this can generate the enough electricity which is needed by army officers in the battle field. One of the applications of the "nanogenerators" is providing power for a
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An Embedded System for Underwater Imaging Application

Deepak N, M.Tech (VLSI Design), SRM University, Chennai, Dr.Dhilsha Rajappan, Scientist-NIOT, Chennai, M Valarmathi, Asst.Proff, SRM University, Chennai. .
Abstract: This paper deals with the underwater imaging for the buried object detection with real time image generation by using the FPGA and implementing the beamforming techniques. The algorithm and the reconfigurable architecture for implementing the matched filter and beamformer for a sonar system has been carried out. Beamforming is the name given to a wide variety of array processing algorithms that, by some means, focus the array signal capturing abilities in a particular direction. A stackable Field programmable Gate Array (FPGA) based hardware system is presented with the implementation details of Filter based Delay-Sum Beamforming algorithm. This project is been carried out in the National Institute of Ocean technology (NIOT), Chennai. Key Words: Sonar, Beamforming, FPGA Signal Processing. Introduction Acoustic Imaging of buried objects under the sea bed has attracted research interests over the past several years. This includes detection and classification of buried pipelines, ordinances materials and other
objects under the sea bed. Several studies have been reported in an underwater imaging system. Among these Beamforming is considered to be, one of the computational intensive part in an underwater imaging system. So the selection of signal processing hardware significantly depends on the algorithm used for the beamforming. In its simplest form, sonar beamforming can be defined as the process of combining the outputs from a number of omnidirectional transducer elements, arranged in an array of arbitrary geometry, so as to enhance signals from some defined spatial location while suppressing those from other sources. There are different types of beamforming methods are available, which include SpaceTime Filtering, Filter and Sum beamforming, frequency Domain Beamforming, Discrete-Time Beamforming, Averaging in Time and Space and Delay and Sum Beamforming. Here we are focusing on the Delay and Sum beamforming. The beamforming operation is accomplished through a series of operations that involve the weighting, delay and summation of the signals received by the spatial elements. The summed output that contains information about a particular direction is called a beam.
542 and a Xilinx Vertex 5 LX110 FPGA backplane for data steaming and basic signal processing respectively. The SBC is powered by a power PC processor running at 800MHz, capable of running RTOS.
This output is then sent to a signal processor and/or a display for frequency and temporal discrimination. In time-delay beamforming, beams are formed by averaging weighted and delayed versions of the receiver signals. Each receiver has a known location and samples the incoming signals spatially. To steer the beams (i.e. to choose beamforming directions), each receivers output has to be delayed appropriately relative to the other receivers. The time delays compensate for the differential travel time between sensors for a signal from the desired beam direction. Beamformers are used both in passive and active sonar systems. In passive sonar, the beamformer acts on the received waveforms. Active sonar also utilizes a conventional beamformer which acts on the waveforms that are reflected from the targets. Hardware The frequency range for the proposed system is from 2kHz to 24 kHz powered by a specially designed transmitter. For improved performance in terms of penetration and spatial resolution, a wide band signal is chosen. The transmitted signal is a chirp signal whose pulse length is 1ms. The back scattered acoustic signal is received using 4x4 planar hydrophone array. Each hydrophone element has an in-built pre-amplifiers for improved sensitivity. The receiving sensitivity of each hydrophone is around -160dBrel V/Pa in the frequency interest. The received signal is pre amplified, filtered and sampled at a rate of 100 kHz from all the channels is streamed to the signal processing hardware over Ethernet cable. The data acquisition system constitutes a single board computer (SBC)
Fig 1: Data Acquisition and Transmission Hardware
The data acquisition system has a DAC as well. The LX110 FPGA is used for generation of chirp signal and is fed to the DAC. The DAC output is fed to the power amplifier and in-turn to the transducer. Here the Beamforming techniques are implemented on the FPGA in order to develop the image. The FPGA device chosen for the implementation is Xilinx Vertex 5 LX330, which is a high density device suitable for DSP applications. It has got 2M ASIC with 51k Vertex-5 Slices, 192 DSP48E Slices which can run at 550MHz (Each DSP48E slice has a 25x18 multiplier, an adder and a accumulator) and dedicated for DSP calculations, dual port Ethernet, DDR2 of 256MB, USB-2 daughter card, NAND flash memory of 128MB and a CPLD. Beamforming When is in the board-side to the array, the received signals are in phase and added up coherently but when the source is not in the board-side, there is a phase difference
543 After applying the phase delay, the frequency domain data is converted back to time domain by taking inverse of FFT (IFFT). Simulation Result The simulation of the 64 point FFT and the CORDIC implementation has been done by using ModelSim 6.3g_p1 version and its been synthesized by using Xilinx.
between the received signals and they do not add coherently, which caused drop in the summer output. Traditionally in SONAR applications, electronic beamforming is achieved by introducing the delay network between the individual hydrophones and weighing each hydrophone output appropriately to get a coherent output. In recent days due to the development in the signal processing and hardware, much robust and high performance beamforming can be applied. Here Delay-Sum technique is implemented in the frequency domain by using Fast Fourier Transform (FFT) and Coordinated Rotation Digital Computer (CORDIC) phase rotator.
Waveform 1: 64 point FFT by using Radix 4.
Fig 2: Frequency Architecture
Domain
Beamforming
In order to apply beamforming in the frequency domain, the phase shift has to be applied to the signals after taking their frequency transform, which is Fourier Transform in this case. FFT is used to get the frequency domain signal. There are various techniques by which the phase delay could be introduced. For FPGA implementation CORDIC based phase rotator is considered to be the best solution.
Waveform 2: CORDIC Implementation.
The further process of summing up and taking its inverse FFT had to proceed and verified with the existing one. During the data receiving process in the data acquisition hardware, a FIFO with
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synchronized pointer comparison, has to be maintained in order to retrieve the data from the ADC channel and later after generating the chirp signal, the data has to be carried out for further processing. The block diagram of FIFO with synchronized pointer comparison is as shown below.
Waveform 3: The FIFO Module
Fig 3: FIFO partitioning with synchronized pointer comparison
FIFO to pass data from one clock domain to another clock domain requires multiasynchronous clock design techniques. The method that is used to design, synthesize and analyze a safe FIFO between different clock domains is by using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. By using the grey code, the time taken for the data processing is less and also the low power is achieved by reducing the power to calculate the difference in each cycle. This is one such type of reducing the power by software coding, which is essential in bigger circuits were the power is an essential factor. The power consumption using the grey codes is shown after synthesizing in the Xilinx.
Figure 4: Power Analysis of FIFO module
Conclusion Design techniques and algorithms to be incorporated in the first version of the underwater imaging system for the buried object detection are discussed. A reconfigurable architecture for implementing the time domain beamformer SONAR system is presented. Future work is under process. By using FPGA more vital parameters like the number of receiving channels and the sampling rare can be increase can be increased. Moreover it can be modified for using it in Autonomous Underwater Vehicles (AUV).
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Reference [1] S.G Schock, A Tellier, J.Wulf and E.Ericken, Burried Object Scanning Sonar, IEEE J. Oceanic Eng, Vol 26, No.4, Oct 2001. [2] S.G Schock, J.Wulf and E.Ericken, Synthetic Aperture processing of Buried Object Scanning Sonar Data , IEEE J. Oceanic Eng, Vol 23, Oct 2005. [3] Dion C.M Horvat , John s.Bird and Maine M, True Time delay Band Pass Beamforming, IEEE J. of Ocean Engg, Vol 19, No.2, April 1992. [4] Peng Chen, Xiang Tian, Frequency domain Sonar Processing on FPGA, ICSP2008 Proceedings. [5] Janssen, R. J. 1987. Sonar Beamforming and Signal Processing. Electronic Progress, Vol. 28, No. 1, Raytheon Co. [6] D Chirp of a bat, Computing in Science & Engineering, vol. 8, pp. 7278, Mar.-Apr. 2006. [7] K. W. Lo, Adaptive array processing for wide-band active sonars, IEEE J. Oceanic Eng., vol. 29, pp. 837846, July 2004. [8] http://www.xilinx.com/support/documentati on/data_sheets/ds100.pdf
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MULTI PURPOSE IDENTIFICATION CARD USING EMBEDDED SYSTEM

A.Jagadeesan1, P.Boorani2, V.Sowmiya3 , K.Karthiga4
Department of Electronics and Instrumentation Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode 638401. e-mail: mails4jagan@gmail.com1,booranip@gmail.com2,sowmiyavelusamy@gmail.com3
1-4
Abstract: The multipurpose identification card has been developed for the convenience of the user. Presently there are many types of cards available such as punch cards, magnetic cards, optical cards, etc., but the user is highly inconvenienced, as they are in need to handle a large number of cards at a time to obtain the diverse information and they have to change over the cards frequently. These cards are also affected by magnetic field and are highly prone to mechanical damages, so we have designed a card which contains information from a variety of cards. Since the data is transferred using RFID system, the card can be detected from a certain distance. Here the security is highly enhanced by locking the data in various options like credit account, voter ID, etc by using separate passwords for each option. KeyWords: RFID, Multipurpose ID card,
Microcontroller. The Microcontroller processes the required data and display the output to the LCD.
3. Block diagram:
Power supply
RFID reader
MAX 232
PIC
LCD
Electromagnetic waves
Keypad
1. Introduction:
The various personal information cards which are in practice are having some disadvantages like They cannot store much information. They cannot be read from a distance. They lose their data if placed under magnetic field or even on scratching. There is no security to protect card data whereas in our card this is achieved with the provision of individual passwords. Fig.1.Proposed system architecture
3.1. MAX232:
Due to these disadvantages, the users are highly inconvenient since they have to change over cards frequently. The card which we have designed contains information from all kinds of personal cards, hence the user is highly convenient to handle this card and it also has a safety provision by locking the data in different options like credit card, voter ID using separate passwords since RFID is used, the card can be detected from a long distance.
2. Overview:
The RFID system which includes a reader and tag is connected with MAX232 which acts as an interface between the RFID and the PIC. Fig.2.Pin diagram of MAX232
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MAX232 converts from RS232 level to TTL levels and vice versa. It uses a +5v power source. This chip has two sets of line drives for transferring and receiving of data. The TXD of MAX232 is connected to the RXD of the microcontroller. And the RXD of the chip is connected to the TXD of PIC. 3.2. PIC Microcontroller: PIC16F877A is the most widely used PIC microcontroller since it is easily programmable. It is a high-performance RISC CPU. The operating voltage of this chip is 4-5.5volts and the operating speed is 20 MHz, 200ns instruction cycle. The industrial temperature range is 40 to +85 degrees.It has 15 interrupt sources and 35 single word instructions The PIC16F877A features 256 bytes of EEPROM data memory, self programming, 2 Comparators, 8 channels of 10-bit Analog-to-Digital (A/D) converter, 2 capture/compare/PWM functions, the synchronous serial port can be configured as either 3-wire Serial Peripheral Interface or the 2-wire Inter-Integrated Circuit LCD display.
3.3. RFID system:

RFID stands for Radio Frequency Identification. It is an automatic method to identify people, animals or object by means of radio waves. A basic RFID system consists of three components: An antenna or coil A transceiver (with decoder) A transponder (RF tag) electronically programmed with unique information
Fig.4.RFID System The antenna emits radio signals to activate the tag and to read and write data to it. The reader emits radio waves in ranges of anywhere from one inch to 100 feet or more, depending upon its power output and the radio frequency used. When an RFID tag passes through the electromagnetic zone, it detects reader's activation signal. The reader decodes the data encoded in the tag's integrated circuit (silicon chip) and the data is passed to the host computer for processing.
Fig.3.Pin diagram of PIC16F877A
The purpose of an RFID system is to enable data to be transmitted by a portable device, called a tag, which is read by an RFID reader and processed according to the needs of a particular application. The data transmitted by the tag may provide identification or location information, or specifics about the product tagged, such as price, color, date of purchase, etc. A typical RFID tag consists of a microchip attached to a radio antenna mounted on a substrate. The tag receives a radio signal from reader and in response to it send a unique ID code throe the radio signal to reader. It includes a 64-bit and 96-bit unique identifier. The chip can store as much as 2 kilobytes of data.To retrieve the data stored on an RFID tag, you need a reader. A typical reader is a device that has one or more antennas that emit radio waves and receive signals back from the tag. The reader then passes the information in digital form to a computer
3.2.1. Peripheral features:

The chip contains 33 I/O pins with 5 I/O ports. There are three timers-Timer0 (8-bit timer/counter with 8-bit prescaler), Timer1 (16-bit timer/counter with prescaler), Timer2 (8-bit timer/counter with 8-bit period register, prescaler and postscaler).They have a Synchronous serial port with two modes and also has USART/SCI with 9-bit address detection along with Parallel slave port.
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system. RFID quickly gained attention because of its ability to track moving objects so RFID technology has been used by thousands of companies for a decade or more.
images.
3.5. Keypad:
The keypad consists of an array of micro switches. Keypad is a set of buttons arranged in a block which is usually bear digits and other symbols but not a complete set of alphabetical letters. If it mostly contains numbers and so it can also be called as numeric keypad. The numeric keypad feature digits 0 to 9.The arrangement of the number of similar the keyboards of calculators. Here 8_pin keypad and it is connected with the microcontroller in PORTD. Especially here numeric keypad is used. Keypad is used to enter the codes. When the code is entered, it will be displayed on LCD.
3.4. LCD display:

LCD display is a very handy tool for showing information, debugging, etc. LCDs require fewer connections than LED displays. Uses less power. LCD is equipped with a controller, which internally does all the functions. Display data RAM (DDRAM), character generator ROM and RAM (CGROM and CGRAM), liquid crystal display driver are also provided. Usually LCD display format ranges from 8 to 80 characters. LCD modules have 14 or 16 (provided on UP3 board) pin connections. There are two models of character generator: A00 (used in LCD provided with UP3 board) and A02. Both have the standard ASCII character set, but the rest differs.
4. Implementation & Result:

The RFID reader is activated using the power supply and sends the electromagnetic waves from its antenna to the tag. The antenna in the tag receives the signal from the reader so that the data encoded in the tags integrated circuit is decoded and sends the signal to the reader. The PIC cannot recognize the signal from the reader so MAX232 is implemented to interface the reader and PIC. The PIC gets the required option like credit account, voter ID, license etc through the keypad and process the required data from the database that is programmed
Fig.5. Microcontroller interface with LCD This is a 16x2 character Liquid Crystal Display. Here 16x2 stands for two 16 character long lines.Each pixel in this has its own dedicated transistor, allowing each column line to access one pixel. When a row line is activated, all of the column lines are connected to a row of pixels and the correct voltage is driven onto all of the column lines. The row line is then deactivated and the next row line is activated. All of the row lines are activated in sequence during a refresh operation. Active-matrix addressed displays look "brighter" and "sharper" than passive-matrix addressed displays of the same size, and generally have quicker response times, producing much better
Fig.6. Proposed system hardware model in it. After the process is completed the user can view his personal information through the LCD. The important point to be noted is that all these process can take place only if the user gives the right password of the option.
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Security, July 2006. [6] R Tessier, D. Jasinski, A. Maheshwari, A. Natarajan, Weifeng Xu, and Wayne Burleson. An energy-aware active smart card, IEEE Transactions on VLSI Systems, 13(10):1190-1199, October 2005. [7] C.-P. Schnorr, Efficient Identification and Signatures for Smart Cards, Proc. Ninth Ann. Int'l Cryptology Conf. (CRYPTO '89), pp.239-252, 1989.
Fig.7. Password Authentication mode
4.1. Advantages:
It is very convenient for the user to handle a single card instead of having many numbers of cards. The information is protected by giving individual passwords for each card.
5. Conclusion & Future scope:

The proposed model of multi purpose card is a key technology for authorized access to network, vending machines, identification card, and licenses. Let technology work with us and for us, so that we can work with technology as well. The security system can be further developed by including multi biometric data like recognition of face, iris, etc. The purchase of goods, payment of bills and other bank transactions can be performed easily using this card.
6. References:
[1] Michael Todd,Hardware emulation of a secure passive RFID sensor system, Masters thesis, University of Massachusetts Amherst, September 2010. [2] Boris Danev, Thomas S. Heydt-Benjamin,and Srdjan Capkun,Physical-layer Identification of RFID Devices,18th USENIX Security Symposium, Montreal, Canada, August 2009. [3] M.Burmester,B. Medeiros and R. Motta, Robust Anonymous RFID Authentication with Constant Key Lookup, Proc. ACM Symp. Information, Computer and Comm. Security (ASIACCS), 2008. [4] A. Juels, RFID security and privacy: A research survey, IEEE Journal on Selected Areas in Communications, 24(2):381--394, February 2006. [5] Kevin Fu, Building RFID applications with security and privacy, In Workshop on RFID
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SMART PURCHASE IN SUPERMARKETS USING RFID SYSTEM

A.Jagadeesan1, G.Vikashini2, T.S.Yuvashree3, K.Selvi4, S.Sathyapriya5 1-5 Department of Electronics and Instrumentation Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode 638401. e-mail: mails4jagan@gmail.com1,vikashini17@gmail.com2
Abstract Our work mainly deals with the concern of simplifying the billing process in the supermarkets, by using the RFID for each product. When these products are collected in the trolley, automatically the total amount of purchase of all the products will be updated to the system, through wireless communication. This will simplify the billing process and hence the long queue will be eliminated KeywordsInstant billing system, transceiver, File management, RFID I.INTRODUCTION Shopping seems to be a good entertainment. But the huge queue in the supermarkets to scan the products frustrates the customers. Barcode scanning is a time consuming process engaging the customers to stick to the billing section for a long time. Hence there is a need to switch to a Radio Frequency Identification (RFID) system for smart purchase and instant billing. Our Application blends Radio Frequency Identification (RFID) and wireless technologies to provide 'on the spot billing in supermarkets. Each product is given a specific RF- Tag. Unlike barcodes, it uniquely identifies the product. In addition, they do not require physical scanning. The RF-Tags are constantly transmitting their presence to the RF Reader positioned on the shopping trolley. When a product is dropped into the trolley, its name and cost are displayed instantly on the LCD fixed to the trolley. At the check-out, the smart shopping trolley system transmits the list of items and total cost to the cashier using wireless technology. This promotes quick shopping and immediate pay without any queuing process. It reduces labor efforts and increases efficiency by minimizing errors. II.EXISTING METHOD Generally in supermarkets, Barcode scanning is a time consuming process engaging the customers to stick to the billing section for a long time. Hence, there is a need to switch to a Radio Frequency Identification (RFID) system for smart purchase and instant billing. RF modem for III. BLOCK DIAGRAM
IV. EXPLANATION Each product has its unique tag. When the product is dropped into the trolley its specific code is scanned by the RF reader. The data is sent to the microcontroller through UART. From the microcontroller the code is sent to the PC through Transceiver section. Transceiver section has RF modem with unipolar antennas. In the PC, database is maintained by file management system using C language. The product corresponding to the code and its cost stored in the files are transferred to the Transceiver section . The corresponding data is sent to the microcontroller. LCD is interfaced with the microcontroller to display the product name and cost. Sometimes people may find difficult to identify where the amount is printed in the pack. Here another advantage is that they can easily identify the product cost by dropping in the smart trolley. Similarly the total cost manipulated by the PC will also be sent to the LCD as well as the Printer. Hence the bill can be got instantly after completion of purchase. Shopping itself a good entertainment. Everything can be got in a less price except satisfaction. People are frustrated while standing in the queues for a long time to get the bills. So we
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A. Active tags Active tags contain both a radio transceiver and battery to power the transceiver. Because there is an onboard radio on the tag, active tags have substantially more range (~300 feet) than passive or active/passive tags. Active tags are also considerably more expensive than passive tags and, as with any battery-powered product; the batteries must be replaced periodically. B. Passive tags Passive tags can be either battery or non-battery operated, as determined by the intended application. Passive tags reflect the RF signal transmitted to them from a reader or transceiver and add information by modulating the reflected signal. A passive tag does not use a battery to boost the energy of the reflected signal. A passive tag may use a battery to maintain memory in the tag or power the electronics that enable the tag to modulate the reflected signal. IX.PIC The PIC16F877 Microcontroller is used in the project. The PIC Microcontroller is a Microchip product. This microcontroller has a built memory, CPU, Peripheral devices. The PIC microcontroller is divided into three ranges, based on the instruction set. They are, Low Range PIC - 12 bits Mid Range PIC - 14 bits High Range PIC - 16 bits A. Peripheral features Operating frequency: DC-20 MHz clock input. DC-200 ns instruction cycle. Wide operating voltage range (2.0V 5.5V). 14-bit wide instructions, 8-bit wide data path. 13-bit program counter, 8 level stack (13-bit). Up to 368 byte of data memory (RAM). Timer0: 8-bit timer/counter with 8-bit prescaler. Timer1: 16-bit timer/counter with prescalar can be incremented Timer2: 8-bit timer/counter with 8-bit period register, prescalar and postscalar. Synchronous serial port (SSP) with SPI (master mode) and 12C (master/slave). Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection. Parallel slave port (PSP) 8-bit wide, with external RD, WR and CS controls (40/44 pin only). B. Analog features
have developed a smart purchasing system for quick billing and to improve operational excellence in modern supermarkets. V.FLOW DIAGRAM
VI. RFID SYSTEM RFID (Radio Frequency Identification) is a means of storing and retrieving data through electromagnetic transmission to an RF compatible integrated circuit, and is now being seen as a radical means of enhancing data handling processes. VII. SYSTEM COMPONENTS RFID systems have several basic components or technical characteristics that define them. These are: A reader, including an antenna The device that is used to read and/or write data to RFID tags. A tag A device that transmits to a reader the data. The communication between them. RFID uses a defined radio frequency and protocol to transmit and receive data from tags. VIII. TYPES OF RFID TAGS RFID tags can be segregated into two major classifications by their power source:
10 bit up to 8-channel analog to digital converter (A/D). Brown out Reset (BOR).
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operating speed and lower access time. The ST16C550 on board status registers provides the error conditions, type and status of the transfer operation being performed. Included are complete MODEM control capability and a processor interrupt system that may be software tailored to the users requirements. The ST16C550 provides internal loop back capability for on board diagnostic testing. The ST16C550 is available in 40 pin PDIP, 44 pin PLCC, and 48 pin TQFP packages. It is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. B. Features Pin to pin functionally compatible to the industry standard 16c550 24 MHz clock operation at 5v 16 MHz clock operation at 3.3v 16 byte transmit FIFO 16 byte receive FIFO with Error flags Full duplex operation Transmit and receive control Four selectable receive FIFO interrupt trigger levels Standard modem interface Compatible with st16C450 C.Pin diagram of uart
Analog Comparator module with: Two analog comparators. Programmable On chip voltage reference (Vref) module. Programmable input multiplexing from device inputs and internal reference. C. Functional description PIC 16F877A is a 40-pin controller. There are pins corresponding to five I/O ports, namely, PORT A, PORT B, PORT C, PORT D and PORT E. Analog inputs to AD converter are AN0 to AN7; and are the alternate functions of PORT A and PORT E. Two pins are for oscillator connections, namely, OSC1 and OSC2. Supply and reference ground pins VDD and VSS, respectively, are in duplicate. Further, functions interrupt associated with the parallel slave port and serial communications are the alternate functions of PORT C and PORT D. RB0/INT is the external pin. X.UART UART (UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER) is microchip with programming that controls a computers interface to its attached serial device. Specifically, it provides the computer with RS232c data terminal. It can take to and exchange data with modems & other serial device. As part of this interface, the UART also Converts the bytes it receives from the computer along parallel circuits into a single serial bit stream for outbound transmission On inbound transmission, converts the serial bit stream into the bytes that the computer handles Adds a parity bit (if its been selected on outbound transmissions and checks the parity of incoming bytes (if selected ) & discards the parity bit Adds start & stop delineators on outbound & strips them from inbound transmissions handles its from the keyboard & mouse ( which are serial device with special ports ) may handle other kinds of interrupt &device management that require co-ordinate the computers speed & operate with device speed. A.ST16C550 The ST16C550 (550) is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. It operates at 3.3 and 5V power supplies. A programmable baud rate generator can select transmit and receive clock rates from 50 bps to 1.5 Mbps. The ST16C550 is an improved version of the NS16C550 UART with higher
Pin diagram of UART
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XI.APPLICATION Immediate pay without any queuing process. Reduces labor efforts. Increases efficiency by minimizing errors. Real time updating of supermarkets inventory. Growing the customers devotedness towards the supermarkets X.FUTURE SCOPE Theft identification. Product identification by database maintenance. Monitoring of offers and discounts in the touch screen based display fitted to the trolley. Displaying information such as expiring date of the products, ingredients, number of calories etc., XII.CONCLUSION Still seeking ways to cut the queues, our smart purchase concept pilots a scheme whereby customers walk out immediately paying the bill. Our future scope is to implement product identification and stock management along with the display of several other product information in a touch screen monitor. XIII.REFERENCE A. Literature reference [1] Rajkamal, Embedded systems, Architecture, Programming, programming & design, Tata Mc. Graw Hill publishing company limited, New Delhi, Edition 2003. [2] Jonathon W. Valvano, Embedded Micro computer system, Real Time Interfacing, Brooks / Cole Thomson Learning, first reprint 2001, by Thomson Asia Private Limited, Singapore. B. Website reference [1] www.pic.com (for information on PIC 16F877A) [2] www.discoverrfid.com (searching for information related to our project) [3] www.ieee.com (searching for information related to our project) [4] www.embeddedindia.com (information on embedded systems and its latest developments)
ProceedingsofPEID2011 INFOInstituteofEngineering
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AUTOMATION OF BOILER IN DIESEL POWER PLANT USING SCADA

Dr.K.GEETHA, MEGHA MURALI, NIMITHA M, REMYAMOL, SIDHIN K.S, TITTO THOMAS
Department of Electrical & Electronics Engineering NSS College of Engineering, Palakkad, Kerala
storage tank associated with pumps, viscosity controllers etc. All there systems are essential for the working of the plant. The power generated at 11KV is stepped up to 110KV, while is interconnected to 110KV bus of 220KV substation at Nallalam
INTRODUCTION Diesel Power Project is suitable for a state like Kerala, which will continue to have shortage of power both in peak demand and energy availability. Hydel power projects need a very long construction period. So it cannot meet the urgent power demand.The KDPP is one of the largest and major power plants in Kerala which supplies power to Malabar area. It consists of 8 diesel generating units each with capacity of 16MW and total power output of 128MW. This paper focus on PLC based power plant automation mainly in generation, controlling and transmission region. It includes starting and stopping process of engines, pressure and temperature control, and synchronization of machines, field controlling, cooling system, alarming system and entire relay operation. Virtual relay schemer only PLC is used as hardware. It works on software logic with one supervisory support. All other static and numerical relays in relay in KDPP can be replaced by the virtual relay with little alterations. PLANT OVERVIEW The Kozhikode Diesel Power Project (KDPP) is a 128MW power generating station under KSEB the plant was commissioned in 1999 and situated near to 220KV substation at Nallalam, Kozhikode. This is one of the major power plants in Kerala and is almost at the centre of Malabar areas. KDPP can meet low voltage problem experienced in this areas especially during peak hours. The prime mover is stroke diesel engines manufactured by WARTSILLA, FINLAND. There are 8 diesel generators sets each of 16MW. The engine has 18 cylinders i.e. 9 on either side. And each cylinder is of diameter 46UM. Engines run on diesel cycle. As the diesel engines are very big, they require complex auxiliary systems like cooling water systems, fuel systems lube oil system, starting air units etc. For cooling water processing, there is
SCADA in Boiler Control SCADA stands for supervisory control and data acquisition. It generally refers to an industrial control system. A computer system monitors and controls the process. The process can be industrial, infrastructure or facility based as described below. Industrial processes include those of manufacturing, production, power generation, fabrication, and refining, and may run in continuous, batch, repetitive, or discrete modes. By this paper it is proposed to build a small industrial plant and a SCADA system. Various types of sensors such as pressure, temperature, gas leakage etc are incorporated in the system. The system will acquire the data such as pressure, temperature, over and under voltage etc and send this data to a PC. If the temperature falls below a certain limit SCADA will turn on the heaters. If a gas leakage is identified it will make an alarm.
MANUALLY CONTROLLED PARAMETERS 1.Soot blowing 2. Total dissolved solvents (TDS) 3. Damper valve adjustment 4.Control of circulation pump,feed water pump,condensate pump and hydrocel pumpBLOCK DIAGRAM REMOTE TERMINAL UNIT DETAILS DAMPER
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The damper is controlled by a stepper motor. The position of valve is controlled by the rotations of stepper. The gas flow ratio is normally kept as 50:50. It can be varied in accordance with the temperature of the exhaust gas. A temperature sensor is employed for this purpose. MAX6675 The MAX6675 performs cold-junction compensation and digitizes the signal from a type-K thermocouple. The data is output in a 12-bit resolution, SPI compatible, read-only format. This converter resolves temperatures to 0.25C, allows readings as high as +1024C, and exhibits thermocouple accuracy of 8LSBs for temperatures ranging from 0C to +700C. The MAX6675 is available in a small, 8-pin SO package.
ZIGBEE GSM LCDDIS PLAY BUZZE R
MC
TEMPS ENSOR HEATER
THERMOCOUPLE
GASLEA KAGESE
SUPERVISORY SYSTEM
PCWITH
APPLICATI ONS/W
BUFFE
ZIGBE E
A thermocouple is a junction between two different metals that produces a voltage related to a temperature difference. Thermocouples are a widely used type of temperature sensor for measurement and control and can also be used to convert heat into electric power. They are inexpensive and interchangeable, are supplied fitted with standard connectors, and can measure a wide range of temperatures. The main limitation is accuracy. System errors of less than one degree Celsius can be difficult to achieve. Any junction of dissimilar metals will produce an electric potential related to temperature. Thermocouples for practical measurement of temperature are junctions of specific alloys which have a predictable and repeatable relationship between temperature and voltage. Different alloys are used for different temperature ranges. Properties such as resistance to corrosion may also be important when choosing a type of thermocouple. Where the
CELL
measurement point is far from the measuring instrument, the intermediate connection can be made by extension wires which are less costly than the materials used to make the sensor. Thermocouples are usually standardized against a reference temperature of 0 degrees Celsius; practical instruments use electronic methods of cold-junction compensation to adjust for varying temperature at the instrument terminals. Electronic instruments can also compensate for the varying characteristics of the thermocouple, and so improve the precision and accuracy of measurements. Thermocouples are widely used in science and industry; applications include temperature measurement for kilns, gas turbine exhaust, diesel engines, and other industrial processes. Voltagetemperature relationship For typical metals used in thermocouples, the output voltage increases almost linearly with the temperature difference (T) over a bounded range of temperatures. For precise measurements or measurements outside of the linear temperature range, non-linearity must be corrected.
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voltage based on thermocouple type and cold junction temperature. SOOT BLOWER A Soot blower is a system for removing the soot that is deposited on the furnace tubes of a boiler during combustion. Various types of soot blowers such as Wall Blowers, Long Retractable Blowers and Air Heater Blowers are used for the cleaning. Steam is normally used as a medium for blowing away the soot. Problems caused by soot Reduced efficiency Soot deposited on the heating surfaces of a boiler acts as a heat insulator. The result is that less heat is transferred to the water to raise steam and more heat is wasted up the chimney. This leads to higher fuel consumption and/or poor steaming. Soot fires A soot fire can be damaging to a boiler because it can cause localized hotspots to occur in the tubes. These hotspots may reach temperatures that weaken the materials of the tubes. Soot blowers reduce the risk of soot fires and their resulting damage. Operation A soot blower may be operated manually or by a remotely controlled motor. The soot, which is removed from the heating surfaces, will be blown out with the flue gases. If the boiler is equipped with a dust collector, it will trap the soot. Otherwise, the soot will be ejected into the outside air through the chimney stack. Here a DC motor is used as a soot blower. The motor is controlled by a microcontroller. It is turned on for 10 minutes in every 2 hours. CIRCULATION PUMP The Circulation pump is used to supply water to the boiler tube from steam drum.
The coefficients an are given for n from 0 to between 5 and 13 depending upon the metals. In some cases better accuracy is obtained with additional non-polynomial terms. Thermocouples measure the temperature difference between two points, not absolute temperature. To measure a single temperature one of the junctionsnormally the cold junctionis maintained at a known reference temperature, and the other junction is at the temperature to be sensed. Having a junction of known temperature, while useful for laboratory calibration, is not convenient for most measurement and control applications. Instead, they incorporate an artificial cold junction using a thermally sensitive device such as a thermistor or diode to measure the temperature of the input connections at the instrument, with special care being taken to minimize any temperature gradient between terminals. Hence, the voltage from a known cold junction can be simulated, and the appropriate correction applied. This is known as cold junction compensation. Some integrated circuits such as the LT1025 are designed to output a compensated
STEAM DRUM
The steam drum consists of water level sensor, temperature sensor and pressure sensor. The water level sensor senses the water level and gives the data to the microcontroller. The controller is programmed to keep the water level at least to 50% of the maximum level. In order to keep this a motor is used to pump water from the tank as required. The pressure sensor is also used to get the pressure level of the steam drum. BLOCK DIAGRAM
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The original Visual Basic .NET was released alongside Visual C# and ASP.NET in 2002. Significant changes broke backward compatibility with older versions and caused a rift within the developer community. CONCLUSION The boiler operation in KDPP was studied and analysed the various opeartions carried out in a boiler and various parameters related to these operations and their control.Certain parameters were controlled manually .This paper suggested automatic control of these parameters using microcontroller and various components as described in the above sections.The parameters were taken in a reduced scale. Automatic control suggested in this paper improve the efficiency enabling time management and also reducing the labour work.
CIRCUIT DIAGRAM
SOFTWARE DESCRIPTION APPLICATION SOFTWARE Visual Basic .NET (VB.NET) is an objectoriented computer programming language that can be viewed as an evolution of Microsoft's Visual Basic (VB) which is generally implemented on the Microsoft .NET Framework. Microsoft currently supplies Visual Basic free of charge. Visual Basic .NET (VB 7)
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Energy Efficient Management in Home Networks Using Network Protocol Agent

S.Hariprasad2 and Mr N.Kumaresan M.E.,Lecturer,Dept. of ECE
Anna University of Technology, Coimbatore, India. hariec07@gmail.com
Abstract To provide digital home services without their suspension or any users waiting, HG(Home Gateway) is to be always in operating state because these home services can be started at any time, by any device and from any network (external or internal home network). Home network devices including HG are required to be ready to operate at any time in digital home environment. In this project, a novel power control scheme is proposed to reduce effectively the power consumed by a HG. The proposed HG is composed of several function blocks which are controlled with separated power. In the proposed HG, all function blocks can be powered down except for NPA (Network Protocol Agent) to maintain network connectivity and to monitor any service interrupt from any interior and exterior environments. With the proposed scheme, the power consumption can be reduced excessively by HG characterized with Always-On. The proposed work is implementation of Distributed Network Protocol used with TCP/IP protocol for efficient reduction of power consumption. Keywords- Home Gateway, Network Protocol Agent, Power consumption. TCP/IP,
an HG with FTTH network as an access network interface. Here an implementation of FTTH based HG is proposed, especially EPON (Ethernet Passive Optical Network) based HG.With the FTTH access network interface, the proposed HG can provide service bandwidth of 100Mbps to 1Gbps to each subscriber. The network bandwidth is enough to provide various home network services for each one. The novel home gateways architecture is proposed to provide various services efficiently and show its implementation. The use of VLAN (Virtual Local Area Network) scheme to isolate two network domains, WAN of public network and LAN of private home network, within single L2 Ethernet switch and the direct packet forwarding scheme without L3 processing for some specific packet are key idea for the HG supporting various services proposed here. An Experimental Study of Throughput for UDP and VOIP Garg [6] presented on the throughput of IEEE 802.11b wireless networks for UDP and VoIP traffic[]. Our experiments show that the maximum data throughput of a single station sending out UDP traffic is 6.1 Mbps. The maximum number of VoIP calls in a single cell of an IEEE 802.11b network is six if the ITU G711a-Law codec is used with 10 milliseconds of audio data per RTP packet. Specifically, for the above codec settings, each VoIP connection reduces the bandwidth available for data traffic by 900 Kbps. In the last few years, wireless networks based on the IEEE 802.11b standard have gained popularity and have been widely deployed in enterprises mostly to provide wireless data access from Laptops, PDAs, etc. to the wired infrastructure of the enterprise. They have also been deployed in public hot-spots such as airports, hotels, conference facilities etc., mainly for internetwork connectivity. The maximal data rate 802.11b currently supports is 11Mbps. Convergence Between Public Switching and The Internet To leverage their installed base in the PSTN/ISDN the optimal strategy for lSPs is the integration of their point of presence into the central office: packetizing and grooming of IP traffic in the local office relieves load on the PSTN/ISDN [8] trunk network, resolves existing bottlenecks due to internet traffic upstream of the CO, and creates new
I. INTRODUCTION A. Home Gateway Home Network has been more and more popularized, which is comprised of HG, home server and many various home devices. HG is a device that connects multiple home network devices to an access network, WAN (Wide Area Network). Home gateway, also called as residential gateway is defined as an intelligent network interface device located at the consumer premises. It provides the means for the residential user to access the Internet services delivered to home and also to access the different services offered by the various smart devices located within home. Essentially the home gateway device provides the necessary connectivity features to enable the consumer to exploit the advantages of a networked home. II. RELATED WORK An Implementation of FTTH Based Home Gateway Supporting Various Services Wanki et.al [7] Home Gateway (HG), or called residential gateway (RG), is a device that connects an access network, WAN(Wide Area Network), to a home network(private network, generally). FTTH (Fiber ToThe Home) based HG is
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A. Energy Efficient Home Gateway The proposed HG uses sleep and wake-up mechanism and includes NPA being activated during the sleeping state. This is composed of, Flash Memory System Processor DDR SDRAM ECE(Service Function) Network Protocol Agent Power Module Ethernet Switch
opportunities for revenue-generating features for both telephony and Internet subscribers. This article intends to show that current telecommunication network elements can be upgraded with innovate cutting-edge technology to build a solid basis for a seamless multimedia network of tomorrow, thereby enabling telecom operators and service providers tremendous investment in existing network infrastructure to be fully utilized. An integrated Internet services platform is presented which turns the CO switch into an optimized link between the PSTN/ISDN and the Internet. This is a prerequisite for the creation of new revenuegenerating features such as supplementary PSTN/ISDN services for Internet calls, voice over IP, IP-activated dialing, and value-added Internet services (on-screen call-waiting indication, near-real-time bill viewing, etc.). As the demand for high-bandwidth subscriber access increases, existing line concentrators can be upgraded with wideband line cards. High-bandwidth IP traffic may be groomed in the concentrator and multiplexed directly on the high-speed (ATM, Ethernet) backbone network. The great benefit of an integrated approach is that the evolution from lower to higher bandwidth is smooth and as the market requires, thus guaranteeing the balance between necessary investment and revenue. This integrated approach is illustrated in this article by means of a concrete example using a state-of-the-art CO switch. IPTV Service Assurance Kerpez et al [9] discussed the IPTV service assurance aspects specific to IPTV services and video quality. Classic network monitoring generally ensures that each network element, network segment, and subnetwork is functioning reliably, and may also encompass routing and reachability across different network domains. IPTV service assurance can encompass much more, including subscriber management and authorization, capacity management, perceived video picture quality, and error correction and concealment; accomplished through integrated test and monitoring for rapid resolution of customer complaints. This is all needed to ensure that the customer has an overall video quality of experience (QoE) at least as enjoyable as current TV delivery methods. The deployment of broadband access to the mass market represents a paradigm shift in public networking. The evolution from dialup modem to integrated services digital network (ISDN) to lower-speed digital subscriber line (DSL) was somewhat gradual. But the more recent deployment of higher-speed DSLs, cable modems, and optical-based access. Users of broadband cannot imagine going back to lower speeds.
Figure 1 Home Gateway Flash Memory Flash memory is non-volatile, no power is needed to maintain the information stored in the chip. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. These characteristics explain the popularity of flash memory in portable devices. System Processor The System Service Processor (often abbreviated as SSP) is a SPARC-based computer that is used to control the Sun Microsystems Enterprise 10000 platform. The term SSP is often used to describe both the computer hardware and the software that are necessary to accomplish task. DDR SDRAM Double data rate synchronous dynamic random access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phaselocked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring
III. REDUCING POWER CONSUMPTION USING HOME GATEWAY
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access servers, switches, bridges, hubs, IP telephones, IP video cameras, computer hosts, and printers. An agent is a network-management software module that resides on a managed device. An agent has local knowledge of management information and translates that information to or from an SNMP specific form. A network management system (NMS) executes applications that monitor and control managed devices. NMS's provide the bulk of the processing and memory resources required for network management. One or more NMSs may exist on any managed network. Power Module A power electronic module provides the physical containment for several power components, usually Power semiconductor devices. This package provides an easy way to cool the devices and to connect them to the outer circuit. Classical example of structures available as power modules are: switch (MOSFET, IGBT), with anti parallel Diode; half bridge (inverter leg, with two switches and their corresponding diodes) three-phases inverter (six switches and the
data on both the rising and falling edges of the clock signal) to lower the clock frequency. Ece (Service Function) Each service has a control handler, the Handler function that is invoked by the control dispatcher when the service process receives a control request from a service control program. A service calls the Register Service Ctrl Handler or Register Service Ctrl Handler Ex function to register its service control handler function. When the service control handler is invoked, the service must call the Set Service Status function to report its status to the SCM only if handling the control code causes the service status to change. If handling the control code does not cause the service status to change, it is not necessary to call Set Service Status. Simple Network Management Protocol (SNMP) Simple Network Management Protocol (SNMP) is an "Internet-standard protocol for managing devices on IP networks. Devices that typically support SNMP include routers, switches, Servers, workstations, printers, modem tracks, and more. It is used mostly in network management systems to monitor network-attached devices for conditions that warrant administrative attention. SNMP is a component of the Internet Protocol Suite as defined by the Internet Engineering Task Force (IETF). It consists of a set of standards for network management, including an application layer protocol, a database schema, and a set of data objects. SNMP exposes management data in the form of variables on the managed systems, which describe the system configuration. These variables can then be queried by managing applications.
corresponding diodes). Ethernet Switch A switch is something that is used to turn on or off various electronic devices. However, in computer networking, a switch is used to connect multiple computers with each other. Since it is an external device it becomes part of the hardware peripherals used in the operation of a computer system. This connection is done within an existing Local Area network (LAN) only and is identical to an Ethernet hub in terms of appearance except with more intelligence. These switches not only receive data packets, but also have the ability to inspect them before passing them on to the next computer. That is, they can figure out the source, the contents of the data, and identify the destination as well. Because of this uniqueness; it sends the data to the relevant connected system only, thereby using less bandwidth at high performance rates. TCP/IP PROTOCOL Transmission Control Protocol (TCP), which uses a set of rules to exchange messages with other Internet points at the information packet level.TCP/IP is a hierarchical protocol made up of interactive modules,each of which which provides a specific fuctionality,but they are not necessarily interdependent.TCP/Ip protocol suite contain relatively independent protocols that can be mixed and matched depending on the needs of the system.
Figure 2. Management Konsole An SNMP-managed network components: Managed device consists of three key
Agent software which runs on managed devices Network management system (NMS) software which runs on the manager
A managed device is a network node that implements an SNMP interface that allows unidirectional (read-only) or bidirectional access to node-specific information. Managed devices exchange node-specific information with the NMSs. Sometimes called network elements, the managed devices can be any type of device, including, but not limited to, routers,
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Ethernet switch via packet buffer only and vice versa without processing of internal NPA function. Home Gateways Operation: State Transition The HGs operation shown in the figure has a circular state transition, which consists of two operating states, PowerOn state and Standby state. In the Active Power-On state, the Power Management scheme determines when the proposed HG goes into sleep state. On the other hand, NPA does as a main component to preserve all network sessions on behalf of the proposed HG system in the Active Standby state.
Figure 3. TCP/IP Protocol Multifunction Home Gateway To provide digital home services without their suspension or any users waiting, multifunction HG (Home Gateway) is to be always in operating state. Home devices including HG are required to be ready to operate at any time in digital home environment.In this work, power control scheme id used to reduce effectively the power consumed by a HG.The power consumption can be reduced excessively by HG characterized with Always-On.
Figure 5 Operation Flow of The Power Management Method Cold Booting state is normal booting procedure including the initialization of the Agent DB. The initialization of Agent DB is required to configure the NPA hardware. After completing cold booting procedure, the proposed HG goes into the circular transition state machine which is made of the Active Power-On state and the Active Standby state. The Active Power-On state is a normal operation mode with fullpower.The proposed HG analyzes network information and updates Agent DB in the Active Power-On state. The Agent DB is used to generate any acknowledge packets by NPA hardware in the Active Standby state. The Active Standby state is standby state with low power. In this state, main components become power-off state and only NPA and self freshened DRAM are operating to preserve working context & network sessions. As shown in Fig 4.6 , there are two Transition States which located between the Active Power-On state and the Active. IMPLEMENTATION OF HOME GATEWAY Here a novel energy-efficient home gateway system based on the proposed energy-aware scheme is implemented. The implemented home gateway hardware consist of processor function module, power manager function module, VoIP service function module, visitor check function module, Ethernet network interface and network protocol agent(NPA). In normal state, the processor function module does most operations such as network traffic processing and management of function modules for home gateway function. But, the processor function and the service functions of visitor check and VoIP service function are not working if the data traffic for any specific service is not on the network interface.
Figure 4. Always on Home Gateway Network Protocol Agent (NPA) Figure 3.11 shows NPAs internal architecture. To reduce the power consumption during sleeping state, the NPA functions on behalf of the other devices, especially main processor, in the HG. During the sleeping state, the NPA processes control packets to maintain a session or to request a simple response in several network protocol such as ARP(address resolution protocol), ICMP(Internet control message protocol) ping, TCP(transport control protocol) SYNCH, IGMP, DHCP(dynamic host configuration protocol) and packet discarding. For this function, the NPA has Agent Information Base being managed by the system software. If any Service Processor detects any user service packet or service event from service function block, the NPA activates system processor for system wake-up from sleep state. In normal state of working, all packets go directly from system processor to
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It does not ether even though there is any control packet to maintain some network session. At that time, the NPA with low power consumption replaces the processor function for maintaining the network session.
Implemented hardware board for the proposed energy efficient home The processor function then goes to sleep mode until the NPA makes it wake-up. On detecting the effective data packet or an event for any home network service, the NPA awakes the sleeping processor function module. If any service is not required from user, the specific service related function is not working under the power manager functions control. The proposed home gateway provides the energy-efficient function using these novel capabilities. IV. PERFORMANCE EVALUATION A. Simulation Model and Parameters Keil uVision4 is used for the simulation. The project demo is CMSIS (Cortex Microcontroller Software Interface Standard) compliant. Tera Term or HyperTerminal window is needed to display the options to enter low power modes. The C language is used for implementation. It has written as a background language. Here two systems has taken for power consumption. Using home gate way the power consumption can be effectively performed on both systems. Distributed Network Protocol can be used with TCP/IP protocol for efficient reduction of power consumption. The Mechanism is more flexible and reliable.In time Activation of Power Saving Functions like DRAM Power Down Low power consumption can be used for both user and non user traffic. Interruption from interior and exterior environments can be avoided power saving functions available to application.
Figure 4.1 Initiating movement on two systems
Figure shows that the initial movement of the two systems.In this state both systems are in idle mode.
Figure 4.2 System 2 in sleep mode
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Figure shows that both systems are in sleep mode. So power consumption can be totally reduced. V. CONCLUSION In this project we have designed a novel power control scheme to minimize effectively the power consumed by a HG. To provide digital home services without their suspension or any users waiting, HG(Home Gateway) is to be always in operating state. Home devices including HG are required to be ready to operate at any time in digital home environment. In this work, power control scheme id used to reduce effectively the power consumed by a HG. The power consumption can be reduced excessively by HG characterized with Always-On.
Figure shows that system 2 in sleep mode. System 1 in run mode. The power will be saved by system 2.
REFERENCES [1]. Chamara Gunarathe, Ken Christensen and Bruce Nordman (2005), Managing energy Consumption costs in desktop PCs and LAN switches with proxing, split TCP connections, and scaling of link speed, International Journal of Network Management, pp.297-310. [2]. Internet Engineering Task Force (1981), Transmission Control Protocol, RFC 793. [3]. Internet Engineering Task Force (1982) Ethernet Address Resolution Protocol, RFC 826. [4]. Kerpezetal,K.(2006) IPTV Service Assurance, IEEE Communications Magazine,Vol. 44, No. 9, pp. 16672. [5]. Saehoon Kang, Daewong Kim, Younghee Lee, Soon Hyun, J. Dongman Lee, and Ben Lee (2007) A Semantic Service Discovery Network for Large-Scale Ubiquitous Computing, ETRI Journal, Vol. 29, No. 5, pp.545-558. [6]. Garg,S. and Kappes, K. (2003) An Experimental Study of throughput for UDP and VoIP Traffic in IEEE 802.11b Networks, IEEE WCNC 2003, Vol. 3 pp.1748-1753. [7]. Wan-Ki Park, Sung-Il Nam, Chang-Sic Choi, YounKwae Jeong, and Kwang rohPark (2006) An Implementation of FTTH based Home Gateway Supporting Various Services, IEEE Transactions on Consumer Electronics, Vol. 52, No.1,pp.110-115. [8]. Ulrich Schoen, Jan Hamann, Alfred Jugel, Hendrik Kurzawa, and Christian Schmidt, Convergence between public switching and the Internet, IEEE Communications Magazine, vol. 35, Issue 1, Jan. 1998, pp.50-65. [9]. K. Kerpez et al., IPTV Service Assurance, IEEE Communications Magazine, vol. 44, no. 9, Sept. 2006, pp. 16672.
Figure 4.3 System 1 in sleep mode Figure shows that system 1 in sleep mode. System 2 in run mode. The power will be saved by system 1.
Figure 4,4 Both systems in sleep mode
Proceedings of PEID 2011 INFO Institute of Engineering, Coimbatore
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AUTONOMOUS AIRCRAFT
Dr.K.Geetha, Sreejesh, Sreejith, Soumya, Shobita, Nideesh Kumar and Nitin K Salim Department of Electrical & Electronics Engineering, NSS College of Engineering, Palakkad, Kerala
PARTS OF AIRCRAFT INTRODUCTION Autonomous vehicles offer a degree of independent flight, able to guide themselves to given waypoints and perform specific tasks without any or little human interaction. Radio control does not offer this independence. The uses for this booming technology are mainly military reconnaissance, civilian surveillance and mobile signal transmission. Recently the uses extend to law enforcement agencies and the planetary exploration of Mars. These aircraft come in all shapes and sizes, from simple hand size micro planes with small video cameras attached, to full size autonomous planes able to fly for long periods of time. These vehicles can one day be used for more than military tasks. They can be used to gather meteorological information like hurricane hunters. They could be used for search and rescue operations and, since these aircraft dont require human control, they could stay on station searching for a much longer period than regular aircraft. They could also be used to quickly and inexpensively transport goods like medical supplies. The autonomous aircraft systems completely or partially remove the human supervision of the vehicle. The remote controlled aircraft systems now present has several disadvantages such as it need a trained pilot on the ground to control and monitor the operations of the aircraft, if the rage of the mission is more than the range of the vision of the pilot on the ground he has to incorporate a camera and has to control the operation of it also along with the control of the aircraft. But the autonomous aircraft system with the implementation of the emerging technologies completely removes the disadvantages of the remote controlled aircraft. The autonomous aircraft take off form the airport autonomously, moves through the predefined path and land on the predefined position without any human interaction during the course of the flight. This section denes the parts of the aircraft, which is relevant for modeling and control, see the figure1 shown below
different parts of the aircraft WingThe function of the wing is to generate the main part of the lift necessary to make the aircraft y. There are two control surfaces on the wing: aileron, and aps. Aileron -is used to change the rollrate of the aircraft. Since the two ailerons work opposite of each other. The control input to the aileron is the deection angle a, which is the anglebetween the two ailerons; such that the angle is positive counter clockwise the -axis. Flaps - are used as air brakes, to reduce the absolute speed of the aircraft during landing. Thecontrol input is dened as f Horizontal stabilizer- is used to stabilize the pitch angle. Elevator- is the control surface used to control the pitch rate. The control input is the deectionangle e, which is the angle between the elevator in start position and the current angle. Positive counter clockwise the axis. Vertical stabilizer- is used to stabilize the yaw rate. Rudderis the control surface used to control the yaw rate. The control input for the rudder is the deection angle r, which is the angle between the

rudder in start position and thecurrent position, axis. positive counter clockwise the Fuselage-is the body of the aircraft. It contain the ight computer, sensors, and batteries for servomotor and ight computer. Propeller-is the thrust generating part of the aircraft. BASIC AERODYNAMICS This section denes the basic aerodynamic forces: lift, drag, and side-force, which is generated when the aircraft is ying through the air. In order make the model the geometry of the airfoils are dened. Aerodynamic Forces In general an aircraft is ying because a force called lift is greater than the gravitational force. As seen on gure four forces is acting on an aircraft: Lift, Drag, Thrust and Gravity. Gravityis strait forward to determine. The dicult part is: thrust, lift, and drag forces. These forcesare determined by the aerodynamics that describes the forces generated by an object movingthrough gases (atmosphere). Lift When an object is moving through a gas a resulting force is created on the object. This forcedepends of: the geometry of the object moving through the gas, velocity of the object, angle of attack, and slipping. The component of the force which is perpendicular to the direction ofmotion between the gas and the aircraft is called Lift. If the lifting force gets greater than thegravity force then the aircraft is ying. Drag In general drag is the force, generated by a solid object moving through a uid or gas, opposesthe direction of movement. There are dierent sources for drag: one is Skin Friction which isgenerated due to the friction between molecules and the solid object. Another source is theform drag which is generated due to pressure changes around an object and adding all the forcesup, the form drag force is the force projected onto the vector oppose the direction of movementthrough the air, also dened as the axis.
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Thrust Thrust is caused by the propeller, which in fact are rotating wings. This rotation courses a liftingforce to . This lifting force is be created in the direction of dened as the Thrust. Torque The two forces lift and drag are generated all over the aircraft and vary with the control surfaces:Flaps, Aileron, Elevator, and Rudder. These force are applied at dierent distances to the CoGthus causing a torque on the aircraft and making it rotate around and Important Aerodynamic Parameters Important parameters for the generation of lift and drag are: geometry of the wing, angle ofattack, and slipping. Slipping and angle of attack is dened in this section.
Denition of angle of attack , and V. V innity is the relative wind speed(V). It is the speed of the air toward the aircraft. It is assumed that there is no wind, thus Angle of attack Angle of attack () is an important parameter for the stability of the aircraftin the vertical plane. The lift of the plane is dependent of this parameter, and a change in gives change in lift and drag. is dened as the angle between the chord line in thewings, and velocity vector V, thus = arctan . Side slipping in the horizontal plane, the slipping angle () an important stability parameter. It describes the angle between vector and the velocity -plane. , in the
forces acting on an aircraft
is given as: = arcsin . AN AIRCRAFT WITH SIX DEGREES OF FREEDOM The aircraft can perform six dierent motions. Three of these are translational motions alongthe axes of B with respect to E and three are angular rotation of B with respect to E. This gives asystem with 6 Degrees of Freedom (DoF), which is shown on gure . The gure also showsthe notation used for the vector components of: force, torques, velocity, and acceleration.Forces, velocities

and accelerations are all given in vectors, which have three components asit is shown in gure . As an example the angular velocity vector shown in equation below. Thisvector is seen from B and measured with respect to E.
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Denition of: velocity, acceleration, forces, angular velocity, torques, and angularaccelerations on the aircraft RC AIRCRAFT Remote controlled (RC) aircraft is controlled by the pilot from the ground using the transmitter-receiver pair. Here the pilot is tracking the aircraft by himself and taking the required decisions to keep the air craft in it stabilized mode of operation.
airborne components of RC controlled aircraft
control of RC aircraft WORKING The airborne components of RC aircraft include the RC receiver, flight by wire MCU or servo interface card, servo motors for controlling the ailerons, rudders and elevator, brushless DC motor and Electronic speed control unit. As shown in the figure . The RC transmitter transmits the required control signals to the aircraft to maintain the stabilized flight. The RC receiver receives these control signals and transmits it to the servo interface. The servo interface card generates the PWM control signals to control the servo motors according to the input from the RC receiver. This is shown in the figure . If the signal from the RC transmitted and received in the form of PWM with out any data frame as in the case of synchronous transmission the servo interface card or flight by wire section can be avoided. The decision about the control of the aircraft is made by the pilot on the ground hence there is no intelligence incorporated in this system. AUTOPILOT SYSTEM In the autopilot system or automatic flight control system the job of pilot is replaced by the computer. The heart of an automatic flight control system is a computer with high-speed processor. To gather the intelligence required to control the plane, the processors communicate with sensors located on the major control surfaces. They can also collect data from other airplane systems and equipment, including gyroscopes, accelerometers, altimeters, compasses and airspeed indicators. The figure shows the autopilot system along with the RC control system. The aircraft contains processor, actuators, sensors, propulsion and the pay load. While the ground control system contains the simulation or ground control software, data radio link and the data radio inter face with the computer.
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Autopilot system The processors in the Automatic Flight Control System (AFCS) then take the input data and, using complex calculations, compare it to a set of control modes. A control mode is a setting entered by the pilot that defines a specific detail of the flight. For example, there is a control mode that defines how an aircraft's altitude will be maintained. There are also control modes that maintain airspeed, heading and flight path.These calculations determine if the plane is obeying the commands set up in the control modes. The processors then send signals to various servomechanism units. A servomechanism, or servo for short, is a device that provides mechanical control at a distance. One servo exists for each control surface included in the autopilot system. The servos take the computer's instructions and use motors or hydraulics to move the craft's control surfaces, making sure the plane maintains its proper course and attitude.
to examine how feedback loops work in the next section. The figure shows the air borne components of an autopilot system. It includes the 3 axis gyroscopic sensors, 3 axis accelerometer, magnetometer, infrared/ Barometric pressure sensors, high speed GPS receiver, Autopilot flight computer, separate data radio modem for auto pilot system to communicate with the ground control software and all the equipments used in the RC aircraft. The main control areas in the autopilot system are takeoff control, stability control, navigation control and landing control.
Rudder control system The above illustration shows how the basic elements of an autopilot system are related. For simplicity, only one control surface -- the rudder -- is shown, although each control surface would have a similar arrangement. Notice that the basic schematic of an autopilot looks like a loop, with sensors sending data to the autopilot computer, which processes the information and transmits signals to the servo, which moves the control surface, which changes the attitude of the plane, which creates a new data set in the sensors, which starts the whole process again. This type of feedback loop is central to the operation of autopilot systems. It's so important that we're going
Airborne components of Autopilot system TAKEOFF CONTROL The take off control logic is shown in the figure . First the start command is given to the takeoff control system and the system goes to the takeoff run mode. Then the aircraft start to run through the runway and when the speed of the aircraft gets more than the rotation speed the aircraft will switch to the rotation mode. At this moment the aircraft will leave the ground. In the rotation mode the aircraft will rotate around the point of leaving the ground. When the altitude of the aircraft is more than the judgment altitude and the ascending rate of the aircraft is more than the take off judgment ascending rate the aircraft will switch to the cruise flight mode. In the cruise flight mode the control is transferred from the take off control unit to the stability and navigation control unit.
Takeoff control Algorithm STABILITY CONTROL The logic used to control the stability of the aircraft is shown in the figure 4.2.1. Three axis

gyroscope and the three axis accelerometer are the main sensors used to sense the attitude of the aircraft. The combination of the outputs from the accelerometer and the gyroscope determines the strap down inertial attitude. The strap down inertial attitude includes the current pitch and roll angles and current yaw, pitch and roll rates. These values are compared with the prefixed values at which the aircraft is stable. The prefixed and the current values of the attitude are given to the PID controllers. And these controllers send the required signals to the respective servos which control the roll,pitch and yaw. Thus the system is maintained in a stabilized position during the entire flight.
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required predefined position are fed to the PID controller. The output of the PID controller will be the signals to the servos such that it will reduce the error of the error between the current position and the predefined position. Thus the aircraft is maintained in the predefined path during the course of the flight. LANDING CONTROL
stability control of Aircraft NAVIGATION CONTROL
Navigation control of Aircraft The figure shows the navigation control logic of the aircraft. In the navigation control the current location of the aircraft is obtained from the high speed GPS receiver. Even though the GPS can completely find the 3D location of the aircraft, a barometric altitude sensor is used in order to determine the altitude of the aircraft because GPS receiver require signals from 4 satellites to determine the 3D position taking more time which can not be permitted in the fast moving aircraft. Thus from the GPS receiver output and barometric sensor output the position and the direction of motion of the aircraft is determined. This is compared with the predefined route of the aircraft using the google map and Ground Control Software (GCS). The current position and the
Landing Control Algorithm The figure shows the landing control algorithm of the autopilot system. The normal flight of the aircraft of the aircraft is defined as the Cruise flight mode. When the aircraft reaches, the landing point the autopilot system switch from the cruise control mode to the glide slope mode. In the glide slope mode the aircraft glides at a prefixed value of slope towards downward direction. During this free glide the altitude of the aircraft is reduced. When the altitude of the aircraft is less than the flare start altitude the autopilot system switches to the flare mode. In flare mode the slope of descent is reduced to reduce the speed of the aircraft. When the speed of the aircraft is less than the landing judgment speed the aircraft is switched to the landing run mode. By that time the aircraft will be grounded. The supply to the BLDC motor is switched of at the stating of the glide slope mode. CONCLUSION The autonomous aircraft systemwhich completely or partially remove the human supervision of the vehicle is presented in this paper. The remote controlled aircraft systems now present has several disadvantages such as it need a trained pilot on the ground to control and monitor the operations of the aircraft, if the rage of the mission is more than the range of the vision of the pilot on the ground he has to incorporate a camera and has to control the operation of it also along with the control of the aircraft. But the autonomous aircraft system with the implementation of the emerging technologies completely removes the disadvantages of the remote controlled aircraft. The autonomous aircraft take off form the airport autonomously, moves through the predefined path and land on the predefined position without any human interaction during the course of the flight.
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Automation on PLC Furnace System

D.Josephine Selvarani Ruth #1 P.Hari Krishnan#2 #1 M.E (Control And Instrumentation Engg) Department of Electrical and Electronics Engineering, Anna University of technology ,Coimbatore
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djsruth@gmail.com
#2
Lecturer, Department of Electrical and Electronics Engineering, Anna University of technology, Coimbatore, India.
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hariora@yahoo.com applications because of that it is difficult to model for furnace as well as the complex working conditions of heat furnace and unreasonable enough algorithm designing. Therefore, it is urgent to improve control technology and optimize control strategy of heat furnace and other industrial furnaces. The existing furnace control system in a special steel plant adopts Siemens S7-300 PLC as the lower machine to finish data collection and actuator control at the scene and uses industrial control computer as the superior machine to monitor it uniformly. The whole system constitutes a DCS control system that is managed centrally and controlled dispersedly. In order to further improve the control accuracy of gas and air flow as well as the effective combustion efficiency of the gas, cut down energy consumption, and reduce environmental pollution, also to achieve optimal control of the whole furnace, a double cross-limiting control strategy based on the air-fuel ratio control is introduced in this paper to improve the existing system as well as the control effects of the furnace combustion process. II. OPTIMIZING CONTROL STRATEGY OF COMBUSTION i. Overall Strategy There are 48 gas heat furnaces in the special steel plant. The original control system is composed by the superior computer monitor system, the PLC control system and the communication net between superior computer and PLC. The superior computer is an Advantech industrial control machine. The industrial configuration software is installed on the superior computer to realize human-machine interface. The lower machine adopts Siemens S7-300 PLC to achieve measurement and control of the furnace temperature. The industrial Ethernet is used in the communication net to realize data transmission and real-time communication. The sketch map of the original control system is shown in Figure1.
Abstract-Furnace as the key equipment and a big energy consumer of the steel industry, its combustion control performance directly affects the quality of steel products as well as the energy consumption of equipments, etc. So, the control technology of the furnace combustion becomes one of the important research topics in the iron and steel enterprises. Based on the original furnace temperature-combustion cascade control system in a special steel plant, this paper focuses on optimal designing and improving of the furnace combustion control loop using PID controller. This is designed for the furnace used in Bharat Heavy Electricals Limited Tiruchirappalli. After the PID control of gas and air flow based on air-fuel ratio is introduced, and these are simulated in LabVIEW, the control performance of the original system is greatly improved and the energy consumption and environmental pollution are reduced. Keywords- furnace; combustion control; cascade control; air-fuel ratio I. INTRODUCTION Heat furnace is a key thermal equipment of the metallurgical industry, and also the main energy consumption equipment. The combustion process of heat furnace is apt to be affected by random interferences and involves characteristics such as time-varying, strong coupling and nonlinear. It is a highly complex industrial process. The quality of billet heating has a direct impact on the quality of steel products, the lifetime of rolling equipments and the energy consumption. Therefore, the control technology of furnace combustion becomes one of the important research topics in the iron and steel enterprises. At present, in the furnace control field, there are still a large number of domestic enterprises of that their technology staying in a simple manual control or manual-electric operation via electronic instrument. This mode of operation is labour-intensive, and requires a higher skill of the operator. Also, it could not meet the requirements of producing automation, saving energy as well as reducing environmental pollution because of its rough control effects and bad energy-saving performance. Although, some advanced computer control systems based on PLC or DCS and some intelligent control strategies are introduced in some enterprises, they are not acclimatized and still cannot achieve ideal control effects in practical
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valve opening of gas and air. Interferences which changed rapidly, such as gas pressure fluctuations, are included in the viceloop, so it could take advantage of the excellent dynamic performance of the vice-loop to suppress the disturbance on the furnace temperature. The structure of temperature andcombustion cascade control system is shown in Figure2.
Fig 1. PLC control system regulate signal, is used to control the opening scale of gas valve, thus ensuring enough gas for corresponding burning. Simultaneously, the air valve is controlled through combination of the optimal air-fuel ratio and the gas flow, which is also a regulate signal, to ensue enough air. The furnace temperature varies with the gas and air flow. It is transmitted to the input as a feedback . The original system uses the PID algorithm to achieve a closed-loop control of the whole control system. In the furnace system, furnace temperature is related to combustion system closely. Based on the original system, this paper still takes the required gas flow that outputting from the temperature controller as a set value of combustion controller. Conversely, the result of combustion control, that is the flow values of required gas and air, directly affects the furnace temperature. Thus, the combustion control and temperature control connected together in series formally to complete control of furnace, they constitute a furnace temperature-combustion cascade control system. Among it, temperature control acts as the main loop, and combustion control acts as vice-loop. In order to improve the control effects of the furnace, the cross-limiting control strategy is introduced in the vice-loop combustion control system to achieve crosslimiting control of gas and air flow. Meanwhile, as the gas pressure or gas calorific value is instability, the gas and air flow can not always be in the optimal ratio, thus easily leading to excess of gas or air flow. When gas is excess, it could not burn fully and smoke is arisen; when air excess, a lot of heat would be taken away along with the exhaust gas is discharged. All of that would waste energy and pollute the environment. So this system also tries best to assure that the air-fuel ratio is always at a reasonable range by introducing the double cross-limiting control of gas and air flow. ii. Furnace Temperature-Combustion Cascade Control It is using the output of one regulator to change the set value of another regulator that so-called cascade control system. From structure, the two controllers are connected together in series [3]. The cascade control can improve the dynamic characteristics of the process. Besides, interferences occurred in the vice-loop is usually corrected by viceregulator before they affect the main controlled variable. Therefore, the cascade control method also has well anti-disturbance performance. The furnace control system designed in this paper is just a cascade system. In the system, the furnace temperature controller is the main controller, and its output, as the set value of the combustion controller to determine the
Fig 2. Structure of Cascade Control system In the stable state, the output values of the furnace temperature controller and combustion controller are relatively stable. The gas valve opening and the air valve opening also remain unchanged. When the steady state has been destroyed, the furnace temperature-combustion cascade controller begins to play its role. When the pressure of gas fluctuates, the flow will change accordingly. In the initial stage, the change of the gas flow does not immediately affect the furnace temperature, so the output of the temperature controller will unchanged temporarily, that is to say the set value of the gas flow remains unchanged. Therefore, the gas flow controller outputs the correcting value of gas flow correspondingly according to the difference value between the measured value that changed and the set value unchanged, and adjusts the gas valve opening. Obviously, when the gas flow change is less, it will not cause change of the furnace temperature through this control process; when the gas flow change is larger, its impact to the furnace temperature will be greatly weakened through the regulating of the viceloop. As the change of gas flow affects the furnace temperature apparently, the furnace temperature controller starts to work, and changes the set value of the combustion controller constantly. Under the action of the two controllers, the furnace temperature will return back to the set value . When the furnace temperature reduces, the temperature controller begins to work, its output, that is, the set value of the gas flow increases according to the reaction of furnace temperature controller, yet the actual gas flow at that time is unchanged. Then, the output of the gas flow controller increases, the valve opening also increases, the furnace temperature increases gradually until up to the expected values. When the furnace temperature increases, the regulating action is just opposite. When the furnace temperature and the gas flow change simultaneously, if the two change in the same direction, the control effects of the two controllers superpose together, the gas flow decreases
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software, produced by National Instruments, is widely used in industry and research labs to control instruments, take measurements and analyze and store data. LabVIEW is a graphical programming language (unlike C++ or FORTRAN, which are text based) that uses objects called Virtual Instruments, or VIs, to construct computer code. In this experiment, you will use LabVIEW to "wire together" several VIs into a program that will regulate the temperature of a furnace. i. Front panel for simple temperature control This front panel is for a simple temperature control having only acquisition and analysis part. This output which is keep on varying between the lower and upper limits. It also has the indicator in order to alert the system when it is going beyond the limits. Temperature status is to check and control the furnace temperature not to exceed beyond the limits assigned. Fig 6 shows the LabView Platform.
or increases drastically along with the increase or decrease of the temperature. If the furnace temperature and the gas flow change in the opposite direction, then the effects of the two controllers subtract algebraically. It turns up or down the gas valve opening according to the difference value to let the furnace temperature back to set value. III PROPOSED SYSTEM i. Using PID controller to control the furnace temperature The PID controller represents the ultimate in control of a continuous process(Continous Discharge Furnace) for which a specific mathematical description.If PID controller is properly tuned, it will produce an acceptable control for most industrial processes. Proportional-Integral-Derivative (PID) control is the most common control algorithm used in industry and has been universally accepted in industrial control. The popularity of PID controllers can be attributed partly to their robust performance in a wide range of operating conditions and partly to their functional simplicity, which allows engineers to operate them in a a simple, straightforward manner. Programming PID Algorithm The PID controller VI consists of four Sub VIs: proportional, integral, derivative and t Sub VIs. The mathematical algorithm of PID controller is as follows:
Fig 6. Temperature Status (1) where e(t) is the error. Kp, KI, Kd are coefficients of proportional, integral, and derivative actions respectively. The PID output is the sum of the outputs of the proportional, integral and derivative actions. The front panel and block diagram of the PID VI are shown in Fig 7 and Fig 8. The values of process variable (Pv) and the error e(t) are passed to the PID VI through the Pv and error controls. The output of the PID passes out through the PID output indicator. If the output of the PID is within the range between upper limit and lower limit controls, then this value passes out at Coerced(x) terminal and a true Boolean value at In Range? terminal of the In Range and Coerce function. If the output of the PID VI is larger than the upper limit, then the value of the upper limit passes out and False passes to the shift register. But if the output of the PID VI is less than the lower limit, the value of the lower limit passes out and False value passes to shift register. Here, the Boolean value is used to prevent the integral wind up. III SIMULATION AND RESULTS LabVIEW is an acronym for Laboratory Virtual Instrument Engineering Workbench. The
Fig 7. Front panel for simple temperarure control
Fig 8. output for a simple temperature control ii. Block diagram for air and fuel ratio control
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In order to control the temperature of the furnace the flow of th amount of both air and fuel to be maintained properly. So Fig 9 shows the block diagram for this ratio control of both air and fuel that which are responosible for the temperature of the furnace.
Fig 9. Air and fuel control iii. Front panel for proposed model Front panel which has the entries for air and fuel ratio , set point for which the temperature of the furnace has to attain and the indicator or the alarm system in order to alert the operator. IV CONCLUSION The acquisition, generation and analysis of measured signals play an important role in most interfacing. LABVIEW provides a vast selection of ready made VIs for this purpose. Thus, the products quality and the produce efficiency of steel plant are improved, the energy consumption and the environmental pollution are reduced. REFERENCES [1] Liu Zenghuan, He Guangxiang, Wang Lizhen, Hebei University of Engineering, Handan, Hebei, 056038, China ,Optimization of Furnace Combustion Control System Based on Double Cross-limiting Strategy 2010 International Conference on Intelligent omputation Technology and Automation. [2] Chen jun, The intelligent control strategy of walking bean reheating furnace combustion and its application, Master Degree thesis. Changsha, Hunan,China:Central South University.2004.5. (in Chinese) [3] N. Depreea,, J. Sneydb, S. Taylorb, M.P. Taylora, J.J.J. Chenc, S. Wangb, M. OConnord Development and validation of models for annealing furnace control from heat transfer fundamentals. [4] Leroy Cockrell and Thomas M. Sander,IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 28, NO. 4, JULY /AUGUST 1992 945, Selecting a Man/Machine Interface for a PLC-Based Process Control System. [5] Kumar and Syed Jaad Ul Haque Industrial Electronics Engineering Institute of Industrial Electronics Engineering, 2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009. [6] Vijay Kumar Khatri, Ahsan Javed Ghangro, Jetandar .Kuala Lumpur, Malaysia Industrial Data Acquisition and Control System using two PLCs Networked over MPI Network .
Fig 10. Front panel for furnace control
Fig 11. Output for the proposed model iv. Block diagram for proposed model This model consists of circuits that which can be used in the operation of furnaces. Normally in such operations it needs programming for acquisition of signals , analysis of those signals and manipulating them. So here we have the circuits for all these operations.
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[7] Lu jianer, Zuo xiqing and Kui xiuhui, Realization of DCS in steel rolling regenerative funace based on PLC and kingview, Manufacturing Automation, vol.9, Sep 2007, pp.66-68. (in Chinese) [8] Song defu, The study of control technology application to walking reheating furnace, Master Degree thesis. Chongqing, China: Chongqing University.2002.10. (in Chinese) 861. [9] Capdevila, C., Garcia-Mateo, C., Caballero, F. G., & Garcia de Andres, C. (2006). Neural network analysis of the influence of processing on strength and ductility of automotive low carbon sheet steels. Computational Materials Science, 38. [10] Hottel, H. C., & Sarofim, A. F. (1967). Radiative transfer. McGraw-Hill. Marlow, D. O. (1996). Modelling direct-fired annealing furnaces for transient operations. Applied Mathematical Modelling, 20.
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THREE PORT SERIES RESONANT DC-DC CONVERTERS TO INTERFACE RENEWABLE ENERGY SOURCES WITH BIDIRECTIONAL LOAD AND ENERGY STORAGE PORTS Mrs. N.Hemalatha1, Mrs. P. J. Vijayakumari 2
1
Final year- ME Power Electronics & Drives, Madha Engineering College, Chennai-600 069 2 Assistant Professor Dept of EEE, Madha Engineering College, Chennai-600 069 Email-rnhemaa@gmail.com
Abstract- In automobile applications using renewable energy sources, power electronic converters are needed to interface multiple renewable energy sources with the load along with energy storage. Recently, multi-port converters have attracted attention for such applications since they use single-stage high frequency ac-link based power conversion as compared to several power conversion stages in conventional dc-link based systems. In this paper, three-port series resonant dc-dc converters are proposed and designed for renewable energy applications and simulate a high frequency ac-link three winding transformer in a single core with a centralized control. A renewable energy source like solar-cell can be connected to one of the ports, batteries or other types of energy storage devices to the second port and the load to the third port. The simulation results are presented for this solution.
Key words- Three port series-resonant dc-dc converter, three winding transformer, series resonant tanks. ultra capacitor applications. To increase the powerhandling capacity of the converter, three-phase version of the converter was proposed later. A highpower converter to interface batteries and ultra capacitors to a high voltage dc bus has been demonstrated using half bridges. Since the power flow between ports is inversely proportional to the impedance offered by the leakage inductance and the external inductance, impedance has to be low at high power levels. Other circuit topologies are suggested for a three-port converter such as the current-fed topologies that have more number of magnetic components and fly back converter topologies that are not bidirectional. Proposed Method Conventional Method A three-port bidirectional converter had been proposed earlier for a fuel-cell and battery system to improve its transient response and also ensure constant power output from fuel-cell source. The circuit uses phase-shift control of three active bridges connected through a three-winding transformer and a network of inductors. Another method to solve port voltage variations is to use a front-end boost converter, for In this paper, a three-port series resonant converter operating at constant switching frequency and retaining all the advantages of a three-port structure was proposed. The series-resonant threeport converter proposed in this project uses a similar phase shift control but between two different sources. The phase shifts can be both positive and negative, and are extended to all bridges, including the loadside bridge along with bidirectional power flow. A three-port converter with three active full bridges, two series-resonant tanks, and a three-winding
I. INTRODUCTION Renewable energy sources such as Fuel-Cells, Photo-Voltaic (PV) arrays are increasingly being used in automobiles, residential and commercial buildings. For stand-alone systems energy storage devices are required for backup power and fast dynamic response. A power electronic converter interfaces the sources with the load along with energy storage. Existing converters for such applications use a common dc-link. High frequency ac-link based systems have recently been explored due to its advantages of reduced part count, reduced size and centralized control. Such a high frequency ac-link based converter is a three-port converter in to whose ports are connected the energy sources, energy storage devices and the load.
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input filter capacitors for port1 and port2 are Cf1 and Cf2 respectively. A constant voltage dc source such as solar-cell can be connected to port1. Batteries are connected to port2.The switches are realized using Mosfets enabling bi-directional current flow in all ports. The switches operate at 50% duty cycle since square wave outputs are required at the output of the bridges. Two phase-shift control variables 13 and 12 are considered .They control the phase-shift between the square wave outputs of the active bridges. The converter is operated at constant switching frequency Fs above resonant frequency of both resonant tanks. Modes of Operation The operating principle of this circuit can be illustrated using different modes of operation. There are two modes of operation, Forward mode and Reverse mode. A. Forward Mode When Port A is in operation Dc power received from the solar panel acts as the dc source. The interval starts with to (to<t<t1).During this interval switches S1, S4, S5, S8, S9, S12 are turned on and the other switches remain OFF. Initially capacitor C1 of the series resonant tanks are charged up to the negative value. As current starts building up in the circuit, the inductor current increases linearly and the capacitor voltage starts increasing to a positive value. As the capacitor voltage reaches a value equal to the dc voltage Vdc, the inductor current iL1 reaches to thee maximum value. Now the voltage Vdc applied at the primary of the three winding transformer induces the voltage at the winding 3 .At the interval t1 all the switches which are in operation are turned OFF .Now during positive half cycle the switches S5 and S8 are turned on and the voltage is applied to the load . During this forward mode due to voltage applied to the winding 2 of the three winding transformer, the winding 2 is also mutually induced and the ac voltage applied is rectified and stored in the battery back up. The switch control is operated between Port A and port B. When Port A is failed to produce the dc power due to its unavailability then Port A is disabled and Port B is connected to the circuit through the switch control. Now port B is in operation, the dc power stored in the battery back up is delivered to the load. During regenerative braking operation the power is stored in the capacitor banks.
transformer is proposed. It uses a single power conversion stage with high-frequency link to control power flow between batteries, load, and a renewable source such as fuel cell. The converter has capabilities of bidirectional power flow in the battery and the load port. Use of series-resonance aids in high switching frequency operation with realizable component values when compared to existing threeport converter with only inductors. In this project, a three-port bidirectional seriesresonant converter is proposed with the following features: 1) All ports are bidirectional, including the load port for applications, such as motor loads with regenerative braking. 2) Centralized control of power flow by phase shifting the square wave outputs of the three bridges. 3) Higher switching frequencies with realizable component values when compared to three-port circuits with only inductors. 4) Reduced switching losses due to soft-switching operation. 5) Voltage gain increased by more than two times due to the phase-shifting between input and output bridges as opposed to a diode bridge at the load side. In this project, a three-port series resonant converter is introduced to interface renewable energy sources and the load, along with energy storage. II. PROPOSED CIRCUIT
Fig 2.1 The Proposed circuit diagram The proposed three-port series resonant converter circuit is shown in Fig 2.1. It has two series resonant tanks formed by L1, C1 and L2, C2 respectively. The
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B .Reverse Mode During regenerative braking, the power is stored in the capacitor banks on the load side. This power is used when both port A and Port B are disabled. Now the power is supplied from the load to the supply. This power is used to charge up the battery backup and the solar panel until both come to the forward mode of operation.
III. THREE PORT SERIES RESONANT CONVERTER A. Basic block diagram The functional block diagram of the proposed circuit in the forward mode is shown in the Fig. 3.1 various block components are represented. B. Three port converter The power circuit consists of a three port converter. The converter has three ports i.e. Port A, Port B, Port C to which sources or loads can be connected. To the port A the renewable energy source like solar panel is connected. To the port B battery back-up is connected .To the port C the load ie dc motor is connected. The converter regulates the power flow between the sources and the loads. All the three ports have the bi-directional power flow capability. Features of three port converter Bi-directional power flow in all of the ports Control of power flow between the ports as application demands Reduced size due to reduced component count when compared to dc link Port voltages can vary between few tenths of a volt to hundreds of volts Galvanic isolation between all ports All ports are interfaced through high frequency ac-link Single power conversion stage reduces component count on semiconductor switches, drive circuits and magnetic High frequency three-winding transformer provides the isolation between the three ports. Fig. 3.1 Basic Block Diagram in Forward Mode C.Series resonant tanks A Series resonant tank gives the maximum average output and also reduces the three-winding transformer size. So reduces the switching losses of the transformer. A series-resonant converter has more freedom in choosing realizable inductance values and the switching frequency, independent of each other. Such a converter can operate at higher switching frequencies for medium and high-power converters. Use of series resonance aids in higher switching frequency operation with realizable component values when compared to existing three-port converter with only inductor. Series resonant converter uses a phase shift control but between two different sources . Port A and port B is connected to the switch control, it is used to the operate the port A otherwise when port A is failure, it operates the port B. The reverse mode act as the input is giving the load and the output is taken from the port A or port B. The forward mode act as the input is giving power to the port A or port B. The output is taken from the load. D. Three-winding transformer Three-winding transformer also reduces the leakage inductance of the transformer. To get the realizable inductance values equal to or more than the leakage inductance of the transformer, the switching frequency has to be reduced. Hence the selection of
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the pulse from the PIC controller is given to the optoisolator and the Opto-isolator drives the MOSFET. H.. Opto -isolator (driver) This unit is used for two purposes. 1. Isolate the PIC controller from power circuit 2. Increase the necessary voltage level to drive the MOSFET from the PIC controller output. IV. SIMULATION RESULTS The simulations are done by using OrCAD Pspic16.0 software for the circuit shown in Fig. 4.1 shows the port A operation of the three port bidirectional series resonant dc-dc converter. Port A connected to the solar panel supplies the motor load. In this case the power flows from the source to the load in the forward mode..Intially port B has no back up in the battery. After the port A operation , port B battery is been charged up. The series resonance gives the maximum average output and reduces the three winding transformer size.
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Fig 3.2 Basic Block Diagram in Reverse Mode E. Full bridge converters The full bridge converter with four power switches, there are four modes of operation: (1) mode 1 when switches Q1 and Q4 are ON, while Q2 and Q3 are OFF; (2) mode 2 when all switches are OFF; (3) mode 3 when switches Q1 and Q4 are OFF; while Q2 and Q3 are ON; (4) mode 4 when all switches are OFF. Switches are switched ON and OFF accordingly to produce a square wave AC at the primary side of the transformer. The output voltage is stepped up (or down), rectified, and then filtered to produce a DC output voltage. The converter has capabilities bi-directional power flow in the battery and load port. F. Power supply unit This unit gives 5v DC supply to enable the PIC controller and 12v supply to enable the Opto-isolator. This unit consists of the following component. 1. Transformer (230v/15v) 2. Bridge Rectifier 3. Filter Circuit 4. Voltage Regulator 5v, 12v G. Pic controller The purpose of this block is to produce the high frequency pulse which is used to control the MOSFET switching action.5v is needed to enable the PIC controller .The output is nearly 5v, 10kHZ.This output is not enough to to drive the MOSFET.MOSFET is a voltage controlled device and it required at least 8v to 12v of power supply. So
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Lbreak 10.5u M8 D6 V14 D7 5u Cbreak
Fig 4.1 Simulation circuit for Port A Operation Fig. 4.3 shows the port B operations of three port bi-directional converter. The input voltage is given by the port B mode and the output is taken from the load. The three winding transformer is connected between the two bridges. The series resonance gives the maximum average output and reduces the three winding transformer size. The converter has capabilities bi-directional power flow between battery and load port. The converter has high efficiency due to soft switching operation. Use of series resonance aids in high switching frequency operation with realizable components values when
Ls2
M12 D11
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compared to existing three port converters with only inductors.

M 1 V 3 IRF 840 D 1 V 5 M 3 IRF 840 D 2 L 1 Lbr ea 10 5 D 4 C 1 Cbr 5 eak u
V + 0 V 1 C 3
1 0
M 2 V 4 IRF 840
D 3
M 4 V 6 IRF 840
M 9 V 7 IRF 840
D 9
M 1 IRF 840
D 1 V + C 5
T X L
.0 8
L p
XFRM_NON LIN/CT SEC V1 0
R 1 10 00
M 1 V 8 IRF 840
D 1
M 1 VIRF 9840
D 1 V
V + V 2 1 0 V
M 5 V 1IRF 840
D 5
M V6 1IRF 840
D 8 L 2 Lbr ea 10 5 D 7 C 2 5 Cbr u eak
Time(ms)
1 5
C 4
M 7 V 1IRF 840
D 6
V 1
M 8
Fig 4.2 Input and Output Waveforms

MODE II
M V 1 3 IRF 840 D 1 V 5 M 3 IRF 840 D 2 L 1 Lbr 10 5 D 4 T X L C 1 Cbr 5 k
Fig 4.5 Simulation Circuit for Reverse Mode

26 24 22
M V 9 7 IRF 840 M 1 IRF 840
V V 1 C 3
20
D 1 V
1 0 V
M V 2 4 IRF 840
D 3
M V 4 6 IRF 840
D 9
18 16
C .0 5 8
L L
XFRM_NON LIN/CT SEC M V 1 V1 8 IRF 0 840
R 1 10 00
14 12
D 1
M 1 VIRF 9840
D 1 V
10 8 77. 77. 78. 78. 79. 79. 80. 80. 81. 81. 82. 82. 83. 83 84.
M V5 1IRF 840
D 5
M V6 1IRF 840
D 8 L 2 Lbr 10 5 D 7 C 2 5 Cbr k
1 5
V 2 1 0 V
Time(ms)
C 4
M V7 1IRF 840
D 6
M V8 1
Fig. 4.6 Input and Output Waveforms Table1 Circuit Specification of the Three port Converter
Fig.4.3 Simulation circuit for Port B Operation

36V 32V 28V 24V 20V 16V 12V 8V 4V 0 16. 16. V(V2 16. 16. 17. 17. 17. 17. 17. 18.
Term Switching frequency Input DC voltage Output Voltage Input supply frequency InputDC link capacitor Series tank inductance Series tank capacitors Transformer ratio
Symbol Fs V1 Vo F C3,C4 L1,L2 C1, C2 TX1, TX2
Value 20 kHz 15 V 58V 50 Hz 10 F 10mH 5 F 2/3
Time(ms)
Fig 4.4 Input and Output Waveforms
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V. CONCLUSION In this paper a new topology of three-port series resonant converter was introduced to interface renewable energy sources and the load, along with energy storage has been proposed. It was proven that the converter designed has the bidirectional power flow capabilities in all ports. This thesis addresses this need by proposing three port series resonant bidirectional dc-dc converter which uses high frequency ac link which has reduced size, reduced power conversion stages when compared to the conventional dc-link based systems. REFERENCES [1] Tao .H, Kotsopulous .A, Duarte .J, Hendrix .M, Transformer-coupled multiport ZVS bidirectional DC-DC converter with wide input range, IEEE Trans. Power Electron., Vol. 23, No.2, pp 771-781, Mar. 2008 [2] Al Atrash .H, Tian .F, and Bataresh .I, Trimodal half-bridge converter topology for three port-interface, IEEE Trans. Power Electron., Vol.22, No. 1, pp 341-345, Jan. 2007 [3] Duarte .J.L, Hendrix .M, and Simoes .M. G., Three-port bidirectional converter for hybrid fuel systems, IEEE Trans. Power Electron., Vol. 22, No .2, pp 480-487, Mar. 2007 [4] Tao .H, Kotsopulous .A, Duarte .J, and Hendrix .M, Family of multiport bidirectional DC-DC converters, Inst. Electr. Eng. Proc. Elect. Power Appl., Vol. 153, No, pp 451-458, May 2006 [5] Su .G. J and Tang .L, A multiphase, modular, bidirectional, triple-voltage DC-DC converter for hybrid and fuel cell vehicle power systems, IEEE Trans. Power Electron., Vol. 23, No.6, pp 3035-3046, Nov. 2008 [6] Krishnaswamy .H and Mohan .N, A currentfed three-port bi-directional DC-DC converter, Proc. IEEE Int. Telecommun. Energy Conf Minneapolis, USA (INTELEC 2007), pp. 523526. [7] Krishnaswamy .H and Mohan .N, Constant switching frequency series resonant three-port bi-directional DC-DC converter, Proc. IEEE Power Electron. Spec. Conf University of Minnesota, Minneapolis, USA (PESC 2008), pp 1640-1645 [8] Dobbs .B and Chapman .P, A multiple-input DC-DC converter topology, IEEE Power Electron. Lett, Vol. 1, No. 1, pp 6-9, Mar. 2003 [9] Tao .H, Duarte .J.L., and Hendrix .M, Highpower three-port three phase bidirectional DCDC converter, Proc. IEEE Ind. Appl. Soc. 42nd Annu. Meet. (IAS 2007), pp 2022-2029 [10] Tao .H, Duarte .J, and Hendrix .M, Three port triple-half bridge bidirectional converter with zero voltage switching, IEEE Trans. Power electron., Vol. 23, No.2, pp 782-792, Mar.2008
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Two leg voltage source converter for voltage and frequency control in standalone wind power generation
K.Gurumoorthi1 PG Scholar, Mrs.K.Premalatha2 Assistant Professor
Department of Electrical and Electronics Engineering Kumaraguru College of Technology, Coimbatore gurumoorthi2@gmail.com In standalone wind power with the IAG, a voltage and frequency controller has been used as three leg voltage source controller and battery energy storage system[3-4].In this paper, an investigation has been made to explore new control algorithm for the VFC of IAG in the wind power generation. The proposed VFC is based on Icos current detection method for generation of reference source current [6]. The twoleg voltage source converter (VSC) with split capacitor is used along with a BESS as a VFC to feed three phase peak loads. The VFC is isolated from the point of common coupling (PCC) through the Tconnected transformer. The use of T-connected transformer reduces the VSC switches rating and with the two-leg VSC, the numbers of controllable switch count are reduced [7]. In this system a delta connected excitation capacitor bank is connected across the generator terminals with required value such that generator develops the rated terminal voltage under no-load and rated speed of IAG. In Icos algorithm, it is considered that the generator supplies only the real component of load currents, I the amplitude of fundamental real component of the load current and cos the displacement angle of fundamental real component of the load current with respect to the source voltage. The reactive power compensation for the load current and regulation of terminal voltage under varying load conditions are taken care by VFC SYSTEM CONFIGURATION Fig. 1 shows the isolated asynchronous generator system with its controller. The proposed system consists of isolated asynchronous generator with the excitation capacitor, a load and a voltage source converter with a battery energy storage system based voltage and frequency controller. The proposed voltage and frequency controller consists of two leg voltage source converter along with battery at the dc link and third leg as split capacitor. The delta connected capacitor bank is used to generate the rated voltage of the machine at no-load while additional demand of reactive power for the load and the generator is met by the controller. The proposed controller is having capability of bidirectional flow of
Abstract - This paper deals with the one of most significant aspects for isolated wind power generating system is stabilization of magnitude and frequency of generated voltage. The two leg voltage source converter with split capacitor along with battery energy storage system are used as the controller to maintain the constant voltage and frequency in the wind energy system. To control the voltage and frequency the reference source are estimated and compared with the sensed current. The controller used in this wind energy conversion system having bidirectional power flow capability. The stand alone wind energy system is modeled and simulated in the MATLAB using the simulink the sim power system.
Index terms - self excited induction generator, Constant voltage and frequency operation, reduced switch voltage source converter,wind energy conversion system
1.Introduction Self-excited induction generators are good candidates for wind powered electric generation application especially in remote areas, because they do not need external power supply to produce the magnetic field[1]. Permanent magnet generators can also be used for wind energy applications but they suffer from uncontrollable magnetic field, which decays over a period due to weakening of the magnets, and the generated voltage tends to fall steeply with load. The SEIG has a self-protection mechanism because the voltage collapses when there is a short circuit at its terminals[2]. Further, the SEIGs have more advantages such as cost, reduced maintenance, rugged and simple construction, brushless rotor (squirrel cage), etc,.
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order low pass filter with inherent phase shift of 90 degree to extract the amplitude of the fundamental component of three-phase load currents [6]. A zero crossing detector (ZCD) is used to detect the negative going zero-crossing of the corresponding phase voltage. The phase-shifted fundamental current is held as the sample input and ZCD output pulse is as a hold input to the sample and hold circuit (SHC) which output is ILp as an amplitude. The output of the frequency PI controller is treated as Ifp and the output of dc voltage proportional-integral (PI) controller as Idcp. The average of three-phase real power component of the load currents is derived using summing amplifier with a gain (1/3) for load balancing. The algebraic difference between the sum (ILp and Idcp) and average of three-phase load currents (ILap,ILbp, ILcp) estimates the amplitude of real power component of the source currents. Similarly the average of three-phase reactive power component of the load currents is derived from summing amplifier with a gain (1/3) for load balancing. The algebraic difference between the output of the voltage PI controller Ivq and average of three-phase reactive power component of the load currents (ILaq, ILbq, ILcq) computes the amplitude of the reactive power component of the reference source currents. Basic equations of the control scheme used in modeling the proposed controller are as follows, A. Computation of Phase Voltages The line voltages vab and vbc are sensed and phase voltages va, vb and vc are computed as [8],
Fig. 1 System configuration of the WECS active and reactive power. The purpose of the reduced switch voltage source converter improves the reliability of the controller and reduces computational burden. The constant speed operation of isolated asynchronous generator takes place by proper management of the generator power using battery energy storage system. When there is deficiency in the generated power, the battery supplies the additional required load demand through process of discharging and maintains the constant frequency along with providing the functions of load leveling. While there is an excess generated power it starts charging and consumes additional generated power which is not consumed by the consumer loads. CONTROL ALGORITM Scheme and Fig. 2 shows the Icos algorithm for VFC. The operation of VFC enforces to maintain the rated terminal voltage under varying load conditions and to maintain a constant supply frequency along with balanced and harmonic free source currents. To achieve this, the reference source currents need to be controlled through proper switching of VSC switches. The reference source currents have two parts for each phase, one is real power component i.e. I.cos and other is reactive power component i.e. I.sin. Both of these components are estimated for each phase. The line voltages vab and vbc are sensed to compute the three phase voltages. A set of inphase and quadrature unit templates are computed using the fundamental phase voltages. Three phase load currents are sensed and filtered using a 2nd
The computed voltages are passed though band pass filter (BPF) to avoid the noise in the phase voltages. B. Computation of In-Phase and Quadrature Unit Templates The in-phase unit templates are derived using an amplitude of point of common coupling voltage (PCC) Vt and instantaneous phase voltages as,
Moreover, the quadrature unit templates are computed as, Uap,Ubp and Ucp The expression for these quadrature unit templates is given by
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Fig.2 simulation diagram of control scheme
C. Estimation of Source Frequency The frequency of terminal voltages is directly taken by using phase locked loop. F. Estimation of Fundamental Reference Real Power The amplitude IL1.cos is the active power component of the respective fundamental load currents. This is extracted as the amplitude of the fundamental load current, phase shifted by +90 degree, at the negative zero-crossing of the phase voltage. A second order low pass filter with a cut-off frequency of 50 Hz is used to extract the fundamental load current with an inherent phase shift of +90 degree. A ZCD is used to detect the negative zero crossing of the corresponding in-phase unit templates. The phase-shifted amplitude of fundamental real power component of the load current is held as the sample input and ZCD output is considered as the hold input to the SHC. The output of SHC is the IL1.cos amplitude. The amplitude of the three-phase fundamental real power component of the load currents are as follows,
where a, b and c are the phase angles of the fundamental currents in a, b and c phases. E. Extraction of Amplitude of Fundamental Reactive Power Component of Load currents The amplitude IL1.sin is the reactive power component of the respective fundamental load currents. This is extracted as the amplitude of the fundamental load current, phase shifted by +90, at the negative zero-crossing of the quadrature phase voltage. The fundamental load current already extracted is used here. A ZCD is used to detect the negative zero crossing of the corresponding quadrature unit templates. The phase shifted amplitude of fundamental reactive component of the load current is held as the sample input and ZCD output is considered as the hold input to the SHC. The output of SHC is the IL1.sin amplitude. F. Estimation of Fundamental Reference Real Power Component of Source Currents The average amplitude of the fundamental real power component of the load currents is subtracted from the sum of the output of the frequency PI controller and the output of dc
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voltage PI controller to estimate the amplitude of the fundamental reference real power component of source currents. The frequency error is given as, where frf the reference frequency ( i.e. 50 Hz in this case) and f is the frequency of the terminal voltage of an IAG. The instantaneous value of f is estimated as discussed above in equation (5). At the nth sampling instant, the output of the frequency PI controller is as, Similarly the error between two capacitor voltages is given as, where Vdc1 is the voltage across upper-side capacitor at the dc bus and Vdc2 is the voltage across the lower-side capacitor. At the nth sampling instant, the output of the voltage PI controller is as, Therefore the amplitude of fundamental reference real source current is as, Where, , For the two-leg VSC, only two phase currents need to be controlled, the third-leg control is inherent. Therefore the fundamental reference real power components of the source currents for two phases A and B are given as, G. Estimation of Fundamental Reference Reactive Power Component of Source Currents The average amplitude of the fundamental reactive power component of the load currents is subtracted from the voltage PI controller output to estimate the amplitude of the fundamental reference reactive power component of the source currents. The ac voltage error at the nth sampling instant is given as, where Vtr(n) is the amplitude of the reference ac terminal phase voltage and Vt(n) is the amplitude of the sensed three phase ac voltage at PCC is computed as given in equation . The output of the voltage PI controller for maintaining a constant ac terminal voltage at the nth sampling instant is expressed as where kpa and kpi are the proportional and integral gain constants of the PI controller. Ve(n) and Ve(n-1) are the voltage errors in the nth and (n-1)th sampling instant and Ivq (n) and Ivq(n-1) is the output of voltage PI controller in the nth and (n-1)th instant needed for the voltage control. Therefore the amplitude of fundamental reference reactive power components of the source current is given as, Where Two phase fundamental reference reactive power component of the source currents for phase A and B are given as,
H. Estimation of Fundamental Power Component of Reference Source Currents Two-phase fundamental power component of the reference source currents are estimated for each phase as the vector sum of individual phase, I. PWM Generator These reference source currents (i*sa, i*sb) are compared with sensed source currents (isa, isb). The resulting current errors are amplified using the proportional controller by gain K and Amplified signals are compared with fixed-frequency (10 kHz) triangular carrier wave to generate the gating signals for the VSC switches of VFC. A. Modeling of the Mechanical System The mechanical power generated by a wind turbine in per unit system is given as, where Pm per unit is the power in per unit of nominal power for particular value of specific density of air () and the swept area of blades (A). Cp per unit is performance coefficient in per unit of maximum value of power coefficient, v wind per unit is the wind speed in per unit of the base wind speed. The base wind speed is the mean value of expected wind speed in m/s.
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To generate a constant frequency, ideally the additional generated power with the increased wind speed is stored into the battery and the speed of the IAG is maintained constant. A generic equation is used to model c(, ). The equation based on the modeling turbine characteristics is as,
B. Modeling of the VFC
Fig.3 Control algorithm The proposed I.cos based VFC consists of a two leg current controlled voltage source converter (CCVSC) with split-capacitor as a third leg and the battery at its dc link. The mid-point of three legs are connected individually to each phase of the secondary windings of T-connected transformer shown in Fig. 3. The VSC is isolated from the generator bus through a isolation connected transformer at point of common coupling. The dc voltage across one capacitor is given as follows,
where voc max and voc min are the maximum and minimum open circuit voltage of the battery under fully charged and fully discharged conditions. In the equivalent model, Rin is the equivalent series resistance of the parallel /series combination of a battery, which is usually a small value. The parallel circuit of Cb and Rb is used to describe the stored energy and the resistance responsible for self discharging. V. RESULTS AND DISCUSSION The proposed I.cos based control algorithm of VFC and fixed pitch wind turbine driven IAG is tested with three phase loads. In first-case, performance of VFC is tested with lagging power factor (pf) loads. In this case the reactive power demand of load is supplied by VSC of VFC. In another-case, the VFC is tested with load. These results are shown in Fig. 4and5. The waveforms of the generator voltage (Vgabc), generator current (igabc), load currents for three phases (iLa), (iLb) and (iLc), VSC currents (ica), (icb) and (icc), load neutral current (iLn), frequency (f), terminal voltage (Vt), dc side split capacitor voltages (Vc1and Vc2), instantaneous active power transfer through the generator (Pg), the load (PL) and the battery (Pb) are shown during different dynamic conditions. A.Constant output voltage:
where m is the modulation index and V is the rms value of phase voltage. Therefore the battery voltage must be given as follows,
Fig.4 The performance of voltage frequency controller with constant output voltage for variable wind speed. B.Constant frequency:
Since the battery is an energy storage unit, its energy is represented in kilowatt-hours (kWh), When a capacitor is used to model the battery unit, its capacitance Cb can be determined as follows,
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REFERENCES
[1] L.L. Lai and T.F. Chan, Distributed Generation Induction and Permanent Magnet Generators John Wiley and Sons Ltd, 2007. [2] G.K. Kasal and B. Singh, Decoupled Voltage and Frequency Controller for Isolated Asynchronous Generators Feeding Three-Phase Four-Wire Loads, IEEE Trans. Power Delivery, pp. 966 973, no.2, vol. 23,April 2008. [3] R.M. Hillowala and A.M. Sharaf, A rule based fuzzy logic controller for a PWM inverter in a stand alone wind energy conversion scheme,IEEE Trans. Ind. Appl., vol. 32, no. 1, pp. 57-65, Jan./Feb. 1996. [4] G.K. Kasal, B. Singh, A. Chandra and K. Al-Haddad, Voltage and frequency control with neutral current compensation in an isolated wind energy conversion system, in Proc. IECON 2008, pp. 2259 2264. [5] C.V. Nayar and J.H. Bundell, Output power controller for wind driven induction generator, IEEE Trans. Aeros. and Electron. Syst., vol. 23, no. 3, pp. 388-401, May 1987. [6] G. Bhuvaneswari and M.G. Nair, Design, Simulation, and Analog Circuit Implementation of a Three-Phase Shunt Active Filter Using the Icos Algorithm, IEEE Trans. Power Delivery, vol. 23, no. 2, pp. 1222 1235,April 2008. [7] Bhim Singh, P. Jayaprakash and D. P. Kothari, "A T-Connected Transformer and Three-leg VSC Based DSTATCOM for Power Quality Improvement," IEEE Trans. Power Electron,. vol. 23, no.6, Nov. 2008. [8] H. Akagi, E.H. Watanabe and M. Aredes, Instantaneous Power Theory and Applications to Power Conditioning, Wiley-Inter-science, IEEE Press, 2007.
Fig.5 The performance of voltage frequency controller with constant output frequency for variable wind speed. VI. CONCLUSION A new control algorithm for voltage and frequency control of IAG has been investigated in isolated WECS. It has been shown that a reduced switch two-leg integrated VSC with a battery energy storage system can be potential candidate as a VFC in isolated direct connected loads. The reduced switch VSC reduces the computational burden of VFC and improves the reliability due to less number of switches. The I.cos based algorithm has been verified for the control of VFC in WECS. The simulation results have demonstrated the capabilities of VFC for power quality improvement
APPENDIX IAG Data: 7.5kW, 320V, 50Hz, Y-Connected, 4-pole, Rs=1, Rr=0.77, Lls=0.00478H, Llr=0.00478H, Lm=0.334 H. Wind Turbine Data: 7.5 kW, Cpmax=0.48, m =8.1, C1 =0.5176, C2=116,C3=0.4,C4=5, C5=21, C6=0.0068, C7=0.008, C8=0.035. VFC Data: Lf=1mH, Rf= 0.05,Cdc1=Cdc2=7500 F, Kpa=0.18, Kia=20, Kpf=5, Kif=250, Kadc=.1,Kidc=0.1. Battery data: Cb=7600 F, Rb=10 k, Rin=0.1 ,Voc =700 V.
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Voltage Profile Improvement In Distribution System With Distributed Generation

Dr.N.Shanmugavadivoo .
Assistant Professer Electrical and Electronics Engineering Thiagarajar College of Engineering Madurai, India. nsveee@tce.edu M.Mahin Abubakkar P.G.Student Electrical and Electronics Engineering Thiagarajar College of Engineering Madurai, India. mahin60@tce.edu
Abstract In developing countries high rate of growth in demand of electric energy is felt, and so the addition of new generating units becomes necessary. In deregulated power systems private sectors are encouraged to add new distributed generations. Finding the optimal location and size of new DG is important for obtaining their maximum potential benefits. These benefits includes the voltage profile improvement, loss reduction and voltage stability improvement etc. This paper presents a load flow based method to determine the optimal location and size to place a DG unit in radial systems to improve the voltage profile of the entire system. To demonstrate the validity of these methods computer simulations with MATLAB programs are carried out on 33-bus test system. Keywords Distribution system, Distributed Generation, Voltage profile improvement,Optimal Location and Size.
Utilities already facing problem of high power losses and poor voltage profile. By optimal allocation, utilities take advantage of reduction in system losses, improve voltage profile and improvement in reliability of supply. The planning of the electric distribution system, with Distributed Generation mostly considered the capacity of units and location of units. The computational procedure required to determine the steady state operation conditions of a power system network is termed as load flow calculation and is an important tool in the area of transmission and distribution system. Here, the Distributed Load Flow method is applied for the load flow calculations. Antonio [1] performed that load flow calculations using the DLF method. Jen-Hao[2] also performed the similar work for radial distribution system. In this calculation, two matrixes and a matrix multiplication are used to find the solutions. Kishinevsky [3] and Chiredaja [4] explained about the inclusion of the Distributed Generation in Distribution system. From the basic concept of the power triangle, the equation for the load reactive power can be expressed in terms of power factor and real power. DG can be operated in three modes. Real power of the DG is assumed. Depends upon the real power, the reactive power is calculated using the formula. The reactive power is absorbed for the leading power factor operation and the reactive power is generated for the lagging power factor operation from the DG. S.Senthil Kumar [5] explained about the voltage profile improvement in Distribution system using DG. In this paper, the general expression for the calculation of Voltage profile is presented. The voltage profile is calculated for the cases of with DG and without DG. Using these voltage profiles, the Voltage Profile Improvement Index (VPII) is calculated. Then with different attributes of VPII, DG which has the improvement in voltage profile is found. The different set of weighting factors are tested with different power factors [6]. This work is tested primarily on a IEEE 33-bus system [7] and the results are obtained. II.
LOAD FLOW FOR RADIAL DISTRIBUTION SYSTEM
I.
INTRODUCTION
The Recent changes in the electric utility infrastructure have created opportunities for many technological innovations, including employment of Distributed Generation (DG) to achieve several benefits. Distributed Generation encompasses any small-scale electricity generation technology that provides electric power at a site close to consumers. The size of DG could range from a few kilowatts to hundreds of megawatts. DG units, which are scattered throughout the distribution system, will be connected to a consumers facility, the utilitys distribution system, power transmission grid, or a combination of these options. Some of the benefits of the DG are 1. 2. 3. 4. Reduced line loss Voltage profile improvement Increased overall energy efficiency Enhanced system reliability and security
Today there is growing interest in DG, particularly as onsite generation for businesses and homeowners, which is simulated by better power quality, higher reliability, and fewer environmental problems. This interest is strengthened by the availability of more efficient and modular electric supply technologies. Electric Power Research Institutes (EPRI) study forecasts that 25% of the new generation will be distributed by 2011 and a similar study by the Natural Gas Foundation believes that inappropriate selection of location and size of DG, may lead to greater system losses than the losses without DG.
Load flow is an important tool in the area of transmission and distribution systems. Load flow algorithms are repeatedly required for design and optimization. They must be
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Then the V is found using the following relations
computationally efficient and robust enough to incorporate composite loads. Many of the distribution feeders have failed to converge while using conventional Newton-Raphson (NR) and Fast Decoupled Load Flow (FDLF) methods. Therefore, it is essential to apply suitble method for load flow algorithm to solve the distribution system efectively. In this paper, Distribution Load Flow (DLF) technique for radial distribution network is presented.
=
Using the above equation, the power flow calculations are performed. The flow chart for the load flow calculations using DLF method is shown in Fig 2.
Fig.1.Equivalent current injection based model of distribution network The equivalent circuit current injection model is shown in Fig .1. From this 6-bus system the relation between the bus current to branch current is given below
B-branch current;
I- bus current;
Therefore the relationship between the bus current injections and branch currents is expressed as
Fig.2. Flow chart for Distribution Load Flow method III.SIZE OF DISTRIBUTED GENERATION With different capacity of DG at each node, the load flow calculations are performed and the voltage profile is calculated. Here the real value of the DG is assumed. Reactive power equation for DG is expressed as:
Where BIBC is the Bus Injection to Branch Current (BIBC) matrix. The constant BIBC matrix is an upper triangular matrix and contains values of 0 and 1 only. BCBV matrix is Branch Current to Bus Voltage matrix. DLF is Distribution Load Flow Matrix
Real power load of each bus
V-bus voltage; Z-line impedance;
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With
Where: nG=1 for leading power factor operation nG=2 for lagging power factor operation and:
Where Voltage magnitude at bus-i in per unit Load at bus-i in per unit Weighting factor for load bus-i The equation (15) provides an opportunity to quantify and aggregate the importance, amounts, and the voltage levels at which loads are being supplied at the various load buses in the system. This expression should be used only after making sure that the voltages at all the load buses are within allowable minimum and maximum limits, typically between 0.95 and 1.05p.u. The weighting factors are chosen based on the importance and criticality of the different loads. No overarching rules can be formulated at the present time. Starting with a set of equal weighting factors, modification can be made and, based on an analysis of the results, the set that will lead to the most acceptable voltage profile on a systemwide basis can be selected. It should be noted that if all the load buses are equally weighted the value of is given as (17) The voltage profile expression recognizes the influences of the amount and importance of load at each bus. It allows the possibility of a low-load bus with important load to have a strong impact. In general, weighting factors are assigned based on the importance/criticality of load at each bus. V.TEST SYSTEM The developed algorithm for distribution system has been tested on 33-bus radial distribution system in Fig.3.
DG can be operated in three modes: lagging, leading and unity power factor. Under lagging power factor operation, DG produces reactive power for the system. Thus Q is positive. Also Q is negative for leading power factor operation because DG absorbs reactive power from network. Thus the various DG values are obtained, added at each node and power flow is carried out. IV.APPROACH TO QUANTIFY THE BENEFITS OF DG In order to evaluate and quantify the benefits of DG suitable mathematical models must be employed along with distribution system models and power flow calculations to arrive at index of benefit. Among the many benefits, one of the major benefits is voltage profile improvement. Voltage Profile Improvement Index (VPII) DG is installed to improve the voltage profile of the system and maintain the voltage at customer terminals to within an acceptable range. By introducing DG in the system, voltage profile can be improved because DG can provide a portion of the real and reactive power to the load, thus helping to decrease current along a section of the distribution line which increases voltage magnitude at the customer site. The VPII quantifies the improvement in the VP with the inclusion of DG. It is defined as the ratio of the voltage profile of the system with DG to the voltage profile of the system without DG (base case system) and is expressed as
Based on equation (14), the following attributes are: VPII<1, DG has not beneficial, VPII=1, DG has no impact on the system voltage profile, VPII>1, DG has improved the voltage profile of the system. Where Voltage Profile of the system without DG
The general expression for VP is given as:
Fig.3. A 33-bus radial distribution system
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10 11 12 13 14 15 16 17 (pu) 0.920 0.919 0.918 0.911 0.909 0.908 0.906 0.904 18 19 20 21 22 23 24 25 (pu) 0.904 0.996 0.993 0.992 0.992 0.979 0.973 0.969 26 27 28 29 30 31 32 33 (pu) 0.947 0.945 0.933 0.925 0.922 0.9118 0.9117 0.9116
The total real power load is 3.72MW and reactive power load is 2.4 Mvar. The line and load data of 33-bus test system are given in Table I [6]. TABLE-I NETWORK DATA FOR IEEE 33-BUS SYSTEM Line No Real Power (KW) 1 1 2 0.0922 0.0470 100 2 2 3 0.4930 0.2511 90 3 3 4 0.3660 0.1864 120 4 4 5 0.3811 0.1941 60 5 5 6 0.8190 0.7070 60 6 6 7 0.1872 0.6188 200 7 7 8 0.7114 0.2351 200 8 8 9 1.300 0.7400 60 9 9 10 1.0440 0.7400 60 10 10 11 0.1966 0.0650 45 11 11 12 0.3744 0.1238 60 12 12 13 1.4680 1.1550 60 13 13 14 0.5416 0.7129 120 14 14 15 0.5910 0.5260 60 15 15 16 0.7463 0.5450 60 16 16 17 1.2890 1.7210 60 17 17 18 0.7320 0.5740 90 18 2 19 0.1640 0.1565 90 19 19 20 1.5042 1.3554 90 20 20 21 0.4095 0.4784 90 21 21 22 0.7089 0.9373 90 22 3 23 0.4512 0.3083 90 23 23 24 0.8980 0.7091 420 24 24 25 0.8960 0.7011 420 25 6 26 0.2030 0.1034 60 26 26 27 0.2842 0.1447 60 27 27 28 1.0590 0.9337 60 28 28 29 0.8042 0.7006 120 29 29 30 0.5975 0.2585 200 30 30 31 0.9744 0.9360 150 31 31 32 0.3105 0.3619 210 32 32 33 0.3410 0.5302 60 Base Voltage=12.66KV; Base Power=10MVA; R() X() From Bus To Bus Reactive Power (KVAR) 60 40 80 30 20 100 100 20 20 30 35 35 80 10 20 20 40 40 40 40 40 50 200 200 25 25 20 70 600 70 100 40
The DG size from 10% to 100% is placed at each node of the system and load flow are performed. The optimal size and location of the DG for the various power factors are tabulated in following tables. The study is made in two cases with different weighting factors of voltage profile. I. Results for the equal weighting factor value (K). In this case, for the voltage profile calculation the weighting factor value is taken as equal for all the buses (K=1/33). TABLE-III OPTIMAL SIZE AND PLACEMENT (lagging power factor) Ratings of DG in Percentage 90 100 20 MW 3.348 3.720 0.744 Node Optimal placement in VPII 1.6330 1.6728 1.6382 Power factor 0.85 0.90 0.95
10 17 30
For the three different power factors, the optimal DG size and placement is tabulated. From the above table, node17 is optimum place with 3.72 MW for lagging power factor. TABLE-IV OPTIMAL SIZE AND PLACEMENT (leading power factor) Rating of DG in Percentage MW 10 0.372 Node 8 Optimal improvement in VPII 1.6148 Power factor 0.95
VI.SIMULATION RESULTS AND ANALYSIS The load flow is done using DLF method on the test system without DG and the voltages at every bus are shown in table II. TABLE-II Bus No. 1 2 3 Bus No Voltage (pu) 1.000 0.997 0.983 Voltage Bus no. 4 5 6 Bus No Voltage (pu) 0.975 0.968 0.949 Voltage Bus No. 7 8 9 Bus No Voltage (pu) 0.946 0.932 0.926 Voltage
Node 8 is the optimal place with 0.372MW for the leading power factor II. Resuls for the weighting factors is depending on the loadability of the bus. In this case, for the voltage profile calculation the weighting factor value is depends on the loadability of the buses.
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V.CONCLUSION Employing DG in a distribution system results in several benefits such as increased overall system efficiency, reduced line loss, and improved system voltage profile and transmission and distribution capacity relief to both utilities and the customers. Location and size is the crucial factor in the application of DG for voltage profile improvement. Voltage profile improvement for different weighting factor and power factors are performed. Optimal location and size was found in the test system using the MATLAB program. 1. Weighting factor with equal weightage (K=1/33) In this case, node 17 with 3.72MW for the lagging power factor and node 8 with 0.372 MW for leading power factor are the optimal location 2. Weighting factor with different weightages In this case, node 2 with 0.372 MW for unity power factor, node 23 with 0.372 MW for lagging power factor and node 10 with 2.604 MW for leading power factor are the optimal location Here the study is performed with single DG at nodes. It can also be performed with multiple DG at different locations. VI.REFERENCES
[1] Antonio Gomez Exposito, Esther Romero Ramos,Reliable Load Flow Technique for Radial Distribution Network, IEEE Transaction on power systems, Volume 14, Issue 3, Pages:1063-1070. Jen-Hao Teng, A Direct Approach for Distribution System Load Flow solutions, IEEE Transactions on Power Delivery, Volume 8.Issue 3, July 2003, Pages:882-887. Kishinevshky.Y, Coming Clean with Fuel Cells, IEEE Transactions on Power and Energy Magazine, 2004 Page:30-37 P.Chiradeja, Benefit fo Distributed Generation: A Line Loss Reduction Analysis,IEEE T&D Transaction, 2005 Senthil Kumar,Optimization of Distribution Generation Capacity for Line Loss Reduction and Voltage Profile Improvement using PSO, Electrika., Malaysia, Volume.10, Issue 2, 2008, Pages:41-48. Pathomthat Chiradeja, R.Ramakuamr,An Approach to Quantify the Technical Benefits of Distributed Generation, IEEE Transactions on Energy Conversion, Volume.19, No.4, December 2004. P.Chiradeja, Benefit fo Distributed Generation: A Line Loss Reduction Analysis,IEEE T&D Transaction, 2005
TABLE-V OPTIMAL SIZE AND PLACEMENT (unity power factor) Rating of DG in Percentage 10 MW 0.372 Node Optimal improvement in VPII 1.7838 Power factor 1
23
For unity power factor, optimal size and place is node 2 with 0.372 MW TABLE-VI OPTIMAL SIZE AND PLACEMENT(lagging power factor) Rating of DG in Percentage 10 90 10 MW 0.372 3.348 0.372 Node Optimal improvement in VPII 1.6220 1.4830 1.6605 Power factor 0.85 0.90 0.95
29 10 23
Node 23with 0.372 MW is chosen as the best location and size for the lagging power factor case. TABLE-VII OPTIMAL SIZE AND PLACEMENT(leading power factor) Rating of DG in Percentage 70 80 10 MW 2.604 2.976 0.372 Node Optimal improvement in VPII 1.7341 1.6169 1.7194 Power factor 0.87 0.90 0.95
[2]
10 25 27
[3] [4]
Node 10 with 2.604 MW is the optimal place and size for the leading power factor case.
[5]
[6]
[7]
593
Conservation of Energy Losses in Snubber through Energy Recovery Method

M.Thenthamizh 1, R.Thangam2, J.Baskaran 3 1. PG Scholar, 2.Assistant Professor, 3. Professor Department of Electricalnd Electronics Engineering Adhiparashakthi Engineering College, Melmaruvathur.
AbstractThis paper presents a regenerative passive snubber circuit for pulse-width modulation (PWM) inverters to achieve soft-switching purposes without significant cost and reliability penalties. This passive soft-switching snubber (PSSS) employs a diode/capacitor snubber circuit for each switching device in an inverter to provide low dv/dt and low switching losses to the device.The PSSS further uses a transformer-based energy regenerative circuit to recover the energy captured in the snubber capacitors.All components in the PSSS circuit are passive, thus leading to reliable and low-cost advantages over those soft-switching schemes relying on additional active switches. The snubber has been incorporated into a 150 kVA PWM inverter. Simulation andexperimental results are given to demonstrate the validity and features of the snubber circuit. Index TermsEMI, PSSS, PWM, soft switching inverters.
snubber category. However, all existing soft-switching inverters use additional active devices to achieve softswitching, thus increasing costs and control complexity and decreasing reliability. Prior to the soft-switching technology, the RCD snubber circuit that con-sists of a resistor (R), capacitor (C), and diode (D), as shown in Fig. 1, had been widely used in PWM inverters to reduce
I. INTRODUCTION
o Reduce switching stresses, losses, and electromagnetic
interference (EMI), soft-switching techniques have been developed for power converters since the 1970s [1]. Thereare many topologies of soft-switching inverters [1][10], such as resonant dc link, resonant snubber, and zero-current transition inverters [8]. Soft-switching inverters can be grouped into two main categories: resonant dc link and resonant snubber.The resonant dc link provides zero dc-link voltage or current intervals to all phase legs during switching instants, whereas the resonant snubber diverts current from and/or provides zero voltage intervals to each main device at switching instants. The active clamped resonant dc link converter [1] and the auxiliary quasiresonant dc link converter [2], [10] are examples of resonant dc link inverters. Auxiliary resonant snubber inverters such as the auxiliary resonant commutated pole (ARCP), zero voltage transition, and resonant snubber inverters [9] belong to the second resonant Corresponding author: M.Thenthamizh is with EEE Department of Adhiparasakthi Engineering College, Melmaruvathur. Email:honeythamizh@gmail.com
Fig. 1. Inverter phase leg with RCD snubbers.
switching stresses and EMI. The traditional RCD snubber is lossy and bulky, and it is difficult to apply to high frequency switching PWM inverters because the losses in the snubber increase proportionally with the switching frequency.This paper presents a regenerative passive snubber circuit for PWM inverters that is able to achieve the aforementioned softswitching objectives without significantly increasing the cost. This passive soft-switching snubber (PSSS) employs a snubber circuit consisting of diodes and capacitors for each phase leg to provide low dv/dt and low switching losses to the switching devices. The PSSS further uses a transformer-based energy regenerative circuit to recover the energy captured in the snubber capacitors. All components in the PSSS circuit are passive, making it reliable and low in cost. The snubber has been applied to a 150 kVA PWM inverter. Simulation and experimental results are given to demonstrate the validity and features of the snubber circuit.
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II. PSSS CIRCUIT AND OPERATING PRINCIPLE Fig. 2(a) shows the proposed PSSS circuit, which consists of a diode/capacitor soft-switching snubber (SSS) circuit for each phase leg, and an energy recovery circuit shared among all the phase legs. The SSS circuit includes a snubber diode, Dsp , and a snubber capacitor, Csp , for the upper main device, Sp , and, symmetrically, Dsn and Csn for the lower main device,Sn . The functions of the snubber diodes, Dsn and Csn and snubber capacitors, Csp and Csn , are very similar to those of the traditional RCD snubber. They are, however, arranged differently so that both snubber capacitors are connected to the midpoint of the phase leg. Because the upper and lower main devices always operate complementarily to each other during normal PWM operation, the sum of both snubber capacitors voltages should remain constant and equal to the dc link voltage, which is further guaranteed by a larger snubber bus capacitor,Cso, connected across the two snubber capacitors.
Fig. 3. Voltage waveforms at a switching instant showing the operating principle.
the transformer. Loop III is the negative counterpart of loop I and includes the stray inductance of the negative dc link, the diodes Dsn and DRn , and the other transformer winding. The transformer is connected like a common mode choke and thus presents a large inductance to Loops I and III, as illustrated in Fig. 4(b), to minimize the loop circulating currents. On the other hand, only the leakage inductance of the transformer is seen in loop II, as indicated in Fig. 4(c), thus maximizing the energy recovery current and efficiency.
A Full-bridge inverter circuit which needs four MOSFETs. The Passive soft switching snubber connected across each switching device of the full-bridge inverter circuit. Positive mode of operation as shown in figure 5(a) during this mode M1 and M2 must be gated simultaneous at frequency f=1/T then, the output voltage will be positive. The Negative mode operation as shown in figure 5(b) during this mode M3 and M4 must be gated 180 degree out of phase with these. Frequency of output voltage can be controlled by varying the time period. When M3 and M4 conduct , the output voltage will be negative. A snubber comes into picture only when the voltage across the switch is bigger than the supply (for a short moment). Due to which the spike may exceed the switch rated blocking voltage and causes damage due to over voltage. To prevent such occurrence, a snubber is put across the switch.Snubbers are connected in parallel or series to the power electronic switch,due to which there will be voltage losses. Through the Energy Recovery Circuit, these losses are captured and stored in a battery by using capacitor bank. So when the main current fails, the energy stored in this battery can be used.
Fig. 2. PSSS circuit for an inverter phase leg. (a) Proposed PSSS circuit foran inverter phase leg.
Fig. 3 shows the operating waveforms during Sp turn-off and Sn turn-on. Assuming the IGBT of Sp is conducting the load current, turning off Sp will divert the current into the snubber circuit, charging the snubber capacitor through the snubber diode Dsp and discharging Csn through Cso . Therefore, Vcsp increases and Vcsn decreases as shown in Fig. 3, whereas voltage, Vcso , remains almost constant. Fig. 4 indicates the operating principle of the energy recovery circuit. This circuit has three current loops as illustrated in Fig. 4(a). Loop I includes the stray inductance of the positive dc link, the diodes Dsp and Dsn, and one of the transformer windings. Loop II is the energy recovery path and consists of the diodes DRp and DRn , the capacitor Cpo, the dc source, and
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Fig.4. Operating principle of the energy recovery circuit (a) Equivalent circuit of energy recovery circuit. (b) The transformer acts as a large inductance to the loop 1 and III to minimize circulating current . (c) The transformer has zero (or minimal leakage) inductance toward loop II to maximize energy recovery current and efficiency.
III. SIMULATION AND EXPERIMENTAL RESULTS
D5 M12 V1 = 0 V6 V2 = 10 TD = 0 TR = 1n TF = 1n PW = 4m PER = 8m V5
V+
R7 100K V1 = 0 M13
D15 D1N4007
R11 100k
D1N4007
IRF840 C9 1u
V-
IRF840 V9 C13 1u C15 .10u R9 100k
C11 .10u R6 500k
V2 = 10 TD = 4m TR = 1n TF = 1n PW = 4m PER = 8m
DC = 25 M11 V1 = 0 V7 V2 = 10 TD = 4m TR = 1n TF = 1n PW = 4m PER = 8m IRF840 C10 1u

V-
V+
D8 D1N4007 R8 100K V1 = 0 V10 V2 = 10 TD = 0 TR = 1n TF = 1n PW = 4m PER = 8m
M14
D16 D1N4007 R12 1k C14 1u
IRF840
Fig.6. positive and negative conduction of full bridge circuit Fig.5(a). Positive mode of operation
Fig.5(b). Negative mode of operation Fig.7. Positive and Negative conduction output waveform

M7 IRF843
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determined by the resonance frequency of 2Ls and Cs,w. The highest di/dt also occurs in Modes 4 and 7, which can be expressed as
U1B 4 6 M8 IRF843 74AC32 V8 R10 25 R9 100k 1k
D12 D1N4007 D1N4007 D5 M12 V1 = 0 V6 V2 = 10 TD = 0 TR = 1n TF = 1n PW = 4m PER = 8m V5 D1N4007 R7 100k V1 = 0 C9 1u C11 1u R6 500k V2 = 10 TD = 4m TR = 1n TF = 1n PW = 4m PER = 8m V9 M13 D15 D1N4007 R11 1k C12 5 1n
di/dt = Vcso /2Ls
..(3)
IRF840
IRF840 C13 1u D14 C15 1u D1N4007 D13
DC = 0 M11 V1 = 0 V7 V2 = 10 TD = 4m TR = 1n TF = 1n PW = 4m PER = 8m IRF840 C10 1u D8 D1N4007 R8 100k V1 = 0 V10 V2 = 10 TD = 0 TR = 1n TF = 1n PW = 4m PER = 8m IRF840 C14 1u M14 D16 D1N4007 R12 1k
Therefore, it is obvious that the stray inductance and snubber capacitor are employed to limit both dv/dt and di/dt. Given target numbers for dv/dt and di/dt, snubber capacitance and stray inductance can be determined. V. CONCLUSION A Conservation of Energy losses in Snubbers through Energy Recovery Method has been proposed. The operation, analysis and design considerations were illustrated. Simulation results were shown to verify the operating principle. It can avoid unnecessary energy circulation and thus reduce conduction losses. In each cycle, all the energy accumulated in the snubber capacitor for soft switching is recuperated to the load.This proposed model employs all components in the Passive Soft Switching Snubber circuit are passive, making it reliable and low in cost. The passive soft switching snubber further uses a transformer-based energy regenerative circuit to recover the energy captured in the snubber capacitor. The presented PSSS circuit has the following features: employs only passive components; requires no additional control; allows any PWM schemes; eliminates dc bus plane layout; utilizes stray inductance; reduces dv/dt and di/dt; lowers total inverter cost and improves reliability. REFERENCES
[1] D. M. Divan, Static power conversion method and apparatus having essentially zero switching losses and clamped voltage levels, U.S. Patent 4 864 483, Sept. 5, 1989. [2] R.W. A. A. DeDonker and J. P. Lyons, Auxiliary quasi-resonant dc link inverter, U.S. Patent 5 172 309, Dec. 15, 1992. [3] H. K. Lauw and R. S. Zedwick, Voltage clamped parallel resonant inverter with controllable duty cycle, U.S. Patent 5 559 685, Sept. 24, 1996. [4] D. M. Divan and G. Venkataramanan, Comparative evaluation of soft switching inverter topologies, EPE Firenze, 1991. [5] T. A. Lipo and D. M. Divan, Resonant links: a new family of inverter topologies for solid state power conversion, in Proc. ABB Symp. Power Semicond. Devices Circuits, Sept. 2627, 1991. [6] J. S. Lai and B. K. Bose, An improved resonant DC link inverter for induction motor drives, in Proc. IEEE Ind. Applicat. Soc. Annu. Meeting, 1988, pp. 742758. [7] T. G. Habetler and D. M. Divan, Performance characterization of a new discrete pulse modulated current regulator, in Proc. IEEE Ind. Applicat. Soc. Annu. Meeting, 1988, pp. 395405. [8] H. Mao, F. C. Lee, X. Zhou, and D. Borojevic, Improved zero-current transition inverter for high power applications, in Proc. IEEE Ind. Applicat. Soc. Annu. Meeting, 1996, pp. 11451152. [9] J. S. Lai, R.W. Young Sr., G.W. Ott, Jr., J.W. McKeever, and F. Z. Peng, A delta configured auxiliary resonant snubber inverter, in Proc. IEEE Ind. Applicat. Soc. Annu. Meeting, 1995, pp. 26182624. [10] F. Z. Peng and D. J. Adams, An auxiliary quasiresonant tank softswitching inverter, in Proc. IEEE Ind. Applicat. Soc. Annu. Meeting, Rome, Italy, Oct. 812, 2000, pp. 23972403.
Fig.8. Full bridge circuit diagram
Fig.9. Full bridge output waveform
IV. PSSS CIRCUIT DESIGN AND CONSIDERATIONS Snubber Circuit Design As discussed in Sections II and III, the dv/dt and di/dt are determined by the snubber capacitance Cs and stray inductance Ls and partially by the load current. The highest dv/dt happens in Modes 4 and 7 when the dc link forms a resonant circuit through the stray inductance and snubber capacitor. For Modes 4 and 7, the upper snubber capacitor voltage Vcsp can be expressed as Vcsp(t) = Vcso [Vcso Vcsp (o)] cos(wt) + Ics(o)/wcs sin(wt) (1) where Vcso is almost a constant that equals the dc voltage as shown in Fig. 3,Vcsp(o) is the initial voltage of the upper snubber capacitor, ILs(o) is the initial current through the stray inductor, and w=1/(2LsCs)1/2 is the resonant frequency. The load current affects the initial voltage of the upper capacitor, Vcsp(o), and initial current,ILs(o). The dv/dt from (2) isobtained as d/dt[Vcsp(t)] = w[Vcso Vcsp (o)] sin(wt) + [ILs(o)/Cs]cos(wt) (2) As can be seen from (3), if the snubber capacitance is properly designed so that the dv/dt contributed by the initial current is contained, the highest dv/dt occurs at w=/2when the load current is zero, which results in zero initial voltage and current. The highest dv/dt, equal towVcso , is therefore
598
Selective Harmonic Elimination (SHE) in Switching Voltage Waveforms of Power Converters Using Passive filters
Beena . S
M.S.Ramaiah Institute of Technology Bangalore, Karnataka
Abstract: In this paper we shall design a well tuned passive filter to eliminate selected harmonics. Selective Harmonic Elimination (SHE) technique is a well known modification of Generalized Harmonic Elimination technique. This technique has an advantage of implementing on both two and three level switching voltage waveforms in POWER CONVERTERS. For the selected harmonic elimination we shall design a circuit using passive filters. The design and values of passive filters are obtained using MATLAB and FOURIER SERIES. SHE suitable for on-line implementation and assures convergence while generating errors within practical limits. Introduction: Harmonics are the byproducts of modern electronics. They occur frequently when there are large numbers of personal computers (single phase loads), uninterruptible power supplies (UPSs), variable frequency drives (AC and DC) or any electronic device using solid state power switching supplies to convert incoming Harmonics are the multiple of the fundamental frequency AC to DC. Total harmonic distortion is the contribution of all the harmonic frequency currents to the fundamental. The effects of three-phase harmonics on circuits are similar to the effects of stress and high blood pressure on the human body. High levels of stress or harmonic distortion can
lead to problems for the utility's distribution system, plant distribution system and any other equipment serviced by that distribution system. Effects can range from spurious operation of equipment to a shutdown of important plant equipment, such as machines or assembly lines. Harmonics can lead to power system inefficiency. One of the method suggested was Generalised Harmonic Elimination (GHE), this proposed method had number of disadvantages hence another effective method called Selective Harmonic Elimination. Selective harmonic elimination/control (SHE) has been a widely researched alternative to traditional pulse-width modulation technique. It has been a research topic since the early 1960s and developed into a mature form during the 1970s. This report will discuss the generalized techniques of selective harmonic elimination. The main aim of this paper is to trap the required harmonics to be eliminated and design passive filter. System Architecture: The proposed technique can be diametrically represented as shown in fig.1.from the figure it can be clearly understood that harmonics are eliminated at the supply side rather than load side. number of such passive filters can be designed to eliminate harmonics as per the requirements.
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In general the proposed model of this technique can shown as below in fig.3.
Fig:1. Typical model of SHE

This method is used in applications with a high non-linear ratio to system to eliminate harmonic currents. Filters are tuned to a specific harmonic such as the 5th, 7th, 11th, etc. In addition, harmonic trap filters provide true distortion power factor correction. Filters can be designed for several non-linear loads or for an individual load as shown in fig.1.
Fig:3. Proposed model Harmonic Elimination.
of
Selective
Benefit of SHE technique: 1. Initial guess of switching angles are not required. 2. No initial guess hence requires less storage space. 3. On line implementation are also applicable which includes MATLAB SIMULINK technique. 4. Another, perhaps less obvious, benefit of reducing harmonics at their source is the release of capacity in the electrical power system. 5. Upgrading existing transformers and wiring is often more costly than the original installation.
Fig:2. Schematic diagram to eliminate 5th and 7th harmonics The above figure is an example for selective harmonic elimination with desired values of passive filters for a 30KW drive circuit. The values of passive filters is designed with the help of Matlab or Simulink.
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Analysis of harmonic elimination costbenefit: This cost-benefit analysis compares the estimated cost of adding a harmonicelimination circuit to the electronic power supply to the potential avoided cost of harmonic related losses in the power system. The avoided cost is based on the previous determination of harmonicrelated losses in commercial building model. This analysis assumes 60 kW of office electronic load. The cost of energy is $.10/kWH. The load includes 240 distributed personal computers on 120 branch circuits, and other related electronic office equipment, which operate 12 hours per day, 365 days per year. Conclusion : The proposed harmonic elimination technique is equally generalised in nature as the commonly used GHE technique. IK does not require initial guess as well as storage space to store the switching angles and assures convergence! while generating errors within practical limits. These major advantages make the proposed technique suitable for on-line implementation. Future Work: Active or tuned passive filters may be required to solve existing harmonic problems. Application data on these filters, particularly their use in both harmonic reduction and reactive compensation, is not adequate in the literature or in standards. Further analysis comparing the cost and effectiveness of the variety of different harmonic mitigation options is needed. The value of released capacity and the concept of linear equivalent power factor are significant issues and need further documentation and development. This is indeed a good research topic for follow-up investigations.
Acknowledgement: This work was supported by LV Drives Department , ABB Ltd. Under a project managed by Laxmikantha Shenoy , ABB Ltd., and Dr.Sanjay Lakshminarayan, MSRIT. References: [1] H. S. Patel and R.G. Hoft, Generalised technique of inverters : Part I : Harmonic elimination, IEEE Trans. on Industry applications, vol. 9, no. 3, May/June 1973. [2]Murphy and F.G. Turnbull, Power Electronic Control of AC Motors, Pergamon Press, Elmsford, New York, 1988. [3]IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems, ANSI/IEEE Std. 519-1992. [4] A. B. V.G. Agelidis, I. Balousktsis, "On Applying a Minisation Technique to the Harmonic Elimination PWM Control: The Bipolar Waveform," in IEEE Power Electronic Letters, in press. [5] F. Swift and A. Kamberis, "A new Walsh domain technique of harmonic elimination and voltage control in pulsewidth modulated inverters," IEEE Transactions on Power Electronics, vol. 8, pp. 170-185, 1993.
601
Novel Circuit Configuration for Reactive Power Compensation in Induction Generator

G.Suresh1 PG Scholar, Mrs.K.Malarvihzi2 Assistant Professor
Department of Electrical and Electronics Engineering Kumaraguru College of Technology, Coimbatore suresh.pgs@rediffmail.com Abstract: A novel circuit configuration for compensating for the reactive power of an induction generator is proposed in this paper. This reactive power compensator includes an ac power capacitor set serially connected to a small-capacity power converter. The ac power capacitor is adapted to provide basic reactive power and reduce the voltage rating and power capacity of the power converter. Because, the ac power capacitor set can also effectively block the dc voltage generated by the power converter to the utility, the salient point of the proposed reactive power compensator is that only a two-arm structure is required for the power converter in the three-phase three-wire application. Consequently, the required number of power electronic switches for the power converter is reduced. The current, generated by the induction generator system, supplied back to the utility is sinusoidal and in phase with the utility voltage following compensation of the proposed reactive power compensator. Index Terms: Induction generator, Reactive power, STATCOM, Power converter. I.INTRODUCTION The conventional energy sources for electrical power generation are hydrogen electric, fossil fuels, and nuclear energy. However, the earths environment has been seriously damaged due to the use of these energy sources; and since the supply of fossil fuels will be exhausted in the future, their costs will increase evidently. Hence, renewable energy sources, such as wind and solar are becoming increasingly important. Because the cost of wind power is dropping very fast to the point where it is very close in cost to conventional electric power generation, wind power use has recently rapidly increased worldwide. The induction generator is generally applied in the wind turbine industry. Establishing a magnetic field in the rotor of a squirrel-cage induction generator requires an external reactive power supply to sustain self-excitation. This reactive power can be supplied from the utility in a grid-connected squirrel-cage induction generator, although, this results in a very low power factor. The power factor of renewable generation must be higher than 0.95, an extra reactive power compensator is required while using the squirrel-cage induction generator. Hence, a reactive power compensator, which can adjust the reactive power along with variations in wind speed, is required to obtain a high power factor for the squirrel-cage induction generator. Therefore, controllable reactive power Static Synchronous (VAR) supporters, such as Compensators (STATCOM) are in some cases necessary to provide dynamic voltage support with their actively controllable VAR injection, especially under voltage depression. This paper presents results from the investigation into the impact of installing a STATCOM at an existing wind farm. This wind farm consists of fixed speed induction generators and is integrated through a weakly connected 25kV utility system. A STATCOM is to be installed at the Point of Common Coupling (PCC), where the wind farm is integrated with the utility system. It utilizes a new power electronic device, the Gate Turn-Off Thyristor (GTO), for enhanced high-power switching performance, simplified triggering technology, and overall reduced device and system costs. AC power capacitors are usually used to supply leading power to compensate for the power factor. The ac power capacitor for power factor correction provides a low impedance path for the harmonic current, ac power capacitors are frequently damaged by harmonics. It results in harmonic resonance between the power capacitor and the distribution power system. As a result, the power capacitor may be damaged due to there being too much voltage or current. In order to solve the application problems of the ac power capacitors used for reactive power compensation, the power converter-based reactive power compensator was developed. Accordingly, the power converter can provide a reactive power by controlling its operation. This means that the reactive power can be adjusted linearly. The power converter is employed to provide overall reactive power compensation in response to the full load. This paper proposes a novel circuit configuration for compensating for the reactive power of the induction generator. This reactive power compensator employs an ac power capacitor set serially connected to a power converter. The proposed reactive power compensator has the following advantages: 1) no power resonance problems; 2) small capacity of power converter; 3) less power electronic switches in the power converter.
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source can be controlled by this method. The other is to control the modulation index of the inverter switching pattern directly while dc capacitor voltage is separately regulated well by another controller.
II.CIRCUIT CONFIGURATION The STATCOM is connected at the Point of Common Coupling (PCC). The STATCOM is modeled as three controllable voltage sources. The controllers of the STATCOM are designed according to commonly known control principles. The outputs of the STATCOM controller are amplified and used as the controllable inputs of the three-phase voltage source. If the STATCOM source voltage is larger than the voltage at the PCC (VPCC), the STATCOM generates reactive power. Otherwise, the STATCOM withdraws reactive power.
Fig. 2. STATCOM system based on VSI STATCOM with independently regulated dc source can be controlled by this method. To achieve more fast dynamic response of reactive power compensation while dc capacitor voltage is regulated well, modulation index control for the required reactive power generation and phase angle control for the regulation of dc capacitor voltage can be done at the same time.
Fig. 1. Block Diagram of STATCOM The power is controlled by the voltage angle difference between the STATCOM and the PCC. In this study, the real power request from the DC link capacitor voltage control is always zero (VDC = VDCref). STATCOM based on VSI (voltage source inverter) is a synchronous voltage source connected to the utility mains in parallel through a link reactor (Ll) as shown in the Fig.2. Injection and absorb of reactive power as explained in Fig. 3, inverter output voltage should be controlled to inject or absorb the reactive current on STACOM. Inverter output voltage of VSI can be generally expressed by equation. (1) Vinvpeak= MI Vdc where, vinvpeak -> inverter output voltage (peak) [V], MI-> modulation index of switching pattern, Vdc->dc capacitor voltage [V], From the equation (1), there are two different methods of controlling the inverter output voltage to generate the leading or lagging reactive power from VSI. One is to change the dc capacitor voltage indirectly by controlling the phase angle between inverter output voltage and source voltage of utility mains. STATCOM without independently regulated dc
Fig. 3. Single phase equivalent circuit The proposed power converter is connected at the point of common coupling where the STATCOM is connected in the circuit. The proposed power converter has the two arm structure and it reduces the number of switches required for the power converter. The Fig.4. shows that the proposed power converter is used for replacement for the STATCOM in the power circuit. The circuit configuration of the proposed reactive power compensator applied to the three-phase three-wire induction generator system. The threephase three-wire induction generator is driven by a wind turbine and generates power for the utility, and the reactive power compensator is used to supply reactive power to the induction generator. So the real power is flowing into the utility. The proposed reactive power compensator consists of an ac power capacitor set serially connected to a power
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dc terminal of the power electronic switch set through an inductor of filter inductor set without passing any power electronic switches. The filter inductor set is adapted to filter out the high-frequency ripple current due to the switching operation of the power electronic switch set. Due to the existence of the ac power capacitor set, the operating voltage of the dc capacitor and the capacity of the power converter can be reduced, and two power electronic switches can be saved. Thereby, the manufacturing cost of the reactive power compensator is reduced. III. REACTIVE POWER REGULATION Because a dc capacitor is connected to the dc bus of the power converter, this power converter is a voltage-source power converter. The voltage-source power converter is controlled by the pulse width modulation (PWM) strategy in which a modulation signal is compared with a highfrequency carrier. In ideal PWM operation, the output voltages vcona(t) and vconb(t) of two-arm power electronic switch set can be represented as vcona(t) = Vdc/2 + kconvma(t) + vrpa (t) vconb(t) = Vdc/2 + kconvmb(t) + vrpb(t) (2) (3)
converter. The ac power capacitor set provides fundamental reactive power and is also used to withstand the major fundamental component of the utility voltage that may reduce the capacity of the power converter.
Fig. 4. Block Diagram of Proposed Power Converter And the ac power capacitor set can also block the dc voltage generated from the power converter to the utility. The power converter is used to solve the harmonic problems of the ac power capacitor, and it permits the proposed reactive power compensator to provide compensation reactive power. The power converter consists of a dc capacitor, a power electronic switch set, and a filter inductor set. The dc capacitor acts as an energy buffer, and provides dc voltage for normally operating the power converter.
Where Vdc is the dc bus voltage, vrpa (t) and vrpb(t) are the switching ripple voltages, vma(t) and vmb(t) are the modulation signals, and kcon is the gain of the power converter.The gain of the power converter can be represented as kcon = Vdc /2Vcar (4) Where Vcar is the amplitude of the high frequency carrier. The frequency of switching ripple voltages is centered on the integer-times carrier frequency. Since the switching frequency of the power converter is very high compared with the interesting harmonic frequency of power system analysis, it can be effectively filtered out by the filter inductor set. Hence, the switching ripple voltages of power converter can be neglected in the following discussion. Consequently, only two components of power converter output voltages, dc component and low frequency ac components, are considered. Fig. 6 is the dc equivalent circuit of the proposed reactive power compensator.
Fig. 5.Circuit configuration of the proposed reactive power compensator. The power electronic switch set is connected to the dc capacitor, switching the dc voltage to generate a desired compensation current. Because the ac power capacitor set can effectively block the dc voltage generated from the power converter to the utility, only a two-arm bridge structure is required for the power electronic switch set in the three-phase three-wire system. This permits one of the ac power capacitor set to be directly connected to the negative
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output voltages. In order to obtain the balanced three-phase compensation reactive current, the voltages across the ac power capacitor set must be derived under losing one phase ac voltage of the power converter. Using the principle of superposition, the effects of the utility voltages and the power converter output voltages to the ac power capacitor set can be analyzed separately. The method of symmetrical components is also used in the following analysis. Since the utility voltages contain only the positive-sequence component under the ideal three-phase power system, the ac power capacitor voltages from the utility voltages still contain only the positive-sequence component. The ac power capacitor voltages (Vpa1,c, Vpb1,c , and Vpc1,c) from the power converter output voltages are unbalanced, and they can be derived as Vpa1,c = (2Vcona1 Vconb1)/3 Vpb1,c = ( Vcona1 + 2Vconb1)/3 (7) (8)
Fig. 6. DC equivalent circuit.
Vpc1,c = ( Vcona1 Vconb1)/3. (9) The symmetrical components of ac power capacitor voltages from the power converter output voltages can be derived as Fig.7.Fundamental frequency equivalent circuit. Since the voltages of utility and induction generator contain no dc component, they are regarded as short circuits. The power converter contains two dc voltage sources in phase a and in phase b. The dc voltage components appearing in the ac power capacitor set can be derived as (Fig. 6) Vpa0 = Vpb0 = 1/6Vdc Vpc0 = 1/3Vdc (5) (6)
where V(0)pa1,c, V(1)pa1,c , and V(2)pa1,c are the zero-sequence, the positive-sequence, and the negative-sequence components of ac power capacitor voltages from the power converter output voltages. The operator a is represented as
where Vpa0, Vpb0, and Vpc0 are the dc voltage components appearing in the ac power capacitor set, respectively. Since ac power capacitors exist in all paths of the power converter to block the dc component of the power converter output voltage, no dc current will be generated by the power converter and injected into the utility. For simplifying the analysis, the utility is assumed very strong. The short circuit level to wind farm capacity (SCR) is high. Hence, the induction generator cannot affect the voltages across the reactive power compensator. Consequently, the effect of induction generator can be neglected in the analysis of fundamental frequency. Fig. 7 shows the fundamental frequency equivalent circuit of the proposed reactive power compensator. The fundamental components of power converter output voltages are vcona1(t) and vconb1(t) and are regarded as two dependent voltage sources. The amplitudes of vcona1(t) and vconb1(t) are proportional to the fundamental components of the modulation signals vma(t) and vmb(t). This figure shows that the power converter generates only two ac
(10) a = 1 120. Because no zero-sequence current passes in the three-phase three-wire distribution power system, the zero-sequence component of the ac power capacitor set voltages from the power converter output voltages can be neglected. In order to obtain the balanced compensation reactive current of the reactive power compensator, the negative-sequence component V(2)pa1,c of ac power capacitor voltages from the power converter output voltages must be zero. Hence, the following equation can be obtained
(11) 1/3(Vpa1,c + a2Vpb1,c + aVpc1,c) = 0. After substituting (6)(8) into (11), the relationship of the power converter output voltages can be derived as Vconb1 = aVcona1. (12) Equation (12) indicates that Vconb1 lags Vcona1 by 60. It can be seen from (7)(9), the positive-sequence component of ac power capacitor voltages due to the power converter output voltages can be derived as V(1)pa1,c = (Vcona1 + aVconb1)/3. (13)
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component S1, a harmonic component S2, and a fundamental real component S3.
Substituting (12) into (13) then results in V(1)pa1,c = (Vcona1 a2Vcona1)/3 = Vcona1 _ 30/ 3. (14) Considering the effects of both the utility voltages and the power converter output voltages, the positive-sequence component of ac power capacitor voltages can be derived as V(1)pa1 = Vsa1 Vcona1 30/ 3 (15) where Vsa1 is the phase a utility voltage. To obtain the desired fundamental reactive current of the reactive power compensator, the positive-sequence component of power converter output voltages must be in phase with that of utility voltage. The equation given in (15) shows that the power converter output voltage of phase a must lag the phase a
by 90. The compensation reactive power can be adjusted by controlling the amplitude of the fundamental component of power converter output voltages. Because the power converter output voltages can be controlled to be positive or negative, the three-phase reactive power (Qh) supplied from the reactive power compensator can be derived as Qh = 3C Vsa1 (Vsa1 Vcona1/ 3) (16) where Vsa1 and Vcona1 are the rms values of the fundamental component for the utility voltage and the power converter output voltage. The maximum rms value (Vcona,max) of the fundamental voltage generated by the power converter without over modulation is dependent on the dc bus voltage of power converter, and it can be represented as (17) Vcona1,max =(1/2 2)Vdc . Then, the minimum and maximum compensation reactive power can be derived by substituting (17) into (16). Hence, the proposed reactive power compensator can linearly adjust the supplied reactive power between the minimum and maximum compensation reactive power. If the variation range of the reactive power demanded by the induction generator is known in advance, the voltage of dc bus and the capacitance of the ac power capacitor set can be determined.
utility voltage by 30. Consequently, the power converter output voltage of phase b must lag the phase a utility voltage
Fig. 8.Control block diagram of phase a. The fundamental reactive component S1 is used to adjust the compensation reactive power, and the harmonic component S2 is used to block the injecting harmonic current. To balance the power loss of the power converter and the operation of the virtual harmonic resistor, the fundamental real component S3 is required. As shown in Fig. 8, the utility voltage and utility current of phase a are detected by a voltage sensor and a current sensor, respectively, and then sent to the reactive power calculation circuit to calculate the compensation reactive power. The output of the reactive power calculation circuit is the amplitude of the fundamental reactive component. The output of the reactive power calculation circuit may be positive or negative depending on the compensation reactive power. The power converter output voltage of phase a must lag the phase a utility voltage
by 30. The outputs of the reactive power calculation circuit and the phase shift circuit are sent to a multiplier to obtain the fundamental reactive component S1. The power converter must generate a harmonic voltage proportional to the harmonic component of the compensation current to act as a harmonic damping resistor to suppress the harmonic current being injected into the reactive power compensator. The compensation current is detected by a current sensor and sent to a band-pass filter to extract the fundamental component. The harmonic component of the compensation current is obtained by subtracting the fundamental component from the compensation current. The harmonic component of the compensation current is sent to an
by 30 to generate the required compensation reactive current. The detected phase a utility voltage is sent to a phase shift circuit. The phase shift circuit will generate a fundamental sinusoidal signal which lags the utility voltage
IV.CONTROL BLOCK DIAGRAM The control block diagram of phase a for the proposed reactive power compensator is shown in the Fig.8. The voltage-mode control is adapted in the proposed reactive power compensator. The modulation signal of the power converter contains three parts, a fundamental reactive
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amplifier in order to obtain the harmonic component S2. In order to regulate the fundamental real power, the power converter must generate a voltage with adjustable amplitude and in phase with the fundamental component of the compensation current. Since the dc capacitor of the power converter acts as the energy buffer, the dc bus voltage can be used as an index to indicate the condition of real power for the power converter and to determine the amplitude of the fundamental real component S3. If the dc bus voltage of the power converter is higher (lower) than the setting value, this indicates that the injected real power of the power converter is too large (not enough) and the amplitude of the fundamental real component S3 must be decreased (increased). In order to regulate the real power, the dc bus voltage of the power converter is detected by a voltage sensor and compared to a setting value, and the compared result is sent to a proportionalintegral (PI) controller to obtain the amplitude of the fundamental real component S3. The outputs of the PI controller and the band-pass filter are sent to a multiplier to obtain the fundamental real component S3. Finally, the modulation signal of the power converter is obtained by summing the fundamental reactive component S1, the harmonic component S2, and the fundamental real component S3. The modulation signal is sent to a PWM circuit to generate the driving signals of the power electronic switches of arm a in the power electronic switches set. The control block diagram of phase b for the proposed reactive power compensator is similar to that of phase a. V.RESULTS In order to verify the performance of the proposed reactive power compensator for a squirrel-cage induction generator, a three-phase prototype with a utility line voltage of 25kV and a utility frequency of 50 Hz is developed. Both the real power and the reactive power of induction generator are proportional to the rotor speed, and the power factor of the induction generator is very poor. The dc bus voltage of the power converter and the capacitance of the power capacitor depend on the maximum and minimal values of compensation reactive power. The dc bus voltage of the power converter and the capacitance of the ac power capacitor calculated by using the compensation reactive power value. Fig.10. Simulation result after applying the STATCOM (Reactive power). The proposed power converter circuit provides reactive power to the Induction generator during its operation. So the power factor of the circuit gets improved after applying the proposed power converter. Fig.9 shows the simulation result of a reactive power absorbed by the Induction generator without power converter circuit. After applying the STATCOM circuit the reactive power is compensated this is shown in the Fig.10. The reactive power generated by the proposed power converter is shown in the Fig.11. If there is no compensating circuit the power system means it reduces the system power factor and it also leads to voltage disturbances. After applying the STATCOM reactive power is injected into the system which is shown in the Fig.10 When the proposed power converter applied to the Fig.9. Simulation result before applying the reactive power compensator (Reactive power).
system, the reactive power becomes positive it shows that the proposed power converter is better than the STATCOM.
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Fig.11. Simulation result after applying the reactive power compensator (Reactive power).
Fig.14. Simulation result after applying the reactive power compensator (Power factor).
Fig.14. Simulation result before applying the STATCOM (Power factor). Fig.12. Simulation result before applying the reactive power compensator (Reactive power). The Fig.12 shows that the active power in the circuit before applying the proposed power converter in the circuit and the Fig.13 shows that the active power in the circuit does not depend on the reactive power compensation and it depends on the load. The Fig.12 and Fig.13 shows the active power in the system remain same after and before applying the compensation circuit in the system. Fig.16. Simulation result after applying the reactive power compensator (Power factor). The power factor of the system gets improved when the proposed power converter is applied to the system. Its used to compensate the reactive power in the system. The Fig.14 shows the power factor of the circuit which is 0.38 when there is no compensation circuit in the system. After applying the SATCOM circuit the power factor is improved to 0.75, which is shown in the Fig.15. The power of the system is nearer to unity when we applied the proposed power converter in the system which is shown in the Fig.16. The total harmonic distortion is shown in the Fig.17 the THD is 32% without applying any compensation circuit in the system. While applying the STATCOM in the power system the THD is minimized to 5%.Which is further reduced when we applied the proposed power converter circuit in the system.
Fig.13. Simulation result after applying the reactive Power Compensator (Active Power)
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REFERENCES [1] C. Chompoo-inwai, C. Yingvivatanapong, K. Methaprayoon, and W. J. Lee, Reactive compensation techniques to improve the ride-through capability of wind turbine during disturbance, IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 666672, May/Jun. 2005. [2] A. Tapia, G. Tapia, J. X. Ostolaza, and J. R. Saenz, Modeling and control of a wind turbine driven doubly fed induction generator, IEEE Trans. Energy onvers., vol. 18, no. 2, pp. 194204, Jun. 2003. [3] S. Muller, M. Deicke, and R. W. De Doncker, Doubly fed induction generator systems for wind turbines, IEEE Ind. Appl. Mag., vol. 8, no. 3, pp. 2633, May/Jun. 2002. [4] F. Zhou, G. Joos, and B. T. Ooi, AC power transmission from remote large scale wind park based on squirrel-cage induction generator, in Proc. IEEE Int. Conf. Power Syst. Technol. PowerCon, Nov. 2124, 2004, vol. 1, pp. 5257. [5] K. K. Sasi and S. Basu, Technology options for utility grade electric power generation from wind, in Proc. IEEE Int. Conf. Ind. Technol., Jan. 1922, 2000, vol. 1, pp. 638 643. [6] A. A. Bayod, J. A. Dominguez, J. Mur, and J. J. Melero, Combined system for reactive power control in wind farms, in Proc. IEEE IECON, Nov. 58, 2002, vol. 4, pp. 32913296. [7] N. Garcia and A. Medina, Fast periodic steady state solution of systems containing thyristor switched capacitors, in Proc. IEEE Power Electron. Spec. Conf., Jul. 1620, 2000, vol. 2, pp. 11271132. [8] N. Mohan, T. M. Undeland, and W. P. Robbins, Power electronics converters, applications and design, in Media Enhanced, 3rd ed. New York: Wiley, 2003. [9] C.Wang, T. C. Cheng, G. Zheng,Y. D. L. Mu,B. Palk, and M. Moon, Failure analysis of composite dielectric of power capacitors in distribution systems, IEEE Trans. Dielectr. Electr. Insul., vol. 5, no. 4, pp. 583588, Aug. 1998. [10] J. R. Harbaugh and J. E. Harder, Important considerations for capacitor applications in the petroleum and chemical process industries, IEEE Trans. Ind. Appl., vol. IA-18, no. 1, pp. 31 40, Jan./Feb. 1982. [11] B. Singh, S. S. Murthy, and S. Gupta, Analysis and design of STATCOM-based voltage regulator for self-excited induction generators, IEEE Trans. Energy Convers., vol. 19, no. 4, pp. 783790, Dec. 2004. [12] M. B. C. Salles, W. Freitas, and A. Morelato, Comparative analysis between SVC and DSTATCOM devices for improvement of induction generator stability, in Proc. IEEE MELECON, May 1215, 2004, vol. 3, pp. 1025 1028.
Fig.17. Simulation result before applying the reactive power compensator (THD).
Fig.18. Simulation result after applying the STATCOM (THD).
Fig.19. Simulation result after applying the reactive power compensator (THD). VI.CONCLUSION The squirrel-cage induction generator has the advantages of low cost and high durability, it is used in wind power generation. This paper proposes a reactive power compensator, comprising an ac power capacitor set in series with a novel circuit configuration of power converter, to improve the power factor for the squirrel-cage induction generator. The salient points of the proposed reactive power compensator are that only a two-arm structure is required for the power converter in the three-phase three-wire application and the capacity of the power converter is small. The simulation results indicate that the proposed reactive power compensator can effectively compensate for the reactive power of the squirrel-cage induction generator.
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[13] L. Xu, V. G. Agelidis, and E. Acha, Development considerations of DSPcontrolled PWM VSC-based STATCOM, Inst. Electr. Eng. Proc. Electr. Power Appl., vol. 148, no. 5, pp. 449455, Sep. 2001. [14] J. J. Grainger andW. D. Stevenson, Power System Analysis. NewYork: McGraw-Hill, 1994. [15] J. C. Wu, H. L. Jou, K. D. Wu, and N. C. Shen, Power converter based method for protecting three-phase power capacitor from harmonic destruction, IEEE Trans. Power Del., vol. 19, no. 3, pp. 14341441, Jul. 2004.
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APPLICATION OF WAVELET MULTIRESOLUTION ANALYSIS FOR CLASSIFICATION AND LOCATION OF FAULTS ON TRANSMISSION LINES
I ANDREWS JUBEN RATCHANYARAJ Department of electrical and electronics engineering, Sri Ramakrishna Engineering College, Coimbatore.
SYNOPSIS: This paper presents a method for fault analysis based on Wavelet Multi Resolution Analysis (MRA). The main focus is towards transmission line protection in a power system. An accurate method for fault classification and location on transmission lines is needed for quick patrol. Transmission line protection is mainly concerned with protection against short circuit faults. In this, a highly efficient and reliable method for the fault analysis is based on wavelet coefficients of current signals. Daubechies eight (D-8) Wavelet transforms of the three Phase currents on a transmission line fed from both ends are used. The time domain signals utilized for the fault classification and location which, for simulation purpose, was generated by MATLAB (simulink). The summation of the 3rd level output of MRA detail signals of current in each phase extracted from the original signals are used as the criterion for the analysis. This makes the fault classification and location technique very effective. INTRODUCTION: An electric power system comprises of generation, transmission and distribution of electric energy. Transmission lines are used to transmit electric power to distant large load centers. The rapid growth of electric power systems over the past few decades has resulted in a large increase of the number of lines in operation and their total length. These lines are exposed to faults as a result of lightning, short circuits, faulty equipments, mis-operation, human errors, overload, and aging. Fault locating has become a standard feature in nearly all microprocessors-based relays. The fault locating information reduces patrol time on permanently faulted lines. The faults locating information can
also be used to evaluate problem areas on transmission lines. Wavelet transform has received great attention in power community in the last years, because they are better suited for the analysis of certain types of transient waveforms than the other transforms approach. There are two main approaches to present wavelet theory: the integral transform approach (continuous time) and the multiresolution analysis (MRA)/filter bank approach (discrete time) [1]. In power system, wavelet transforms (WTs) are better suited for the analysis of certain types of transient waveforms than the Fourier Transforms (FT) and Short-Time Fourier Transforms (STFT) approaches. A wavelet is described as a little wave, little in the sense of being of short duration with finite energy which integrates to zero, and hence if its suitability for transients. Power system transients, which often have an adverse effect on the normal operation of the system, are quite common like, lighting transients, transformer inrush currents, motor starting currents, capacitor and line-switching transients are just a few of the typical electromagnetic power system transients that occur in practice. Some of the methods employed for analysis of the transient phenomena at present are, transforming the data into the frequency domain via Fourier and STFT [2]. These methods also have served the power engineering community. Fourier has a few drawbacks, they require periodicity in all the time functions involved and also location of transient in time axis is lost. STFT have the following drawbacks, they have the limitations of fixed window width and it will consume more time in transient location. If WTs are opted, they overcome the above discussed disadvantages, as wavelet transforms employ analysis functions that are both in time and
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frequency domain. It focuses on short-time intervals for high frequency components and long-time intervals for low frequency components. Wavelets have a window that automatically adapts to give appropriate resolution. GENERAL CONSIDERATION: The essential part of the design of a power supply network is the calculation of the fault currents, which flow in the fault components when fault of various types occur. In a fault survey, faults are applied at various points in the network and the resulting currents obtained by hand calculations are more likely now on large networks by computer computation. The magnitude of the fault currents gives the engineer the current settings for the protection to be used and the ratings of circuit breakers. The protection is needed to isolate as speedily as possible any element of a power system in which a fault has developed WAVELET TRANSFORMS: Wavelets are mathematical functions that cut up data into different frequency components, and then study each component with a resolution matched to its scale. They have advantages over traditional Fourier methods in analyzing physical situations where the signal contains discontinuities and sharp spikes. Wavelets were developed independently in the fields of mathematics, quantum physics, electrical engineering, and seismic geology. The first record mention of what is now calling a wavelet seems to be in 1909, in a thesis by Alferd Haar. The concept of wavelet transforms in its present theoretical form was first proposed by Jean Morlet and the team at the Marseille Theoretical Centre working under Alex Grossmann in France. The methods of wavelet analysis have been developed mainly by Y.Meyer and his colleagues, who have ensured the methods dissemination. The MultiResolution Analysis (MRA) is one of the most active branches of the Wavelet Transforms. The main algorithm dates back to the work of Stephane Mallet in 1989 [1]. MRA provides an effective way to examine the features of a signal at different frequency bands. Hence, if is suited
for the fault classification and location problems in the power system [3], [4]. The fundamental idea behind wavelets is to analyze according to scale.. Wavelet algorithms process data at different scales or resolutions. If we look at a signal with a large window, we would notice gross features. Similarly, if we look at a signal with a small window, we would notice small features. For many decades, scientists have wanted more appropriate functions than the sines and cosines which comprise the bases of Fourier analysis, to approximate choppy signals. By their definition, these functions are non-local (and stretch out to infinity). They therefore do a very poor job in approximating sharp spikes. But with wavelet analysis, we can use approximating functions that are contained neatly infinite domains. Wavelets are well-suited for approximating data with sharp discontinuities. The wavelet analysis procedure is to adopt a wavelet prototype function, called an analyzing wavelet or mother wavelet. Temporal analysis is performed with a contracted, high-frequency version of the prototype wavelet, while frequency analysis is performed with a dilated, low-frequency version of the same wavelet. Because the original signal or function can be represented in terms of a wavelet expansion (using coefficients in a linear combination of the wavelet functions), data operations can be performed using just the corresponding wavelet coefficients. And if you further choose the best wavelets adapted to your data, or truncate the coefficients below a threshold, your data is sparsely represented. This sparse coding makes wavelets an excellent tool in the field of data compression. MULTI-RESOLUTION AND WAVELET DECOMPOSITION: The WT represents powerful signal processing with a wide variety of applications, Acoustics, communications, transient analysis, medicine etc. the main reason for this growing activity is the ability of the wavelet transform not to be decompose a signal into its frequency components, but also unlike the Fourier transforms to provide a non-uniform
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division of frequency domain [2]. Whereby it focuses on short time Fourier intervals for the high frequency components and long intervals for low frequencies. This attribute to tailor the frequency resolution can be greatly facilitate signal analysis and the detection of the signal features, which can be very useful in characterizing the sources of the transients and or the state of the post disturbance system. The wavelet transforms normally uses both the analysis and synthesis wavelet pair. Synthesis is used for wavelet reconstruction. The original signal is decomposed into its constituent wavelet sub bands or levels. Each of these levels represents that part of original signal occurring at the particular time and in that particular frequency band. These individual frequency bands are logarithmically spaced rather than uniform spaced as in the Fourier transforms. The original signal is divided into different scales of resolution, rather than different frequencies, as in the case of Fourier analysis. IMPLEMENTATION OF DWT:The foundations of the DWT go back to 1976 when Croiser, Esteban, and Galand devised a technique to decompose discrete time signals [5]. Crochiere, Weber, and Flanagan did a similar work on coding of speech signals in the same year. They named their analysis scheme as subband coding. In 1983, Burt defined a technique very similar to subband coding and named it pyramidal coding which is also known as multi-resolution analysis. Later in 1989, Vetterli and Le Gall made some improvements to the subband coding scheme, removing the existing redundancy in the pyramidal coding scheme. Analogous to the relationship between continuous Fourier transform and discrete Fourier transform, the continuous wavelet transform has digitally implementable counterpart called the discrete wavelet transform and is defined as
m k nbo ao ) (1) m ao n Where a and b are the scaling and translation parameters. Where as a=aom and b=nbo aom giving rise to a family of dilated mother wavelet, i.e. daughter wavelet. Scaling gives the DWT logarithmic frequency coverage in contrast to the uniform frequency coverage of, say, the windowed-DFT (i.e. WDFT). The DWT output can be represented in a two-dimensional grid in a manner similar to the WDFT but with very different divisions in time and frequency By simple interchange of the variables n, k and
DWT (a, b) = a
x(n)g (
rearrangement of the Equation 1 gives.
1 DWT (m, n) = a
m
x(n)g (a
n
m o
n bo k ) (2)
On closer observation of this equation, we notice there is a remarkable similarity to the convolution equation for the finite impulse response (FIR) digital filters, namely 1 y (n) = x(k )h(n k ) (3) c where h(n-k) is the impulse responses of the FIR filter. By comparing Equation (2) and Equation (3), it is evident that the impulse response of the filter in the DWT equation is
g ( ao m n bo k )
(4)
the aforementioned characteristic feature of the DWT is very different from the WDFT. The DWT is thus very effective in isolating the highest frequency band at precisely the quarter cycle of its occurrence while the 50Hz power frequency is fully preserved as a continuous magnitude. This simple example clearly explains the multi-resolution attributes of the wavelet transforms in analyzing a non-stationary transient signal comprising both high and low-frequency components.
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By selecting a=2 and bo=1, the CWT can be implemented by using a multi-stage filter with the mother wavelet as the low-pass filter l(n) and its dual as the high-pass filter h(n), As evident from the example considered, down sampling the output of the low-pass filter l(n) by factor 2(2) effectively scales the wavelet by a factor of 2 for the next stage, thereby simplifying the process of dilation. h[l 1 n] = (1) n l (n) (5) Where l is the filter length. Note that the filter length are odd index alternated reversed versions of each other, and the low-pass to highpass conversion is provided by the (-1)n term, filters satisfying this condition are commonly used in signal processing, and they are known as the quadrature mirror filters. The implementation of the DWT with a filter bank is computationally efficient. The output of the highpass filter in Fig1 gives the detailed version of the high-frequency component of the signal. As can be seen, the low-frequency component is further split further to get the other detail of the input signal. By suing this technique, any wavelet can be implemented
The algorithm proceeds as follows: If Sa =Summation of 3ed level values in phase a Sb =Summation of 3ed level values in phase b Sc =Summation of 3ed level values in phase c The complete flow chart for classification is as shown in Fig 2.
for current for current for current the fault
Fig 2: Flowchart for fault classification algorithm Fig 1 Implementation of the Discrete Wavelet Transform (DWT)
FAULT CLASSIFICATION AND LOCATION ALGORITHM: The types of faults considered in the analysis are L-G, L-L-G, L-L, L-L-L, faults. Through an exhaustive experimentation, the parameter identified for the classification is the summation of 3ed level output for the three phase currents.
PRINCIPLE AND LOCATOR DESIGN: A sudden change in system voltage on a power line will generate a wideband signal which covers the entire frequency range. The initial values of these waves are dependent, among other factors, on the fault position on the line, the fault path resistance and, the most important of all, the instance of fault occurrence. These different frequency
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components propagate away from the fault point in both directions. In time, these signals reach other discontinuities on the line and are reflected back towards the fault point. In the frequency domain, the magnitude of the individual signal components decreases, as the frequency rises and the travelling speed increases [6]. Assuming a fault occurs at a point distance x from bus bar R, is given by: v * tr2 (6) x= 2 travelling waves would be initiated towards both bus bars. The principle of the fault location method is based on the successive identification arrival of the travelling high-frequency voltage signals at the bus bar where the locator is installed. In particular, the timing of the first received in subsequent signals referenced to that first signal. Used to identify the fault position, data is often available in the form of sampled time function that is represented by a time series of amplitudes. Neural networks, known for their ability to adapt dynamically to the system operating conditions can make correct decisions if the signals are uncertain SIMULATION RESULTS: The base values of the voltage and the power in the system are taken as 735kV and 6*350MVA. The frequency of the system is taken to be 50Hz. The sequence parameter line model is selected for the transmission line, as this is the most suitable model for a transmission line in the event of faults. The transmission line parameters are: (A) Zero sequence parameters: Ro=0.4054 ohm/km, Xo=2.8125mH/km, C0=0.0044 microF/km; (B)Positive sequence parameters: R1=0.07375 ohm/km, Xl=1.0794mH/km, C1=0.0075 microF/km; and (C) Negative sequence parameters: Same as Positive sequence parameters
Fig. 3 Current Waveforms for Single line to Ground fault
Fig. 4 Current Waveforms for Double Line to Ground Fault
Fig. 5 Current Waveforms for Three phase to Ground Fault
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REFERENCES:
1. S. Mallet, A Theory for Multi resolution Signal Decomposition: The Wavelet Presentation, IEEE Transaction on Pattern Analysis and Machine Intelligence, vol. 11, No. 7, 1989, pp. 674-693. D. Das, N. K. Singh, A. K. Sinhat, A Comparision of Fourier Transforms and Wavelet Transform Methods for Detection and Classification of Faults on Transmission lines, IEEE Trans. on Power Delivery, 2005, vol.20, pp.250-257. D. Chanda, N. Kishore, A..K. Sinha., A Wavelet Multiresolution Analysis for Classification of Faults on Transmission lines, IEEE Transaction on Electrical Power and Energy, , 2003, vol.25, pp. 5969. C.David, Robertson. Octavia, I.Campus, S.Mayer, William B. Gish Wavelet and Electromagnetic Power System Transients , IEEE Trans. on Power Delivery, April 1996.vol. 11, no. 2, pp. 1050-1058. T. M. Lai, L. A. Snider, E. Lo, D. Sutanto HighImpedance Fault Detection Using Discrete Wavelet Transform and Frequency Range and RMS Conversion, IEEE Trans. on Power Delivery, , January 2005, vol.20, no. 1, pp. 397-407. Z. Q. Bo, G. Weller, M. A. Redfern, Accurate Fault location Technique for Distribution System Using Fault-Generated High-Frequency Transient Voltage Signals, IEEE Proceedings on Gener. Transm. Distrib., Vol. 146,No. 1, January 1999
2.
Fig. 6 Fault classification dialogue box for Single line to Ground fault
3.
4.
Fig. 7 Fault classification dialogue box for Double line to Ground fault
5.
6.
Fig. 8 fault location waveform in fault transmission line
CONCLUSION: Protecting the transmission line is important task for the safeguard of electrical power systems. When a fault anywhere on the system is encountered, the fault has to be detected, classified, and located accurately and clearly as quickly as possible. The proposed wavelet based method reduces the quantity of extracted features of the line current signals without losing its essential property, thus requires less memory space and commutating time for proper classification of fault types. The result shows that the proposed method has the ability of identifying and locating different fault types and locates the faulty section quite accurately and efficiently
AUTHORS PROFILE: Andrews Juben Ratchanyaraj I is a lecturer in Sri Ramakrishna Engineering College, Coimbatore. He is graduated from Sri Ramakrishna Institute of Technology, Coimbatore in 2007 with a B.E. in Electrical and Electronics Engineering and received M.E. in Power Electronics and Drives from PSG College of Technology, Coimbatore in 2009. His main research interests include Special Machines Drives and Wavelet Multiresolution Analysis.
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Design and implementation of Hybrid regenerative three phase power supply system combining Grid-Tie and UPS functions
Mrs D. Rajalakshmi1 ,Assistant Professor, N.Vikranth2 ,P.G Scholar Department of Electrical and Electronics Engineering, Kumaraguru College of Technology, Coimbatore
Abstract: A hybrid regenerative power system including photovoltaic (PV) and wind powers and combining the functions of the gridtie system and uninterruptible power for a three phase system employing three phase rectifier, three phase inverter, and a three arm converter. The three arm converter employs one arm for battery discharging and two arms for power conversion of the PV module and wind turbine generator. The operation modes include the gridtie mode and the UPS mode depending on the grid status. A power balance control scheme is presented, which can reduce the utilization of grid power by substituting the Regenerative power in the most effective way for fulfilling the two requirements of a three-stage power supply without the interruption of the load. Also, the PV and wind powers can be utilized with priority in order to provide the flexibility for adapting to local circumstances. A three-phase 25 kW/400 V three phase system is designed and implemented, and the effectiveness of the proposed system and control methodology are verified with some experimental results. 1. INTRODUCTION Due to the fact that environmental concerns have constrained the use of polluted energy resources for electric power generation, the interest in looking for possible alternativesconcerning clean and renewable energy sources is growing worldwide. The increasing number of renewable energy sources and distributed generators requires new control strategies for the operation and management of the power converters in order to maintain the reliability and improve the flexibility and quality of the new power supply system embedded with complex energy conversion units. In recent years, the wind turbine generator (WTG) and photovoltaic (PV) generation technologies have brought opportunities for utilising wind and solar resources for electric power generation. It is well known that renewable energy
sources have unpredictable random behaviours; however, some of them, such as solar radiation and wind speed, have complementary features in many aspects. It has been reported that , the WTG/PV hybrid systems better than a single WTG or PV generation since it suppresses rapid changes in the output power of the single source such as the wind turbine system. In addition, based on the research results reported in, the grid interface of the WTG/PV hybrid system equipped with a battery storage/supply unit can greatly improve the system reliability and operating flexibility. Based on the operating functions, there are a number of possible system configurations in designing the WTG/PV hybrid system as shown in Fig. 1. The stand-alone system configuration shown in Fig. 1a can provide a wellregulated load voltage but the reliability of power supply cannot be fully guaranteed [5]. To overcome the above shortcoming, Fig. 1b shows a gridsupported stand-alone system configuration that has a well-regulated load voltage and also has a reliable charging/discharging source for the battery bank. In low-battery voltage applications such as those shown in Figs. 1a and 1b, the DC-to-DC Converter 3 is required to boost the voltage to a level that is high enough for the rear stage DC-to-AC Inverter; otherwise this stage can be omitted. A gridtie hybrid system allowing the injection of extra power from the WTG and PV to the grid is shown in Fig. 1c . In some design cases, the stand-alone and gridtie configurations are combined as shown in Fig. 1d to achieve better operating flexibility. It should be noted that the load voltage in these two configurations is not regulated and will be floating with the grid voltage. So, for the critical load applications, the configuration combining on-line uninterruptible power supply (UPS) shown in Fig. 1e must be used. In this paper, we propose a three phase rectifier, three phase inverter for AC-DC-AC conversion, and a three arm converter topology with three arms for the UPS rectifierinverter and three arms for the PV, WTG and battery to combine the on-line UPS and the gridtie regenerative power system. A novel power
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balance control scheme is presented. It is designed so as to reduce the grid power and utilize the regenerative power in the most effective way and most importantly to satisfy the two requirements of a three-stage charging of the battery for a high state of charge and no interruption of the load for high reliability. In addition, the utilization of PV and wind powers can be designed with priority. This feature is important for adapting to weather variations and local circumstances to enhance the flexibility and performance of the system. The detailed modeling and controller design of the converter is provided. A three phase 25 kW/4000 V system is designed and implemented, and the effectiveness of the proposed system and control methodology is verified with some experimental results. 2 Circuit configuration and Operation mode of the proposed Hybrid generation system 2.1 System description and operating modes. According to the status of the grid, the proposed system can be divided into the gridtie mode and the UPS mode. In practical operations, the gridtie mode and the UPS mode also can be catalogued into two and three operation modes, respectively, based on various conditions of the PV, WTG, battery bank and the grid. In the gridtie mode, the PV and WTG are operated at their maximum power point (MPP). As shown in Fig. 2a, if the total output power from the PV and WTG is higher than the load demand, The power from the (PV, WTG, BATTERY) is supplied to the load, At the same time as shown in the Fig. 2b if the GRID power fails as in the mode 2 the (PV, WTG, BATTERY) supplies the load until the grid status works again and this mode is meant as UPS mode.
Figure 1 Possible system configuration in designing the WTG/PV hybrid system

a b c d e The stand-alone system The grid-supported stand-alone system configuration The gridtie hybrid system configuration The combined stand-alone and gridtie configuration The combined UPS and gridtie configuration
2 Circuit configuration and operation mode of the proposed hybrid generation system 2.1
3 Design of input voltage controllers for
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the PV and WTG converters: Due to that fact that the same control structure and design method can be used for developing the related voltage controllers used in the PV and WTG, in this subsection, only the design details concerning the PV module are addressed. In this particular application case, the voltage to be regulated is on the input side of the converter rather than the voltage at its output terminal. To design the voltage controller, the transfer function describing the input voltage and the controlled voltage must be derived first. The designed converter system can be treated as a boosttype converter as shown in Fig. 4, in which the outputs of PV or WTG are modelled as a current source. Although the PV module characteristic is equivalent to a voltage source in series with a resistance near the MPP as well as the negative dP/dVp region, it can also be equivalent to a current source like the positive dP/dVp equations can be formulated 1 LdIi/dt = Vp- (1 - D) Vd CdV/dt Ip - Ii 2
a.
ReCdV/dt V =Vp 3 In the continuous current mode (CCM), the ratio of input voltage and output voltage must satisfy the following expression Vp (1 - D)Vd 4 In the steady state Ip=Ii 5
Applying a small disturbance to and using linearisation techniques, one can have the small signal model of the converter formulated as follows LdI i/dt =Vp VdD 6 CdV/dt=-I i 7 ReC dV/dt V= Vp 8 By applying the Laplace transformation to ( 6 to 8) the transfer function of input voltage of the converter to thecontrol duty can be obtained as expressed in V p/D=[-(ReVb=L) (s (1=CRe)] / [S2 Re=L)s(1=LC)] 9
b.
fig 2 a The discharge mode b. The grid supply mode
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a.
b.
c. Fig3. a Six arm converter topology b. Three phase rectifier and Three phase inverter c. DEF arm controller for DEF arms
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generate
the
final
voltage
command.
Fig 4 Designed boost-type converter
a. 3.5 Adaptive MPPT controller: The outer loop of the proposed PV and WT converter systems is an MPPT controller designed for tracking the peak power of the PV module based on the PV characteristic and the slope signal of dP/dV. The modified MPPT control algorithm proposed in this paper is adopted. Named as the incremental conductance method for PV and the hill-climb searching (HCS) method for WTG. Let us take the PV module as an example to address the control actions of the proposed MPPT. Fig. 5a shows the P V characteristic of the PV module used. In the positive slope region (dP/dVp . 0) the operation voltage needs to increase. On the other hand, in the negative slope region (dP/dVp , 0) the operation voltage needs to decrease. In this study, the MPPT controller is implemented in MATLAB real-time control as shown in Fig. 5b. To avoid possible slope calculation error induced by the voltage and current ripples, a fourth-order moving average filter is used. As can be seen from Fig. 5b, the amount of change and the direction of the voltage command after each sampling time are decided by multiplying DP/DVp and Gain 1 and working with a limiter (limiter 1). This voltage control signal with direction information is accumulated with a memory cell and operated with a gain factor (Gain 2) to adjust the control voltage within a proper range. The summation of this control voltage and a given initial voltage (init voltage)passes through a limiter (Limiter 2) to
b Figure 5. MPPT of the PV module

a The PV characteristic of a PV module b The proposed adaptive MPPT controller
The open loop voltage of the PV module is chosen as the initial voltage to make the MPPT start working from that voltage and Limiter 2 is designed for setting the voltage operating range of the PV module. In this particular arrangement, the proposed MPPT controller is adaptive, that is, its adjusting speed of the MPPT is proportional to the slope of DP/DVp and the maximum adjusting speed is limited by Limiter 1. This design enables the MPPT to achieve a fast and precise tracking objective. The HCS method of the WTG in the proposed paper also employs the same MPPT controller shown in Fig. 5b as the PV module, except that the sampling time is longer to consider the WTG having a larger mechanical time constant
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6. Simulation circuit . Modelling and controller design ofthe DEF arms: Based on the need of balancing power flow and performing the energy management functions developed in all operating modes shown in Fig. 2, the required controllers designed for the DEF arms are presented in Fig. 3c. For both the PV module and WTG, the same control structure Can be applied; that is, the outer loop is designed for performing MPPT functions and to give the voltage commands, whereas the inner loop is dedicated for the required voltage controller to track the voltage commands. The duty parameters for the converters can then be decided by the regulated voltages operating with a PWM unit. Since the F-arm is designed for charging and discharging the battery bank, regulating DC-link voltage and balancing Power in real time, the related controllers is to be designed. In Fig. 3c, MS1MS3 is, respectively, the mode selecting switches for the PV, WTG and battery charger. In the grid Tie operating mode, as shown in Figs. 2a and b, the DC-link voltage is regulated by the rectifier of the three-arm rectifier and three phase inverter. Both MS1 and MS2 are set to 0 to allow the PV and WTG to be operated at their MPP by the Designed MPPT controllers, and the MS3 of the battery arm (F-arm) is switched to receive the control signals from the battery charger. The charging current command is obtained from the voltage regulator of the charge controller with a limiter for setting the constant charging current level. The inner control loop of the charging controller is a current regulator designed to track the charging current command via a PWM control signal. When a grid blackout occurs, the system is switched to the UPS mode and the rectifier-arm (A-arm) of the three-arm rectifierinverter is stopped. In this case, the MS3 will Immediately connect the control signal of the batteryarm to the output of the DC voltage controller to take over the DC-link voltage regulation. For preventing over-current during the gridtie mode and UPS-mode transition Period, the battery-arm has added a current limitation loop to provide damping of the response and protect the power switches as well.
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b.
a. 7 a. Grid- tie mode b. discharge mode Conclusion This paper has investigated a hybrid generation system consisting of wind, PV and battery storage energy modules designed to supply continuous and high-quality power to critical loads. A versatile energy management and control scheme has been presented to determine the operation mode of the hybrid generation system and to improve the overall controllability and flexibility. The feasibility and performance of the proposed hybrid generation system operated by the designed controllers are verified with a series of tests and the measured results on a 25kvKW 50Hz experimental system. Employing the three-phase rectifier and the three-phase inverter and constant load voltage is obtained for different mode changes. Refrences: [1] CHIANG S.J., LEE T.S., CHANG J.M.: Design and implementation of a singlephase three-arms rectifier inverter, IEE Proc. Electric Power Appl., 2000 [2] NEHRIR M.H., LAMERES B.J., VENKATARAMANAN G., GEREZ V., ALVARADO L.A.: An approach to evaluate the general performance of stand-
alone wind/photovoltaic generating systems, IEEE Trans. Energy Convers., 2000. [3] NEHRIR M.H., WANG C., GUDA S.R.: Alternativeenergydistributed generation: need for multi-source operation. 38th North American Power Symp. (NAPS), 2006 [4] WANG L., LIN T.J.: Stability and performance of an autonomous hybrid windpv-battery system. Int. Conf. Intelligent Systems Applications to Power System (ISAP), 2007, [5] VALENCIAGA F., PULESTON P.F.: Supervisor control for a stand-alone hybrid generation system using wind and photovoltaic energy, IEEE Trans. Energy Converters., 2005, .[6] Design and implementation of a hybrid regenerative power system combining gridtie and uninterruptible power supply functions H.C. Chiang1 T.T. Ma1 Y.H. Cheng1 Published in IET Renewable Power generation 2009
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Comparison of Modified Z Source Inverter and Voltage Source Inverter for PV Cell Application
Kohila.J (Student member IEEE), P.Sivaraman PG student, Senior Lecturer, Bannari Amman Institute of Technology, Sathyamangalam Dr.A.Nirmal Kumar HOD/EEE Dept, Info Institute of Technology, Coimbatore
Abstract - This paper proposes a solar power system using Modified Z source inverter. The modified Z source inverter employs a unique impedance network couple with the solar cell and inverter main circuit. Modified Z Source inverter has advantages over Z source inverter such as fewer reactive components, less harmonic distortion. Modified Z Source inverter is utilized to realize boost function and inversion in a single stage. The benefits of modified ZSI improve the system performance. Index Term Modified ZSI, PV cell
be minimized. Thus, the overall cost of the system is minimized. 2. SOLAR POWER SYSTEM A. Basic Requirements In order to transfer the energy from solar PV array into residential circuits, the converter systems must fulfill the following requirements: (a) To convert the D.C voltage to A.C voltage. (b) To boost the voltage if the PV array voltage is less than the utility voltage. B. Traditional Converter
1. INTRODUCTION
The oil, coal and gas price is rising and global warming becoming more severe due to environmental pollution. Therefore, countries are now looking for alternative energy sources to partially replace fossil fuels. Due to environmental concerns, more efforts are now being put into green power sources like solar power, wind power, geothermal, fuel cell etc. Solar cells or photovoltaic (PV) cells directly use the energy from the sun to generate electricity. As the energy from the sun is free, the major cost of PV generation is the installation cost. The installation cost mainly consists of the costs of solar modules and the converter interface i.e. the power conditioning system (PCS). With the development of PV technology, the price of solar modules has dropped dramatically. A recent worldwide survey shows that in the last three years, the retail price of solar modules has dropped by 16.95%. However, at the same time, the prices for the solar power system almost remain the same. Furthermore, compared with converters used in drive systems, the prices for the converters used in solar power systems are still up to 50% higher [1]. Reducing the cost of these systems has become a major issue in deploying residential solar power systems. Solar power system converts the DC output from PV cell to AC output. This paper proposes a modified Z-source inverter based solar power system for residential use. By utilizing the Z-source inverter, the number of switching components and the total volume of the system can
Fig. 2.1: DC to AC with step up transformer in traditional PV system
Fig. 2.2: DC to AC with boost in traditional PV system
Fig. 2.1 and Fig. 2.2 show the two most commonly used converter system configurations in practice. In the system shown in Fig 2.1 a transformer at line frequency is utilized to boost the voltage after the DCAC inverter. Usually, a line frequency transformer is associated with huge size, loud acoustic noise and high cost. In addition, the inverter has to be oversized to cope with the wide
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PV array voltage change. The KVA rating of the inverter is doubled if the PV voltage varies at a 1: 2 range. So in order to eliminate the transformer and to minimize the KVA rating requirement of the inverter, in many applications, a high frequency DC-DC converter is used to boost the voltage to a constant value as shown in Fig. 2.2. Unfortunately, the switch in the DCDC converter is very expensive and also reduces the system efficiency. 3. PHOTOVOLTAIC MODULE A PV cell is an electronic device which directly converts sunlight into electricity. Light shining on the solar cell produces both a current and a voltage to generate electric power. PV cell are made up of various semiconductor materials. But monocrystalline silicon and poly-crystalline silicon are mainly used for commercial use. One meter square areas of PV cell produce 1 to 2 watts. The power produced by solar panel depends on two factors which are irradiation and temperature. As irradiation and temperature level changes rapidly, the voltage produced fluctuates and becomes inconstant. The use of equivalent electric circuits makes it possible to model characteristics of a PV cell. The method used here is implemented in PSIM.
(2) where: Io is the reverse saturation current of diode (A), q is the electron charge (1.60210-19 C), Vd is the voltage across the diode (V), k is the Boltzmanns constant (1.38110-23 J/K), T is the junction temperature in Kelvin (K). By using these equation PV module simulated using PSIM software. 4. MODIFIED Z SOURCE INVERTER Inverters with variable voltage which have an input from a PV module are mostly realized in the following three basic topologies: (a) PWM VSI+DC/DC boost converter without transformer (b) PWM VSI + DC/DC boost converter with transformer (c) PWM CSI. None of these solutions is fully satisfactory. Therefore there is a continuous effort to find newer and better solutions. A more interesting solution utilizes the Z source inverter. The distinguishing feature of this inverter is its input symmetrical LC lattice network which has four impedances. In this design, ZSI provides the single stage voltage Buck-Boost operation, which results in lower cost and decreased losses [1]. To eliminate the inconvenience of the typically Z-source inverter, there were modifications of its basic structure that consisted mainly in the change of primary source position. These modifications led to quasi-Z-source inverters (qZSI) [5]. The main advantages of qZSI circuits are improved input profiles and a common DC rail between the Zsource and inverter, unlike the traditional ZSI circuits. Present research indicates another possibility: that is, to incorporate different passive networks at the input to the inverters, a technique that differs from the symmetrical LC lattice network [3] which is typically used in ZSI. These alternative passive networks have been known from many years from circuit theory. Utilization of there will open new possibilities for one step, energy processing BuckBoost voltage converters. Modified Z-source inverter has fewer reactive components in comparison to conventional Z-source inverter. The most significant advantage of the modified Zsource inverter is its use of a common voltage source of the passive arrangement [1]. By utilizing the modified Z-source inverter, the number of switching components and the total volume of the system can be minimized. Thus, the overall cost of the system is minimized. This paper deals with modified Z source inverter based solar power system. Compare to conventional Z source based system, it has less harmonic distortion and increase in output voltage.
Id =Io (eqVd /kT -1)
Fig 3.1: Equivalent circuit of PV cell
Fig: 3.1 shows the simplest model of a PV cell is shown as an equivalent circuit below that consists of an ideal current source in parallel with an ideal diode. The current source represents the current generated by photons (often denoted as Iph or IL), and its output is constant under constant temperature and constant incident radiation of light. The output current (I) from the PV cell is found by applying the Kirchoffs current law (KCL) on the equivalent circuit shown in Fig.3.1. V Isc -Id - d -IPV =0 (1) RP where: Isc is the short-circuit current that is equal to the photon generated current Id is the current shunted through the intrinsic diode. Vd is the voltage across the diode (V) RP is Parallel Resistance (ohm)
The diode current Id is given by the Shockleys diode equation:
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voltage through the transformer inductances should be equal to zero for the switching time period, VL =vL =[TO.VC +T .(VIN -VC )/n]/T=0 (3) 1 Both capacitor voltage VC and output voltage VOUT are functions of the shoot-through coefficient D=TO /T .
VC T1 (1-D) = = VIN (T1 -n.TO ) [1-(n+1).D]
(4)
Fig: 4.1.Passive networks alternative to basic LC lattice network
The LC lattice applied in the ZSI successfully replaces the DC-DC input stage in boost-type voltage source inverters. To minimize the Z-source size, the couple inductors are designed, and the two inductors are built together on one core. To show the possibility of extending the operation range of the ZSI, the use of a low leakage inductance transformer and one capacitor instead of the LClattice is proposed here. . A high frequency transformer based modified Z-source inverter is developed in this section. The topology of modified Z source inverter using modification from Fig.1 is shown in the Fig.2, while the Fig.3. Show the equivalent circuit of modified ZSI topology operating in two modes. The modified ZSI topology requires a very low leakage inductance transformer which should be made with high precision. In such a way, the number of passive elements is reduced because only the transformer and the capacitor are needed. It should be noted that the function of the input diode can be served by other power electronics systems as well, including a diode rectifier similar to Z - source inverter.
Where D satisfies a condition D<1/(n+1). Hence the maximum value of D for MODIFIED ZSI n>1 is smaller than for the conventional Z-source. This is the advantage of the MODIFIED ZSI with n>1 in comparison with ZSI because the same output voltage can be obtained with smaller time period of short-circuits transistor current. Using (4) the amplitude VDC of voltage vDC in non shoot through states can obtain from:
V -V VIN VDC =VC + C IN = n [1-(n+1).D]
(5)
a)
Shoot through mode
b)
Non shoot through mode
Fig: 4.3. Operating modes of modified ZSI
Fig: 4.2. Low leakage inductance transformer based Modified ZSI
As with a conventional ZSI, the modified ZSI can handle shoot through states when both switches in the same phase leg are turned on. The T-network is used instead of the LC-network for boosting the output voltage by inserting shoot through states in the PWM. The modified ZSI governing equations can be developed for the Fig. 3. using Kirchhofs laws and voltage averaging [6]. The average
In practice, the influence of leakage on inductance of the transformer is very important. The lower the inductance, the closer it is to theoretical dependences. The performance of modified ZSI depends on the precision of the transformer design. The PWM modulation of Z-source inverter is modified accordingly by meeting the above criteria i.e. the shoot trough states are inserted within the zero states without affecting the volt-sec average and are added adjacent to the instants of state transitions as shown in Fig: 4.4,
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keeping no. of device commutations, duration of active state unchanged (same as that of conventional VSI, no change in switching loses) per switching cycle. Hence zero state (includes shoot through state) time is not only used to control the average voltage, but also provides buck-boost phenomenon to the Inverter.
Fig. 4.4 PWM Gating signals a) VSI b) modified ZSI
The impedance network of the modified ZSI at a given time can operate in any one of the six possible states given in Table 4.1.
Table: 4.1 Operating states of Impedance Network Fig 4.1: simulated results of modified Z source inverter for PV cell application
INPUT STATE Open Active Shoot through
DIODE STATE ON OFF ON OFF OFF ON
IMPEDANCE NETWORK STATE Open 1 Open 2 Active 1 Active 2 Shoot through 1 Shoot through - 2
Open-1, Active-1 and Shoot-Through-1 states are the desired states in practical applications as they would occur in continuous conduction of inductor current. The other three states, Open-2, Active-2 and Shoot-Through-2 are undesirable states leading to discontinuous conduction and are be avoided by properly sizing the inductors and capacitors of the impedance network. Since both open and shootthrough sates apply zero voltage across the load terminals, there is no difference to the load voltage if all or part of open states is converted to a shoot through states. 5. SIMULATED RESULTS The simulation of modified Z source inverter for PV cell application has done in PSIM software. Fig. 4.1 shows the simulated results at temperature 292 K and irradiance 1000w/m2. Fig: 5.2 and 5.3 show the simulated result of I V and P V characteristic of PV module at different irradiation condition.
Fig : 4.2 I V characteristics of PV Module at different irradiation condition
Fig : 4.3 P V characteristics of PV Module at different irradiation condition
Table 4.1 shows the comparison of simulated results of modified Z source inverter and z source inverter for PV cell application. Compared to voltage source inverter, modified Z source inverter provides higher boosted voltage and less harmonic distortion.
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Table 4.1: comparison of modified Z source inverter and voltage source inverter results for different irradiance
G (w/m2)
1000 800 600 400
Modified Z source Inverter Vo THD (V) (%) 175.635 1.7539 173.045 166.645 155.485 1.7542 1.7621 1.7650
Voltage source Inverter Vo THD (V) (%) 150.818 1.7681 148.838 144.62 137.022 1.8060 1.8106 1.8164
(IEEE Xpolre, 10.1109/CPE.2007.4296565), p.1-9. [8] Huan-Liang Tsai, Ci-Siang Tu, and Yi-Jie Su, Development of Generalized Photovoltaic model Using MATLAB/SIMULINK in proceedings on World Congress on Engineering and Computer Science, 2008. [9] Photovoltaic Module Data sheet, UPL_M5_100W
BIOGRAPHY
Kohila.J completed her B.E EEE in Kamaraj college of Engineering and Technology, Virudhunagar, Tamil Nadu. Currently she is pursuing M.E - Power Electronics and Drives in Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu. Her Area of Interest includes Solar Energy conversion system and Inverters. P.Sivaraman received the BE degree in Electrical and Electronics Engineering from Bharathiar University, Coimbatore, Tamilnadu, India, in 2002 and M.Tech. degree from the School of Electrical and Electronics Engineering SASTRA University, Thanjur, Tamilnadu, India in 2004. Now he is pursuing Ph.D in Anna University of Technology, Coimbatore. From 2004 onwards he was working with the Bannari Amman Institute of Technology,Sathyamangalam,Erode,Tamilnadu, India,where his current research interest includes Power converters for photovoltaic applications and Distributed power generation for rural area applications.
5. CONCLUSION
The proposed system shows that inversion and boost function in single stage and it has fewer reactive components and less number of switching devices. Compared to Voltage source inverter based system, proposed system has less harmonic distortion. It is shown in simulated results and also output voltage can be increased with the help of transformer.
REFERENCES
[1] Ryszard Strzelecki, Marek Adamowicz, Natalia Strzelecka, Wieslaw Bury, New Type T Source Inverter in proceeding on Compatibility and Power Electronics,6th International Conference CPE2009. [2] Amitava Das, Debasish Lahiri, and Arup Kumar Goswami, A New Inverter Topology for Adjustable Speed Drive Systems , in Proc. of Int. Conf. on Control, Communication and Power Engineering, 2010. [3] F.Z.Peng. Z-Source Inverter,in Proc. of the 37th IAS Annual Meeting, 2002, p.775- 781. [4] Amitava Das, Debasish Lahiri, A.K.Dhakar, Residential solar power system using Z source inverter, in proceeding of IEEE TENCON 2008, 19-21 Nov 2008,pp. 1-6. [5] J. Anderson, F.Z. Peng, Four Quasi-Z-Source Inverters,in Proc. of IEEE PESC 2008, 15-19 June 2008, pp . 2743 2749. [6] Poh Chiang Loh, , D. Mahinda Vilathgamuwa, , Yue Sen Lai, Geok Tin Chua, and Yunwei Li, Pulse - Width Modulation of Z source Inverters IEEE Transactions on Power Electronics, Vol. 20, No. 6, November 2005. [7] R. Strzelecki, M. Adamowicz, D. Wojciechowski, Buck-Boost Inverters with Symmetrical Passive Four-terminal Networks, in Proc. of 5th Int. ConferenceWorkshop CPE07, Gdansk, Poland, 2007 ,
Dr.A.Nirmalkumar completed his graduation and post graduation in Electrical Engg from Calicut and Kerala University in 1972 &1976 respectively. Completed his Doctorate from Bharathiar University in 1992. His area of specialization includes Power converters for renewable energy application and drives. He has more than 30 years of teaching experience. He is guiding at present 20 research scholars. He is the recipient of Institution of Engineers Gold Medal for the year 1989. He has many publications in national and international journals to his credit
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Fault Detection and Diagnosis for CLBs and Interconnect Resources in FPGA
MAYA T GOVIND
ME-APPLIED ELECTRONICS(PG)
Dr.MCET, POLLACHI
mayatgovind37@yahoo.com
Mr. S.THIRUVENKADAM , M.E., (Ph.D) ASSISTANT PROFESSOR(SS) , DEPT. OF EEE Dr.MCET, POLLACHI sthiruvenkadam@drmcet.ac.in is configured, or programmed, with a configuration bit stream, that determines which logic and routing resources are used, and in what manner. Fault detection is defined as the process of finding out the faults, whether any faults is present or not. After the detection of faults the diagnosis process taking place. Here the identification of the fault that detected above is done. In this Built-in-Self Test design technique is used for the designing of test process. The BIST, which allows the machine to test itself, no external device is needed. This paper thus presents a built-in self-test structure to effectively detect and diagnose faults on both interconnect resources and CLBs in the FPGA.
Abstract BIST(Built In Self Test) is a design technique that allows a circuit to test itself. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production. The use of Field-Programmable Gate Arrays (FPGAs) to implement complex logic functions in digital applications has become increasingly common. FPGAs are regular structures of logic modules that communicate through an interconnected architecture of lines and switches. The logic modules and the interconnect structures are programmed to select a particular function of each logic module and specific interconnect paths to realize the global function of the FPGA. This proposed work presents a built-in self-test design for fault detection and fault diagnosis of field-programmable gate arrays. The proposed FPGA-BIST structure can test both the interconnect resources [wire channels and Programmable Switches (PSs)] and lookup tables (LUTs) in the Configurable Logic Blocks (CLBs). The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults in LUTs.
II.
RELATED WORK
A. SRAM-Based Architecture SRAM-based FPGAs are of special interest due to their compatibility with mainstream integrated circuit fabrication technology, as well as because of their wide use in practical applications. The SRAM-based FPGA (see Fig. 1) consists of an array of n n CLBs and local/global interconnect resources[2]. The CLBs can be programmed with configuration cell data to generate logical functions. The set of all configuration cell data makes up an FPGA configuration. The basic internal architecture of a CLB is made up of lookup tables, multiplexers and D-type flipflops.The local interconnects are associated with CLBs, including wire segments and connecting blocks. Note that a connecting block contains some Programmable-Interconnect-Point PSs (PIPPSs) and Multiplexer PSs (MUX-PSs) to bring signals into and out of CLBs. On the other hand, wire segments and Programmable Cross-Point PSs (PCP-PSs) within the Switch Matrix (SM) in global interconnects form horizontal and vertical routing channels that connect signals between CLBs. The inputoutput signals can be transmitted into or out of the FPGA using the InputOutput Blocks (IOBs). In this the CLBs consist of look up tables, D flip flops and multiplexers. In the look up tables, the datas are stored in the form of 0s and 1s. So there is a chance of occurring in the storage of data. These types of faults are called stuck-at-0 and stuck-at-1 fault. The first on-line Built-In Self-Test and BISTbased diagnosis of programmable logic resources in Field Programmable Gate Arrays,see in[3].
Index Terms Built-in self-test, configurable logic block , fault coverage, fault diagnosis, field-programmable gate array.
I. INTRODUCTION
An application-independent FPGA is one whose configuration may change several times throughout its lifetime[1]. Since the customers designs are not known a priori, all resources must be guaranteed to be defect-free by the manufacturer. An FPGA contains both configurable logic block and routing resources. The basic internal architecture of a CLB is made up of three components: lookup tables, multiplexers (MUXs) and D-type flipflops (DFFs). Blocks are interconnected by the global/local routing resources, or interconnection network: connecting blocks and switch matrice. A switch matrix (or programmable multiplexer) is made up primarily of PIPs and MUXs. A Programmable switches consist of a pass transistor controlled by an associated memory cell that determines whether the transistor is on (conducting) or off (non-conducting). Finally, an FPGA
.
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Fig. 1. SRAM-based FPGA architecture
III.
DESIGNING
FPGA, better fault coverage can be obtained. Four CLBs are tested at a time, so the time required to complete the test is minimum. In addition to all these it has easier customer support also.
A. BIST design for FPGA There exist a number of fault detection schemes based on the error detecting codes, see [4] and [5] for the basic parity based schemes. Although BIST techniques in general are associated with high performance, they are also associated with high area overhead incurred by on-chip test hardware[6]. However, the BIST overhead is not an issue for FPGA BIST because the test hardware is easily reconfigured by inserting and removing Test Pattern Generators (TPGs) and ORAs(Output Response Analyzers). This is particularly important for the testing of FPGAs. The testing strategy of the proposed FPGA BIST structure is to configure groups of ten CLBs into a test block, as illustrated in Fig. 2. In each test block, four CLBs are configured as a TPG to generate the addresses for test patterns. Additionally, two CLBs are configured as an ORA for comparison with each output of the block under test (BUT) to observe the test results. The global/local interconnect resources and CLBs in a BUT, which are configured by four CLBs in a test block, are then sequentially tested. To guarantee the testing of all global/local interconnect resources and CLBs, the FPGA has to be reconfigured to shift the test blocks for testing. A generic built-in self-test strategy for devices implementing symmetric encryption algorithms are also present,see in[7]. Engineers are mainly going for BIST due to its advantages compared to other methods. The BIST has low cost, because it doesnt need any external devices for its operation. Due to large number of reconfiguration of
Fig. 2. BIST design for FPGA
B. Fault Models The aim of this paper is to design a BIST structure for both CLB and interconnect resource testing in SRAM based
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major groups, namely, open/short, stuck-on/off,stuck-at-0/1
FPGAs. The faults in this paper can be categorized into four
Fig. 3. Fault models. (a) Stuck-on/off faults in the local interconnects (b) Open/short faults in the global interconnects. (c) Stuck-at-0/1 faults on a RAM cell in an LUT. (d) Interconnect delay fault in a PUT.
interconnect resource and CLB testing are the same and the TPG and ORA of the proposed and interconnect delay faults. Fig. 3 illustrates all the fault models. The stuck-on/off faults appear in the pass transistor of PIP-PSs or MUX-PSs in local interconnects, while open/short faults occur on PCP-PSs or wire segments in global interconnects. Significantly, the delay fault is presented with a Path Under Test (PUT). On the other hand, the stuck-at-0/1 faults can be found in the LUTs of CLBs. Note that it is assumed that IOBs were previously tested. This assumption is proper since the IOBs can be tested by the boundary scan. Fig. 3(a) shows cases of PIP-PSs and MUX-PSs with stuck-on/off faults in the local interconnects. Note that a stuck-on/off fault causes the pass transistor in PIP-PSs or MUX-PSs to be permanently on/off, regardless of the value of the SRAM cell controlling the pass transistor in PIP-PSs or MUX-PSs. An open fault in the global interconnect is a disconnection of any wires, while a short fault indicates a bridging between two wires. Fig. 3(b) illustrates cases of wire open/short faults. Furthermore, Fig. 3(b) shows cases of PCP-PS open/short faults that occur when there is a stuck-off fault and a stuckon fault in the PIP-PS of the connectable and nonconnectable directions of wire segments, respectively. Moreover, since the TC(Test Configuration)s for
BIST design are built by using the LUTs, the faults in a CLB only consider the stuck-at-0/1 faults on every RAM cell in LUTs [see Fig. 3(c)]. In other words, for an LUT, the fault can occur in any one of the memory cells, making it incapable of storing the correct logic value (an LUT has a single-bit output, and therefore, this value is either 0 or 1). Thus, the stuck-at-1 or the stuck-at-0 fault may occur at a memory cell. Note that there is no need to separately consider the stuck-at fault model in interconnects, since these faults can be modeled as short circuits to power supply and ground lines. On the other hand, by setting the clock period to the specification time and generating a transition to go through the PUT, we can be determine whether the PUT is fault free or not. Fig. 3(d) shows an example of testing a PUT. If the two DFFs initially store logic 0 and generate a rising-transition propagation from A to B, then logic 1 in DFF2 can be obtained in the fault-free situation. Otherwise, the logic value of DFF2 will remain 0 after a specified time if the PUT is faulty. The faults in FPGA are classified in to two types, permanent faults and temporary faults. The faults describe above are coming under the permanent fault category. The
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the output and finding out whether the fault is present or not. If fault is present, then it pass the output to the fault pass circuit. It consist of a fault dictionary, it compares the present output with the original output and diagnose the fault.
temporary faults are occurring due to power supply variation, loose connection and defective equipment. IV.
RESULT
A. Simulation In Very Large Scale Integrated Circuit(VLSI) the two programming languages used are Very high speed Hardware Description Language(VHDL) and verilog HDL. Here the programs were written in VHDL. VHDL is a very large language and only a small subset of it is suitable for logic synthesis. It is a programming language like C or Java with added features specific to describing the behaviour of a hardware system. As shown Figure 4, VHDL can be used todescribe digital hardware in the same way as HTML describes a web page.
Fig. 5. Schema of a BIST structure in a test block. Fig.4. VHDL
B. Fault Detection And Diagnosis To effectively achieve the fault detection and diagnosis, a BIST controller is required to control the test and diagnosis processes in FPGAs. According to the proposed FPGA BIST structure(see Fig. 2), specifically, the self-tester contains a TPG that applies pseudo exhaustive test patterns to two identical CLBs. The outputs of the test CLBs are compared by an ORA, which latches and reports mismatches as test failures. The signal start/reset is provided to initiate the self-test sequence and to reset the TPG and ORA functions. It should be noted that the TPG and ORA can be easily realized by the CLBs (see Fig. 1); however, a faulty CLB in a TPG or an ORA may not produce an error if its fault does not affect the operation of the TPG or ORA. Based on the self-test processes, the CLBs in FPGA can be checked offline to confirm whether the elements in the CLBs are fault free or not. After the self-test processes and according to the proposed FPGA BIST structure in Fig. 2, a BIST scheme for a test block (see Fig. 2) is shown in Fig. 5 to detect and diagnose the faults on both interconnect resources and LUTs in CLBs online. The testing process is performed by configuring the TPG, ORA, and BUT in each test block. Additionally, the TPG and ORA of the proposed FPGA-BIST structure are designed using the existing CLBs to reduce the extra area and test cost needed. The TPG in Fig. 5 is an address generator, which consists of eight MUXs, eight LUTs, and eight DFFs to continuously generate the addresses (015) in the LUTs to produce the corresponding test patterns. The first part will produce the test patterns, the generated test patterns will act as the input to the block under test and the output from the block under test will pass to the output response analyzer. The output response analyzer will check
In each MUX, it consist of two inputs, one selection line and one output. According to the selection line the output will be varying. The input for the look up table is the output from the MUX, each four bit length. The output from the look up table is named as C1-C8. With respect to the address, ie input to the LUTs, the output value will also change. The output of the LUT is given to the DFF. according to the clock value,the flip flop will produce the output. So at the output of the flip flop we will get the test patterns. These patterns are given to the block under test. In figure5, one of the wire is configure to test the open faultin global inter connects. Next two wires are designed two wires are designed to detect the stuck-on/off fault. The fourth and fifth wires are designed to detect the stuck-at-0/1 fault. Finally the sixth wire is designad to detect the short fault. The simulation result is shown in figure6.
Fig.6 Simulation output
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Here the programming is made such that each line shows the fault.
V. CONCLUSION A new BIST approach for fault detection and fault diagnosis of SRAM-based FPGAs has been proposed in this paper. The proposed FPGA-BIST structure has high fault coverage on the modeled interconnect and CLB faults, including short/open and delay faults in wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults in LUTs. The programming were done in VHDL and simulated using Modelsim software. Comparisons with previous works have also shown that the proposed FPGA-BIST structure possesses the ability to simultaneously detect and diagnose faults on both interconnect resources and CLBs. The simulation result for the fault detection and diagnosis were obtained. IV. REFERENCE
[1] Sudheer Vemula, Student Member, IEEE, and Charles Stroud, Fellow, IEEE, Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs, from Proc. IEEE Southeastern Symp. on System Theory, pp. 534-538, 2006 [2] Miron Abramovici, Fellow, IEEE, and Charles E. Stroud, Senior Member, IEEE, BIST-Based Test and Diagnosis of FPGA Logic Blocks, Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 9, No. 1, February 2001 [3] Miron Abramovici, Fellow, IEEE, Charles E. Stroud, Senior Member, IEEE, John M. Emmert, Senior Member, IEEE, On-Line BIST and BIST-Based Diagnosis of FPGA Logic Blocks, from IEEE Trans. on VLSI Systems, Vol. 12, No. 12, pp. 1284-1294, 2004. [4] Mehran Mozaffari-Kermani, Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard,IEEE Trans.computers ., vol. 59, no. 5, May,2010. [5] Mehdi B. Tahoori, High Resolution Application Specific Fault Diagnosis of FPGAs IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, Mar.07,2010 [6] Charles Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici BIST-Based Diagnosis of FPGA Interconnect, Proceedings of IEEE International Test Conference, pp. 618-627, 2002 [7] Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, and Bruno Rouzeyre, Self-Test Techniques for Crypto-Devices, IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 329333, Feb.2010
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An Integrated Four Port DC/DC Soft Switching Boost Converter with SARC for Renewable Energy Applications
N.Dhivya Devi1 , R.Radika2,J.Baskar3 1.PG Scholar, 2. Assistant Professor, 3. Professor Adhiparasakthi Engineering College Department of Electrical and Electronics Engineering Melmaruvathur.
AbstractThis paper proposes a new converter topology that interfaces four ports: two sources, one bi-directional storage port and one isolated load port. In order to improve the efficiency of energy conversion, a sot switching boost converter using a simple auxiliary resonant circuit(SARC) which is composed of an auxiliary switch, a diode, a resonant inductor and a resonant capacitor is adopted. The conventional boost converter decreases the efficiency because of hard switching which generate losses when the switches are turned ON and turned OFF. But all the switches in proposed system perform zero current switching by resonant inductor at turn-ON and zero voltage switching by resonant capacitor at turn-OFF. This switching pattern reduces the switching loss, voltage and current stress of the switching device. The proposed topology reduces the losses and cost for renewable energy power harvesting systems. Index TermsAuxiliary resonant circuit, photovoltaic (PV), soft-switching boost converter, zero-current switching (ZCS),zero-voltage switching (ZVS).
But, due to the advantages like low cost and compact structure, multiport converters are reported to be designed for various applications. A soft-switching boost converter uses a simple auxiliary resonant circuit, which is composed of an auxiliary switch, a diode, a resonant inductor and a resonant capacitor All switches in the adopted circuit perform zero-current switching by the resonant inductor at turn-on, and zerovoltage switching by the resonant capacitor at turn-off. This switching pattern can reduce the switching losses, voltage and current stress of the switching device[5]. II. RENEWABLE SOURCES Most of the energy used in industry depended on fossil fuel. But these days, because of fuel fossil exhaustion, which is due to limited reserves and environmental problems, the development and demand for renewable energy has increased. Fuel cells, Water, wind, and photovoltaic (PV) energy are all renewable Energy sources. As the world is concerned with fossil-fuel exhaustion and environmental problems caused by conventional power generation, renewable energy sources, particularly solar and wind energy, have become very popular and demanding. Photovoltaic (PV) sources are used today in many applications because they have the advantages of being maintenance and pollution free. Solar-electric-energy demand has grown consistently by 20%25% per annum over the past 20 years, which is mainly due to the decreasing costs and prices. This decline has been driven by the following: 1. An increasing efficiency of solar cells; 2. Manufacturing-technology improvements; and 3. Economies of scale. A. Solar Cell Solar cells (as the name implies) are designed to convert (at least a portion of) available light into electrical energy. They
I.
INTRODUCTION
As interest in renewable energy systems with various sources becomes greater than before, there is a supreme need for integrated power converters that are capable of interfacing, and concurrently, controlling several power terminals with low cost and compact structure. Meanwhile, due to the intermittent nature of renewable sources, a battery backup is normally required when the ac mains is not available. This paper proposes a new four-port-integrated dc/dc topology, which is suitable for various renewable energy harvesting applications. It can achieve maximum power-point tracking (MPPT) for both PV and wind power simultaneously or individually, while maintaining a regulated output voltage. Compared to the effort spent on the traditional two-port converter, less work has been done on the multiport converter. Corresponding Author: - N. Dhivya Devi is with Electrical and Electronics Engineering department of Adhiparasakthi Engineering college, Melmaruvathur. email id: dhivyadevi.n@gmail.com.
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windmill. If the mechanical energy is not used directly but is converted into electricity, machine is called a wind generator. According to the aerodynamic characteristics of wind turbine, the output mechanical power is given by Pm = cp (, ) A/2 (Vwind)3 (3) where Pm Mechanical output power of the turbine (W) cp Performance coefficient of the turbine Air density (kg/m3) A Turbine swept area (m2) Vwind Wind speed (m/s)
do this without the use of either chemical reactions or moving parts. A solar cell is a kind of p-n junction semiconductor device. It converts light energy into electrical energy. Generally, as shown in Fig.2, the equivalent circuit of the solar cell is composed of the internal serial resistance (Rs) and the shunt resistance (Rsh) of the diode. The output characteristics of the solar cell depend on the irradiance and the operating temperature of the cell[9].
Fig.1. Equivalent Circuit for Solar Cell
Tip speed ratio of the rotor blade tip speed to wind speed Blade pitch angle (deg) Equation (3) can be normalized. In the per unit (pu) system we have: Pm_pu = Kp Cp_pu (Vwind_pu)3 where
Fig.2. I-V Characteristics for Solar Cell
(4)
Is = Iph Isat [exp(q (Vs + IsRs)/AKT) 1] (Vs + IsRs)/Rsh (1) In (1.1), it is assumed that Rs equals zero and that Rsh equals infinity; thus, the equation can be simplified as Is = Iph Isat[exp( qVs /AKT) 1] (2)
Pm_pu Power in pu of nominal power for particular values of and A cp_pu Performance coefficient in pu of the maximum value of cp
vwind_ Wind speed in pu of the base wind speed. The base wind speed is the mean value of the expected wind speed in m/s. kp Power gain for cp_pu=1 pu and vwind_pu=1 pu, kp is less than or equal to 1
Irradiance and operating temperature are important factors influencing the solar cell characteristics. Fig. 1.2 shows the I V curves of the PV module. If irradiance increases, the fluctuation of the open-circuit voltage is very little. However, the short circuit current has sharp fluctuations with respect to irradiance. However, for a rising operating temperature, the variation of the short-circuit current is decreased, and the open-circuit voltage is decreased in a nonlinear fashion. As shown in Fig. 1.2, the output-voltage range of the PV module varies. Owing to this characteristic, the adopted converter must be designed for soft switching based on the output-voltage range of the PV module. B. Wind Turbine A wind turbine is an engine that takes the kinetic energy of wind and converts it into mechanical energy. If energy is used directly by machinery, we usually call this machine a
A generic equation is used to model cp(,). This equation, based on the modeling turbine characteristics is
(5) The coefficients c1 to c6 are: c1 = 0.5176, c2 = 116, c3 = 0.4, c4 = 5, c5 = 21 and c6 = 0.0068. The cp- characteristics, for different values of the pitch angle , are illustrated below. The maximum value of cp (cpmax = 0.48) is achieved for = 0 degree and for = 8.1. This particular value of is defined as the nominal value (_nom).The figure below shows a sketch a
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switch. This paper proposes the soft-switching boost converter applied to an auxiliary resonant circuit for a PV/wind/battery generation system. It has better efficiency than a conventional boost converter. Moreover, this converter boosts the lower output voltage of the solar cell /wind to the useful voltage for the load. The adopted converter has a simple auxiliary resonant circuit (SARC). Through this circuit, all of the switching devices perform soft-switching under zero-voltage and zero-current conditions. Therefore, the periodic losses generated at turn-on and turn-off can be decreased.
how the power output from a wind turbine varies with steady wind speed. At very low wind speeds, there is insufficient torque exerted by the wind on the turbine blades to make them rotate. However, as the speed increases, the wind turbine will begin to rotate and generate electrical power. The speed at which the turbine first starts to rotate is called the cut-in speed and is typically between 3 and 4 meters/sec.
Fig.4. Circuit diagram of the soft-switching boost converter Fig.3. Power-Wind Speed Characteristics
As the wind speed rises above the cut-in speed, the level of electrical output power rises rapidly as shown. However, typically somewhere between 12 and 17 meters per second, the power output reaches the limit that the electrical generator is capable of. This limit to the generator output is called the rated power output and the wind speed at which it is reached is called the rated output wind speed. At higher wind speeds, the design of the turbine is arranged to limit the power to this maximum level and there is no further rise in the output power. How this is done varies from design to design but typically with large turbines, it is done by adjusting the blade angles so as to keep the power at the constant level. As the speed increases above the rate output wind speed, the forces on the turbine structure continue to rise and, at some point, there is a risk of damage to the rotor. As a result, a braking system is employed to bring the rotor to a standstill. This is called the cut-out speed and is usually around 25 meters per second. III. SOFT SWITCHING BOOST CONVERTER
The auxiliary circuit is composed of an auxiliary switch (S2),a resonant capacitor (Cr), a resonant inductor (Lr), and twodiodes (D1 and D2).Shown in Fig. 4, the operational principle of this converter can be divided into six intervals. For a simple analysis of each interval of this converter, the following assumptions are made[10]. 1) All switching devices and passive elements are ideal. 2) The parasitic components of all switching devices and elements are negligible. 3) The input voltage (Vs) is in the range of 150230 V. 4) This converter operates the continuous conduction mode at all intervals. A. Operation of Mode 1
Fig.5. Mode 1 operation
Recently, switch-mode power supplies has become smaller and lighter because the switching frequency has increased. However, as the switching frequency has increased, the periodic losses at turn-on/off have also increased. As a result, this loss brings increasing loss of whole system. Therefore, to reduce these switching losses, a soft-switching method is proposed, which involves an added auxiliary circuit, instead of a conventional hard-switching converter. However the auxiliary circuit for resonance increases the complexity and cost. For some resonant converter with auxiliary switch, main switch achieves soft-switching but auxiliary switch performs hard switching. Thus, these converters cannot improve the whole system efficiency owing to switching loss of auxiliary
Switches S1 and S2 are both in the OFF state, the current cannot flow through switches S1 and S2, and the accumulated energy of the main inductor is transferred to the load (Fig.3.7).In this interval, the main inductor current decreases linearly. During this time, the current does not flow to the resonant inductor, and the resonant capacitor has charged as output voltage. After two of the switches have been turned on, interval 1 is over. These conditions are as follows: V L (t) =Vs Vo I L (t) =I L (t0) [(Vo Vs ) L]t I Do (t) = I L (t) (6) (7) (8)
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(9) (10) vCr (t) =Vo cos rt vCr (t2) =Vo vCr (t3) = 0 r = 1 /LrCr Zr = Lr /Cr D. Operation of Mode 4 (18) (19) (20)
I Lr (t) =0 vcr (t) =Vo. B. Operation of Mode 2
After turning on switches S1 and S2, the current flows to the resonant inductor. At that time, two of the switches are turned on under zero-current condition. This is known as zero-current switching (ZCS). Because the main and auxiliary switches implement ZCS, this converter has lower switch loss than the conventional hard switching converter. As the resonant current rises linearly, the load current gradually decreases. At t2, the main inductor current equals the resonant inductor current, and the output diode current is zero. When the resonant capacitor voltage equals Vo, the output diode is turned off, and interval 2 is over. I Lr (t1) =0 v Lr (t) = Vo I Lr (t) = (Vo Lr)t I L (t) =I L (t1) [(Vo Vs ) L]t I L(t2) =iLr (t2) I Do (t2) =0. C. Operation of Mode 3 (11) (12) (13) (14) (15)
After the resonant period in interval 3, when the voltage of the resonant capacitor equals zero, interval 4 begins. In this interval, the freewheeling diodes of D1 and D2 are turned on, and the current of the resonant inductor is the maximum value. The resonant inductor current flows to the freewheeling diodes S1LrD2 and S2LrD1 along the freewheeling path. iLr (t) =iL(t) + iD1 (t) + iD2 (t) iLr (t3) =iLr (t4) = ILr,max. (21) (22)
During this time, the main inductor voltage equals the input voltage, and the current accumulating energy increases linearly. vL(t) =Vs iL(t) =Imin + (Vs / L)t. E. Operation of Mode 5 (23) (24)
The current that flowed to the load through output diode Do no longer flows, since t2 and the resonant capacitor Cr, and the resonant inductor Lr start a resonance. The current flowing to the resonant inductor is a combination of the main inductor current and the resonant capacitor current. The amount of resonant current is expressed as (17 ). iL(t) Imin iLr (t) =Imin + Vo Zr sin r. (16) (17)
In interval 5, all of switches are turned off under the zero voltage condition by the resonant capacitor. During this interval, the initial conditions of the resonant inductor current and resonant capacitor voltage are as follows: iLr (t4) =ILr,max vCr (t4) =0. (25) (26)
During this resonant period, the resonant capacitor Cr is discharged from Vo to zero. This is expressed as (18). Resonant frequency and impedance are given by (19) and (20). When the voltage of the resonant capacitor equals zero, the interval 3 is over.
When all of the switches are turned off, the resonant capacitor Cr is charged to the output voltage by two of the inductor currents. Until the resonant capacitor has been charged to Vo, the output diode is in the OFF state. iL(t) Imax (27)
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(28) (29) (30)
iLr (t) =Imax (Imax + ILr,max) cos rt vCr (t) =Zr(Imax + ILr,max) sinrt vCr (t5) =Vo. F. Operation of Mode 6
Interval 6 begins when the resonant capacitor equals the output voltage, and the output diode is turned on under the zero voltage condition. During this interval, the main inductor current iL and the resonant inductor current iLr flow to the output through the output diode Do. iDo (t) =iL(t) + iLr (t) ILr (t5) =(Imax + ILr,max) cos r(t5 t4) Imax vCr (t) =Vo. (31) (32) (33)
Fig.11 Proposed circuit
At that time, two of the inductor currents are linearly decreased, and the energy of the resonant inductor is completely transferred to the load. Then, the interval 6 is over. iL(t) =Imax [(Vo Vs) /Lr]t iLr (t) =iLr (t6) (Vo / Lr)t iLr (t6) =0. IV. SIMULATION RESULTS In the proposed system there are three inputs, they are solar, wind and battery. These inputs are given to the MPPT. The MPPT tracks the maximum power of the input and it is given to the soft switching boost converter. Then the output from converter is fed to the full bridge inverter and to the load. The simulation of the proposed circuit and the outputs from the solar cell, wind turbine are shown in figures. (34) (35) (36) Voltage(V)
Fig.12. Constant DC Voltage Curve
Fig.13. Wind Turbine Circuit
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Voltage(v)
Fig.16. Output Wave for Solar Input
Time(ms)
Voltage(v)
Fig.17. Output Wave for Wind Input
Time(ms)
Speed(m/s)
Fig.14. Power-Speed Characteristics
Voltage(v)
Fig.18. Output Wave for Battery Input
Time(ms) IV. CONCLUSION
Time(ms)
Fig.15. Output Wave from Boost Converter
In this paper has presented a novel dc/dc converter topology capable of interfacing four dc power ports: two input source ports, a bidirectional storage port, and an isolated loading port. This four-port converter is suitable for renewable energy systems, where the energy storage is required while allowing tight load regulation. It is suitable for low-power applications since based on the half-bridge topology, while the multiport converter based on the full-bridge topology maybe suitable for high-power applications. For the hybrid PV wind system, the proposed control structure is able to achieve maximum power harvesting for PV and/or wind power sources, meanwhile maintaining a regulated output voltage. In this paper, we proposed a soft-switching boost converter, which involved an added SARC in the conventional boost converter. This soft-switching boost converter is easy to control because the two switches are controlled by the same PWM signal. All of the switching devices in this converter achieved ZCS and ZVS by the resonant inductor and capacitor at turn/off. Therefore, the switching losses were reduced dramatically. This paper has analyzed the operational principles of the adopted converter and applied them to the P&O algorithm, which is a kind of MPPT method. Moreover, this converter was verified by the simulation results.
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[4] Y. Liu and Y. M. Chen, A systematic approach to synthesizing multi input DCDC converters, IEEE Trans. Power Electron., vol. 24, no. 2, pp. 116127, Jan. 2009. [5] Sang-Hoon Park,Gil-Ro Cha ,Yong-Chae Jung and Chung-Yuen Won, (2010)Design and Application for PV Generation System Using a SoftSwitching Boost Converter With SARC,IEEE Trans.Power Electron.,vol.57,no.2,pp.515-522. [6] Z. Qian, O. Abdel-Rahman, J. Reese, H. Al-Atrash, and I. Batarseh, (2009)Dynamic analysis of three-port DC/DC converter for space applications, in Proc. IEEE Appl. Power Electron. Conf., pp. 2834. [7] Z. Qian, O. Abdel-Rahman, H. Al-trash, and I. Batarseh,(2010) Modeling and control of three-port DC/DC converter interface for satellite applications, IEEE Trans. Power Electron., vol. 25, no. 3, pp. 637649. [8] Zhijun Qian, Osama Abdel- Rahman and Issa Batarseh,(2010)An Integrated Four-Port DC/DC Converter for Renewable Energy Applications, IEEE Trans. Power Electron. vol.25, no.7, pp.1877-1887. [9] F. Liu, S. Duan, F. Liu, and Y. Kang, A variable step size INC MPPT method for PV system, IEEE Trans. Ind. Electron., vol. 55, no.7,pp.26222628,Jul.2008. [10] G.-R. Cha, S.-H. Park, C.-Y. Won, Y.-C. Jung, and S.-H. Song, High efficiency soft switching boost converter for photovoltaic system, in proc. 13th EPE-PEMC, Sep. 13, 2008, pp. 383397.
V. ACKNOWLEDGEMENT The work described in this paper was substantially supported by the management of Adhiparasakthi Engineering College and faculty members of Electrical and Electronics Engineering Department. VI. REFERENCES
[1] R. Gules, J. De Pellegrin Pacheco, H. L. Hey, and J. Rnhoff,(2008) A maximum power point tracking system with parallel connection for PV stand alone applications, IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 26742683. [2] H. Krishnaswami and N. Mohan, (2009)Three-port series-resonant DC DC converter to interface renewable energy sources with bidirectional load and energy storage ports, IEEE Trans. Power Electron., vol. 24, no. 910, pp. 22892297. [3] D. Liu and H. Li, (2006)A ZVS bi-directional DC-DC converter for multiple energy storage elements, IEEE Trans. Power Electron., vol. 21, no. 5,pp. 15131517.
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Solar Air Conditioner Using Nitrogen Gas as Coolant

Amrutharaj.M, Camelia Sengupta, Reshma Maria George
Info Institute of Engineering, Coimbatore
Abstract- The solar energy is a non-renewable source of energy. Solar air conditioners are an area of solar energy that is ripe for future development. In the current solar air conditioning, Freon gas, which is dangerous to the atmosphere, is used as the coolant. But, the solar air conditioner we propose use the nitrogen gas as coolant. It is providing an eco-friendly approach in the air conditioning field. Solar panels are installed to trap the solar energy and it is used to power the air conditioning unit.
I. INTRODUCTION
cooling process of a typical air conditioning system which in turn reduces the electrical consumption required to run the compressor. It is similar to a regular A/C in that the refrigeration takes place by evaporating liquid with a very low boiling point. In both cases, when a liquid evaporates or boils, it takes some heat away with it, and can continue to do so either until the liquid is all boiled, or until everything has become so cold that the sub-zero boiling point has been reached. The difference between the two is how the gas is changed back into a liquid so that it may be used again. A regular air conditioning system uses a compressor to increase the pressure on the gas, forcing it to become a liquid again through the use of the condenser coil. The change of state of the refrigerant, starts to take place approximately 2/3rds of the way down the condenser. This Solar Air Conditioning System uses a different method. It uses the solar heat from the sun to superheat the refrigerant which enables the refrigerant to begin changing state at the top 2/3rds of the condenser coil. By using this method it reduces the superheat of compression required to achieve the cooling process in the conventional cooling systems as well as utilizing more of the condenser cooling face of the coil. The conventional air conditioning system is only able to change a portion of the gas into a liquid state so as when the refrigerant enters into the metering device it is a saturated vapor. The Solar A/C process allows more of the refrigerant to change state back into a liquid faster as well as allowing the transformation of more liquid into the metering device. If a normal air conditioner of 1 Ton is used for average 8 hours per day, its input power is 1500 W, the electricity consumption would be 12 KWH/ day. The solar air conditioner would use only 900 W or about 40% of electricity which means 900W x 8 = 7.2 KWH / day which saves 12-7.2= 4.8 KWH / day and the total saving amount is 4.830 = 144 KWH per month. Suppose the price of electricity is Rs 5 /KWH (Rs 10 kwh on diesel generator & Rs 15 / Kwh on solar/nuclear), then the total saved money would be Rs 720 in one month, typically this gadget can pay for itself in around 8 year.
SPECIFICATIONS:
The solar air conditioning refers to any air conditioning system that uses solar power. As we just mentioned, the internal components of an air conditioning unit powered by the sun arent all that different than one powered by electric. However, solar energy is what powers the solar air conditioner as opposed to electrical power provided by your local power company. The summer months are when the sun seems to shine the most and is also the time when the temperatures are the highest. Solar panels or tubes soak up the sunlight that shines down during the day. That energy heats up the refrigerant, which delivers a high pressure gas to the condenser, then to the evaporator, and then to the compressor. The heat from the air has been removed and is then distributed as cool air into your home. Any power that hasnt been used during the day is stored in the backup batteries and used to cool your home during the night. There are various types of air conditioning such as photovoltaic solar cooling, passive solar cooling, solar desiccant air conditioning and solar thermal solar cooling. In photovoltaic solar cooling solar panels are used to generate energy from sunlight, to run the air conditioning system. Passive solar cooling uses the design of a building to naturally heat and cool using passive solar energy. Solar desiccant Air conditioning is an ingenious new way of cooling the air by using a material such as salt that will dry out the air, thus lowering the temperature. Solar Thermal Solar Cooling is often used in larger buildings, and uses solar energy to collect heat from the sun which then operates chillers which cool the air.
II. THE WORKING PRINCIPLE
This Air Conditioning system is a system that utilizes the sun as a heat source to assist the energy needed to drive the
Capacity Cooling: 12000 Btu/h OR 3500 W Heating: 13000 Btu/h OR 3800 W
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Solar A/C 1 Ton, Split AC Initial cost Rs 75,000 ( Including Taxes & Installation) ; Running Cost if used for 8 hours for 30 days Rs 1,200 / month, Rs 14,400 / year or Rs 2,88,000 for 20 years.Total : 75,000 + 2,88,000 = Rs 3,63,000 == Rs 3.5 Lakhs approx..(maintenance cost not included) These savings are not really very impressive because you get coal electricity at a high subsidized cost by nature and government from coal at Rs 5 / Kwh, however nuclear or solar electricity would have been at Rs 15 / Kwh at which the savings would have been better.
COST COMPARISON WITH SOLAR PANELS
Power Input power Cooling: 920 W Heating: 930 W Noise Indoor: 40 db (A) Outdoor: 50 db (A) Air Circulation: 720 m/h Suitable Area: 15~25 m EER: 3.8 w/w Indoor Unit Size: 1010 x 325 x200 mm; Weight 15 Kg Shipping: 1065 x 375 x 255 mm; Weight 18.5 Kg Outdoor Unit Net: 930 x 330 x 600 mm; Weight 51 Kg Shipping: 995 x 390 x 650 mm; Weight 56 Kg Solar Panel Collector Dimensions: 1000 x 550 x 87 mm Weight: 14 Kgs
INSTALLATION:
To save the 5 Kwh this system manages if were to be generated using solar panels would mean a min 1000W of solar panels the cost of which itself would have been more than Rs 1.5 lakhs. Batteries, Inverters, charge controllers could add more.
SOLAR AC USING NITROGEN GAS AS COOLANT
There are two tanks of dimensions 50x100. One tank contains nitrogen gas which is the coolant. The nitrogen has the ability to cool twice as that of the usual gas used. There are two sets of tubes. Through one set of tube the hot air from the room is being taken in. The coolant passes through the other set of coil. The hot air gets cooled and it is passed to the second tank through copper tube. There is a non-return valve. The pressure gauge is provided to indicate the difference in pressure. The process is repeated again and the nitrogen gas is reused.
We suggest you find your local technician to assistant you in installation. The installation method of solar air conditioner is similar to normal air conditioner. The standard distance between outdoor unit and indoor unit is 10-15 meters. The maximum is up to 30 meters. The standard distance between outdoor unit and solar panel is 1.5-3 meters. The panel does not need to be installed directly facing the sun. The detailed installation guide will be provided.
LIFE OF SYSTEM:
Life of the solar A/C is expected to be 20 years.

LIFE CYCLE COST COMPARISON:
Normal A/C 1 Ton, Split AC Initial Cost Rs 20,000 ( Including Taxes & Installation) ; Running Costs if used for 8 hours for 30 days Rs 1,800 / month or Rs 21,600 / year or Rs 4,32,000 for 20 years.Total : 20,000 + 4,32,000 = Rs 4,42,000 == Rs 4.5 Lakhs approximately(maintenance cost not included)
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SPECIFICATION:
Tubes used for Design = Diameter 6mm and Diameter 8mm. Tank Used for Design = Dimension 50x100. Total Length of Diameter 6mm Tube = 231.00mm Total Length of Diameter 8mm Tube = 100.00mm Number of Tank used = 2
FORMULA USED:
Apply Formula: Volume of the Hollow cylinder = (r1-r2) x Length Copper tank to store liquid nitrogen Copper tubes for passing hot and cold air Temperature control circuit Battery to store the energy Nitrogen as a coolant Safety valve Non-return valve Pressure gauge Applying the formula we got the volume the total unit : = 490865.418mm = 490.86m
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We have developed a solar air conditioner using nitrogen gas as coolant. This is an eco-friendly approach in the air conditioning field, which uses solar energy in an efficient way. The nitrogen has the ability to cool twice as that of the usual gas used. This air conditioner reduces the use of electrical consumption. The solar energy is trapped by using solar panels and it is used to power the AC circuit. This approach is mainly to reduce the consumption of power and to go for an innovative methodology.
ACKNOWLEDGMENT
CONCLUSION
We express our preformed gratitude to Dr. A. NIRMAL KUMAR; Head of the Electrical and Electronics Engineering department his unique innovative plans, dynamic guidance with constant encouragement and motivation, which triggered us to great extent in completion. We are highly obliged and express our sense of gratitude to Mr. T. RAJESH M.E., Mr. A. ANICKS SALOMON, M.E, for their valuable support and help.
REFERENCES [1] Rohit Sharma, Vivek Kumar Sehgal, Nitin Adnan, Munir Khan, Ashish Sharma, Pankaj Sharma, Peltier effect based solar powered air conditioning system, Brno, Czech Republic, September 2009. [2] Al-Azzawi, A., Almuhtadi, W., Algonquin Coll. Energy saving by using newly designed automated solar powered evaporative air cooler (aspeac), Ottawa, ON, Canada, October 2009. [3] Qian Zhao, Peng Wang, Goel, L.,Optimal PV panel tilt angle based on solar radiation prediction, June 2010 [4] B H Khan, Non-conventional energy resources, McGraw-Hill companies, 2nd edition, 2009. [5] G.D Rai, Non-conventional energy sources, Khanna Publishers, 4th edition, 2008.
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ANALYSIS OF POWER CONVERTER to put power back into the grid at user USED IN WIND ENERGY SYSTEMdemands sites. Moreover, there are social
1
1
A.Edwin Isaac raj
Mr. S. Ganesan
Post graduate student in the Department of Electrical and Electronics Engineering, Mailam Engineering College, Mailam, Tamilnadu.
2
for cheaper, less polluting, safer and more reliable and sustainable energy for suppliers, The
Senior lecturer in the Department of Electrical and Electronics Engineering, Mailam Engineering College, Mailam, Tamilnadu. Email: edwinisaacraj@gmail.com,
1
ganesh_blossom@yahoo.co.in
ABSTRACT: In this paper, I am going to propose the inverter technology for power conditioning and utility interface of renewable energy sources based power generation (Wind power generation) .A comparison between the traditional(Three phase bridge inverter) and new inverter system configurations is presented (Multi level inverter and Matrix inverter). In Simulation results is shown to verify the efficacy of the inverter systems for renewable energy sources.
consumers, policy
generators DG,
and
makers.
including
integration of
renewable sources, is a Traditionally, there are two
promising solution to solve those demands. types of inverters used; commonly known as voltage source inverter (VSI) and current source inverter (CSI). Both of these inverters have limited operating range even though both are used in DG applications. To overcome the limited operating range, both these inverters need to be connected with a separate DC-DC converter stage at the front end. This enables them to operate in both buck and boost modes. This topology is commonly known as a twostage inverter. Small scale two-stage inverters have been developed for domestic DG applications with fuel cells. However, two-stage inverters are not cost effective and also controlling them is known to be cumbersome. As a solution to this problem, Z-source inverter was proposed recently. This is a single-stage inverter and it can operate in both buck and boost modes. The buck-boost characteristic is achieved due to the unique impedance network interfacing the
1. INTRODUCTION Recent trend in meeting increasing energy demand is moving towards generating power with sustainable energy resources, and most of them are renewable as they have greater advantages due to their environmentally friendly nature and their ability of on-site generation. Furthermore, reliability of service and power quality are enhanced by proximity to the customer. This concept is commonly known as distributed generation (DG) and it has gained acceptance over the years. The DG complements centralized generation by having a relatively inexpensive response to incremental increases in power demand, by preventing existing transmission and distribution capacity upgrades, by locating power where it is most desired and by having the flexibility
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inverter with the DC source. Moreover, it has better EMI properties due to the absence of the dead-time. Z SOURCE INVERTER BASED WIND ENERGY SYSTEM 2.1 Block diagram
Fig 2.5 Equivalent circuit of the Z-Source inverter viewed from the dc link 2.2 Circuit Analysis and Obtainable Output Voltage Vc1=Vc2=Vc and vL1=vL2=vL--------------(1) vL=Vc, vd=2Vc, and vi=0------------------(2) vL=V0-Vc, vd=V0 and vi=Vc-vL=2Vc-V0--------------------------(3) T=T0+T1 VL=vL =(T0.Vc+T1.(V0-Vc))/T=0,-------(4) Or
Fig 2.1 Block diagram V0))/T= B=
Vi=vi= (T0.0+T1.(2Vc-
T1 V0 =Vc------------------(5) T1 T0
1 T 1 2 0 T 1 ------------------ (6)
T1 = T1 T0
B is the boost factor resulted from the shoot-through zero state. Fig 2.4 Equivalent circuit of the Z-Source inverter viewed from the dc link when the inverter bridge is in the shoot-through zero state The peak dc link voltage
v i is the
equivalent dc link voltage of the inverter. On the other side, the output peak phase voltage from the inverter can be expressed as
v v ac M . i -----------(9) 2
Where M is the modulation index. The above equation can be expressed as

v ac M .B.
V0 ---------(10) 2
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For
the
traditional we have
V-source the well
PWM known
inverter,
relationship:
v ac M .
V0 2
Equation (10) shown that the output voltage can be stepped up and down by choosing an appropriate buck-boost factor BB, BB=B.M=(0 ). The capacitor voltage can be expressed as
T 1 0 T V . Vc1=Vc2=Vc= T0 0 1 2 T
Fig 3.1 Block diagram Description A multilevel inverter can eliminate the need for the step-up transformer and reduce the harmonics produced by the inverter. Although the multilevel inverter structure was initially introduced as a means of reducing the output waveform harmonic content, it was found that the dc bus voltage could be increased beyond the voltage rating of an individual power device by the use of a voltage clamping network consisting of diodes. A multilevel structure with more than three levels can significantly reduce the harmonic content. By using voltageclamping techniques, the system KV rating can be extended beyond the limits of an individual device. The intriguing feature of the multilevel inverter structures is their ability to scale up the kilovolt-ampere rating and also to improve the harmonic performance greatly without having to resort to PWM techniques. The key features of a multilevel structure follow:
The buck-boost factor, BB, is determined by the modulation index, M and boost factor, B. The boost factor, B can be controlled by duty cycle (ie .interval ratio) of the shoot-through zero state over the non shoot-through states of the inverter PWM. Note that the shoot-through zero state does not affect the PWM control of the inverter, because it equivalently produce the same zero voltage to the load terminal. The available shoot-through period is limited by the zero-state period that is determined by the modulation index. 3. Multilevel Inverter fed wind energy system 3.1 Block diagram
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The
output
voltage and
power increase with number of levels. Adding a voltage level involves adding a main switching device to each phase.The harmonic content decreases as the number of levels increases and filtering requirements are reduced With additional voltage levels.The voltage waveform has more free-switching angles, which can be preselected for harmonic selection. In the absence of any PWM techniques, the switching losses can be avoided. Increasing output voltage and power does not require an increase in rat individual device. Static and dynamic voltage sharing among the switching devices is built into the structure through either clamping diodes or capacitors. The switching devices do not encounter any voltage-sharing problems. For this reason, multilevel inverters can easily be applied for high-power applications such as large motor drives and utility supplies. The fundamental output voltage of the inverter is set by the dc bus voltage Vdc, which can be controlled through a variable dc link. Fig 3.3 Single leg h-bridge five level inverter Fig 3.2 Cascaded Multilevel inverter Circuit Diagram
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3.1.1 MODES OF OPERATION: S1 0 (Charging +v) +v/2 +v 0 (dischargin g +v) 0 (Charging -v) -v/2 O N O N O N O N O FF O FF S2 O FF O FF O FF O FF O N O N S3 O FF O FF O FF O FF O N O N S4 O N O N O N O N O FF O FF S5 O FF O FF O N O FF O N O FF S6 O N O FF O FF O N O FF O FF Simulation of z source inverter fed wind energy system with Filter Inverter Current without filter Chat for FFT Analysis:
Simulation of z source inverter fed wind energy system without Filter Inverter output voltage
Inverter Output Voltage
Inverter current With Filter
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Chat for FFT Analysis:
Simulation of five level inverter fed wind energy system with Filter
Simulation of five level inverter fed wind energy system with Out Filter
FFT for Current

Z-SOURCE INVERTER MULTI LEVEL INVERTER 230V 400 17.6 2.07
INPUT VOLTGAE
230
Phase to Phase Output Voltage
OUTPUT VOLTAGE THD WITHOUT FILTER THD WITH FILTER
315 25.43 4.23
CONCLUSION The Paper is enhanced with the scope of conserving conventional fuel and increase the usage of Renewable energy Output Current with the main objective of faster interface, reduced harmonics and improved power quality. Further analysis includes comparison between various inverters using mat lab 7.5 and closed loop control system
Inverter current
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REFERENCES
Proceedings of PEID-2011 INFO Institute of Engineering , Coimbatore
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A SOFT-SWITCHING CURRENT DRIVEN FULL BRIDGE PWM DC/DC CONVERTER WITH SNUBBER CIRCUIT.
P.YUVARAJ
Anna University of Technology, Coimbatore
ABSTRACT: The proposed system presents a soft switching technique to operate the PWM full bridge converters with improved switching frequency and efficiency. The converters use a simple snubber formed by two unidirectional switches and a capacitor to realize soft switching operation over a wide line and load range. The circuit complexity of the existing converters including loss of the duty cycle and undesirable conduction loss is minimized. In addition to ZVS(Zero voltage switching) mechanism used in previous converters, a ZCS(Zero current switching) condition is achieved in this system thus reducing over voltage across the rectifier. Soft switching at light load is presented which uses snubber energy that is load adaptable. More resonant energy is available only when needed at light load. The snubber energy ensures soft switching and is load adaptable. ZCS is achieved by using a resonance process with a snubber formed by a resonant inductance and a resonant capacitance. The ZCS range can be increased by decreasing the characteristic impedance of the resonant rank. Thus less resonant energy is used and the efficiency is increased by reducing the conduction loss. 1.1 POWER CONVERSION
voltage thereby saving space instead of using multiple batteries to accomplish the same thing.
Fig 1.1 Block diagram of DC-DC converter Most DC to DC converters also regulate the output voltage. Some exceptions include high-efficiency LED power sources, which are a kind of DC to DC converter that regulates the current through the LEDs, and simple charge pumps which double or triple the input voltage. The power switch was the key to practical switching regulators. Prior to the invention of the Vertical Metal Oxide Semiconductor (VMOS) power switch. The inductor's main function is to limit the current slew rate through the power switch. This action limits the otherwise high-peak current that would be limited by the switch resistance alone. The key advantage for using an inductor in switching regulators is that an inductor stores energy. This energy can be expressed in Joules as a function of the current by: E = L I .. (1) 1.1.2 SWITCHING REGULATOR A switching regulator is a circuit that uses a power switch, an inductor, and a diode to transfer energy from input to output.The basic components of the switching circuit can be rearranged to form a step-down (buck), step-up (boost), or an inverter (flyback). These designs are shown in Figures 1.1, 1.2, 1.3, and 1.4 respectively, where Figures 3 and 4 are the same except for the transformer and the diode polarity. Feedback and control circuitry can be carefully nested around these circuits to regulate the energy transfer and maintain a
1.1.1
DC-TO-DC CONVERTER
In electrical engineering, power conversion has a more specific meaning, namely converting electric power from one form to another. This could be as simple as a transformer to change the voltage of AC power but also Power conversion systems often incorporate redundancy and voltage regulation. DC to DC converters are important in portable electronic devices such as cellular phones and laptop computers, which are supplied with power from batteries primarily. Such electronic devices often contain several sub-circuits, each with its own voltage level requirement different from that supplied by the battery or an external supply (sometimes higher or lower than the supply voltage). Additionally, the battery voltage declines as its stored power is drained. Switched DC to DC converters offer a method to increase voltage from a partially lowered battery

constant output.
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Figure 1.2. Buck converter topology.
A basic boost configuration is depicted, assuming that the switch has been open for a long time and that the voltage drop across the diode is negative, the voltage across the capacitor is equal to the input voltage. When the switch closes, the input voltage, +VIN, is impressed across the inductor and the diode prevents the capacitor from discharging +VOUT to ground. Because the input voltage is DC, current through the inductor rises linearly with time at a rate proportional to V. .
Figure 1.3. Simple boost converter. Figure 1.6.Charging phase Discharge phase Figure 1.7 shows the discharge phase. When the switch opens again, the inductor current continues to flow into the rectification diode to charge the output. As the output voltage raises, the slope of the current, di/dt, though the inductor reverses. The output voltage rises until equilibrium is reached VL=Ldi/dt..(2) Figure 1.4. Inverting topology.
Figure 1.7. Discharge phase MOTIVATION OF THE WORK Figure 1.5. Transformer flyback topology. In electrical engineering, power conversion has a more specific meaning, namely converting electric power from one form to another. This could be as simple as a transformer to change the voltage of AC power, but also includes far more complex systems. The term can also refer to a class of electrical machinery that is used to convert one frequency of electrical power into another frequency. Power conversion systems often incorporate redundancy and voltage regulation. Various switching techniques are adopted but at the expense of high circuit complexity or over voltage at the rectifier. This project proposes a soft switching current driven full bridge converter with snubber circuit. It has an improved switching frequency and high efficiency. 1.3OBJECTIVE OF THE WORK
1.1.3
NECESSITY OF A SWITCHING REGULATOR
Switching regulators offer three main advantages compared to a linear regulators. First, switching efficiency can be much better than linear. Second, because less energy is lost in the transfer, smaller components and less thermal management are required. Third, the energy stored by an inductor in a switching regulator can be transformed to output voltages that can be greater than the input (boost), negative (inverter), or can even be transferred through a transformer to provide electrical isolation with respect to the input. Charge phase

All primary-side switches are operated with zerocurrent switching (ZCS) and the snubber switches are operated with zero-voltage switching. The energy used for softswitching is self-adaptable.For a given input current, the snubber capacitor is charged to the minimum required energy for ZCS of the switches. Thus, less resonant energy is used and the conduction loss can be kept minimal. The cyclical switching operation and control of the converter will be discussed. The input voltage range and load variation that ensure both output voltage regulation and soft switching are to be determined. By studying the small-signal characteristics of the entire system, a current-controlled feedback control circuit will be implemented CHAPTER 2 LITERATURE SURVEY Nowadays, full-bridge (FB) converter is predominantly the front-end power processor in typical power supply systems. It constitutes a part of power factor correction (PFC) in a single-stage acdc conversion. Or, it is the stage that fol-lows the boost-type PFC for converting universal ac line into dc bus in a two-stage system. In order to operate the pulse width-modulated (PWM) FB converters at high switching frequency and efficiency, various soft-switching techniques have been proposed. 2.1 ZVS FB CONVERTERS A large body of literature on zero-voltage-switched (ZVS) and zero-voltage-zero-current-switched (ZVZCS) converters is available. In ZVS FB converters, phase-shift control strategy allows the primary-side switches to operate under a zero-voltage condition .Two of the switches are operated in leading phase while the other two are operated in lagging phase. In this case, MOSFETs are the most suitable candidates for the switching devices on the primary side of the converter. 2.2 ZVZCS CONVERTERS In ZVZCS converters, the ZVS mechanism of the leading switches is similar to that in the previous converters. However, a zero-current switching (ZCS) condition is achieved to switch the lagging switches on and off by resetting the primary current during the freewheeling stage. The rst consequence is the avoidance of the circulation of the primary current during the freewheeling stage. To bring and keep the primary current to zero before nishing the turn-ON/turn-OFF process, a number of passive and active solutions have been proposed , at the expense of either higher circuit complexity and/or overvoltage across the rectier. 2.3 RESONANCE SNUBBER In these methods,ZCS is achieved by utilizing a resonance process with a snubber formed by a resonant inductance Lr (with the inclusion of the leakage inductance of the transformer) and a resonant capacitor Cr (with the inclusion of the reected winding capacitance).However, ZCS is lost at high input current. In order to extend the ZCS range, the
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characteristic impedance of the resonant tank has to be decreased, either by decreasing Lr or increasing Cr . A resonant cell, formed by a transistor, an inductor, a capacitor, and a diode is placed in parallel with each lower primary switch in [50]. For turning off the lower switch with ZCS, the snubbers transistor is turned on with ZCS, and the primary current is diverted to the auxiliary path. However, the auxiliary switch is then turned off with hard switching. CHAPTER 3 PWM CONTROL TECHNIQUES In a steady-state operating condition the average voltage across the inductor over the entire switching cycle is zero. This implies that the average current through the inductor is also in steady state. This is an important rule governing all inductor-based switching topologies. Taking this one step further, we can establish that for a given charge time, tON, and a given input voltage and with the circuit in equilibrium 3.1.1 CONTROL TECHNIQUES From the derivations for the boost, buck, and inverter (flyback), it can be seen that changing the duty cycle controls the steady-state output with respect to the input voltage. This is a key concept governing all inductor-based switching sample of the output voltage and subtracts this from a reference voltage to establish a small error signal (VERROR). This error signal is compared to an oscillator ramp signal. The comparator outputs a digital output (PWM) that operates the power switch. When the circuit output voltage changes, VERROR also changes and thus causes the comparator threshold to change. Consequently, the output pulse width (PWM) also changes. This duty cycle change then moves the output voltage to reduce to error signal to zero, thus completing the control loop. A practical circuit using the boost topology formed with the MAX1932. This IC is an integrated controller with an onboard programmable digital-to-analog converter (DAC). The DAC sets the output voltage digitally through a serial link. R5 and R8 form a divider that meters the output voltage. R6 is effectively out of circuit when the DAC voltage is the same as the reference voltage (1.25V). This is because there is zero volts across R6 and so zero current. When the DAC output is zero (ground), R6 is effectively in parallel with R8. These two conditions correspond to the minimum and maximum output adjustment range of 40V and 90V, respectively

Figure 3.3. Current-mode pulse-width modulation.The circuit in Figure3.4 uses CMC with the MAX668 controller. This boost circuitis similar to Figures 7 and 8 except that R1 senses the inductor current for CMC. R1 and some internal comparators provide acurrent limit. R5 in conjunction with C9 filters the switching noise on the sense resistor to prevent false triggering of the current limit. The MAX668's internal currentlimit threshold is fixed; changing the resistor, R1, adjusts the current-limit setting. The resistor, R2, sets the operating frequency. The MAX668 is a versatile integrated circuit that can provide a wide range of DC-DC conversions.
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tON/(tON + tOFF) = D .. (6)For the buck circuit: D = VOUT/VIN .. (7) 3.2 MAXIM'S PROPRIETARY QUICK-PWM CONTROL Maxim's proprietary Quick-PWM control method offers some advantages over PWM. Quick-PWM control generates a new cycle when the output voltage falls below the regulation threshold. Consequently, heavy transients force the output to fall, immediately firing a new on-cycle. This action results in a 100ns load-step response. It is also important to note that unlike the buck circuit in Figure 1, Figure 11 uses a MOSFET (Q2) instead of a diode for the discharge path. This design reduces the losses associated with the diode drop; the on-resistance of the MOSFET channel doubles as a current sense. Because outputvoltage ripple is required to stimulate the circuit to switch, an output filter capacitor with some ESR is required to maintain stability. 3.3 EFFICIENCY One of the largest power-loss factors for switchers is the rectifying diode. The power dissipated is simply the forward voltage drop multiplied by the current going through it. The reverse recovery for silicon diodes can also create loss. These power losses reduce overall efficiency and require thermal management in the form of a heat sink or fan. . When a MOSFET is used as a synchronous switch, the current normally flows in reverse (source to drain), and this allows the integrated body diode to conduct current during the dead time. When the synchronous rectifier switch closes, the current flows through the MOSFET channel.
Figure 3.4.MAX668 for current-mode-controlled boost circuit. Figure 3.5 shows a simplified version of Maxim's QuickPWM architecture. To analyze this buck circuit, we start with the feedback signal below the regulating threshold defined by the reference. If there are no forward current faults, then the tON one-shot timer that calculates the on-time for DH is turned on immediately along with DH.
Figure 3.7. Synchronous rectification for the buck circuit 3.4 SKIP MODE TO IMPROVE LIGHT LOAD EFFICIENCY A feature offered in many modern switching controllers is skip mode. Skip mode allows the regulator to skip cycles when they are not needed, which greatly improves efficiency at light loads. For the standard buck circuit (Figure 1) with a rectifying diode, not initiating a new cycle simply allows the inductor current or inductor energy to discharge to zero.
Figure 3.5 Simplified block diagram of Maxim's Quick-PWM control . tON (VIN - VOUT) = tOFF VOUT .. (3) Rearranging: VOUT/(VIN-VOUT) = tON/tOFF .. (4) Adding 1 to both side and collecting terms: VOUT/VIN = tON/(tON + tOFF) .. (5) Because the duty factor is D:

ZVS AND ZCS CONVERTER
655
Figure 3.8. In discontinuous mode the inductor fully discharges Figure 3.9 shows that skip mode offers improved light-load efficiencies but at the expense of noise, because the switching frequency is not fixed. The forced-PWM control technique maintains a constant switching frequency, and varies the ratio of charge cycle to discharge cycle as the operating parameters vary. Because the switching frequency is fixed
The basic structure of a typical two-stage front-end converter for DC distributed power systems, often used in systems requiring power factor correction (PFC) and power levels above about 500 - 600 W. For universal AC input line applications, the intermediate voltage between the two stages is approximately 380 Vdc.Typically, the peak total change in this voltage due to variations in line, load, and the effects of the 120 Hz ripple current is within 5 %. DC/DC converter requires passing the output voltage control signal across the isolation boundary and then providing the necessary logic functions to pulse-width-modulate the four bridge switches based on this control signal.
Figure 4.1 Traditional two stage concept Figure 3.9. Efficiency with and without skip mode. Although switching techniques are more difficult to implement, switching circuits have almost completely replaced linear power supplies in a wide range of portable and stationary designs. This is because switching circuits offer better efficiency, smaller components, and fewer thermal management issues 3.5 MOSFET POWER-SWITCH TECHNOLOGIES MOSFET power switches are now integrated with controllers to form single-chip solutions, like the MAX1945 circuit shown in Figure 3.10. This chip has a metallic slug on the underside that removes heat from the die so the 28-pin TSSOP package can dissipate over 1W, allowing the circuit to supply over 10W to its load. With a 1MHz switching frequency, the output inductor and filter capacitors can be reduced in size, further saving valuable space and component count.. Constant-frequency, phase-shifted operation of the primary side switches provides a convenient method for achieving zero-voltage turn-on of the switches, significantly A more load independent situation for ZVS can be created by incorporating some form of switching action in the converter secondary. In this scenario, secondary switches are used to prevent the magnetizing current from exiting the primary through the secondary.
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Figure 4.2 Two stage design with simplified secondary side DC/DC control Consequently, all the magnetizing energy is available for capacitor charge and discharge. No external energy storage element is necessary and ZVS is obtained through the use of a minimum amount of circulating energy. In addition to achieving a more load independent ZVS characteristic, the use of controlled switching in the secondary simplifies the overall control structure of the DC/DC converter. It describes the analysis, design, and experimental evaluation of an improved 100 kHz, 1 kW, full-bridge, ZVS PWM converter employing secondary-side magamp control. 4.1 THEORY OF OPERATION The basic operation of pulse-width-modulated, (PWM) phaseshifted, full-bridge converter employing secondary-side switching is illustrated . The switches on the same leg of the bridge are (ideally) switched with a 50 % duty cycle and are 180 out of phase. The switching time for one leg is then phase-shifted relative to the other. In the absence of the secondary-side switches, S5 and S6 (i.e., they are replaced with rectifiers), controlling the bridge phase shift (f) varies the volt-seconds applied to the output inductor and hence the resulting DC output voltage, Vo. ..
Figure 4.3 Waveforms T3 - T4: At T3, the leakage inductor current has decayed to the point where it is equal in value to the magnetizing current. D1 unclamps the secondary voltage and all of the load current commutes to the freewheeling diode. Because of the presence of S6 and the fact that it is open, the (very large) magnetizing inductance is now free to join the resonance with the switch capacitance. The primary advantages of secondary-side regulation are the removal of the need to pass a voltage feedback signal across the isolation barrier and the subsequent elimination of control of the phase-shifting for the FB switches. Also, secondary-side control can have the capability to isolate load faults from the primary or, in the case of a multiple output converter, from other outputs (S5 and S6 could be left open for the duration of an output short). CONCULSION DC-DC converter has been studied in detail and various soft switching techniques were discussed. The SVS and ZCS technique has been discussed in detail along with its advantages and disadvantages. The ZVS full bridge PWM converter has been analyzed with its design and working in Chapter-4. A literature survey has been done in all the existing soft switching techniques using different methods. Various techniques used in the existing systems have resulted in circuit complexity and increase conduction losses. Hence decreased efficiencies and low frequency switching speeds has always been reported as a major disadvantage in all the existing systems that have been discussed. The ZVS-ZCS conduction archived in the proposed system combined with the advantage of snubber energy will over come the above said disadvantages. The snubber energy obtained from the resonant circuit formed using a Lr and Cr is self adaptable and to great extent can be concluded as the snubber energy will facilitate high frequency switching speeds without much losses and will result in a increased in efficiency. FUTURE WORK MATLAB simulation work has to be carried out and the result for various loads at high frequency switching speeds has to be obtained. The results are to be compared with those of the

existing systems and detailed analysis has to be done. The percentage increase in efficiency between the two systems should be tabulated. REFERENCES [1] r. Fisher, k. Ngo, and m. Kuo, a 500 kHz, 250 w dcdc converter with multiple outputs controlled by phaseshifted pwm and magnetic amplifiers, in Proc. High Freq. Power Conf., May 1988, pp. 100110. [2] l. h. Mweene, c. a. Wright, and m. f. Schlecht, a 1 kW, 500 kHz front-end converter for a distributed power supply system, in Proc. IEEE Appl. Power Electron. Conf., 1989, pp. 423432. [3] j. Sabate, v. Vlatkovic, r. Ridley, f. Lee, and b. Cho, Design considerations for high-voltage high-power fullbridge zero-voltage-switched pwm converter, in Proc. IEEE Appl. Power Electron. Conf., 1990, pp. 275284. [4] r. Redl, n. Sokal, and l. Balogh, a novel soft-switching full-bridge dc/dc converter: Analysis, design considerations, and experimental results at 1.5 kW, 100 kHz, in Proc. IEEE Power Electron. Spec. Conf., 1990, pp. 162172. [5] j. Sabate, v. Vlatkovic, r. Ridley, and f. Lee, Highvoltage, high-power, zvs, full-bridge pwm converter employing an active snubber, in Proc. IEEE Appl. Power Electron. Conf., 1991, pp. 158163. [6] g. Hua, f. Lee, and m. Jovanovic, An improved fullbridge zero-voltage-switched pwm converter using a saturable inductor, IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530534, Oct. 1993. [7] r. Redl, l. Balogh, and d. Edwards, Optimum zvs fullbridge dc/dc converter with pwm phase-shift control: Analysis, design considerations, and experimental results, in Proc. IEEE Appl. Power Electron. Conf., 1994, pp. 159165.
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First National Conference On "RECENT TRENDS IN POWER ELECTRONICS AND INDUSTRIAL DRIVES" PEID-2011

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First National Conference on RECENT TRENDS IN POWER ELECTRONICS AND INDUSTRIAL DRIVES PEID-2011

March 04-05, 2011

Organized By DEPARTMENT OF ELECTRICAL& ELECTRONICS ENGINEERING

INFO INSTITUTE OF ENGINEERING COIMBATORE

All rights reserved

Copyright 2011 Info Institute of Engineering, Coimbatore

Department of Electrical & Electronics Engineering

Coimbatore District, Tamil Nadu

Info Institute of Engineering, Coimbatore 641 107

INFO INSTITUTE OF ENGINEERING MESSAGE

INFO INSTITUTE OF ENGINEERING COIMBATORE MESSAGE Dr.Chitra Manohar Secretary, IIE

Coimbatore- 641 107 Tamil Nadu

ABOUT THE COLLEGE

BACHELOR OF TECHNOLOGY (B.Tech.) 4 years Information Technology

FIRST NATIONAL CONFERENCE

Advisory Board Members PEID 2011

Printing, Designing & Proceedings

Audio & Video Photography

Student volunteers S.NISHA T.RAMYA G.MANOCHITRA

Student volunteer K.VIJAYALAKSHMI R.BALAHEMALATHA R.ANANDHI V.M.RAMAKRISHNAN S.MANIRATHNAM R.V.NIRMAL RAJ

Overall Coordination : Ms R Bagyalakshmi

INVITED CHAIR PERSONS

Ms R Vidhya Assistant Professor Dept. of EEE INFO Institute of Engineering

Mr.V.Kumarchinnayan Professor and Head Dept. of EEE Jansons Institute of Engineering

Ms.Bagyalakshmi Assistant Professor Dept. of EEE INFO Institute of Engineering

Mr.VijayBaskar Professor Anna University of Technology

Mr.Aravind Assistant Professor Dept. of EEE INFO Institute of Engineering

Mr.Pongiyannan Profesor Department of EEE Bannari Amman Institute of Technology

Ms.Sasipriya Professor Dept. Of ECE INFO Institute of Engineering

Mr.Vijayakumar Professor Dept. of EEE Karpagam College of Engineering

Mr.Veerakumar Professor Dept. of EEE Bannari Amman Institute of Technology

Recent Advances in Power Electronics and Industrial Drives PEID 2011

Seminal Hall 1 DAY 1: FRIDAY MARCH 04, 2011

SATURDAY MARCH 05, 2011

Seminar Hall I Session 2A Power Converters - II

01.00 pm to 2.00 pm Session 2D, 2E, 2F 02.00 pm-5.15 pm

PEID 2011 SCHEDULE

Schedule for Paper Presentation

PEID 2011 SCHEDULE

Session 2A Power Converters II March 05, 2011 (09:45am- 01.00pm)

PEID 2011 SCHEDULE

Session 2C Applied Electronics I March 05, 2011 (09:45am-01:00pm)

PEID 2011 SCHEDULE

Session 2D Applied Electronics II March 05, 2011 (02:00- 05:15 pm)

Session 2E Engineering Applications March 05, 2011 (02:00- 05.15 pm)

Application of Intelligent Systems in Model Order Reduction---------------------------------------------------(525) S.Priya, K.Ramesh

Automation on PLC Furnace System-------------------(570)

PEID 2011 SCHEDULE

Session 2F Power Quality & Application to Power System III

Session 2F Power Quality & Application to Power System III

PEID 2011 SCHEDULE

Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore

A 9 Level Cascaded Multilevel Inverter Using Transformer Connections

Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore

Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore

VAK 2 -1 -1 Vak T VBK = . -1 2 -1 . Vbk 3 -1 -1 2 Vck VCK

Flying capacit ors

Convent ional Cascade d Hbridge

Propose d Cascade d Hbridge

Switch Diode Capacitor Input DC source Output transformer

VAB VAS VA1+VA2+....VAk VBC = VBS = VB1+VB2+....VBk VCA VCS VC1+VC2+....VCk

Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore

Proceedings of PEID-2011 INFO Institute of Engineering, Coimbatore